1 /* $OpenBSD: ciphyreg.h,v 1.2 2006/02/28 08:13:47 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/mii/ciphyreg.h,v 1.2 2005/01/06 01:42:55 imp Exp $ 35 * $DragonFly: src/sys/dev/netif/mii_layer/ciphyreg.h,v 1.2 2006/08/06 10:32:23 sephe Exp $ 36 */ 37 38 #ifndef _DEV_MII_CIPHYREG_H_ 39 #define _DEV_MII_CIPHYREG_H_ 40 41 /* 42 * Register definitions for the Cicada CS8201 10/100/1000 gigE copper 43 * PHY, embedded within the VIA Networks VT6122 controller. 44 */ 45 46 /* Command register */ 47 #define CIPHY_MII_BMCR 0x00 48 #define CIPHY_BMCR_RESET 0x8000 49 #define CIPHY_BMCR_LOOP 0x4000 50 #define CIPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */ 51 #define CIPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */ 52 #define CIPHY_BMCR_PDOWN 0x0800 /* Power down */ 53 #define CIPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */ 54 #define CIPHY_BMCR_FDX 0x0100 /* Duplex mode */ 55 #define CIPHY_BMCR_CTEST 0x0080 /* Collision test enable */ 56 #define CIPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */ 57 58 #define CIPHY_S1000 CIPHY_BMCR_SPD1 /* 1000mbps */ 59 #define CIPHY_S100 CIPHY_BMCR_SPD0 /* 100mpbs */ 60 #define CIPHY_S10 0 /* 10mbps */ 61 62 /* Status register */ 63 #define CIPHY_MII_BMSR 0x01 64 #define CIPHY_BMSR_100T4 0x8000 /* 100 base T4 capable */ 65 #define CIPHY_BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */ 66 #define CIPHY_BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */ 67 #define CIPHY_BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */ 68 #define CIPHY_BMSR_10THDX 0x0800 /* 10 base T half duplex capable */ 69 #define CIPHY_BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */ 70 #define CIPHY_BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */ 71 #define CIPHY_BMSR_EXTSTS 0x0100 /* Extended status present */ 72 #define CIPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */ 73 #define CIPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */ 74 #define CIPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */ 75 #define CIPHY_BMSR_ANEG 0x0008 /* Autoneg capable */ 76 #define CIPHY_BMSR_LINK 0x0004 /* Link status */ 77 #define CIPHY_BMSR_JABBER 0x0002 /* Jabber detected */ 78 #define CIPHY_BMSR_EXT 0x0001 /* Extended capability */ 79 80 /* PHY ID registers */ 81 #define CIPHY_MII_PHYIDR1 0x02 82 #define CIPHY_MII_PHYIDR2 0x03 83 84 /* Autoneg advertisement */ 85 #define CIPHY_MII_ANAR 0x04 86 #define CIPHY_ANAR_NP 0x8000 /* Next page */ 87 #define CIPHY_ANAR_RF 0x2000 /* Remote fault */ 88 #define CIPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */ 89 #define CIPHY_ANAR_PC 0x0400 /* Pause capable */ 90 #define CIPHY_ANAR_T4 0x0200 /* local device supports 100bT4 */ 91 #define CIPHY_ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */ 92 #define CIPHY_ANAR_TX 0x0080 /* local device supports 100bTx */ 93 #define CIPHY_ANAR_10_FD 0x0040 /* local device supports 10bT FD */ 94 #define CIPHY_ANAR_10 0x0020 /* local device supports 10bT */ 95 #define CIPHY_ANAR_SEL 0x001F /* selector field, 00001=Ethernet */ 96 97 /* Autoneg link partner ability */ 98 #define CIPHY_MII_ANLPAR 0x05 99 #define CIPHY_ANLPAR_NP 0x8000 /* Next page */ 100 #define CIPHY_ANLPAR_ACK 0x4000 /* link partner acknowledge */ 101 #define CIPHY_ANLPAR_RF 0x2000 /* Remote fault */ 102 #define CIPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */ 103 #define CIPHY_ANLPAR_PC 0x0400 /* Pause capable */ 104 #define CIPHY_ANLPAR_T4 0x0200 /* link partner supports 100bT4 */ 105 #define CIPHY_ANLPAR_TX_FD 0x0100 /* link partner supports 100bTx FD */ 106 #define CIPHY_ANLPAR_TX 0x0080 /* link partner supports 100bTx */ 107 #define CIPHY_ANLPAR_10_FD 0x0040 /* link partner supports 10bT FD */ 108 #define CIPHY_ANLPAR_10 0x0020 /* link partner supports 10bT */ 109 #define CIPHY_ANLPAR_SEL 0x001F /* selector field, 00001=Ethernet */ 110 111 #define CIPHY_SEL_TYPE 0x0001 /* ethernet */ 112 113 /* Antoneg expansion register */ 114 #define CIPHY_MII_ANER 0x06 115 #define CIPHY_ANER_PDF 0x0010 /* Parallel detection fault */ 116 #define CIPHY_ANER_LPNP 0x0008 /* Link partner can next page */ 117 #define CIPHY_ANER_NP 0x0004 /* Local PHY can next page */ 118 #define CIPHY_ANER_RX 0x0002 /* Next page received */ 119 #define CIPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */ 120 121 /* Autoneg next page transmit regisyer */ 122 #define CIPHY_MII_NEXTP 0x07 123 #define CIPHY_NEXTP_MOREP 0x8000 /* More pages to follow */ 124 #define CIPHY_NEXTP_MESS 0x2000 /* 1 = message page, 0 = unformatted */ 125 #define CIPHY_NEXTP_ACK2 0x1000 /* MAC acknowledge */ 126 #define CIPHY_NEXTP_TOGGLE 0x0800 /* Toggle */ 127 #define CIPHY_NEXTP_CODE 0x07FF /* Code bits */ 128 129 /* Autoneg link partner next page receive register */ 130 #define CIPHY_MII_NEXTP_LP 0x08 131 #define CIPHY_NEXTPLP_MOREP 0x8000 /* More pages to follow */ 132 #define CIPHY_NEXTPLP_MESS 0x2000 /* 1 = message page, 0 = unformatted */ 133 #define CIPHY_NEXTPLP_ACK2 0x1000 /* MAC acknowledge */ 134 #define CIPHY_NEXTPLP_TOGGLE 0x0800 /* Toggle */ 135 #define CIPHY_NEXTPLP_CODE 0x07FF /* Code bits */ 136 137 /* 1000BT control register */ 138 #define CIPHY_MII_1000CTL 0x09 139 #define CIPHY_1000CTL_TST 0xE000 /* test modes */ 140 #define CIPHY_1000CTL_MSE 0x1000 /* Master/Slave manual enable */ 141 #define CIPHY_1000CTL_MSC 0x0800 /* Master/Slave select */ 142 #define CIPHY_1000CTL_RD 0x0400 /* Repeater/DTE */ 143 #define CIPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */ 144 #define CIPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */ 145 146 #define CIPHY_TEST_TX_JITTER 0x2000 147 #define CIPHY_TEST_TX_JITTER_MASTER_MODE 0x4000 148 #define CIPHY_TEST_TX_JITTER_SLAVE_MODE 0x6000 149 #define CIPHY_TEST_TX_DISTORTION 0x8000 150 151 /* 1000BT status register */ 152 #define CIPHY_MII_1000STS 0x0A 153 #define CIPHY_1000STS_MSF 0x8000 /* Master/slave fault */ 154 #define CIPHY_1000STS_MSR 0x4000 /* Master/slave result */ 155 #define CIPHY_1000STS_LRS 0x2000 /* Local receiver status */ 156 #define CIPHY_1000STS_RRS 0x1000 /* Remote receiver status */ 157 #define CIPHY_1000STS_LPFD 0x0800 /* Link partner can FD */ 158 #define CIPHY_1000STS_LPHD 0x0400 /* Link partner can HD */ 159 #define CIPHY_1000STS_IEC 0x00FF /* Idle error count */ 160 161 #define CIPHY_MII_EXTSTS 0x0F /* Extended status */ 162 #define CIPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */ 163 #define CIPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */ 164 #define CIPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */ 165 #define CIPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */ 166 167 /* 1000BT status extension register #1 */ 168 #define CIPHY_MII_1000STS1 0x0F 169 #define CIPHY_1000STS1_1000XFDX 0x8000 /* 1000baseX FDX capable */ 170 #define CIPHY_1000STS1_1000XHDX 0x4000 /* 1000baseX HDX capable */ 171 #define CIPHY_1000STS1_1000TFDX 0x2000 /* 1000baseT FDX capable */ 172 #define CIPHY_1000STS1_1000THDX 0x1000 /* 1000baseT HDX capable */ 173 174 /* Vendor-specific PHY registers */ 175 176 /* 100baseTX status extention register */ 177 #define CIPHY_MII_100STS 0x10 178 #define CIPHY_100STS_DESLCK 0x8000 /* descrambler locked */ 179 #define CIPHY_100STS_LKCERR 0x4000 /* lock error detected/lock lost */ 180 #define CIPHY_100STS_DISC 0x2000 /* disconnect state */ 181 #define CIPHY_100STS_LINK 0x1000 /* current link state */ 182 #define CIPHY_100STS_RXERR 0x0800 /* receive error detected */ 183 #define CIPHY_100STS_TXERR 0x0400 /* transmit error detected */ 184 #define CIPHY_100STS_SSDERR 0x0200 /* false carrier error detected */ 185 #define CIPHY_100STS_ESDERR 0x0100 /* premature end of stream error */ 186 187 /* 1000BT status extention register #2 */ 188 #define CIPHY_MII_1000STS2 0x11 189 #define CIPHY_1000STS2_DESLCK 0x8000 /* descrambler locked */ 190 #define CIPHY_1000STS2_LKCERR 0x4000 /* lock error detected/lock lost */ 191 #define CIPHY_1000STS2_DISC 0x2000 /* disconnect state */ 192 #define CIPHY_1000STS2_LINK 0x1000 /* current link state */ 193 #define CIPHY_1000STS2_RXERR 0x0800 /* receive error detected */ 194 #define CIPHY_1000STS2_TXERR 0x0400 /* transmit error detected */ 195 #define CIPHY_1000STS2_SSDERR 0x0200 /* false carrier error detected */ 196 #define CIPHY_1000STS2_ESDERR 0x0100 /* premature end of stream error */ 197 #define CIPHY_1000STS2_CARREXT 0x0080 /* carrier extention err detected */ 198 #define CIPHY_1000STS2_BCM5400 0x0040 /* non-complient BCM5400 detected */ 199 200 /* Bypass control register */ 201 #define CIPHY_MII_BYPASS 0x12 202 #define CIPHY_BYPASS_TX 0x8000 /* transmit disable */ 203 #define CIPHY_BYPASS_4B5B 0x4000 /* bypass the 4B5B encoder */ 204 #define CIPHY_BYPASS_SCRAM 0x2000 /* bypass scrambler */ 205 #define CIPHY_BYPASS_DSCAM 0x1000 /* bypass descrambler */ 206 #define CIPHY_BYPASS_PCSRX 0x0800 /* bypass PCS receive */ 207 #define CIPHY_BYPASS_PCSTX 0x0400 /* bypass PCS transmit */ 208 #define CIPHY_BYPASS_LFI 0x0200 /* bypass LFI timer */ 209 #define CIPHY_BYPASS_TXCLK 0x0100 /* enable transmit clock on LED4 pin */ 210 #define CIPHY_BYPASS_BCM5400_F 0x0080 /* force BCM5400 detect */ 211 #define CIPHY_BYPASS_BCM5400 0x0040 /* bypass BCM5400 detect */ 212 #define CIPHY_BYPASS_PAIRSWAP 0x0020 /* disable automatic pair swap */ 213 #define CIPHY_BYPASS_POLARITY 0x0010 /* disable polarity correction */ 214 #define CIPHY_BYPASS_PARALLEL 0x0008 /* parallel detect enable */ 215 #define CIPHY_BYPASS_PULSE 0x0004 /* disable pulse shaping filter */ 216 #define CIPHY_BYPASS_1000BNP 0x0002 /* disable 1000BT next page exchange */ 217 218 /* RX error count register */ 219 #define CIPHY_MII_RXERR 0x13 220 221 /* False carrier sense count register */ 222 #define CIPHY_MII_FCSERR 0x14 223 224 /* Ddisconnect error counter */ 225 #define CIPHY_MII_DISCERR 0x15 226 227 /* 10baseT control/status register */ 228 #define CIPHY_MII_10BTCSR 0x16 229 #define CIPHY_10BTCSR_DLIT 0x8000 /* Disable data link integrity test */ 230 #define CIPHY_10BTCSR_JABBER 0x4000 /* Disable jabber detect */ 231 #define CIPHY_10BTCSR_ECHO 0x2000 /* Disable echo mode */ 232 #define CIPHY_10BTCSR_SQE 0x1000 /* Disable signal quality error */ 233 #define CIPHY_10BTCSR_SQUENCH 0x0C00 /* Squelch control */ 234 #define CIPHY_10BTCSR_EOFERR 0x0100 /* End of Frame error */ 235 #define CIPHY_10BTCSR_DISC 0x0080 /* Disconnect status */ 236 #define CIPHY_10BTCSR_LINK 0x0040 /* current link state */ 237 #define CIPHY_10BTCSR_ITRIM 0x0038 /* current reference trim */ 238 #define CIPHY_10BTCSR_CSR 0x0006 /* CSR behavior control */ 239 240 #define CIPHY_SQUELCH_300MV 0x0000 241 #define CIPHY_SQUELCH_197MV 0x0400 242 #define CIPHY_SQUELCH_450MV 0x0800 243 #define CIPHY_SQUELCH_RSVD 0x0C00 244 245 #define CIPHY_ITRIM_PLUS2 0x0000 246 #define CIPHY_ITRIM_PLUS4 0x0008 247 #define CIPHY_ITRIM_PLUS6 0x0010 248 #define CIPHY_ITRIM_PLUS6_ 0x0018 249 #define CIPHY_ITRIM_MINUS4 0x0020 250 #define CIPHY_ITRIM_MINUS4_ 0x0028 251 #define CIPHY_ITRIM_MINUS2 0x0030 252 #define CIPHY_ITRIM_ZERO 0x0038 253 254 /* Extended PHY control register #1 */ 255 #define CIPHY_MII_ECTL1 0x17 256 #define CIPHY_ECTL1_ACTIPHY 0x0020 /* Enable ActiPHY power saving */ 257 #define CIPHY_ECTL1_IOVOL 0x0e00 /* MAC interface and I/O voltage select */ 258 #define CIPHY_ECTL1_INTSEL 0xf000 /* select MAC interface */ 259 260 #define CIPHY_IOVOL_3300MV 0x0000 /* 3.3V for I/O pins */ 261 #define CIPHY_IOVOL_2500MV 0x0200 /* 2.5V for I/O pins */ 262 263 #define CIPHY_INTSEL_GMII 0x0000 /* GMII/MII */ 264 #define CIPHY_INTSEL_RGMII 0x1000 265 #define CIPHY_INTSEL_TBI 0x2000 266 #define CIPHY_INTSEL_RTBI 0x3000 267 268 /* Extended PHY control register #2 */ 269 #define CIPHY_MII_ECTL2 0x18 270 #define CIPHY_ECTL2_ERATE 0xE000 /* 10/1000 edge rate control */ 271 #define CIPHY_ECTL2_VTRIM 0x1C00 /* voltage reference trim */ 272 #define CIPHY_ECTL2_CABLELEN 0x000E /* Cable quality/length */ 273 #define CIPHY_ECTL2_ANALOGLOOP 0x0001 /* 1000BT analog loopback */ 274 275 #define CIPHY_CABLELEN_0TO10M 0x0000 276 #define CIPHY_CABLELEN_10TO20M 0x0002 277 #define CIPHY_CABLELEN_20TO40M 0x0004 278 #define CIPHY_CABLELEN_40TO80M 0x0006 279 #define CIPHY_CABLELEN_80TO100M 0x0008 280 #define CIPHY_CABLELEN_100TO140M 0x000A 281 #define CIPHY_CABLELEN_140TO180M 0x000C 282 #define CIPHY_CABLELEN_OVER180M 0x000E 283 284 /* Interrupt mask register */ 285 #define CIPHY_MII_IMR 0x19 286 #define CIPHY_IMR_PINENABLE 0x8000 /* Interrupt pin enable */ 287 #define CIPHY_IMR_SPEED 0x4000 /* speed changed event */ 288 #define CIPHY_IMR_LINK 0x2000 /* link change/ActiPHY event */ 289 #define CIPHY_IMR_DPX 0x1000 /* duplex change event */ 290 #define CIPHY_IMR_ANEGERR 0x0800 /* autoneg error event */ 291 #define CIPHY_IMR_ANEGDONE 0x0400 /* autoneg done event */ 292 #define CIPHY_IMR_NPRX 0x0200 /* page received event */ 293 #define CIPHY_IMR_SYMERR 0x0100 /* symbol error event */ 294 #define CIPHY_IMR_LOCKERR 0x0080 /* descrambler lock lost event */ 295 #define CIPHY_IMR_XOVER 0x0040 /* MDI crossover change event */ 296 #define CIPHY_IMR_POLARITY 0x0020 /* polarity change event */ 297 #define CIPHY_IMR_JABBER 0x0010 /* jabber detect event */ 298 #define CIPHY_IMR_SSDERR 0x0008 /* false carrier detect event */ 299 #define CIPHY_IMR_ESDERR 0x0004 /* parallel detect error event */ 300 #define CIPHY_IMR_MASTERSLAVE 0x0002 /* master/slave resolve done event */ 301 #define CIPHY_IMR_RXERR 0x0001 /* RX error event */ 302 303 /* Interrupt status register */ 304 #define CIPHY_MII_ISR 0x1A 305 #define CIPHY_ISR_IPENDING 0x8000 /* Interrupt is pending */ 306 #define CIPHY_ISR_SPEED 0x4000 /* speed changed event */ 307 #define CIPHY_ISR_LINK 0x2000 /* link change/ActiPHY event */ 308 #define CIPHY_ISR_DPX 0x1000 /* duplex change event */ 309 #define CIPHY_ISR_ANEGERR 0x0800 /* autoneg error event */ 310 #define CIPHY_ISR_ANEGDONE 0x0400 /* autoneg done event */ 311 #define CIPHY_ISR_NPRX 0x0200 /* page received event */ 312 #define CIPHY_ISR_SYMERR 0x0100 /* symbol error event */ 313 #define CIPHY_ISR_LOCKERR 0x0080 /* descrambler lock lost event */ 314 #define CIPHY_ISR_XOVER 0x0040 /* MDI crossover change event */ 315 #define CIPHY_ISR_POLARITY 0x0020 /* polarity change event */ 316 #define CIPHY_ISR_JABBER 0x0010 /* jabber detect event */ 317 #define CIPHY_ISR_SSDERR 0x0008 /* false carrier detect event */ 318 #define CIPHY_ISR_ESDERR 0x0004 /* parallel detect error event */ 319 #define CIPHY_ISR_MASTERSLAVE 0x0002 /* master/slave resolve done event */ 320 #define CIPHY_ISR_RXERR 0x0001 /* RX error event */ 321 322 /* LED control register */ 323 #define CIPHY_MII_LED 0x1B 324 #define CIPHY_LED_LINK10FORCE 0x8000 /* Force on link10 LED */ 325 #define CIPHY_LED_LINK10DIS 0x4000 /* Disable link10 LED */ 326 #define CIPHY_LED_LINK100FORCE 0x2000 /* Force on link10 LED */ 327 #define CIPHY_LED_LINK100DIS 0x1000 /* Disable link100 LED */ 328 #define CIPHY_LED_LINK1000FORCE 0x0800 /* Force on link1000 LED */ 329 #define CIPHY_LED_LINK1000DIS 0x0400 /* Disable link1000 LED */ 330 #define CIPHY_LED_FDXFORCE 0x0200 /* Force on duplex LED */ 331 #define CIPHY_LED_FDXDIS 0x0100 /* Disable duplex LED */ 332 #define CIPHY_LED_ACTFORCE 0x0080 /* Force on activity LED */ 333 #define CIPHY_LED_ACTDIS 0x0040 /* Disable activity LED */ 334 #define CIPHY_LED_PULSE 0x0008 /* LED pulse enable */ 335 #define CIPHY_LED_LINKACTBLINK 0x0004 /* enable link/activity LED blink */ 336 #define CIPHY_LED_BLINKRATE 0x0002 /* blink rate 0=10hz, 1=5hz */ 337 338 /* Auxilliary control and status register */ 339 #define CIPHY_MII_AUXCSR 0x1C 340 #define CIPHY_AUXCSR_ANEGDONE 0x8000 /* Autoneg complete */ 341 #define CIPHY_AUXCSR_ANEGOFF 0x4000 /* Autoneg disabled */ 342 #define CIPHY_AUXCSR_XOVER 0x2000 /* MDI/MDI-X crossover indication */ 343 #define CIPHY_AUXCSR_PAIRSWAP 0x1000 /* pair swap indication */ 344 #define CIPHY_AUXCSR_APOLARITY 0x0800 /* polarity inversion pair A */ 345 #define CIPHY_AUXCSR_BPOLARITY 0x0400 /* polarity inversion pair B */ 346 #define CIPHY_AUXCSR_CPOLARITY 0x0200 /* polarity inversion pair C */ 347 #define CIPHY_AUXCSR_DPOLARITY 0x0100 /* polarity inversion pair D */ 348 #define CIPHY_AUXCSR_FDX 0x0020 /* duplex 1=full, 0=half */ 349 #define CIPHY_AUXCSR_SPEED 0x0018 /* speed */ 350 #define CIPHY_AUXCSR_MDPPS 0x0004 /* No idea, not documented */ 351 #define CIPHY_AUXCSR_STICKYREST 0x0002 /* reset clears sticky bits */ 352 353 #define CIPHY_SPEED10 0x0000 354 #define CIPHY_SPEED100 0x0008 355 #define CIPHY_SPEED1000 0x0010 356 357 /* Delay skew status register */ 358 #define CIPHY_MII_DSKEW 0x1D 359 #define CIPHY_DSKEW_PAIRA 0x7000 /* Pair A skew in symbol times */ 360 #define CIPHY_DSKEW_PAIRB 0x0700 /* Pair B skew in symbol times */ 361 #define CIPHY_DSKEW_PAIRC 0x0070 /* Pair C skew in symbol times */ 362 #define CIPHY_DSKEW_PAIRD 0x0007 /* Pair D skew in symbol times */ 363 364 #endif /* _DEV_CIPHY_MIIREG_H_ */ 365