1 /* $FreeBSD: src/sys/dev/mii/e1000phy.c,v 1.1.2.2 2002/11/08 21:53:49 semenu Exp $ */ 2 /* $DragonFly: src/sys/dev/netif/mii_layer/e1000phy.c,v 1.8 2006/08/06 10:32:23 sephe Exp $ */ 3 /* $OpenBSD: eephy.c,v 1.26 2006/06/08 00:27:12 brad Exp $ */ 4 /* 5 * Principal Author: Parag Patel 6 * Copyright (c) 2001 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * Additonal Copyright (c) 2001 by Traakan Software under same licence. 32 * Secondary Author: Matthew Jacob 33 */ 34 35 /* 36 * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY. 37 */ 38 39 /* 40 * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and 41 * 1000baseSX PHY. 42 * Nathan Binkert <nate@openbsd.org> 43 * Jung-uk Kim <jkim@niksun.com> 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/socket.h> 50 #include <sys/bus.h> 51 52 #include <net/if.h> 53 #include <net/if_media.h> 54 55 #include "mii.h" 56 #include "miivar.h" 57 #include "miidevs.h" 58 59 #include "e1000phyreg.h" 60 61 #include "miibus_if.h" 62 63 static int e1000phy_probe(device_t); 64 static int e1000phy_attach(device_t); 65 static int e1000phy_service(struct mii_softc *, struct mii_data *, int); 66 static void e1000phy_status(struct mii_softc *); 67 static int e1000phy_mii_phy_auto(struct mii_softc *, int); 68 static void e1000phy_reset(struct mii_softc *); 69 70 static device_method_t e1000phy_methods[] = { 71 /* device interface */ 72 DEVMETHOD(device_probe, e1000phy_probe), 73 DEVMETHOD(device_attach, e1000phy_attach), 74 DEVMETHOD(device_detach, ukphy_detach), 75 DEVMETHOD(device_shutdown, bus_generic_shutdown), 76 { 0, 0 } 77 }; 78 79 static const struct mii_phydesc e1000phys[] = { 80 MII_PHYDESC(xxMARVELL, E1000_2), 81 MII_PHYDESC(xxMARVELL, E1000_3), 82 MII_PHYDESC(xxMARVELL, E1000_5), 83 MII_PHYDESC(xxMARVELL, E1111), 84 MII_PHYDESC(MARVELL, E1000), 85 MII_PHYDESC(MARVELL, E1011), 86 MII_PHYDESC(MARVELL, E1000_3), 87 MII_PHYDESC(MARVELL, E1000_4), 88 MII_PHYDESC(MARVELL, E1000_5), 89 MII_PHYDESC(MARVELL, E1000_6), 90 MII_PHYDESC(MARVELL, E1111), 91 MII_PHYDESC(MARVELL, E1116), 92 MII_PHYDESC_NULL 93 }; 94 95 static devclass_t e1000phy_devclass; 96 97 static driver_t e1000phy_driver = { 98 "e1000phy", 99 e1000phy_methods, 100 sizeof(struct mii_softc) 101 }; 102 DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, e1000phy_devclass, 0, 0); 103 104 static int 105 e1000phy_probe(device_t dev) 106 { 107 struct mii_attach_args *ma = device_get_ivars(dev); 108 const struct mii_phydesc *mpd; 109 110 mpd = mii_phy_match(ma, e1000phys); 111 if (mpd != NULL) { 112 device_set_desc(dev, mpd->mpd_name); 113 return 0; 114 } 115 return (ENXIO); 116 } 117 118 static int 119 e1000phy_attach(device_t dev) 120 { 121 struct mii_softc *sc; 122 struct mii_attach_args *ma; 123 struct mii_data *mii; 124 const char *sep = ""; 125 126 sc = device_get_softc(dev); 127 ma = device_get_ivars(dev); 128 mii_softc_init(sc, ma); 129 sc->mii_dev = device_get_parent(dev); 130 mii = device_get_softc(sc->mii_dev); 131 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 132 133 sc->mii_inst = mii->mii_instance; 134 sc->mii_service = e1000phy_service; 135 sc->mii_reset = e1000phy_reset; 136 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 137 sc->mii_pdata = mii; 138 139 sc->mii_flags |= MIIF_NOISOLATE; 140 141 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_MARVELL && 142 MII_MODEL(ma->mii_id2) == MII_MODEL_MARVELL_E1011 && 143 (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK)) 144 sc->mii_flags |= MIIF_HAVEFIBER; 145 146 mii->mii_instance++; 147 148 e1000phy_reset(sc); 149 150 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 151 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 152 153 #if 0 154 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 155 E1000_CR_ISOLATE); 156 #endif 157 158 device_printf(dev, " "); 159 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 160 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 161 E1000_CR_SPEED_1000 | E1000_CR_FULL_DUPLEX); 162 PRINT("1000baseTX-FDX"); 163 /* 164 TODO - apparently 1000BT-simplex not supported? 165 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 166 E1000_CR_SPEED_1000); 167 PRINT("1000baseTX"); 168 */ 169 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst), 170 E1000_CR_SPEED_100 | E1000_CR_FULL_DUPLEX); 171 PRINT("100baseTX-FDX"); 172 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst), 173 E1000_CR_SPEED_100); 174 PRINT("100baseTX"); 175 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst), 176 E1000_CR_SPEED_10 | E1000_CR_FULL_DUPLEX); 177 PRINT("10baseTX-FDX"); 178 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst), 179 E1000_CR_SPEED_10); 180 PRINT("10baseTX"); 181 } else { 182 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 183 E1000_CR_SPEED_1000); 184 PRINT("1000baseSX-FDX"); 185 } 186 187 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 188 PRINT("auto"); 189 190 printf("\n"); 191 #undef ADD 192 #undef PRINT 193 194 MIIBUS_MEDIAINIT(sc->mii_dev); 195 return(0); 196 } 197 198 static void 199 e1000phy_reset(struct mii_softc *sc) 200 { 201 uint32_t reg; 202 int i; 203 204 /* initialize custom E1000 registers to magic values */ 205 reg = PHY_READ(sc, E1000_SCR); 206 reg &= ~E1000_SCR_AUTO_X_MODE; 207 PHY_WRITE(sc, E1000_SCR, reg); 208 209 /* normal PHY reset */ 210 /*mii_phy_reset(sc);*/ 211 reg = PHY_READ(sc, E1000_CR); 212 reg |= E1000_CR_RESET; 213 PHY_WRITE(sc, E1000_CR, reg); 214 215 for (i = 0; i < 500; i++) { 216 DELAY(1); 217 reg = PHY_READ(sc, E1000_CR); 218 if (!(reg & E1000_CR_RESET)) 219 break; 220 } 221 222 /* set more custom E1000 registers to magic values */ 223 reg = PHY_READ(sc, E1000_SCR); 224 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 225 PHY_WRITE(sc, E1000_SCR, reg); 226 227 reg = PHY_READ(sc, E1000_ESCR); 228 reg |= E1000_ESCR_TX_CLK_25; 229 PHY_WRITE(sc, E1000_ESCR, reg); 230 231 /* even more magic to reset DSP? */ 232 PHY_WRITE(sc, 29, 0x1d); 233 PHY_WRITE(sc, 30, 0xc1); 234 PHY_WRITE(sc, 30, 0x00); 235 } 236 237 static int 238 e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 239 { 240 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 241 int reg; 242 243 switch (cmd) { 244 case MII_POLLSTAT: 245 /* 246 * If we're not polling our PHY instance, just return. 247 */ 248 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 249 return (0); 250 break; 251 252 case MII_MEDIACHG: 253 /* 254 * If the media indicates a different PHY instance, 255 * isolate ourselves. 256 */ 257 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 258 reg = PHY_READ(sc, E1000_CR); 259 PHY_WRITE(sc, E1000_CR, reg | E1000_CR_ISOLATE); 260 return (0); 261 } 262 263 /* 264 * If the interface is not up, don't do anything. 265 */ 266 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) { 267 break; 268 } 269 270 switch (IFM_SUBTYPE(ife->ifm_media)) { 271 case IFM_AUTO: 272 /* 273 * If we're already in auto mode, just return. 274 */ 275 if (sc->mii_flags & MIIF_DOINGAUTO) { 276 return (0); 277 } 278 e1000phy_reset(sc); 279 e1000phy_mii_phy_auto(sc, 1); 280 break; 281 282 case IFM_1000_SX: 283 e1000phy_reset(sc); 284 285 PHY_WRITE(sc, E1000_CR, 286 E1000_CR_FULL_DUPLEX | E1000_CR_SPEED_1000); 287 PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD); 288 break; 289 290 case IFM_1000_T: 291 if (sc->mii_flags & MIIF_DOINGAUTO) 292 return (0); 293 294 e1000phy_reset(sc); 295 296 /* TODO - any other way to force 1000BT? */ 297 e1000phy_mii_phy_auto(sc, 1); 298 break; 299 300 case IFM_100_TX: 301 e1000phy_reset(sc); 302 303 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 304 PHY_WRITE(sc, E1000_CR, 305 E1000_CR_FULL_DUPLEX | E1000_CR_SPEED_100); 306 PHY_WRITE(sc, E1000_AR, E1000_AR_100TX_FD); 307 } else { 308 PHY_WRITE(sc, E1000_CR, E1000_CR_SPEED_100); 309 PHY_WRITE(sc, E1000_AR, E1000_AR_100TX); 310 } 311 break; 312 313 case IFM_10_T: 314 e1000phy_reset(sc); 315 316 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 317 PHY_WRITE(sc, E1000_CR, 318 E1000_CR_FULL_DUPLEX | E1000_CR_SPEED_10); 319 PHY_WRITE(sc, E1000_AR, E1000_AR_10T_FD); 320 } else { 321 PHY_WRITE(sc, E1000_CR, E1000_CR_SPEED_10); 322 PHY_WRITE(sc, E1000_AR, E1000_AR_10T); 323 } 324 325 break; 326 327 default: 328 return (EINVAL); 329 } 330 331 break; 332 333 case MII_TICK: 334 /* 335 * If we're not currently selected, just return. 336 */ 337 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 338 return (0); 339 } 340 341 /* 342 * Is the interface even up? 343 */ 344 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) { 345 return (0); 346 } 347 348 /* 349 * Only used for autonegotiation. 350 */ 351 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 352 break; 353 } 354 355 /* 356 * Check to see if we have link. If we do, we don't 357 * need to restart the autonegotiation process. Read 358 * the BMSR twice in case it's latched. 359 */ 360 reg = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR); 361 if (reg & E1000_SR_LINK_STATUS) 362 break; 363 364 /* 365 * Only retry autonegotiation every mii_anegticks seconds. 366 */ 367 if (++(sc->mii_ticks) != sc->mii_anegticks) { 368 return (0); 369 } 370 sc->mii_ticks = 0; 371 372 e1000phy_reset(sc); 373 374 if (e1000phy_mii_phy_auto(sc, 0) == EJUSTRETURN) { 375 return (0); 376 } 377 378 break; 379 } 380 381 /* Update the media status. */ 382 e1000phy_status(sc); 383 384 /* Callback if something changed. */ 385 mii_phy_update(sc, cmd); 386 return (0); 387 } 388 389 static void 390 e1000phy_status(struct mii_softc *sc) 391 { 392 struct mii_data *mii = sc->mii_pdata; 393 int bmsr, bmcr, esr, ssr, isr, ar, lpar; 394 395 mii->mii_media_status = IFM_AVALID; 396 mii->mii_media_active = IFM_ETHER; 397 398 bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR); 399 esr = PHY_READ(sc, E1000_ESR); 400 bmcr = PHY_READ(sc, E1000_CR); 401 ssr = PHY_READ(sc, E1000_SSR); 402 isr = PHY_READ(sc, E1000_ISR); 403 ar = PHY_READ(sc, E1000_AR); 404 lpar = PHY_READ(sc, E1000_LPAR); 405 406 if (bmsr & E1000_SR_LINK_STATUS) 407 mii->mii_media_status |= IFM_ACTIVE; 408 409 if (bmcr & E1000_CR_LOOPBACK) 410 mii->mii_media_active |= IFM_LOOP; 411 412 if ((sc->mii_flags & MIIF_DOINGAUTO) && 413 (!(bmsr & E1000_SR_AUTO_NEG_COMPLETE) || !(ssr & E1000_SSR_LINK) || 414 !(ssr & E1000_SSR_SPD_DPLX_RESOLVED))) { 415 /* Erg, still trying, I guess... */ 416 mii->mii_media_active |= IFM_NONE; 417 return; 418 } 419 420 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 421 if (ssr & E1000_SSR_1000MBS) 422 mii->mii_media_active |= IFM_1000_T; 423 else if (ssr & E1000_SSR_100MBS) 424 mii->mii_media_active |= IFM_100_TX; 425 else 426 mii->mii_media_active |= IFM_10_T; 427 } else { 428 if (ssr & E1000_SSR_1000MBS) 429 mii->mii_media_active |= IFM_1000_SX; 430 } 431 432 if (ssr & E1000_SSR_DUPLEX) 433 mii->mii_media_active |= IFM_FDX; 434 else 435 mii->mii_media_active |= IFM_HDX; 436 437 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 438 /* FLAG0==rx-flow-control FLAG1==tx-flow-control */ 439 if ((ar & E1000_AR_PAUSE) && (lpar & E1000_LPAR_PAUSE)) { 440 mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1; 441 } else if (!(ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) && 442 (lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) { 443 mii->mii_media_active |= IFM_FLAG1; 444 } else if ((ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) && 445 !(lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) { 446 mii->mii_media_active |= IFM_FLAG0; 447 } 448 } 449 } 450 451 static int 452 e1000phy_mii_phy_auto(struct mii_softc *sc, int waitfor) 453 { 454 int bmsr, i; 455 456 if ((sc->mii_flags & MIIF_DOINGAUTO) == 0) { 457 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 458 PHY_WRITE(sc, E1000_AR, E1000_AR_10T | E1000_AR_10T_FD | 459 E1000_AR_100TX | E1000_AR_100TX_FD | 460 E1000_AR_PAUSE | E1000_AR_ASM_DIR); 461 PHY_WRITE(sc, E1000_1GCR, E1000_1GCR_1000T_FD); 462 } else { 463 PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | 464 E1000_FA_SYM_PAUSE | E1000_FA_ASYM_PAUSE); 465 } 466 PHY_WRITE(sc, E1000_CR, 467 E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG); 468 } 469 470 if (waitfor) { 471 /* Wait 5 seconds for it to complete. */ 472 for (i = 0; i < 5000; i++) { 473 bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR); 474 475 if (bmsr & E1000_SR_AUTO_NEG_COMPLETE) { 476 return (0); 477 } 478 DELAY(1000); 479 } 480 481 /* 482 * Don't need to worry about clearing MIIF_DOINGAUTO. 483 * If that's set, a timeout is pending, and it will 484 * clear the flag. [do it anyway] 485 */ 486 return (EIO); 487 } 488 489 /* 490 * Just let it finish asynchronously. This is for the benefit of 491 * the tick handler driving autonegotiation. Don't want 500ms 492 * delays all the time while the system is running! 493 */ 494 if (sc->mii_flags & MIIF_AUTOTSLEEP) { 495 sc->mii_flags |= MIIF_DOINGAUTO; 496 tsleep(&sc->mii_flags, 0, "miiaut", hz >> 1); 497 mii_phy_auto_timeout(sc); 498 } else if ((sc->mii_flags & MIIF_DOINGAUTO) == 0) { 499 sc->mii_flags |= MIIF_DOINGAUTO; 500 callout_reset(&sc->mii_auto_ch, 5 * hz, 501 mii_phy_auto_timeout, sc); 502 } 503 return (EJUSTRETURN); 504 } 505