xref: /dragonfly/sys/dev/netif/mii_layer/qsphyreg.h (revision 36a3d1d6)
1 /*	OpenBSD: qsphyreg.h,v 1.2 1999/03/09 00:02:45 jason Exp 	*/
2 /*	NetBSD: qsphyreg.h,v 1.1 1998/08/11 00:01:03 thorpej Exp 	*/
3 /*	$FreeBSD: src/sys/dev/mii/qsphyreg.h,v 1.1.2.1 2001/06/08 19:58:33 semenu Exp $	*/
4 /*	$DragonFly: src/sys/dev/netif/mii_layer/qsphyreg.h,v 1.2 2003/06/17 04:28:28 dillon Exp $	*/
5 
6 /*-
7  * Copyright (c) 1998 The NetBSD Foundation, Inc.
8  * All rights reserved.
9  *
10  * This code is derived from software contributed to The NetBSD Foundation
11  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
12  * NASA Ames Research Center.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions
16  * are met:
17  * 1. Redistributions of source code must retain the above copyright
18  *    notice, this list of conditions and the following disclaimer.
19  * 2. Redistributions in binary form must reproduce the above copyright
20  *    notice, this list of conditions and the following disclaimer in the
21  *    documentation and/or other materials provided with the distribution.
22  * 3. All advertising materials mentioning features or use of this software
23  *    must display the following acknowledgement:
24  *	This product includes software developed by the NetBSD
25  *	Foundation, Inc. and its contributors.
26  * 4. Neither the name of The NetBSD Foundation nor the names of its
27  *    contributors may be used to endorse or promote products derived
28  *    from this software without specific prior written permission.
29  *
30  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
31  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
32  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
33  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
34  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
35  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
36  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
37  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
38  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
39  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40  * POSSIBILITY OF SUCH DAMAGE.
41  */
42 
43 #ifndef _DEV_MII_QSPHYREG_H_
44 #define	_DEV_MII_QSPHYREG_H_
45 
46 /*
47  * Register definitions for the Quality Semiconductor QS6612
48  * Further documentation can be found at:
49  * 	http://www.qualitysemi.com/products/network.html
50  */
51 
52 #define	MII_QSPHY_MCTL		0x11	/* Mode control */
53 #define	MCTL_T4PRE		0x1000	/* 100baseT4 interface present */
54 #define	MCTL_BTEXT		0x0800	/* reduce 10baseT squelch level */
55 #define	MCTL_FACTTEST		0x0100	/* factory test mode */
56 #define	MCTL_PHYADDRMASK	0x00f8	/* PHY address */
57 #define	MCTL_FACTTEST2		0x0004	/* another factory test mode */
58 #define	MCTL_NLPDIS		0x0002	/* disable link pulse tx */
59 #define	MCTL_SQEDIS		0x0001	/* disable SQE */
60 
61 #define	MII_QSPHY_ISRC		0x1d	/* Interrupt source */
62 #define	MII_QSPHY_IMASK		0x1e	/* Interrupt mask */
63 #define	IMASK_TLINTR		0x8000	/* ThunderLAN interrupt mode */
64 #define	IMASK_ANCPL		0x0040	/* autonegotiation complete */
65 #define	IMASK_RFD		0x0020	/* remote fault detected */
66 #define	IMASK_LD		0x0010	/* link down */
67 #define	IMASK_ANLPA		0x0008	/* autonegotiation LP ACK */
68 #define	IMASK_PDT		0x0004	/* parallel detection fault */
69 #define	IMASK_ANPR		0x0002	/* autonegotiation page received */
70 #define	IMASK_REF		0x0001	/* receive error counter full */
71 
72 #define	MII_QSPHY_PCTL		0x1f	/* PHY control */
73 #define	PCTL_RXERDIS		0x2000	/* receive error counter disable */
74 #define	PCTL_ANC		0x1000	/* autonegotiation complete */
75 #define	PCTL_RLBEN		0x0200	/* remote coopback enable */
76 #define	PCTL_DCREN		0x0100	/* DC restoration enable */
77 #define	PCTL_4B5BEN		0x0040	/* 4b/5b encoding */
78 #define	PCTL_PHYISO		0x0020	/* isolate PHY */
79 #define	PCTL_OPMASK		0x001c	/* operation mode mask */
80 #define	PCTL_AN			0x0000	/* autonegotiation in-progress */
81 #define	PCTL_10_T		0x0004	/* 10baseT */
82 #define	PCTL_100_TX		0x0008	/* 100baseTX */
83 #define	PCTL_100_T4		0x0010	/* 100baseT4 */
84 #define	PCTL_10_T_FDX		0x0014	/* 10baseT-FDX */
85 #define	PCTL_100_TX_FDX		0x0018	/* 100baseTX-FDX */
86 #define	PCTL_MLT3DIS		0x0002	/* disable MLT3 */
87 #define	PCTL_SRCDIS		0x0001	/* disable scrambling */
88 
89 #endif /* _DEV_MII_QSPHYREG_H_ */
90