1 /* $OpenBSD: rgephy.c,v 1.12 2006/06/27 05:36:58 brad Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/mii/rgephy.c,v 1.7 2005/09/30 19:39:27 imp Exp $ 35 */ 36 37 /* 38 * Driver for the RealTek 8211B/8169S/8110S internal 10/100/1000 PHY. 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/module.h> 45 #include <sys/socket.h> 46 #include <sys/bus.h> 47 48 #include <machine/clock.h> 49 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_media.h> 53 54 #include <dev/netif/mii_layer/mii.h> 55 #include <dev/netif/mii_layer/miivar.h> 56 57 #include <dev/netif/re/if_rereg.h> 58 #include <dev/netif/mii_layer/rgephyreg.h> 59 60 #include "miibus_if.h" 61 #include "miidevs.h" 62 63 static int rgephy_probe(device_t); 64 static int rgephy_attach(device_t); 65 66 static device_method_t rgephy_methods[] = { 67 /* device interface */ 68 DEVMETHOD(device_probe, rgephy_probe), 69 DEVMETHOD(device_attach, rgephy_attach), 70 DEVMETHOD(device_detach, ukphy_detach), 71 DEVMETHOD(device_shutdown, bus_generic_shutdown), 72 DEVMETHOD_END 73 }; 74 75 static const struct mii_phydesc rgephys[] = { 76 MII_PHYDESC(REALTEK2, RTL8169S), 77 MII_PHYDESC(xxREALTEK, RTL8169S), 78 MII_PHYDESC(xxREALTEK, RTL8251), 79 MII_PHYDESC_NULL 80 }; 81 82 static devclass_t rgephy_devclass; 83 84 static driver_t rgephy_driver = { 85 "rgephy", 86 rgephy_methods, 87 sizeof(struct mii_softc) 88 }; 89 90 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, NULL, NULL); 91 92 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 93 static void rgephy_status(struct mii_softc *); 94 static int rgephy_mii_phy_auto(struct mii_softc *); 95 static void rgephy_reset(struct mii_softc *); 96 static void rgephy_loop(struct mii_softc *); 97 static void rgephy_load_dspcode(struct mii_softc *); 98 99 static int 100 rgephy_probe(device_t dev) 101 { 102 struct mii_attach_args *ma = device_get_ivars(dev); 103 const struct mii_phydesc *mpd; 104 105 mpd = mii_phy_match(ma, rgephys); 106 if (mpd != NULL) { 107 device_set_desc(dev, mpd->mpd_name); 108 if (bootverbose) 109 device_printf(dev, "rev: %d\n", MII_REV(ma->mii_id2)); 110 return (0); 111 } 112 return(ENXIO); 113 } 114 115 static int 116 rgephy_attach(device_t dev) 117 { 118 struct mii_softc *sc; 119 struct mii_attach_args *ma; 120 struct mii_data *mii; 121 122 sc = device_get_softc(dev); 123 ma = device_get_ivars(dev); 124 mii_softc_init(sc, ma); 125 sc->mii_dev = device_get_parent(dev); 126 127 mii = device_get_softc(sc->mii_dev); 128 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 129 130 sc->mii_inst = mii->mii_instance; 131 sc->mii_service = rgephy_service; 132 sc->mii_reset = rgephy_reset; 133 sc->mii_pdata = mii; 134 135 sc->mii_flags |= MIIF_NOISOLATE; 136 mii->mii_instance++; 137 138 rgephy_reset(sc); 139 140 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 141 if (sc->mii_capabilities & BMSR_EXTSTAT) 142 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 143 144 device_printf(dev, " "); 145 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 && 146 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) 147 kprintf("no media present"); 148 else 149 mii_phy_add_media(sc); 150 kprintf("\n"); 151 152 MIIBUS_MEDIAINIT(sc->mii_dev); 153 return(0); 154 } 155 156 static int 157 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 158 { 159 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 160 int reg, speed, gig; 161 uint16_t id2; 162 163 switch (cmd) { 164 case MII_POLLSTAT: 165 /* 166 * If we're not polling our PHY instance, just return. 167 */ 168 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 169 return (0); 170 break; 171 172 case MII_MEDIACHG: 173 /* 174 * If the media indicates a different PHY instance, 175 * isolate ourselves. 176 */ 177 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 178 reg = PHY_READ(sc, MII_BMCR); 179 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 180 return (0); 181 } 182 183 /* 184 * If the interface is not up, don't do anything. 185 */ 186 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 187 break; 188 189 rgephy_reset(sc); /* XXX hardware bug work-around */ 190 191 switch (IFM_SUBTYPE(ife->ifm_media)) { 192 case IFM_AUTO: 193 #ifdef foo 194 /* 195 * If we're already in auto mode, just return. 196 */ 197 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 198 return (0); 199 #endif 200 rgephy_mii_phy_auto(sc); 201 break; 202 case IFM_1000_T: 203 speed = RGEPHY_S1000; 204 goto setit; 205 case IFM_100_TX: 206 speed = RGEPHY_S100; 207 goto setit; 208 case IFM_10_T: 209 speed = RGEPHY_S10; 210 setit: 211 rgephy_loop(sc); 212 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 213 speed |= RGEPHY_BMCR_FDX; 214 gig = RGEPHY_1000CTL_AFD; 215 } else { 216 gig = RGEPHY_1000CTL_AHD; 217 } 218 219 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0); 220 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed); 221 PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE); 222 223 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 224 break; 225 226 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 227 PHY_WRITE(sc, RGEPHY_MII_BMCR, 228 speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG); 229 230 /* 231 * When settning the link manually, one side must 232 * be the master and the other the slave. However 233 * ifmedia doesn't give us a good way to specify 234 * this, so we fake it by using one of the LINK 235 * flags. If LINK0 is set, we program the PHY to 236 * be a master, otherwise it's a slave. 237 */ 238 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 239 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 240 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC); 241 } else { 242 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 243 gig|RGEPHY_1000CTL_MSE); 244 } 245 break; 246 #ifdef foo 247 case IFM_NONE: 248 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 249 break; 250 #endif 251 case IFM_100_T4: 252 default: 253 return (EINVAL); 254 } 255 break; 256 257 case MII_TICK: 258 /* 259 * If we're not currently selected, just return. 260 */ 261 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 262 return (0); 263 264 /* 265 * Is the interface even up? 266 */ 267 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 268 return (0); 269 270 /* 271 * Only used for autonegotiation. 272 */ 273 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 274 break; 275 276 /* 277 * Check to see if we have link. If we do, we don't 278 * need to restart the autonegotiation process. 279 * 280 * XXX Read the BMSR twice in case it's latched? 281 */ 282 id2 = PHY_READ(sc, MII_PHYIDR2); 283 284 if (MII_REV(id2) < 2) { 285 reg = PHY_READ(sc, RE_GMEDIASTAT); 286 if (reg & RE_GMEDIASTAT_LINK) { 287 sc->mii_ticks = 0; 288 break; 289 } 290 } else { 291 reg = PHY_READ(sc, RGEPHY_SR); 292 if (reg & RGEPHY_SR_LINK) { 293 sc->mii_ticks = 0; 294 break; 295 } 296 } 297 298 /* 299 * Only retry autonegotiation every mii_anegticks seconds. 300 */ 301 if (++sc->mii_ticks <= sc->mii_anegticks) 302 break; 303 304 sc->mii_ticks = 0; 305 306 /* 307 * Although rgephy_mii_phy_auto() always returns EJUSTRETURN, 308 * we should not rely on that. 309 */ 310 if (rgephy_mii_phy_auto(sc) == EJUSTRETURN) 311 return (0); 312 break; 313 } 314 315 /* Update the media status. */ 316 rgephy_status(sc); 317 318 /* 319 * Callback if something changed. Note that we need to poke 320 * the DSP on the RealTek PHYs if the media changes. 321 */ 322 if (sc->mii_media_active != mii->mii_media_active || 323 sc->mii_media_status != mii->mii_media_status || 324 cmd == MII_MEDIACHG) 325 rgephy_load_dspcode(sc); 326 mii_phy_update(sc, cmd); 327 return (0); 328 } 329 330 static void 331 rgephy_status(struct mii_softc *sc) 332 { 333 struct mii_data *mii = sc->mii_pdata; 334 int bmsr, bmcr; 335 uint16_t id2; 336 337 mii->mii_media_status = IFM_AVALID; 338 mii->mii_media_active = IFM_ETHER; 339 340 id2 = PHY_READ(sc, MII_PHYIDR2); 341 342 if (MII_REV(id2) < 2) { 343 bmsr = PHY_READ(sc, RE_GMEDIASTAT); 344 if (bmsr & RE_GMEDIASTAT_LINK) 345 mii->mii_media_status |= IFM_ACTIVE; 346 } else { 347 bmsr = PHY_READ(sc, RGEPHY_SR); 348 if (bmsr & RGEPHY_SR_LINK) 349 mii->mii_media_status |= IFM_ACTIVE; 350 } 351 352 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 353 354 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 355 356 if (bmcr & RGEPHY_BMCR_LOOP) 357 mii->mii_media_active |= IFM_LOOP; 358 359 if (bmcr & RGEPHY_BMCR_AUTOEN) { 360 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 361 /* Erg, still trying, I guess... */ 362 mii->mii_media_active |= IFM_NONE; 363 return; 364 } 365 } 366 367 if (MII_REV(id2) < 2) { 368 bmsr = PHY_READ(sc, RE_GMEDIASTAT); 369 if (bmsr & RE_GMEDIASTAT_1000MBPS) 370 mii->mii_media_active |= IFM_1000_T; 371 else if (bmsr & RE_GMEDIASTAT_100MBPS) 372 mii->mii_media_active |= IFM_100_TX; 373 else if (bmsr & RE_GMEDIASTAT_10MBPS) 374 mii->mii_media_active |= IFM_10_T; 375 else 376 mii->mii_media_active |= IFM_NONE; 377 if (bmsr & RE_GMEDIASTAT_FDX) 378 mii->mii_media_active |= IFM_FDX; 379 } else { 380 bmsr = PHY_READ(sc, RGEPHY_SR); 381 if (RGEPHY_SR_SPEED(bmsr) == 2) 382 mii->mii_media_active |= IFM_1000_T; 383 else if (RGEPHY_SR_SPEED(bmsr) == 1) 384 mii->mii_media_active |= IFM_100_TX; 385 else if (RGEPHY_SR_SPEED(bmsr) == 0) 386 mii->mii_media_active |= IFM_10_T; 387 else 388 mii->mii_media_active |= IFM_NONE; 389 if (bmsr & RGEPHY_SR_FDX) 390 mii->mii_media_active |= IFM_FDX; 391 } 392 } 393 394 static int 395 rgephy_mii_phy_auto(struct mii_softc *sc) 396 { 397 uint16_t id2; 398 399 id2 = PHY_READ(sc, MII_PHYIDR2); 400 if (MII_REV(id2) < 2) { 401 rgephy_loop(sc); 402 rgephy_reset(sc); 403 } 404 405 PHY_WRITE(sc, RGEPHY_MII_ANAR, 406 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA); 407 DELAY(1000); 408 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 409 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD); 410 DELAY(1000); 411 PHY_WRITE(sc, RGEPHY_MII_BMCR, 412 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 413 DELAY(100); 414 415 return (EJUSTRETURN); 416 } 417 418 static void 419 rgephy_loop(struct mii_softc *sc) 420 { 421 uint32_t bmsr; 422 int i; 423 uint16_t id2; 424 425 id2 = PHY_READ(sc, MII_PHYIDR2); 426 if (MII_MODEL(id2) != MII_MODEL_xxREALTEK_RTL8251 && 427 MII_REV(id2) < 2) { 428 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 429 DELAY(1000); 430 } 431 432 for (i = 0; i < 15000; i++) { 433 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 434 if (!(bmsr & RGEPHY_BMSR_LINK)) { 435 #if 0 436 device_printf(sc->mii_dev, "looped %d\n", i); 437 #endif 438 break; 439 } 440 DELAY(10); 441 } 442 } 443 444 #define PHY_SETBIT(x, y, z) \ 445 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 446 #define PHY_CLRBIT(x, y, z) \ 447 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 448 449 /* 450 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 451 * existing revisions of the 8169S/8110S chips need to be tuned in 452 * order to reliably negotiate a 1000Mbps link. This is only needed 453 * for rev 0 and rev 1 of the PHY. Later versions work without 454 * any fixups. 455 */ 456 static void 457 rgephy_load_dspcode(struct mii_softc *sc) 458 { 459 int val; 460 461 if (sc->mii_model == MII_MODEL_xxREALTEK_RTL8251 || sc->mii_rev > 1) 462 return; 463 464 PHY_WRITE(sc, 31, 0x0001); 465 PHY_WRITE(sc, 21, 0x1000); 466 PHY_WRITE(sc, 24, 0x65C7); 467 PHY_CLRBIT(sc, 4, 0x0800); 468 val = PHY_READ(sc, 4) & 0xFFF; 469 PHY_WRITE(sc, 4, val); 470 PHY_WRITE(sc, 3, 0x00A1); 471 PHY_WRITE(sc, 2, 0x0008); 472 PHY_WRITE(sc, 1, 0x1020); 473 PHY_WRITE(sc, 0, 0x1000); 474 PHY_SETBIT(sc, 4, 0x0800); 475 PHY_CLRBIT(sc, 4, 0x0800); 476 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 477 PHY_WRITE(sc, 4, val); 478 PHY_WRITE(sc, 3, 0xFF41); 479 PHY_WRITE(sc, 2, 0xDE60); 480 PHY_WRITE(sc, 1, 0x0140); 481 PHY_WRITE(sc, 0, 0x0077); 482 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 483 PHY_WRITE(sc, 4, val); 484 PHY_WRITE(sc, 3, 0xDF01); 485 PHY_WRITE(sc, 2, 0xDF20); 486 PHY_WRITE(sc, 1, 0xFF95); 487 PHY_WRITE(sc, 0, 0xFA00); 488 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 489 PHY_WRITE(sc, 4, val); 490 PHY_WRITE(sc, 3, 0xFF41); 491 PHY_WRITE(sc, 2, 0xDE20); 492 PHY_WRITE(sc, 1, 0x0140); 493 PHY_WRITE(sc, 0, 0x00BB); 494 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 495 PHY_WRITE(sc, 4, val); 496 PHY_WRITE(sc, 3, 0xDF01); 497 PHY_WRITE(sc, 2, 0xDF20); 498 PHY_WRITE(sc, 1, 0xFF95); 499 PHY_WRITE(sc, 0, 0xBF00); 500 PHY_SETBIT(sc, 4, 0x0800); 501 PHY_CLRBIT(sc, 4, 0x0800); 502 PHY_WRITE(sc, 31, 0x0000); 503 504 DELAY(40); 505 } 506 507 static void 508 rgephy_reset(struct mii_softc *sc) 509 { 510 uint16_t id2; 511 512 mii_phy_reset(sc); 513 514 id2 = PHY_READ(sc, MII_PHYIDR2); 515 if (MII_REV(id2) < 2) { 516 DELAY(1000); 517 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_AUTOEN); 518 DELAY(1000); 519 } 520 rgephy_load_dspcode(sc); 521 } 522