1 /* 2 * ---------------------------------------------------------------------------- 3 * "THE BEER-WARE LICENSE" (Revision 42): 4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you 5 * can do whatever you want with this stuff. If we meet some day, and you think 6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp 7 * ---------------------------------------------------------------------------- 8 * 9 * $Id: if_mn.c,v 1.1 1999/02/01 13:06:40 phk Exp $ 10 * 11 * Driver for Siemens reference design card "Easy321-R1". 12 * 13 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC 14 * controller. 15 * 16 * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't 17 * check it coming in. 18 * 19 * The FALC54 and MUNICH32X have far too many registers and weird modes for 20 * comfort, so I have not bothered typing it all into a "fooreg.h" file, 21 * you will (badly!) need the documentation anyway if you want to mess with 22 * this gadget. 23 * 24 * $FreeBSD: src/sys/pci/if_mn.c,v 1.11.2.3 2001/01/23 12:47:09 phk Exp $ 25 * $DragonFly: src/sys/dev/netif/mn/if_mn.c,v 1.7 2004/09/14 23:49:51 joerg Exp $ 26 */ 27 28 /* 29 * Stuff to describe the MUNIC32X and FALC54 chips. 30 */ 31 32 #define M32_CHAN 32 /* We have 32 channels */ 33 #define M32_TS 32 /* We have 32 timeslots */ 34 35 #define NG_MN_NODE_TYPE "mn" 36 37 #include <sys/param.h> 38 #include <sys/kernel.h> 39 #include <sys/sysctl.h> 40 #include <sys/bus.h> 41 #include <sys/mbuf.h> 42 #include <sys/systm.h> 43 #include <sys/malloc.h> 44 45 #include <bus/pci/pcireg.h> 46 #include <bus/pci/pcivar.h> 47 #include "pci_if.h" 48 49 #include <machine/bus.h> 50 #include <machine/resource.h> 51 #include <machine/clock.h> 52 53 #include <sys/rman.h> 54 55 #include <vm/vm.h> 56 #include <vm/pmap.h> 57 58 #include <netgraph/ng_message.h> 59 #include <netgraph/netgraph.h> 60 61 62 static int mn_maxlatency = 1000; 63 SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW, 64 &mn_maxlatency, 0, 65 "The number of milliseconds a packet is allowed to spend in the output queue. " 66 "If the output queue is longer than this number of milliseconds when the packet " 67 "arrives for output, the packet will be dropped." 68 ); 69 70 #ifndef NMN 71 /* Most machines don't support more than 4 busmaster PCI slots, if even that many */ 72 #define NMN 4 73 #endif 74 75 /* From: PEB 20321 data sheet, p187, table 22 */ 76 struct m32xreg { 77 u_int32_t conf, cmd, stat, imask; 78 u_int32_t fill10, piqba, piql, fill1c; 79 u_int32_t mode1, mode2, ccba, txpoll; 80 u_int32_t tiqba, tiql, riqba, riql; 81 u_int32_t lconf, lccba, fill48, ltran; 82 u_int32_t ltiqba, ltiql, lriqba, lriql; 83 u_int32_t lreg0, lreg1, lreg2, lreg3; 84 u_int32_t lreg4, lreg5, lre6, lstat; 85 u_int32_t gpdir, gpdata, gpod, fill8c; 86 u_int32_t ssccon, sscbr, ssctb, sscrb; 87 u_int32_t ssccse, sscim, fillab, fillac; 88 u_int32_t iomcon1, iomcon2, iomstat, fillbc; 89 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1; 90 u_int32_t iomtmo, iomrmo, filld8, filldc; 91 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3; 92 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7; 93 }; 94 95 /* From: PEB 2254 data sheet, p80, table 10 */ 96 struct f54wreg { 97 u_int16_t xfifo; 98 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2; 99 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 100 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 101 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 102 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 103 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3; 104 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 105 u_int8_t lim2, fill39[7]; 106 u_int8_t fill40[8]; 107 u_int8_t fill48[8]; 108 u_int8_t fill50[8]; 109 u_int8_t fill58[8]; 110 u_int8_t dec, fill61, test2, fill63[5]; 111 u_int8_t fill68[8]; 112 u_int8_t xs[16]; 113 }; 114 115 /* From: PEB 2254 data sheet, p117, table 10 */ 116 struct f54rreg { 117 u_int16_t rfifo; 118 u_int8_t fill2, mode, rah1, rah2, ral1, ral2; 119 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 120 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 121 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 122 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 123 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13; 124 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 125 u_int8_t lim2, fill39[7]; 126 u_int8_t fill40[8]; 127 u_int8_t fill48[4], frs0, frs1, rsw, rsp; 128 u_int16_t fec, cvc, cec1, ebc; 129 u_int16_t cec2, cec3; 130 u_int8_t rsa4, rsa5, rsa6, rsa7; 131 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis; 132 u_int16_t rbc; 133 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr; 134 u_int8_t rs[16]; 135 }; 136 137 /* Transmit & receive descriptors */ 138 struct trxd { 139 u_int32_t flags; 140 vm_offset_t next; 141 vm_offset_t data; 142 u_int32_t status; /* only used for receive */ 143 struct mbuf *m; /* software use only */ 144 struct trxd *vnext; /* software use only */ 145 }; 146 147 /* Channel specification */ 148 struct cspec { 149 u_int32_t flags; 150 vm_offset_t rdesc; 151 vm_offset_t tdesc; 152 u_int32_t itbs; 153 }; 154 155 struct m32_mem { 156 vm_offset_t csa; 157 u_int32_t ccb; 158 u_int32_t reserve1[2]; 159 u_int32_t ts[M32_TS]; 160 struct cspec cs[M32_CHAN]; 161 vm_offset_t crxd[M32_CHAN]; 162 vm_offset_t ctxd[M32_CHAN]; 163 }; 164 165 struct softc; 166 struct sockaddr; 167 struct rtentry; 168 169 static int mn_probe (device_t self); 170 static int mn_attach (device_t self); 171 static void mn_create_channel(struct softc *sc, int chan); 172 static int mn_reset(struct softc *sc); 173 static struct trxd * mn_alloc_desc(void); 174 static void mn_free_desc(struct trxd *dp); 175 static void mn_intr(void *xsc); 176 static u_int32_t mn_parse_ts(const char *s, int *nbit); 177 #ifdef notyet 178 static void m32_dump(struct softc *sc); 179 static void f54_dump(struct softc *sc); 180 static void mn_fmt_ts(char *p, u_int32_t ts); 181 #endif /* notyet */ 182 static void f54_init(struct softc *sc); 183 184 static ng_constructor_t ngmn_constructor; 185 static ng_rcvmsg_t ngmn_rcvmsg; 186 static ng_shutdown_t ngmn_shutdown; 187 static ng_newhook_t ngmn_newhook; 188 static ng_connect_t ngmn_connect; 189 static ng_rcvdata_t ngmn_rcvdata; 190 static ng_disconnect_t ngmn_disconnect; 191 192 static struct ng_type mntypestruct = { 193 NG_VERSION, 194 NG_MN_NODE_TYPE, 195 NULL, 196 ngmn_constructor, 197 ngmn_rcvmsg, 198 ngmn_shutdown, 199 ngmn_newhook, 200 NULL, 201 ngmn_connect, 202 ngmn_rcvdata, 203 ngmn_rcvdata, 204 ngmn_disconnect, 205 NULL 206 }; 207 208 static MALLOC_DEFINE(M_MN, "mn", "Mx driver related"); 209 210 #define NIQB 64 211 212 struct schan { 213 enum {DOWN, UP} state; 214 struct softc *sc; 215 int chan; 216 u_int32_t ts; 217 char name[8]; 218 struct trxd *r1, *rl; 219 struct trxd *x1, *xl; 220 hook_p hook; 221 222 time_t last_recv; 223 time_t last_rxerr; 224 time_t last_xmit; 225 226 u_long rx_error; 227 228 u_long short_error; 229 u_long crc_error; 230 u_long dribble_error; 231 u_long long_error; 232 u_long abort_error; 233 u_long overflow_error; 234 235 int last_error; 236 int prev_error; 237 238 u_long tx_pending; 239 u_long tx_limit; 240 }; 241 242 enum framing {WHOKNOWS, E1, E1U, T1, T1U}; 243 244 struct softc { 245 int unit; 246 device_t dev; 247 struct resource *irq; 248 void *intrhand; 249 enum framing framing; 250 int nhooks; 251 void *m0v, *m1v; 252 vm_offset_t m0p, m1p; 253 struct m32xreg *m32x; 254 struct f54wreg *f54w; 255 struct f54rreg *f54r; 256 struct m32_mem m32_mem; 257 u_int32_t tiqb[NIQB]; 258 u_int32_t riqb[NIQB]; 259 u_int32_t piqb[NIQB]; 260 u_int32_t ltiqb[NIQB]; 261 u_int32_t lriqb[NIQB]; 262 char name[8]; 263 u_int32_t falc_irq, falc_state, framer_state; 264 struct schan *ch[M32_CHAN]; 265 char nodename[NG_NODELEN + 1]; 266 node_p node; 267 268 u_long cnt_fec; 269 u_long cnt_cvc; 270 u_long cnt_cec1; 271 u_long cnt_ebc; 272 u_long cnt_cec2; 273 u_long cnt_cec3; 274 u_long cnt_rbc; 275 }; 276 277 static int 278 ngmn_constructor(node_p *nodep) 279 { 280 281 return (EINVAL); 282 } 283 284 static int 285 ngmn_shutdown(node_p nodep) 286 { 287 288 return (EINVAL); 289 } 290 291 static void 292 ngmn_config(node_p node, char *set, char *ret) 293 { 294 struct softc *sc; 295 enum framing wframing; 296 297 sc = node->private; 298 299 if (set != NULL) { 300 if (!strncmp(set, "line ", 5)) { 301 wframing = sc->framing; 302 if (!strcmp(set, "line e1")) { 303 wframing = E1; 304 } else if (!strcmp(set, "line e1u")) { 305 wframing = E1U; 306 } else { 307 strcat(ret, "ENOGROK\n"); 308 return; 309 } 310 if (wframing == sc->framing) 311 return; 312 if (sc->nhooks > 0) { 313 sprintf(ret, "Cannot change line when %d hooks open\n", sc->nhooks); 314 return; 315 } 316 sc->framing = wframing; 317 #if 1 318 f54_init(sc); 319 #else 320 mn_reset(sc); 321 #endif 322 } else { 323 printf("%s CONFIG SET [%s]\n", sc->nodename, set); 324 strcat(ret, "ENOGROK\n"); 325 return; 326 } 327 } 328 329 } 330 331 static int 332 ngmn_rcvmsg(node_p node, struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp) 333 { 334 struct softc *sc; 335 struct schan *sch; 336 char *s, *r; 337 int pos, i; 338 339 sc = node->private; 340 341 if (msg->header.typecookie != NGM_GENERIC_COOKIE) { 342 if (resp != NULL) 343 *resp = NULL; 344 FREE(msg, M_NETGRAPH); 345 return (EINVAL); 346 } 347 348 if (msg->header.cmd != NGM_TEXT_CONFIG && 349 msg->header.cmd != NGM_TEXT_STATUS) { 350 if (resp != NULL) 351 *resp = NULL; 352 FREE(msg, M_NETGRAPH); 353 return (EINVAL); 354 } 355 356 NG_MKRESPONSE(*resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE, 357 M_INTWAIT); 358 if (*resp == NULL) { 359 FREE(msg, M_NETGRAPH); 360 return (ENOMEM); 361 } 362 363 if (msg->header.arglen) 364 s = (char *)msg->data; 365 else 366 s = NULL; 367 r = (char *)(*resp)->data; 368 *r = '\0'; 369 370 if (msg->header.cmd == NGM_TEXT_CONFIG) { 371 ngmn_config(node, s, r); 372 (*resp)->header.arglen = strlen(r) + 1; 373 FREE(msg, M_NETGRAPH); 374 return (0); 375 } 376 377 pos = 0; 378 pos += sprintf(pos + r,"Framer status %b;\n", sc->framer_state, "\20" 379 "\40LOS\37AIS\36LFA\35RRA" 380 "\34AUXP\33NMF\32LMFA\31frs0.0" 381 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 382 "\24TS16LFA\23frs1.2\22XLS\21XLO" 383 "\20RS1\17rsw.6\16RRA\15RY0" 384 "\14RY1\13RY2\12RY3\11RY4" 385 "\10SI1\7SI2\6rsp.5\5rsp.4" 386 "\4rsp.3\3RSIF\2RS13\1RS15"); 387 pos += sprintf(pos + r," Framing errors: %lu", sc->cnt_fec); 388 pos += sprintf(pos + r," Code Violations: %lu\n", sc->cnt_cvc); 389 390 pos += sprintf(pos + r," Falc State %b;\n", sc->falc_state, "\20" 391 "\40LOS\37AIS\36LFA\35RRA" 392 "\34AUXP\33NMF\32LMFA\31frs0.0" 393 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 394 "\24TS16LFA\23frs1.2\22XLS\21XLO" 395 "\20RS1\17rsw.6\16RRA\15RY0" 396 "\14RY1\13RY2\12RY3\11RY4" 397 "\10SI1\7SI2\6rsp.5\5rsp.4" 398 "\4rsp.3\3RSIF\2RS13\1RS15"); 399 pos += sprintf(pos + r, " Falc IRQ %b\n", sc->falc_irq, "\20" 400 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 401 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 402 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 403 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 404 for (i = 0; i < M32_CHAN; i++) { 405 if (!sc->ch[i]) 406 continue; 407 sch = sc->ch[i]; 408 409 pos += sprintf(r + pos, " Chan %d <%s> ", 410 i, sch->hook->name); 411 412 pos += sprintf(r + pos, " Last Rx: "); 413 if (sch->last_recv) 414 pos += sprintf(r + pos, "%lu s", time_second - sch->last_recv); 415 else 416 pos += sprintf(r + pos, "never"); 417 418 pos += sprintf(r + pos, ", last RxErr: "); 419 if (sch->last_rxerr) 420 pos += sprintf(r + pos, "%lu s", time_second - sch->last_rxerr); 421 else 422 pos += sprintf(r + pos, "never"); 423 424 pos += sprintf(r + pos, ", last Tx: "); 425 if (sch->last_xmit) 426 pos += sprintf(r + pos, "%lu s\n", time_second - sch->last_xmit); 427 else 428 pos += sprintf(r + pos, "never\n"); 429 430 pos += sprintf(r + pos, " RX error(s) %lu", sch->rx_error); 431 pos += sprintf(r + pos, " Short: %lu", sch->short_error); 432 pos += sprintf(r + pos, " CRC: %lu", sch->crc_error); 433 pos += sprintf(r + pos, " Mod8: %lu", sch->dribble_error); 434 pos += sprintf(r + pos, " Long: %lu", sch->long_error); 435 pos += sprintf(r + pos, " Abort: %lu", sch->abort_error); 436 pos += sprintf(r + pos, " Overflow: %lu\n", sch->overflow_error); 437 438 pos += sprintf(r + pos, " Last error: %b Prev error: %b\n", 439 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN", 440 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN"); 441 pos += sprintf(r + pos, " Xmit bytes pending %ld\n", 442 sch->tx_pending); 443 } 444 (*resp)->header.arglen = pos + 1; 445 FREE(msg, M_NETGRAPH); 446 return (0); 447 } 448 449 static int 450 ngmn_newhook(node_p node, hook_p hook, const char *name) 451 { 452 u_int32_t ts, chan; 453 struct softc *sc; 454 int nbit; 455 456 sc = node->private; 457 458 if (name[0] != 't' || name[1] != 's') 459 return (EINVAL); 460 461 ts = mn_parse_ts(name + 2, &nbit); 462 printf("%d bits %x\n", nbit, ts); 463 if (sc->framing == E1 && (ts & 1)) 464 return (EINVAL); 465 if (sc->framing == E1U && nbit != 32) 466 return (EINVAL); 467 if (ts == 0) 468 return (EINVAL); 469 if (sc->framing == E1) 470 chan = ffs(ts) - 1; 471 else 472 chan = 1; 473 if (!sc->ch[chan]) 474 mn_create_channel(sc, chan); 475 else if (sc->ch[chan]->state == UP) 476 return (EBUSY); 477 sc->ch[chan]->ts = ts; 478 sc->ch[chan]->hook = hook; 479 sc->ch[chan]->tx_limit = nbit * 8; 480 hook->private = sc->ch[chan]; 481 sc->nhooks++; 482 return(0); 483 } 484 485 486 static struct trxd *mn_desc_free; 487 488 static struct trxd * 489 mn_alloc_desc(void) 490 { 491 struct trxd *dp; 492 493 dp = mn_desc_free; 494 if (dp) 495 mn_desc_free = dp->vnext; 496 else 497 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_INTWAIT); 498 return (dp); 499 } 500 501 static void 502 mn_free_desc(struct trxd *dp) 503 { 504 dp->vnext = mn_desc_free; 505 mn_desc_free = dp; 506 } 507 508 static u_int32_t 509 mn_parse_ts(const char *s, int *nbit) 510 { 511 unsigned r; 512 int i, j; 513 char *p; 514 515 r = 0; 516 j = -1; 517 *nbit = 0; 518 while(*s) { 519 i = strtol(s, &p, 0); 520 if (i < 0 || i > 31) 521 return (0); 522 while (j != -1 && j < i) { 523 r |= 1 << j++; 524 (*nbit)++; 525 } 526 j = -1; 527 r |= 1 << i; 528 (*nbit)++; 529 if (*p == ',') { 530 s = p + 1; 531 continue; 532 } else if (*p == '-') { 533 j = i + 1; 534 s = p + 1; 535 continue; 536 } else if (!*p) { 537 break; 538 } else { 539 return (0); 540 } 541 } 542 return (r); 543 } 544 545 #ifdef notyet 546 static void 547 mn_fmt_ts(char *p, u_int32_t ts) 548 { 549 char *s; 550 int j; 551 552 s = ""; 553 ts &= 0xffffffff; 554 for (j = 0; j < 32; j++) { 555 if (!(ts & (1 << j))) 556 continue; 557 sprintf(p, "%s%d", s, j); 558 p += strlen(p); 559 s = ","; 560 if (!(ts & (1 << (j+1)))) 561 continue; 562 for (; j < 32; j++) 563 if (!(ts & (1 << (j+1)))) 564 break; 565 sprintf(p, "-%d", j); 566 p += strlen(p); 567 s = ","; 568 } 569 } 570 #endif /* notyet */ 571 572 /* 573 * OUTPUT 574 */ 575 576 static int 577 ngmn_rcvdata(hook_p hook, struct mbuf *m, meta_p meta) 578 { 579 struct mbuf *m2; 580 struct trxd *dp, *dp2; 581 struct schan *sch; 582 struct softc *sc; 583 int chan, pitch, len; 584 585 sch = hook->private; 586 sc = sch->sc; 587 chan = sch->chan; 588 589 if (sch->state != UP) { 590 NG_FREE_DATA(m, meta); 591 return (0); 592 } 593 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) { 594 NG_FREE_DATA(m, meta); 595 return (0); 596 } 597 NG_FREE_META(meta); 598 pitch = 0; 599 m2 = m; 600 dp2 = sc->ch[chan]->xl; 601 len = m->m_pkthdr.len; 602 while (len) { 603 dp = mn_alloc_desc(); 604 if (!dp) { 605 pitch++; 606 m_freem(m); 607 sc->ch[chan]->xl = dp2; 608 dp = dp2->vnext; 609 while (dp) { 610 dp2 = dp->vnext; 611 mn_free_desc(dp); 612 dp = dp2; 613 } 614 sc->ch[chan]->xl->vnext = 0; 615 break; 616 } 617 dp->data = vtophys(m2->m_data); 618 dp->flags = m2->m_len << 16; 619 dp->flags += 1; 620 len -= m2->m_len; 621 dp->next = vtophys(dp); 622 dp->vnext = 0; 623 sc->ch[chan]->xl->next = vtophys(dp); 624 sc->ch[chan]->xl->vnext = dp; 625 sc->ch[chan]->xl = dp; 626 if (!len) { 627 dp->m = m; 628 dp->flags |= 0xc0000000; 629 dp2->flags &= ~0x40000000; 630 } else { 631 dp->m = 0; 632 m2 = m2->m_next; 633 } 634 } 635 if (pitch) 636 printf("%s%d: Short on mem, pitched %d packets\n", 637 sc->name, chan, pitch); 638 else { 639 #if 0 640 printf("%d = %d + %d (%p)\n", 641 sch->tx_pending + m->m_pkthdr.len, 642 sch->tx_pending , m->m_pkthdr.len, m); 643 #endif 644 sch->tx_pending += m->m_pkthdr.len; 645 sc->m32x->txpoll &= ~(1 << chan); 646 } 647 return (0); 648 } 649 650 /* 651 * OPEN 652 */ 653 static int 654 ngmn_connect(hook_p hook) 655 { 656 int i, nts, chan; 657 struct trxd *dp, *dp2; 658 struct mbuf *m; 659 struct softc *sc; 660 struct schan *sch; 661 u_int32_t u; 662 663 sch = hook->private; 664 chan = sch->chan; 665 sc = sch->sc; 666 667 if (sch->state == UP) 668 return (0); 669 sch->state = UP; 670 671 /* Count and configure the timeslots for this channel */ 672 for (nts = i = 0; i < 32; i++) 673 if (sch->ts & (1 << i)) { 674 sc->m32_mem.ts[i] = 0x00ff00ff | 675 (chan << 24) | (chan << 8); 676 nts++; 677 } 678 679 /* Init the receiver & xmitter to HDLC */ 680 sc->m32_mem.cs[chan].flags = 0x80e90006; 681 /* Allocate two buffers per timeslot */ 682 if (nts == 32) 683 sc->m32_mem.cs[chan].itbs = 63; 684 else 685 sc->m32_mem.cs[chan].itbs = nts * 2; 686 687 /* Setup a transmit chain with one descriptor */ 688 /* XXX: we actually send a 1 byte packet */ 689 dp = mn_alloc_desc(); 690 MGETHDR(m, MB_WAIT, MT_DATA); 691 if (m == NULL) 692 return (ENOBUFS); 693 m->m_pkthdr.len = 0; 694 dp->m = m; 695 dp->flags = 0xc0000000 + (1 << 16); 696 dp->next = vtophys(dp); 697 dp->vnext = 0; 698 dp->data = vtophys(sc->name); 699 sc->m32_mem.cs[chan].tdesc = vtophys(dp); 700 sc->ch[chan]->x1 = dp; 701 sc->ch[chan]->xl = dp; 702 703 /* Setup a receive chain with 5 + NTS descriptors */ 704 705 dp = mn_alloc_desc(); 706 m = NULL; 707 MGETHDR(m, MB_WAIT, MT_DATA); 708 if (m == NULL) { 709 mn_free_desc(dp); 710 return (ENOBUFS); 711 } 712 MCLGET(m, MB_WAIT); 713 if ((m->m_flags & M_EXT) == 0) { 714 mn_free_desc(dp); 715 m_freem(m); 716 return (ENOBUFS); 717 } 718 dp->m = m; 719 dp->data = vtophys(m->m_data); 720 dp->flags = 0x40000000; 721 dp->flags += 1600 << 16; 722 dp->next = vtophys(dp); 723 dp->vnext = 0; 724 sc->ch[chan]->rl = dp; 725 726 for (i = 0; i < (nts + 10); i++) { 727 dp2 = dp; 728 dp = mn_alloc_desc(); 729 m = NULL; 730 MGETHDR(m, MB_WAIT, MT_DATA); 731 if (m == NULL) { 732 mn_free_desc(dp); 733 m_freem(m); 734 return (ENOBUFS); 735 } 736 MCLGET(m, MB_WAIT); 737 if ((m->m_flags & M_EXT) == 0) { 738 mn_free_desc(dp); 739 m_freem(m); 740 return (ENOBUFS); 741 } 742 dp->m = m; 743 dp->data = vtophys(m->m_data); 744 dp->flags = 0x00000000; 745 dp->flags += 1600 << 16; 746 dp->next = vtophys(dp2); 747 dp->vnext = dp2; 748 } 749 sc->m32_mem.cs[chan].rdesc = vtophys(dp); 750 sc->ch[chan]->r1 = dp; 751 752 /* Initialize this channel */ 753 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 754 sc->m32x->cmd = 0x1; 755 DELAY(1000); 756 u = sc->m32x->stat; 757 if (!(u & 1)) 758 printf("%s: init chan %d stat %08x\n", sc->name, chan, u); 759 sc->m32x->stat = 1; 760 761 return (0); 762 } 763 764 /* 765 * CLOSE 766 */ 767 static int 768 ngmn_disconnect(hook_p hook) 769 { 770 int chan, i; 771 struct softc *sc; 772 struct schan *sch; 773 struct trxd *dp, *dp2; 774 u_int32_t u; 775 776 sch = hook->private; 777 chan = sch->chan; 778 sc = sch->sc; 779 780 if (sch->state == DOWN) 781 return (0); 782 sch->state = DOWN; 783 784 /* Set receiver & transmitter off */ 785 sc->m32_mem.cs[chan].flags = 0x80920006; 786 sc->m32_mem.cs[chan].itbs = 0; 787 788 /* free the timeslots */ 789 for (i = 0; i < 32; i++) 790 if (sc->ch[chan]->ts & (1 << i)) 791 sc->m32_mem.ts[i] = 0x20002000; 792 793 /* Initialize this channel */ 794 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 795 sc->m32x->cmd = 0x1; 796 DELAY(30); 797 u = sc->m32x->stat; 798 if (!(u & 1)) 799 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u); 800 sc->m32x->stat = 1; 801 802 /* Free all receive descriptors and mbufs */ 803 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) { 804 if (dp->m) 805 m_freem(dp->m); 806 sc->ch[chan]->r1 = dp2 = dp->vnext; 807 mn_free_desc(dp); 808 } 809 810 /* Free all transmit descriptors and mbufs */ 811 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) { 812 if (dp->m) { 813 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len; 814 m_freem(dp->m); 815 } 816 sc->ch[chan]->x1 = dp2 = dp->vnext; 817 mn_free_desc(dp); 818 } 819 sc->nhooks--; 820 return(0); 821 } 822 823 /* 824 * Create a new channel. 825 */ 826 static void 827 mn_create_channel(struct softc *sc, int chan) 828 { 829 struct schan *sch; 830 831 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan], 832 M_MN, M_WAITOK | M_ZERO); 833 sch->sc = sc; 834 sch->state = DOWN; 835 sch->chan = chan; 836 sprintf(sch->name, "%s%d", sc->name, chan); 837 return; 838 } 839 840 #ifdef notyet 841 /* 842 * Dump Munich32x state 843 */ 844 static void 845 m32_dump(struct softc *sc) 846 { 847 u_int32_t *tp4; 848 int i, j; 849 850 printf("mn%d: MUNICH32X dump\n", sc->unit); 851 tp4 = (u_int32_t *)sc->m0v; 852 for(j = 0; j < 64; j += 8) { 853 printf("%02x", j * sizeof *tp4); 854 for(i = 0; i < 8; i++) 855 printf(" %08x", tp4[i+j]); 856 printf("\n"); 857 } 858 for(j = 0; j < M32_CHAN; j++) { 859 if (!sc->ch[j]) 860 continue; 861 printf("CH%d: state %d ts %08x", 862 j, sc->ch[j]->state, sc->ch[j]->ts); 863 printf(" %08x %08x %08x %08x %08x %08x\n", 864 sc->m32_mem.cs[j].flags, 865 sc->m32_mem.cs[j].rdesc, 866 sc->m32_mem.cs[j].tdesc, 867 sc->m32_mem.cs[j].itbs, 868 sc->m32_mem.crxd[j], 869 sc->m32_mem.ctxd[j] ); 870 } 871 } 872 873 /* 874 * Dump Falch54 state 875 */ 876 static void 877 f54_dump(struct softc *sc) 878 { 879 u_int8_t *tp1; 880 int i, j; 881 882 printf("%s: FALC54 dump\n", sc->name); 883 tp1 = (u_int8_t *)sc->m1v; 884 for(j = 0; j < 128; j += 16) { 885 printf("%s: %02x |", sc->name, j * sizeof *tp1); 886 for(i = 0; i < 16; i++) 887 printf(" %02x", tp1[i+j]); 888 printf("\n"); 889 } 890 } 891 #endif /* notyet */ 892 893 /* 894 * Init Munich32x 895 */ 896 static void 897 m32_init(struct softc *sc) 898 { 899 900 sc->m32x->conf = 0x00000000; 901 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */ 902 #if 1 903 sc->m32x->mode2 = 0x00000081; 904 sc->m32x->txpoll = 0xffffffff; 905 #elif 1 906 sc->m32x->mode2 = 0x00000081; 907 sc->m32x->txpoll = 0xffffffff; 908 #else 909 sc->m32x->mode2 = 0x00000101; 910 #endif 911 sc->m32x->lconf = 0x6060009B; 912 sc->m32x->imask = 0x00000000; 913 } 914 915 /* 916 * Init the Falc54 917 */ 918 static void 919 f54_init(struct softc *sc) 920 { 921 sc->f54w->ipc = 0x07; 922 923 sc->f54w->xpm0 = 0xbd; 924 sc->f54w->xpm1 = 0x03; 925 sc->f54w->xpm2 = 0x00; 926 927 sc->f54w->imr0 = 0x18; /* RMB, CASC */ 928 sc->f54w->imr1 = 0x08; /* XMB */ 929 sc->f54w->imr2 = 0x00; 930 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */ 931 sc->f54w->imr4 = 0x00; 932 933 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */ 934 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */ 935 if (sc->framing == E1) 936 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */ 937 else if (sc->framing == E1U) 938 sc->f54w->fmr2 = 0x33; /* dais, rtm, Auto Rem-Alarm, Auto resync */ 939 940 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */ 941 sc->f54w->pcd = 0x0a; 942 sc->f54w->pcr = 0x15; 943 sc->f54w->xsw = 0x9f; /* fmr4 */ 944 if (sc->framing == E1) 945 sc->f54w->xsp = 0x1c; /* fmr5 */ 946 else if (sc->framing == E1U) 947 sc->f54w->xsp = 0x3c; /* tt0, fmr5 */ 948 sc->f54w->xc0 = 0x07; 949 sc->f54w->xc1 = 0x3d; 950 sc->f54w->rc0 = 0x05; 951 sc->f54w->rc1 = 0x00; 952 sc->f54w->cmdr = 0x51; 953 } 954 955 static int 956 mn_reset(struct softc *sc) 957 { 958 u_int32_t u; 959 int i; 960 961 sc->m32x->ccba = vtophys(&sc->m32_mem.csa); 962 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb); 963 964 bzero(sc->tiqb, sizeof sc->tiqb); 965 sc->m32x->tiqba = vtophys(&sc->tiqb); 966 sc->m32x->tiql = NIQB / 16 - 1; 967 968 bzero(sc->riqb, sizeof sc->riqb); 969 sc->m32x->riqba = vtophys(&sc->riqb); 970 sc->m32x->riql = NIQB / 16 - 1; 971 972 bzero(sc->ltiqb, sizeof sc->ltiqb); 973 sc->m32x->ltiqba = vtophys(&sc->ltiqb); 974 sc->m32x->ltiql = NIQB / 16 - 1; 975 976 bzero(sc->lriqb, sizeof sc->lriqb); 977 sc->m32x->lriqba = vtophys(&sc->lriqb); 978 sc->m32x->lriql = NIQB / 16 - 1; 979 980 bzero(sc->piqb, sizeof sc->piqb); 981 sc->m32x->piqba = vtophys(&sc->piqb); 982 sc->m32x->piql = NIQB / 16 - 1; 983 984 m32_init(sc); 985 f54_init(sc); 986 987 u = sc->m32x->stat; 988 sc->m32x->stat = u; 989 sc->m32_mem.ccb = 0x4; 990 sc->m32x->cmd = 0x1; 991 DELAY(1000); 992 u = sc->m32x->stat; 993 sc->m32x->stat = u; 994 995 /* set all timeslots to known state */ 996 for (i = 0; i < 32; i++) 997 sc->m32_mem.ts[i] = 0x20002000; 998 999 if (!(u & 1)) { 1000 printf( 1001 "mn%d: WARNING: Controller failed the PCI bus-master test.\n" 1002 "mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n", 1003 sc->unit, sc->unit); 1004 return (0); 1005 } 1006 return (1); 1007 } 1008 1009 /* 1010 * FALC54 interrupt handling 1011 */ 1012 static void 1013 f54_intr(struct softc *sc) 1014 { 1015 unsigned g, u, s; 1016 1017 g = sc->f54r->gis; 1018 u = sc->f54r->isr0 << 24; 1019 u |= sc->f54r->isr1 << 16; 1020 u |= sc->f54r->isr2 << 8; 1021 u |= sc->f54r->isr3; 1022 sc->falc_irq = u; 1023 /* don't chat about the 1 sec heart beat */ 1024 if (u & ~0x40) { 1025 #if 0 1026 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20" 1027 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 1028 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 1029 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 1030 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 1031 #endif 1032 s = sc->f54r->frs0 << 24; 1033 s |= sc->f54r->frs1 << 16; 1034 s |= sc->f54r->rsw << 8; 1035 s |= sc->f54r->rsp; 1036 sc->falc_state = s; 1037 1038 s &= ~0x01844038; /* undefined or static bits */ 1039 s &= ~0x00009fc7; /* bits we don't care about */ 1040 s &= ~0x00780000; /* XXX: TS16 related */ 1041 s &= ~0x06000000; /* XXX: Multiframe related */ 1042 #if 0 1043 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20" 1044 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0" 1045 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO" 1046 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4" 1047 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15"); 1048 #endif 1049 if (s != sc->framer_state) { 1050 #if 0 1051 for (i = 0; i < M32_CHAN; i++) { 1052 if (!sc->ch[i]) 1053 continue; 1054 sp = &sc->ch[i]->ifsppp; 1055 if (!(sp->pp_if.if_flags & IFF_UP)) 1056 continue; 1057 if (s) 1058 timeout((timeout_t *)sp->pp_down, sp, 1 * hz); 1059 else 1060 timeout((timeout_t *)sp->pp_up, sp, 1 * hz); 1061 } 1062 #endif 1063 sc->framer_state = s; 1064 } 1065 } 1066 /* Once per second check error counters */ 1067 /* XXX: not clear if this is actually ok */ 1068 if (!(u & 0x40)) 1069 return; 1070 sc->cnt_fec += sc->f54r->fec; 1071 sc->cnt_cvc += sc->f54r->cvc; 1072 sc->cnt_cec1 += sc->f54r->cec1; 1073 sc->cnt_ebc += sc->f54r->ebc; 1074 sc->cnt_cec2 += sc->f54r->cec2; 1075 sc->cnt_cec3 += sc->f54r->cec3; 1076 sc->cnt_rbc += sc->f54r->rbc; 1077 } 1078 1079 /* 1080 * Transmit interrupt for one channel 1081 */ 1082 static void 1083 mn_tx_intr(struct softc *sc, u_int32_t vector) 1084 { 1085 u_int32_t chan; 1086 struct trxd *dp; 1087 struct mbuf *m; 1088 1089 chan = vector & 0x1f; 1090 if (!sc->ch[chan]) 1091 return; 1092 if (sc->ch[chan]->state != UP) { 1093 printf("%s: tx_intr when not UP\n", sc->name); 1094 return; 1095 } 1096 for (;;) { 1097 dp = sc->ch[chan]->x1; 1098 if (vtophys(dp) == sc->m32_mem.ctxd[chan]) 1099 return; 1100 m = dp->m; 1101 if (m) { 1102 #if 0 1103 printf("%d = %d - %d (%p)\n", 1104 sc->ch[chan]->tx_pending - m->m_pkthdr.len, 1105 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m); 1106 #endif 1107 sc->ch[chan]->tx_pending -= m->m_pkthdr.len; 1108 m_freem(m); 1109 } 1110 sc->ch[chan]->last_xmit = time_second; 1111 sc->ch[chan]->x1 = dp->vnext; 1112 mn_free_desc(dp); 1113 } 1114 } 1115 1116 /* 1117 * Receive interrupt for one channel 1118 */ 1119 static void 1120 mn_rx_intr(struct softc *sc, u_int32_t vector) 1121 { 1122 u_int32_t chan, err; 1123 struct trxd *dp; 1124 struct mbuf *m; 1125 struct schan *sch; 1126 1127 chan = vector & 0x1f; 1128 if (!sc->ch[chan]) 1129 return; 1130 sch = sc->ch[chan]; 1131 if (sch->state != UP) { 1132 printf("%s: rx_intr when not UP\n", sc->name); 1133 return; 1134 } 1135 vector &= ~0x1f; 1136 if (vector == 0x30000b00) 1137 sch->rx_error++; 1138 for (;;) { 1139 dp = sch->r1; 1140 if (vtophys(dp) == sc->m32_mem.crxd[chan]) 1141 return; 1142 m = dp->m; 1143 dp->m = 0; 1144 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff; 1145 err = (dp->status >> 8) & 0xff; 1146 if (!err) { 1147 ng_queue_data(sch->hook, m, NULL); 1148 sch->last_recv = time_second; 1149 m = 0; 1150 /* we could be down by now... */ 1151 if (sch->state != UP) 1152 return; 1153 } else if (err & 0x40) { 1154 sch->short_error++; 1155 } else if (err & 0x10) { 1156 sch->crc_error++; 1157 } else if (err & 0x08) { 1158 sch->dribble_error++; 1159 } else if (err & 0x04) { 1160 sch->long_error++; 1161 } else if (err & 0x02) { 1162 sch->abort_error++; 1163 } else if (err & 0x01) { 1164 sch->overflow_error++; 1165 } 1166 if (err) { 1167 sch->last_rxerr = time_second; 1168 sch->prev_error = sch->last_error; 1169 sch->last_error = err; 1170 } 1171 1172 sc->ch[chan]->r1 = dp->vnext; 1173 1174 /* Replenish desc + mbuf supplies */ 1175 if (!m) { 1176 MGETHDR(m, MB_DONTWAIT, MT_DATA); 1177 if (m == NULL) { 1178 mn_free_desc(dp); 1179 return; /* ENOBUFS */ 1180 } 1181 MCLGET(m, MB_DONTWAIT); 1182 if((m->m_flags & M_EXT) == 0) { 1183 mn_free_desc(dp); 1184 m_freem(m); 1185 return; /* ENOBUFS */ 1186 } 1187 } 1188 dp->m = m; 1189 dp->data = vtophys(m->m_data); 1190 dp->flags = 0x40000000; 1191 dp->flags += 1600 << 16; 1192 dp->next = vtophys(dp); 1193 dp->vnext = 0; 1194 sc->ch[chan]->rl->next = vtophys(dp); 1195 sc->ch[chan]->rl->vnext = dp; 1196 sc->ch[chan]->rl->flags &= ~0x40000000; 1197 sc->ch[chan]->rl = dp; 1198 } 1199 } 1200 1201 1202 /* 1203 * Interupt handler 1204 */ 1205 1206 static void 1207 mn_intr(void *xsc) 1208 { 1209 struct softc *sc; 1210 u_int32_t stat, lstat, u; 1211 int i, j; 1212 1213 sc = xsc; 1214 stat = sc->m32x->stat; 1215 lstat = sc->m32x->lstat; 1216 #if 0 1217 if (!stat && !(lstat & 2)) 1218 return; 1219 #endif 1220 1221 if (stat & ~0xc200) { 1222 printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat); 1223 } 1224 1225 if ((stat & 0x200) || (lstat & 2)) 1226 f54_intr(sc); 1227 1228 for (j = i = 0; i < 64; i ++) { 1229 u = sc->riqb[i]; 1230 if (u) { 1231 sc->riqb[i] = 0; 1232 mn_rx_intr(sc, u); 1233 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00) 1234 continue; 1235 u &= ~0x30000400; /* bits we don't care about */ 1236 if ((u & ~0x1f) == 0x00000900) 1237 continue; 1238 if (!(u & ~0x1f)) 1239 continue; 1240 if (!j) 1241 printf("%s*: RIQB:", sc->name); 1242 printf(" [%d]=%08x", i, u); 1243 j++; 1244 } 1245 } 1246 if (j) 1247 printf("\n"); 1248 1249 for (j = i = 0; i < 64; i ++) { 1250 u = sc->tiqb[i]; 1251 if (u) { 1252 sc->tiqb[i] = 0; 1253 mn_tx_intr(sc, u); 1254 if ((u & ~0x1f) == 0x20000800) 1255 continue; 1256 u &= ~0x20000000; /* bits we don't care about */ 1257 if (!u) 1258 continue; 1259 if (!j) 1260 printf("%s*: TIQB:", sc->name); 1261 printf(" [%d]=%08x", i, u); 1262 j++; 1263 } 1264 } 1265 if (j) 1266 printf("\n"); 1267 sc->m32x->stat = stat; 1268 } 1269 1270 /* 1271 * PCI initialization stuff 1272 */ 1273 1274 static int 1275 mn_probe (device_t self) 1276 { 1277 u_int id = pci_get_devid(self); 1278 1279 if (sizeof (struct m32xreg) != 256) { 1280 printf("MN: sizeof(struct m32xreg) = %d, should have been 256\n", sizeof (struct m32xreg)); 1281 return (ENXIO); 1282 } 1283 if (sizeof (struct f54rreg) != 128) { 1284 printf("MN: sizeof(struct f54rreg) = %d, should have been 128\n", sizeof (struct f54rreg)); 1285 return (ENXIO); 1286 } 1287 if (sizeof (struct f54wreg) != 128) { 1288 printf("MN: sizeof(struct f54wreg) = %d, should have been 128\n", sizeof (struct f54wreg)); 1289 return (ENXIO); 1290 } 1291 1292 if (id != 0x2101110a) 1293 return (ENXIO); 1294 1295 device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller"); 1296 return (0); 1297 } 1298 1299 static int 1300 mn_attach (device_t self) 1301 { 1302 struct softc *sc; 1303 u_int32_t u; 1304 u_int32_t ver; 1305 static int once; 1306 int rid, error; 1307 struct resource *res; 1308 1309 if (!once) { 1310 if (ng_newtype(&mntypestruct)) 1311 printf("ng_newtype failed\n"); 1312 once++; 1313 } 1314 1315 sc = (struct softc *)malloc(sizeof *sc, M_MN, M_WAITOK | M_ZERO); 1316 device_set_softc(self, sc); 1317 1318 sc->dev = self; 1319 sc->unit = device_get_unit(self); 1320 sc->framing = E1; 1321 sprintf(sc->name, "mn%d", sc->unit); 1322 1323 rid = PCIR_MAPS; 1324 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid, 1325 0, ~0, 1, RF_ACTIVE); 1326 if (res == NULL) { 1327 device_printf(self, "Could not map memory\n"); 1328 return ENXIO; 1329 } 1330 sc->m0v = rman_get_virtual(res); 1331 sc->m0p = rman_get_start(res); 1332 1333 rid = PCIR_MAPS + 4; 1334 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid, 1335 0, ~0, 1, RF_ACTIVE); 1336 if (res == NULL) { 1337 device_printf(self, "Could not map memory\n"); 1338 return ENXIO; 1339 } 1340 sc->m1v = rman_get_virtual(res); 1341 sc->m1p = rman_get_start(res); 1342 1343 /* Allocate interrupt */ 1344 rid = 0; 1345 sc->irq = bus_alloc_resource(self, SYS_RES_IRQ, &rid, 0, ~0, 1346 1, RF_SHAREABLE | RF_ACTIVE); 1347 1348 if (sc->irq == NULL) { 1349 printf("couldn't map interrupt\n"); 1350 return(ENXIO); 1351 } 1352 1353 error = bus_setup_intr(self, sc->irq, INTR_TYPE_NET, mn_intr, sc, &sc->intrhand); 1354 1355 if (error) { 1356 printf("couldn't set up irq\n"); 1357 return(ENXIO); 1358 } 1359 1360 u = pci_read_config(self, PCIR_COMMAND, 1); 1361 printf("%x\n", u); 1362 pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN, 1); 1363 #if 0 1364 pci_write_config(self, PCIR_COMMAND, 0x02800046, 4); 1365 #endif 1366 u = pci_read_config(self, PCIR_COMMAND, 1); 1367 printf("%x\n", u); 1368 1369 ver = pci_get_revid(self); 1370 1371 sc->m32x = (struct m32xreg *) sc->m0v; 1372 sc->f54w = (struct f54wreg *) sc->m1v; 1373 sc->f54r = (struct f54rreg *) sc->m1v; 1374 1375 /* We must reset before poking at FALC54 registers */ 1376 u = mn_reset(sc); 1377 if (!u) 1378 return (0); 1379 1380 printf("mn%d: Munich32X", sc->unit); 1381 switch (ver) { 1382 case 0x13: 1383 printf(" Rev 2.2"); 1384 break; 1385 default: 1386 printf(" Rev 0x%x\n", ver); 1387 } 1388 printf(", Falc54"); 1389 switch (sc->f54r->vstr) { 1390 case 0: 1391 printf(" Rev < 1.3\n"); 1392 break; 1393 case 1: 1394 printf(" Rev 1.3\n"); 1395 break; 1396 case 2: 1397 printf(" Rev 1.4\n"); 1398 break; 1399 case 0x10: 1400 printf("-LH Rev 1.1\n"); 1401 break; 1402 case 0x13: 1403 printf("-LH Rev 1.3\n"); 1404 break; 1405 default: 1406 printf(" Rev 0x%x\n", sc->f54r->vstr); 1407 } 1408 1409 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) { 1410 printf("ng_make_node_common failed\n"); 1411 return (0); 1412 } 1413 sc->node->private = sc; 1414 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit); 1415 if (ng_name_node(sc->node, sc->nodename)) { 1416 ng_rmnode(sc->node); 1417 ng_unref(sc->node); 1418 return (0); 1419 } 1420 1421 return (0); 1422 } 1423 1424 1425 static device_method_t mn_methods[] = { 1426 /* Device interface */ 1427 DEVMETHOD(device_probe, mn_probe), 1428 DEVMETHOD(device_attach, mn_attach), 1429 DEVMETHOD(device_suspend, bus_generic_suspend), 1430 DEVMETHOD(device_resume, bus_generic_resume), 1431 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1432 1433 {0, 0} 1434 }; 1435 1436 static driver_t mn_driver = { 1437 "mn", 1438 mn_methods, 1439 0 1440 }; 1441 1442 static devclass_t mn_devclass; 1443 1444 DECLARE_DUMMY_MODULE(if_mn); 1445 DRIVER_MODULE(if_mn, pci, mn_driver, mn_devclass, 0, 0); 1446 1447