1 /******************************************************************************* 2 3 Copyright (c) 2006-2013, Myricom Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Myricom Inc, nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 $FreeBSD: head/sys/dev/mxge/if_mxge_var.h 247160 2013-02-22 19:23:33Z gallatin $ 29 30 ***************************************************************************/ 31 32 #define MXGE_ETH_STOPPED 0 33 #define MXGE_ETH_STOPPING 1 34 #define MXGE_ETH_STARTING 2 35 #define MXGE_ETH_RUNNING 3 36 #define MXGE_ETH_OPEN_FAILED 4 37 38 #define MXGE_FW_OFFSET (1024*1024) 39 #define MXGE_EEPROM_STRINGS_SIZE 256 40 #define MXGE_MAX_SEND_DESC 128 41 42 #define MXGE_INTR_COAL_DELAY 150 43 44 struct mxge_softc; 45 typedef struct mxge_softc mxge_softc_t; 46 47 typedef struct { 48 uint32_t data0; 49 uint32_t data1; 50 uint32_t data2; 51 } mxge_cmd_t; 52 53 struct mxge_buffer_state { 54 struct mbuf *m; 55 bus_dmamap_t map; 56 }; 57 58 typedef struct { 59 volatile mcp_kreq_ether_recv_t *lanai; /* lanai ptr for recv ring */ 60 mcp_kreq_ether_recv_t *shadow; /* host shadow of recv ring */ 61 struct mxge_buffer_state *info; 62 bus_dma_tag_t dmat; 63 bus_dmamap_t extra_map; 64 int cnt; 65 int16_t cl_size; 66 int16_t mask; /* number of rx slots -1 */ 67 } mxge_rx_ring_t; 68 69 typedef struct { 70 mcp_slot_t *entry; 71 int idx; 72 int mask; 73 } mxge_rx_done_t; 74 75 typedef struct { 76 struct lwkt_serialize tx_serialize; 77 volatile mcp_kreq_ether_send_t *lanai; /* lanai ptr for sendq */ 78 volatile uint32_t *send_go; /* doorbell for sendq */ 79 volatile uint32_t *send_stop; /* doorbell for sendq */ 80 mcp_kreq_ether_send_t *req_list; /* host shadow of sendq */ 81 bus_dma_segment_t *seg_list; 82 struct mxge_buffer_state *info; 83 bus_dma_tag_t dmat; 84 struct ifaltq_subque *ifsq; 85 struct ifsubq_watchdog watchdog; 86 int req; /* transmits submitted */ 87 int mask; /* number of transmit slots -1 */ 88 int done; /* transmits completed */ 89 int pkt_done; /* packets completed */ 90 int max_desc; /* max descriptors per xmit */ 91 int queue_active; /* fw currently polling this queue*/ 92 int activate; 93 int deactivate; 94 int watchdog_rx_pause; /* cache of pause rq recvd */ 95 } mxge_tx_ring_t; 96 97 struct mxge_rx_data { 98 struct lwkt_serialize rx_serialize; 99 mxge_rx_done_t rx_done; 100 mxge_rx_ring_t rx_small; 101 mxge_rx_ring_t rx_big; 102 } __cachealign; 103 104 struct mxge_slice_state { 105 struct mxge_rx_data rx_data; 106 mxge_tx_ring_t tx; /* transmit ring */ 107 mxge_softc_t *sc; 108 mcp_irq_data_t *fw_stats; 109 volatile uint32_t *irq_claim; 110 bus_dmamem_t fw_stats_dma; 111 bus_dmamem_t rx_done_dma; 112 struct sysctl_oid *sysctl_tree; 113 struct sysctl_ctx_list sysctl_ctx; 114 115 struct lwkt_serialize *intr_serialize; 116 driver_intr_t *intr_func; 117 void *intr_hand; 118 struct resource *intr_res; 119 int intr_rid; 120 int intr_cpuid; 121 const char *intr_desc; 122 char intr_desc0[64]; 123 } __cachealign; 124 125 struct mxge_softc { 126 struct arpcom arpcom; 127 struct ifnet* ifp; /* points to arpcom.ac_if */ 128 struct lwkt_serialize main_serialize; 129 int nserialize; 130 struct lwkt_serialize **serializes; 131 struct mxge_slice_state *ss; 132 int tx_boundary; /* boundary transmits cannot cross*/ 133 bus_dma_tag_t parent_dmat; 134 volatile uint8_t *sram; 135 int sram_size; 136 volatile uint32_t *irq_deassert; 137 mcp_cmd_response_t *cmd; 138 bus_dmamem_t cmd_dma; 139 bus_dmamem_t zeropad_dma; 140 struct pci_dev *pdev; 141 int intr_type; 142 int link_state; 143 unsigned int rdma_tags_available; 144 int intr_coal_delay; 145 volatile uint32_t *intr_coal_delay_ptr; 146 int wc; 147 int wake_queue; 148 int stop_queue; 149 int down_cnt; 150 int watchdog_resets; 151 int pause; 152 struct resource *mem_res; 153 struct resource *msix_table_res; 154 const char *fw_name; 155 char eeprom_strings[MXGE_EEPROM_STRINGS_SIZE]; 156 char fw_version[128]; 157 int fw_ver_major; 158 int fw_ver_minor; 159 int fw_ver_tiny; 160 int adopted_rx_filter_bug; 161 device_t dev; 162 struct ifmedia media; 163 int read_dma; 164 int write_dma; 165 int read_write_dma; 166 int fw_multicast_support; 167 int link_width; 168 int max_mtu; 169 int throttle; 170 int media_flags; 171 int need_media_probe; 172 int num_slices; 173 int num_tx_rings; 174 int rx_intr_slots; 175 int use_rss; 176 int dying; 177 int connector; 178 int current_media; 179 bus_dmamem_t dmabench_dma; 180 struct callout co_hdl; 181 u_long opackets; /* saved ifnet.opackets */ 182 u_long ipackets; /* saved ifnet.ipackets */ 183 struct sysctl_oid *slice_sysctl_tree; 184 struct sysctl_ctx_list slice_sysctl_ctx; 185 struct if_ringmap *ring_map; 186 int rdr_table[NETISR_CPUMAX]; 187 uint8_t mac_addr[6]; /* eeprom mac address */ 188 uint16_t pectl; /* save PCIe CTL state */ 189 char product_code_string[64]; 190 char serial_number_string[64]; 191 }; 192 193 #define MXGE_PCI_VENDOR_MYRICOM 0x14c1 194 #define MXGE_PCI_DEVICE_Z8E 0x0008 195 #define MXGE_PCI_DEVICE_Z8E_9 0x0009 196 #define MXGE_PCI_REV_Z8E 0 197 #define MXGE_PCI_REV_Z8ES 1 198 199 #define MXGE_XFP_COMPLIANCE_BYTE 131 200 #define MXGE_SFP_COMPLIANCE_BYTE 3 201 202 #define MXGE_MIN_THROTTLE 416 203 #define MXGE_MAX_THROTTLE 4096 204 205 /* Types of connectors on NICs supported by this driver */ 206 #define MXGE_CX4 0 207 #define MXGE_XFP 1 208 #define MXGE_SFP 2 209 #define MXGE_QRF 3 210 #define MXGE_UNK 4 211 212 #define MXGE_HIGHPART_TO_U32(X) \ 213 (sizeof (X) == 8) ? ((uint32_t)((uint64_t)(X) >> 32)) : (0) 214 #define MXGE_LOWPART_TO_U32(X) ((uint32_t)(X)) 215 216 struct mxge_media_type { 217 int flag; 218 uint8_t bitmask; 219 char *name; 220 }; 221 222 #if defined(__GNUC__) 223 #if defined(__i386__) || defined(__x86_64__) 224 #define wmb() __asm__ __volatile__ ("sfence;": : :"memory") 225 #else 226 #error "unknown arch" 227 #endif 228 #else 229 #error "unknown compiler" 230 #endif 231 232 static __inline void 233 mxge_pio_copy(volatile void *to_v, void *from_v, size_t size) 234 { 235 register volatile uintptr_t *to; 236 volatile uintptr_t *from; 237 size_t i; 238 239 to = (volatile uintptr_t *)to_v; 240 from = from_v; 241 for (i = (size / sizeof(uintptr_t)); i; i--) { 242 *to = *from; 243 to++; 244 from++; 245 } 246 } 247