1 /* 2 * Copyright (c) 2002 Myson Technology Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/ 27 * 28 * $FreeBSD: src/sys/dev/my/if_my.c,v 1.2.2.4 2002/04/17 02:05:27 julian Exp $ 29 * $DragonFly: src/sys/dev/netif/my/if_my.c,v 1.20 2005/06/14 11:05:47 joerg Exp $ 30 * 31 * Myson fast ethernet PCI NIC driver 32 * 33 * $Id: if_my.c,v 1.40 2001/11/30 03:55:00 <yen_cw@myson.com.tw> wpaul Exp $ 34 */ 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/queue.h> 43 #include <sys/thread2.h> 44 #include <sys/bus.h> 45 #include <sys/module.h> 46 47 #include <net/if.h> 48 #include <net/ifq_var.h> 49 #include <net/if_arp.h> 50 #include <net/ethernet.h> 51 #include <net/if_media.h> 52 #include <net/if_dl.h> 53 #include <net/bpf.h> 54 55 #include <vm/vm.h> /* for vtophys */ 56 #include <vm/pmap.h> /* for vtophys */ 57 #include <machine/clock.h> /* for DELAY */ 58 #include <machine/bus_memio.h> 59 #include <machine/bus_pio.h> 60 #include <machine/bus.h> 61 #include <machine/resource.h> 62 #include <sys/bus.h> 63 #include <sys/rman.h> 64 65 #include <bus/pci/pcireg.h> 66 #include <bus/pci/pcivar.h> 67 68 #include "../mii_layer/mii.h" 69 #include "../mii_layer/miivar.h" 70 71 #include "miibus_if.h" 72 73 /* 74 * #define MY_USEIOSPACE 75 */ 76 77 static int MY_USEIOSPACE = 1; 78 79 #if (MY_USEIOSPACE) 80 #define MY_RES SYS_RES_IOPORT 81 #define MY_RID MY_PCI_LOIO 82 #else 83 #define MY_RES SYS_RES_MEMORY 84 #define MY_RID MY_PCI_LOMEM 85 #endif 86 87 88 #include "if_myreg.h" 89 90 /* 91 * Various supported device vendors/types and their names. 92 */ 93 static struct my_type my_devs[] = { 94 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"}, 95 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"}, 96 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"}, 97 {0, 0, NULL} 98 }; 99 100 /* 101 * Various supported PHY vendors/types and their names. Note that this driver 102 * will work with pretty much any MII-compliant PHY, so failure to positively 103 * identify the chip is not a fatal error. 104 */ 105 static struct my_type my_phys[] = { 106 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"}, 107 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"}, 108 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"}, 109 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"}, 110 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"}, 111 {0, 0, "<MII-compliant physical interface>"} 112 }; 113 114 static int my_probe(device_t); 115 static int my_attach(device_t); 116 static int my_detach(device_t); 117 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *); 118 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *); 119 static void my_rxeof(struct my_softc *); 120 static void my_txeof(struct my_softc *); 121 static void my_txeoc(struct my_softc *); 122 static void my_intr(void *); 123 static void my_start(struct ifnet *); 124 static int my_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 125 static void my_init(void *); 126 static void my_stop(struct my_softc *); 127 static void my_watchdog(struct ifnet *); 128 static void my_shutdown(device_t); 129 static int my_ifmedia_upd(struct ifnet *); 130 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *); 131 static u_int16_t my_phy_readreg(struct my_softc *, int); 132 static void my_phy_writereg(struct my_softc *, int, int); 133 static void my_autoneg_xmit(struct my_softc *); 134 static void my_autoneg_mii(struct my_softc *, int, int); 135 static void my_setmode_mii(struct my_softc *, int); 136 static void my_getmode_mii(struct my_softc *); 137 static void my_setcfg(struct my_softc *, int); 138 static u_int8_t my_calchash(caddr_t); 139 static void my_setmulti(struct my_softc *); 140 static void my_reset(struct my_softc *); 141 static int my_list_rx_init(struct my_softc *); 142 static int my_list_tx_init(struct my_softc *); 143 static long my_send_cmd_to_phy(struct my_softc *, int, int); 144 145 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 146 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 147 148 static device_method_t my_methods[] = { 149 /* Device interface */ 150 DEVMETHOD(device_probe, my_probe), 151 DEVMETHOD(device_attach, my_attach), 152 DEVMETHOD(device_detach, my_detach), 153 DEVMETHOD(device_shutdown, my_shutdown), 154 155 {0, 0} 156 }; 157 158 static driver_t my_driver = { 159 "my", 160 my_methods, 161 sizeof(struct my_softc) 162 }; 163 164 static devclass_t my_devclass; 165 166 DECLARE_DUMMY_MODULE(if_my); 167 DRIVER_MODULE(if_my, pci, my_driver, my_devclass, 0, 0); 168 169 static long 170 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad) 171 { 172 long miir; 173 int i; 174 int mask, data; 175 176 /* enable MII output */ 177 miir = CSR_READ_4(sc, MY_MANAGEMENT); 178 miir &= 0xfffffff0; 179 180 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO; 181 182 /* send 32 1's preamble */ 183 for (i = 0; i < 32; i++) { 184 /* low MDC; MDO is already high (miir) */ 185 miir &= ~MY_MASK_MIIR_MII_MDC; 186 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 187 188 /* high MDC */ 189 miir |= MY_MASK_MIIR_MII_MDC; 190 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 191 } 192 193 /* calculate ST+OP+PHYAD+REGAD+TA */ 194 data = opcode | (sc->my_phy_addr << 7) | (regad << 2); 195 196 /* sent out */ 197 mask = 0x8000; 198 while (mask) { 199 /* low MDC, prepare MDO */ 200 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 201 if (mask & data) 202 miir |= MY_MASK_MIIR_MII_MDO; 203 204 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 205 /* high MDC */ 206 miir |= MY_MASK_MIIR_MII_MDC; 207 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 208 DELAY(30); 209 210 /* next */ 211 mask >>= 1; 212 if (mask == 0x2 && opcode == MY_OP_READ) 213 miir &= ~MY_MASK_MIIR_MII_WRITE; 214 } 215 216 return miir; 217 } 218 219 220 static u_int16_t 221 my_phy_readreg(struct my_softc * sc, int reg) 222 { 223 long miir; 224 int mask, data; 225 226 if (sc->my_info->my_did == MTD803ID) 227 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2); 228 else { 229 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg); 230 231 /* read data */ 232 mask = 0x8000; 233 data = 0; 234 while (mask) { 235 /* low MDC */ 236 miir &= ~MY_MASK_MIIR_MII_MDC; 237 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 238 239 /* read MDI */ 240 miir = CSR_READ_4(sc, MY_MANAGEMENT); 241 if (miir & MY_MASK_MIIR_MII_MDI) 242 data |= mask; 243 244 /* high MDC, and wait */ 245 miir |= MY_MASK_MIIR_MII_MDC; 246 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 247 DELAY(30); 248 249 /* next */ 250 mask >>= 1; 251 } 252 253 /* low MDC */ 254 miir &= ~MY_MASK_MIIR_MII_MDC; 255 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 256 } 257 258 return (u_int16_t) data; 259 } 260 261 262 static void 263 my_phy_writereg(struct my_softc * sc, int reg, int data) 264 { 265 long miir; 266 int mask; 267 268 if (sc->my_info->my_did == MTD803ID) 269 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data); 270 else { 271 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg); 272 273 /* write data */ 274 mask = 0x8000; 275 while (mask) { 276 /* low MDC, prepare MDO */ 277 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 278 if (mask & data) 279 miir |= MY_MASK_MIIR_MII_MDO; 280 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 281 DELAY(1); 282 283 /* high MDC */ 284 miir |= MY_MASK_MIIR_MII_MDC; 285 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 286 DELAY(1); 287 288 /* next */ 289 mask >>= 1; 290 } 291 292 /* low MDC */ 293 miir &= ~MY_MASK_MIIR_MII_MDC; 294 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 295 } 296 } 297 298 static u_int8_t 299 my_calchash(caddr_t addr) 300 { 301 u_int32_t crc, carry; 302 int i, j; 303 u_int8_t c; 304 305 /* Compute CRC for the address value. */ 306 crc = 0xFFFFFFFF; /* initial value */ 307 308 for (i = 0; i < 6; i++) { 309 c = *(addr + i); 310 for (j = 0; j < 8; j++) { 311 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 312 crc <<= 1; 313 c >>= 1; 314 if (carry) 315 crc = (crc ^ 0x04c11db6) | carry; 316 } 317 } 318 319 /* 320 * return the filter bit position Note: I arrived at the following 321 * nonsense through experimentation. It's not the usual way to 322 * generate the bit position but it's the only thing I could come up 323 * with that works. 324 */ 325 return (~(crc >> 26) & 0x0000003F); 326 } 327 328 329 /* 330 * Program the 64-bit multicast hash filter. 331 */ 332 static void 333 my_setmulti(struct my_softc * sc) 334 { 335 struct ifnet *ifp = &sc->arpcom.ac_if; 336 int h = 0; 337 u_int32_t hashes[2] = {0, 0}; 338 struct ifmultiaddr *ifma; 339 u_int32_t rxfilt; 340 int mcnt = 0; 341 342 rxfilt = CSR_READ_4(sc, MY_TCRRCR); 343 344 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 345 rxfilt |= MY_AM; 346 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 347 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF); 348 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF); 349 350 return; 351 } 352 /* first, zot all the existing hash bits */ 353 CSR_WRITE_4(sc, MY_MAR0, 0); 354 CSR_WRITE_4(sc, MY_MAR1, 0); 355 356 /* now program new ones */ 357 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 358 if (ifma->ifma_addr->sa_family != AF_LINK) 359 continue; 360 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr)); 361 if (h < 32) 362 hashes[0] |= (1 << h); 363 else 364 hashes[1] |= (1 << (h - 32)); 365 mcnt++; 366 } 367 368 if (mcnt) 369 rxfilt |= MY_AM; 370 else 371 rxfilt &= ~MY_AM; 372 CSR_WRITE_4(sc, MY_MAR0, hashes[0]); 373 CSR_WRITE_4(sc, MY_MAR1, hashes[1]); 374 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 375 } 376 377 /* 378 * Initiate an autonegotiation session. 379 */ 380 static void 381 my_autoneg_xmit(struct my_softc * sc) 382 { 383 u_int16_t phy_sts = 0; 384 385 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 386 DELAY(500); 387 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 388 389 phy_sts = my_phy_readreg(sc, PHY_BMCR); 390 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR; 391 my_phy_writereg(sc, PHY_BMCR, phy_sts); 392 } 393 394 395 /* 396 * Invoke autonegotiation on a PHY. 397 */ 398 static void 399 my_autoneg_mii(struct my_softc * sc, int flag, int verbose) 400 { 401 u_int16_t phy_sts = 0, media, advert, ability; 402 u_int16_t ability2 = 0; 403 struct ifnet *ifp = &sc->arpcom.ac_if; 404 struct ifmedia *ifm = &sc->ifmedia; 405 406 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 407 408 #ifndef FORCE_AUTONEG_TFOUR 409 /* 410 * First, see if autoneg is supported. If not, there's no point in 411 * continuing. 412 */ 413 phy_sts = my_phy_readreg(sc, PHY_BMSR); 414 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 415 if (verbose) 416 printf("my%d: autonegotiation not supported\n", 417 sc->my_unit); 418 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 419 return; 420 } 421 #endif 422 switch (flag) { 423 case MY_FLAG_FORCEDELAY: 424 /* 425 * XXX Never use this option anywhere but in the probe 426 * routine: making the kernel stop dead in its tracks for 427 * three whole seconds after we've gone multi-user is really 428 * bad manners. 429 */ 430 my_autoneg_xmit(sc); 431 DELAY(5000000); 432 break; 433 case MY_FLAG_SCHEDDELAY: 434 /* 435 * Wait for the transmitter to go idle before starting an 436 * autoneg session, otherwise my_start() may clobber our 437 * timeout, and we don't want to allow transmission during an 438 * autoneg session since that can screw it up. 439 */ 440 if (sc->my_cdata.my_tx_head != NULL) { 441 sc->my_want_auto = 1; 442 return; 443 } 444 my_autoneg_xmit(sc); 445 ifp->if_timer = 5; 446 sc->my_autoneg = 1; 447 sc->my_want_auto = 0; 448 return; 449 case MY_FLAG_DELAYTIMEO: 450 ifp->if_timer = 0; 451 sc->my_autoneg = 0; 452 break; 453 default: 454 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag); 455 return; 456 } 457 458 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 459 if (verbose) 460 printf("my%d: autoneg complete, ", sc->my_unit); 461 phy_sts = my_phy_readreg(sc, PHY_BMSR); 462 } else { 463 if (verbose) 464 printf("my%d: autoneg not complete, ", sc->my_unit); 465 } 466 467 media = my_phy_readreg(sc, PHY_BMCR); 468 469 /* Link is good. Report modes and set duplex mode. */ 470 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 471 if (verbose) 472 printf("my%d: link status good. ", sc->my_unit); 473 advert = my_phy_readreg(sc, PHY_ANAR); 474 ability = my_phy_readreg(sc, PHY_LPAR); 475 if ((sc->my_pinfo->my_vid == MarvellPHYID0) || 476 (sc->my_pinfo->my_vid == LevelOnePHYID0)) { 477 ability2 = my_phy_readreg(sc, PHY_1000SR); 478 if (ability2 & PHY_1000SR_1000BTXFULL) { 479 advert = 0; 480 ability = 0; 481 /* 482 * this version did not support 1000M, 483 * ifm->ifm_media = 484 * IFM_ETHER | IFM_1000_T | IFM_FDX; 485 */ 486 ifm->ifm_media = 487 IFM_ETHER | IFM_100_TX | IFM_FDX; 488 media &= ~PHY_BMCR_SPEEDSEL; 489 media |= PHY_BMCR_1000; 490 media |= PHY_BMCR_DUPLEX; 491 printf("(full-duplex, 1000Mbps)\n"); 492 } else if (ability2 & PHY_1000SR_1000BTXHALF) { 493 advert = 0; 494 ability = 0; 495 /* 496 * this version did not support 1000M, 497 * ifm->ifm_media = IFM_ETHER | IFM_1000_T; 498 */ 499 ifm->ifm_media = IFM_ETHER | IFM_100_TX; 500 media &= ~PHY_BMCR_SPEEDSEL; 501 media &= ~PHY_BMCR_DUPLEX; 502 media |= PHY_BMCR_1000; 503 printf("(half-duplex, 1000Mbps)\n"); 504 } 505 } 506 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 507 ifm->ifm_media = IFM_ETHER | IFM_100_T4; 508 media |= PHY_BMCR_SPEEDSEL; 509 media &= ~PHY_BMCR_DUPLEX; 510 printf("(100baseT4)\n"); 511 } else if (advert & PHY_ANAR_100BTXFULL && 512 ability & PHY_ANAR_100BTXFULL) { 513 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 514 media |= PHY_BMCR_SPEEDSEL; 515 media |= PHY_BMCR_DUPLEX; 516 printf("(full-duplex, 100Mbps)\n"); 517 } else if (advert & PHY_ANAR_100BTXHALF && 518 ability & PHY_ANAR_100BTXHALF) { 519 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 520 media |= PHY_BMCR_SPEEDSEL; 521 media &= ~PHY_BMCR_DUPLEX; 522 printf("(half-duplex, 100Mbps)\n"); 523 } else if (advert & PHY_ANAR_10BTFULL && 524 ability & PHY_ANAR_10BTFULL) { 525 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 526 media &= ~PHY_BMCR_SPEEDSEL; 527 media |= PHY_BMCR_DUPLEX; 528 printf("(full-duplex, 10Mbps)\n"); 529 } else if (advert) { 530 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 531 media &= ~PHY_BMCR_SPEEDSEL; 532 media &= ~PHY_BMCR_DUPLEX; 533 printf("(half-duplex, 10Mbps)\n"); 534 } 535 media &= ~PHY_BMCR_AUTONEGENBL; 536 537 /* Set ASIC's duplex mode to match the PHY. */ 538 my_phy_writereg(sc, PHY_BMCR, media); 539 my_setcfg(sc, media); 540 } else { 541 if (verbose) 542 printf("my%d: no carrier\n", sc->my_unit); 543 } 544 545 my_init(sc); 546 if (sc->my_tx_pend) { 547 sc->my_autoneg = 0; 548 sc->my_tx_pend = 0; 549 my_start(ifp); 550 } 551 } 552 553 /* 554 * To get PHY ability. 555 */ 556 static void 557 my_getmode_mii(struct my_softc * sc) 558 { 559 struct ifnet *ifp = &sc->arpcom.ac_if; 560 u_int16_t bmsr; 561 562 bmsr = my_phy_readreg(sc, PHY_BMSR); 563 if (bootverbose) 564 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr); 565 566 /* fallback */ 567 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 568 569 if (bmsr & PHY_BMSR_10BTHALF) { 570 if (bootverbose) 571 printf("my%d: 10Mbps half-duplex mode supported\n", 572 sc->my_unit); 573 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 574 0, NULL); 575 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 576 } 577 if (bmsr & PHY_BMSR_10BTFULL) { 578 if (bootverbose) 579 printf("my%d: 10Mbps full-duplex mode supported\n", 580 sc->my_unit); 581 582 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 583 0, NULL); 584 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 585 } 586 if (bmsr & PHY_BMSR_100BTXHALF) { 587 if (bootverbose) 588 printf("my%d: 100Mbps half-duplex mode supported\n", 589 sc->my_unit); 590 ifp->if_baudrate = 100000000; 591 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 592 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 593 0, NULL); 594 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 595 } 596 if (bmsr & PHY_BMSR_100BTXFULL) { 597 if (bootverbose) 598 printf("my%d: 100Mbps full-duplex mode supported\n", 599 sc->my_unit); 600 ifp->if_baudrate = 100000000; 601 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 602 0, NULL); 603 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 604 } 605 /* Some also support 100BaseT4. */ 606 if (bmsr & PHY_BMSR_100BT4) { 607 if (bootverbose) 608 printf("my%d: 100baseT4 mode supported\n", sc->my_unit); 609 ifp->if_baudrate = 100000000; 610 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL); 611 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4; 612 #ifdef FORCE_AUTONEG_TFOUR 613 if (bootverbose) 614 printf("my%d: forcing on autoneg support for BT4\n", 615 sc->my_unit); 616 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL): 617 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 618 #endif 619 } 620 #if 0 /* this version did not support 1000M, */ 621 if (sc->my_pinfo->my_vid == MarvellPHYID0) { 622 if (bootverbose) 623 printf("my%d: 1000Mbps half-duplex mode supported\n", 624 sc->my_unit); 625 626 ifp->if_baudrate = 1000000000; 627 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 628 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX, 629 0, NULL); 630 if (bootverbose) 631 printf("my%d: 1000Mbps full-duplex mode supported\n", 632 sc->my_unit); 633 ifp->if_baudrate = 1000000000; 634 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 635 0, NULL); 636 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX; 637 } 638 #endif 639 if (bmsr & PHY_BMSR_CANAUTONEG) { 640 if (bootverbose) 641 printf("my%d: autoneg supported\n", sc->my_unit); 642 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 643 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 644 } 645 } 646 647 /* 648 * Set speed and duplex mode. 649 */ 650 static void 651 my_setmode_mii(struct my_softc * sc, int media) 652 { 653 struct ifnet *ifp = &sc->arpcom.ac_if; 654 u_int16_t bmcr; 655 656 /* 657 * If an autoneg session is in progress, stop it. 658 */ 659 if (sc->my_autoneg) { 660 printf("my%d: canceling autoneg session\n", sc->my_unit); 661 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0; 662 bmcr = my_phy_readreg(sc, PHY_BMCR); 663 bmcr &= ~PHY_BMCR_AUTONEGENBL; 664 my_phy_writereg(sc, PHY_BMCR, bmcr); 665 } 666 printf("my%d: selecting MII, ", sc->my_unit); 667 bmcr = my_phy_readreg(sc, PHY_BMCR); 668 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 | 669 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK); 670 671 #if 0 /* this version did not support 1000M, */ 672 if (IFM_SUBTYPE(media) == IFM_1000_T) { 673 printf("1000Mbps/T4, half-duplex\n"); 674 bmcr &= ~PHY_BMCR_SPEEDSEL; 675 bmcr &= ~PHY_BMCR_DUPLEX; 676 bmcr |= PHY_BMCR_1000; 677 } 678 #endif 679 if (IFM_SUBTYPE(media) == IFM_100_T4) { 680 printf("100Mbps/T4, half-duplex\n"); 681 bmcr |= PHY_BMCR_SPEEDSEL; 682 bmcr &= ~PHY_BMCR_DUPLEX; 683 } 684 if (IFM_SUBTYPE(media) == IFM_100_TX) { 685 printf("100Mbps, "); 686 bmcr |= PHY_BMCR_SPEEDSEL; 687 } 688 if (IFM_SUBTYPE(media) == IFM_10_T) { 689 printf("10Mbps, "); 690 bmcr &= ~PHY_BMCR_SPEEDSEL; 691 } 692 if ((media & IFM_GMASK) == IFM_FDX) { 693 printf("full duplex\n"); 694 bmcr |= PHY_BMCR_DUPLEX; 695 } else { 696 printf("half duplex\n"); 697 bmcr &= ~PHY_BMCR_DUPLEX; 698 } 699 my_phy_writereg(sc, PHY_BMCR, bmcr); 700 my_setcfg(sc, bmcr); 701 } 702 703 /* 704 * The Myson manual states that in order to fiddle with the 'full-duplex' and 705 * '100Mbps' bits in the netconfig register, we first have to put the 706 * transmit and/or receive logic in the idle state. 707 */ 708 static void 709 my_setcfg(struct my_softc * sc, int bmcr) 710 { 711 int i, restart = 0; 712 713 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { 714 restart = 1; 715 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE)); 716 for (i = 0; i < MY_TIMEOUT; i++) { 717 DELAY(10); 718 if (!(CSR_READ_4(sc, MY_TCRRCR) & 719 (MY_TXRUN | MY_RXRUN))) 720 break; 721 } 722 if (i == MY_TIMEOUT) 723 printf("my%d: failed to force tx and rx to idle \n", 724 sc->my_unit); 725 } 726 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000); 727 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10); 728 if (bmcr & PHY_BMCR_1000) 729 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000); 730 else if (!(bmcr & PHY_BMCR_SPEEDSEL)) 731 MY_SETBIT(sc, MY_TCRRCR, MY_PS10); 732 if (bmcr & PHY_BMCR_DUPLEX) 733 MY_SETBIT(sc, MY_TCRRCR, MY_FD); 734 else 735 MY_CLRBIT(sc, MY_TCRRCR, MY_FD); 736 if (restart) 737 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE); 738 } 739 740 static void 741 my_reset(struct my_softc * sc) 742 { 743 int i; 744 745 MY_SETBIT(sc, MY_BCR, MY_SWR); 746 for (i = 0; i < MY_TIMEOUT; i++) { 747 DELAY(10); 748 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) 749 break; 750 } 751 if (i == MY_TIMEOUT) 752 printf("m0x%d: reset never completed!\n", sc->my_unit); 753 754 /* Wait a little while for the chip to get its brains in order. */ 755 DELAY(1000); 756 } 757 758 /* 759 * Probe for a Myson chip. Check the PCI vendor and device IDs against our 760 * list and return a device name if we find a match. 761 */ 762 static int 763 my_probe(device_t dev) 764 { 765 struct my_type *t; 766 uint16_t vendor, product; 767 768 vendor = pci_get_vendor(dev); 769 product = pci_get_device(dev); 770 771 for (t = my_devs; t->my_name != NULL; t++) { 772 if (vendor == t->my_vid && product == t->my_did) { 773 device_set_desc(dev, t->my_name); 774 return (0); 775 } 776 } 777 778 return (ENXIO); 779 } 780 781 /* 782 * Attach the interface. Allocate softc structures, do ifmedia setup and 783 * ethernet/BPF attach. 784 */ 785 static int 786 my_attach(device_t dev) 787 { 788 int i; 789 u_char eaddr[ETHER_ADDR_LEN]; 790 u_int32_t command, iobase; 791 struct my_softc *sc; 792 struct ifnet *ifp; 793 int media = IFM_ETHER | IFM_100_TX | IFM_FDX; 794 unsigned int round; 795 caddr_t roundptr; 796 struct my_type *p; 797 u_int16_t phy_vid, phy_did, phy_sts = 0; 798 int rid, unit, error = 0; 799 struct my_type *t; 800 uint16_t vendor, product; 801 802 vendor = pci_get_vendor(dev); 803 product = pci_get_device(dev); 804 805 for (t = my_devs; t->my_name != NULL; t++) { 806 if (vendor == t->my_vid && product == t->my_did) 807 break; 808 } 809 810 if (t->my_name == NULL) 811 return(ENXIO); 812 813 sc = device_get_softc(dev); 814 unit = device_get_unit(dev); 815 816 /* 817 * Map control/status registers. 818 */ 819 command = pci_read_config(dev, PCIR_COMMAND, 4); 820 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 821 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4); 822 command = pci_read_config(dev, PCIR_COMMAND, 4); 823 824 if (t->my_did == MTD800ID) { 825 iobase = pci_read_config(dev, MY_PCI_LOIO, 4); 826 if (iobase & 0x300) 827 MY_USEIOSPACE = 0; 828 } 829 if (MY_USEIOSPACE) { 830 if (!(command & PCIM_CMD_PORTEN)) { 831 printf("my%d: failed to enable I/O ports!\n", unit); 832 error = ENXIO; 833 return(error); 834 } 835 } else { 836 if (!(command & PCIM_CMD_MEMEN)) { 837 printf("my%d: failed to enable memory mapping!\n", 838 unit); 839 error = ENXIO; 840 return(error); 841 } 842 } 843 844 rid = MY_RID; 845 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE); 846 847 if (sc->my_res == NULL) { 848 printf("my%d: couldn't map ports/memory\n", unit); 849 error = ENXIO; 850 goto fail; 851 } 852 sc->my_btag = rman_get_bustag(sc->my_res); 853 sc->my_bhandle = rman_get_bushandle(sc->my_res); 854 855 rid = 0; 856 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 857 RF_SHAREABLE | RF_ACTIVE); 858 859 if (sc->my_irq == NULL) { 860 printf("my%d: couldn't map interrupt\n", unit); 861 error = ENXIO; 862 goto fail; 863 } 864 callout_init(&sc->my_stat_ch); 865 866 sc->my_info = t; 867 868 /* Reset the adapter. */ 869 my_reset(sc); 870 871 /* 872 * Get station address 873 */ 874 for (i = 0; i < ETHER_ADDR_LEN; ++i) 875 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); 876 877 sc->my_unit = unit; 878 879 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8, 880 M_DEVBUF, M_WAITOK); 881 if (sc->my_ldata_ptr == NULL) { 882 printf("my%d: no memory for list buffers!\n", unit); 883 error = ENXIO; 884 goto fail; 885 } 886 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr; 887 round = (unsigned int)sc->my_ldata_ptr & 0xF; 888 roundptr = sc->my_ldata_ptr; 889 for (i = 0; i < 8; i++) { 890 if (round % 8) { 891 round++; 892 roundptr++; 893 } else 894 break; 895 } 896 sc->my_ldata = (struct my_list_data *) roundptr; 897 bzero(sc->my_ldata, sizeof(struct my_list_data)); 898 899 ifp = &sc->arpcom.ac_if; 900 ifp->if_softc = sc; 901 if_initname(ifp, "my", unit); 902 ifp->if_mtu = ETHERMTU; 903 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 904 ifp->if_ioctl = my_ioctl; 905 ifp->if_start = my_start; 906 ifp->if_watchdog = my_watchdog; 907 ifp->if_init = my_init; 908 ifp->if_baudrate = 10000000; 909 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 910 ifq_set_ready(&ifp->if_snd); 911 912 if (sc->my_info->my_did == MTD803ID) 913 sc->my_pinfo = my_phys; 914 else { 915 if (bootverbose) 916 printf("my%d: probing for a PHY\n", sc->my_unit); 917 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) { 918 if (bootverbose) 919 printf("my%d: checking address: %d\n", 920 sc->my_unit, i); 921 sc->my_phy_addr = i; 922 phy_sts = my_phy_readreg(sc, PHY_BMSR); 923 if ((phy_sts != 0) && (phy_sts != 0xffff)) 924 break; 925 else 926 phy_sts = 0; 927 } 928 if (phy_sts) { 929 phy_vid = my_phy_readreg(sc, PHY_VENID); 930 phy_did = my_phy_readreg(sc, PHY_DEVID); 931 if (bootverbose) { 932 printf("my%d: found PHY at address %d, ", 933 sc->my_unit, sc->my_phy_addr); 934 printf("vendor id: %x device id: %x\n", 935 phy_vid, phy_did); 936 } 937 p = my_phys; 938 while (p->my_vid) { 939 if (phy_vid == p->my_vid) { 940 sc->my_pinfo = p; 941 break; 942 } 943 p++; 944 } 945 if (sc->my_pinfo == NULL) 946 sc->my_pinfo = &my_phys[PHY_UNKNOWN]; 947 if (bootverbose) 948 printf("my%d: PHY type: %s\n", 949 sc->my_unit, sc->my_pinfo->my_name); 950 } else { 951 printf("my%d: MII without any phy!\n", sc->my_unit); 952 error = ENXIO; 953 goto fail; 954 } 955 } 956 957 /* Do ifmedia setup. */ 958 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts); 959 my_getmode_mii(sc); 960 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1); 961 media = sc->ifmedia.ifm_media; 962 my_stop(sc); 963 ifmedia_set(&sc->ifmedia, media); 964 965 ether_ifattach(ifp, eaddr); 966 967 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET, 968 my_intr, sc, &sc->my_intrhand, NULL); 969 if (error) { 970 ether_ifdetach(ifp); 971 printf("my%d: couldn't set up irq\n", unit); 972 goto fail; 973 } 974 975 return (0); 976 977 fail: 978 my_detach(dev); 979 return (error); 980 } 981 982 static int 983 my_detach(device_t dev) 984 { 985 struct my_softc *sc = device_get_softc(dev); 986 struct ifnet *ifp = &sc->arpcom.ac_if; 987 988 crit_enter(); 989 if (device_is_attached(dev)) { 990 ether_ifdetach(ifp); 991 my_stop(sc); 992 } 993 994 if (sc->my_intrhand) 995 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand); 996 997 crit_exit(); 998 999 if (sc->my_irq) 1000 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 1001 if (sc->my_res) 1002 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 1003 1004 return (0); 1005 } 1006 1007 1008 /* 1009 * Initialize the transmit descriptors. 1010 */ 1011 static int 1012 my_list_tx_init(struct my_softc * sc) 1013 { 1014 struct my_chain_data *cd; 1015 struct my_list_data *ld; 1016 int i; 1017 1018 cd = &sc->my_cdata; 1019 ld = sc->my_ldata; 1020 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1021 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i]; 1022 if (i == (MY_TX_LIST_CNT - 1)) 1023 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0]; 1024 else 1025 cd->my_tx_chain[i].my_nextdesc = 1026 &cd->my_tx_chain[i + 1]; 1027 } 1028 cd->my_tx_free = &cd->my_tx_chain[0]; 1029 cd->my_tx_tail = cd->my_tx_head = NULL; 1030 return (0); 1031 } 1032 1033 /* 1034 * Initialize the RX descriptors and allocate mbufs for them. Note that we 1035 * arrange the descriptors in a closed ring, so that the last descriptor 1036 * points back to the first. 1037 */ 1038 static int 1039 my_list_rx_init(struct my_softc * sc) 1040 { 1041 struct my_chain_data *cd; 1042 struct my_list_data *ld; 1043 int i; 1044 1045 cd = &sc->my_cdata; 1046 ld = sc->my_ldata; 1047 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1048 cd->my_rx_chain[i].my_ptr = 1049 (struct my_desc *) & ld->my_rx_list[i]; 1050 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) 1051 return (ENOBUFS); 1052 if (i == (MY_RX_LIST_CNT - 1)) { 1053 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0]; 1054 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]); 1055 } else { 1056 cd->my_rx_chain[i].my_nextdesc = 1057 &cd->my_rx_chain[i + 1]; 1058 ld->my_rx_list[i].my_next = 1059 vtophys(&ld->my_rx_list[i + 1]); 1060 } 1061 } 1062 cd->my_rx_head = &cd->my_rx_chain[0]; 1063 return (0); 1064 } 1065 1066 /* 1067 * Initialize an RX descriptor and attach an MBUF cluster. 1068 */ 1069 static int 1070 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c) 1071 { 1072 struct mbuf *m_new = NULL; 1073 1074 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1075 if (m_new == NULL) { 1076 printf("my%d: no memory for rx list -- packet dropped!\n", 1077 sc->my_unit); 1078 return (ENOBUFS); 1079 } 1080 MCLGET(m_new, MB_DONTWAIT); 1081 if (!(m_new->m_flags & M_EXT)) { 1082 printf("my%d: no memory for rx list -- packet dropped!\n", 1083 sc->my_unit); 1084 m_freem(m_new); 1085 return (ENOBUFS); 1086 } 1087 c->my_mbuf = m_new; 1088 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t)); 1089 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift; 1090 c->my_ptr->my_status = MY_OWNByNIC; 1091 return (0); 1092 } 1093 1094 /* 1095 * A frame has been uploaded: pass the resulting mbuf chain up to the higher 1096 * level protocols. 1097 */ 1098 static void 1099 my_rxeof(struct my_softc * sc) 1100 { 1101 struct mbuf *m; 1102 struct ifnet *ifp = &sc->arpcom.ac_if; 1103 struct my_chain_onefrag *cur_rx; 1104 int total_len = 0; 1105 u_int32_t rxstat; 1106 1107 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status) 1108 & MY_OWNByNIC)) { 1109 cur_rx = sc->my_cdata.my_rx_head; 1110 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc; 1111 1112 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */ 1113 ifp->if_ierrors++; 1114 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1115 continue; 1116 } 1117 /* No errors; receive the packet. */ 1118 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift; 1119 total_len -= ETHER_CRC_LEN; 1120 1121 if (total_len < MINCLSIZE) { 1122 m = m_devget(mtod(cur_rx->my_mbuf, char *), 1123 total_len, 0, ifp, NULL); 1124 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1125 if (m == NULL) { 1126 ifp->if_ierrors++; 1127 continue; 1128 } 1129 } else { 1130 m = cur_rx->my_mbuf; 1131 /* 1132 * Try to conjure up a new mbuf cluster. If that 1133 * fails, it means we have an out of memory condition 1134 * and should leave the buffer in place and continue. 1135 * This will result in a lost packet, but there's 1136 * little else we can do in this situation. 1137 */ 1138 if (my_newbuf(sc, cur_rx) == ENOBUFS) { 1139 ifp->if_ierrors++; 1140 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1141 continue; 1142 } 1143 m->m_pkthdr.rcvif = ifp; 1144 m->m_pkthdr.len = m->m_len = total_len; 1145 } 1146 ifp->if_ipackets++; 1147 (*ifp->if_input)(ifp, m); 1148 } 1149 } 1150 1151 1152 /* 1153 * A frame was downloaded to the chip. It's safe for us to clean up the list 1154 * buffers. 1155 */ 1156 static void 1157 my_txeof(struct my_softc * sc) 1158 { 1159 struct ifnet *ifp = &sc->arpcom.ac_if; 1160 struct my_chain *cur_tx; 1161 1162 /* Clear the timeout timer. */ 1163 ifp->if_timer = 0; 1164 if (sc->my_cdata.my_tx_head == NULL) 1165 return; 1166 /* 1167 * Go through our tx list and free mbufs for those frames that have 1168 * been transmitted. 1169 */ 1170 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) { 1171 u_int32_t txstat; 1172 1173 cur_tx = sc->my_cdata.my_tx_head; 1174 txstat = MY_TXSTATUS(cur_tx); 1175 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT) 1176 break; 1177 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { 1178 if (txstat & MY_TXERR) { 1179 ifp->if_oerrors++; 1180 if (txstat & MY_EC) /* excessive collision */ 1181 ifp->if_collisions++; 1182 if (txstat & MY_LC) /* late collision */ 1183 ifp->if_collisions++; 1184 } 1185 ifp->if_collisions += (txstat & MY_NCRMASK) >> 1186 MY_NCRShift; 1187 } 1188 ifp->if_opackets++; 1189 m_freem(cur_tx->my_mbuf); 1190 cur_tx->my_mbuf = NULL; 1191 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) { 1192 sc->my_cdata.my_tx_head = NULL; 1193 sc->my_cdata.my_tx_tail = NULL; 1194 break; 1195 } 1196 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc; 1197 } 1198 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { 1199 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask); 1200 } 1201 } 1202 1203 /* 1204 * TX 'end of channel' interrupt handler. 1205 */ 1206 static void 1207 my_txeoc(struct my_softc * sc) 1208 { 1209 struct ifnet *ifp = &sc->arpcom.ac_if; 1210 1211 ifp->if_timer = 0; 1212 if (sc->my_cdata.my_tx_head == NULL) { 1213 ifp->if_flags &= ~IFF_OACTIVE; 1214 sc->my_cdata.my_tx_tail = NULL; 1215 if (sc->my_want_auto) 1216 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1217 } else { 1218 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) { 1219 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC; 1220 ifp->if_timer = 5; 1221 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); 1222 } 1223 } 1224 } 1225 1226 static void 1227 my_intr(void *arg) 1228 { 1229 struct my_softc *sc = arg; 1230 struct ifnet *ifp = &sc->arpcom.ac_if; 1231 u_int32_t status; 1232 1233 if (!(ifp->if_flags & IFF_UP)) 1234 return; 1235 1236 /* Disable interrupts. */ 1237 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1238 1239 for (;;) { 1240 status = CSR_READ_4(sc, MY_ISR); 1241 status &= MY_INTRS; 1242 if (status) 1243 CSR_WRITE_4(sc, MY_ISR, status); 1244 else 1245 break; 1246 1247 if (status & MY_RI) /* receive interrupt */ 1248 my_rxeof(sc); 1249 1250 if ((status & MY_RBU) || (status & MY_RxErr)) { 1251 /* rx buffer unavailable or rx error */ 1252 ifp->if_ierrors++; 1253 #ifdef foo 1254 my_stop(sc); 1255 my_reset(sc); 1256 my_init(sc); 1257 #endif 1258 } 1259 if (status & MY_TI) /* tx interrupt */ 1260 my_txeof(sc); 1261 if (status & MY_ETI) /* tx early interrupt */ 1262 my_txeof(sc); 1263 if (status & MY_TBU) /* tx buffer unavailable */ 1264 my_txeoc(sc); 1265 1266 #if 0 /* 90/1/18 delete */ 1267 if (status & MY_FBE) { 1268 my_reset(sc); 1269 my_init(sc); 1270 } 1271 #endif 1272 1273 } 1274 1275 /* Re-enable interrupts. */ 1276 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1277 if (!ifq_is_empty(&ifp->if_snd)) 1278 my_start(ifp); 1279 } 1280 1281 /* 1282 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1283 * pointers to the fragment pointers. 1284 */ 1285 static int 1286 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head) 1287 { 1288 struct my_desc *f = NULL; 1289 int total_len; 1290 struct mbuf *m, *m_new = NULL; 1291 1292 /* calculate the total tx pkt length */ 1293 total_len = 0; 1294 for (m = m_head; m != NULL; m = m->m_next) 1295 total_len += m->m_len; 1296 /* 1297 * Start packing the mbufs in this chain into the fragment pointers. 1298 * Stop when we run out of fragments or hit the end of the mbuf 1299 * chain. 1300 */ 1301 m = m_head; 1302 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1303 if (m_new == NULL) { 1304 printf("my%d: no memory for tx list", sc->my_unit); 1305 return (1); 1306 } 1307 if (m_head->m_pkthdr.len > MHLEN) { 1308 MCLGET(m_new, MB_DONTWAIT); 1309 if (!(m_new->m_flags & M_EXT)) { 1310 m_freem(m_new); 1311 printf("my%d: no memory for tx list", sc->my_unit); 1312 return (1); 1313 } 1314 } 1315 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1316 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1317 m_freem(m_head); 1318 m_head = m_new; 1319 f = &c->my_ptr->my_frag[0]; 1320 f->my_status = 0; 1321 f->my_data = vtophys(mtod(m_new, caddr_t)); 1322 total_len = m_new->m_len; 1323 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable; 1324 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */ 1325 f->my_ctl |= total_len; /* buffer size */ 1326 /* 89/12/29 add, for mtd891 *//* [ 89? ] */ 1327 if (sc->my_info->my_did == MTD891ID) 1328 f->my_ctl |= MY_ETIControl | MY_RetryTxLC; 1329 c->my_mbuf = m_head; 1330 c->my_lastdesc = 0; 1331 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]); 1332 return (0); 1333 } 1334 1335 /* 1336 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1337 * to the mbuf data regions directly in the transmit lists. We also save a 1338 * copy of the pointers since the transmit list fragment pointers are 1339 * physical addresses. 1340 */ 1341 static void 1342 my_start(struct ifnet * ifp) 1343 { 1344 struct my_softc *sc = ifp->if_softc; 1345 struct mbuf *m_head = NULL; 1346 struct my_chain *cur_tx = NULL, *start_tx; 1347 1348 crit_enter(); 1349 1350 if (sc->my_autoneg) { 1351 sc->my_tx_pend = 1; 1352 crit_exit(); 1353 return; 1354 } 1355 /* 1356 * Check for an available queue slot. If there are none, punt. 1357 */ 1358 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) { 1359 ifp->if_flags |= IFF_OACTIVE; 1360 crit_exit(); 1361 return; 1362 } 1363 1364 start_tx = sc->my_cdata.my_tx_free; 1365 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) { 1366 m_head = ifq_dequeue(&ifp->if_snd); 1367 if (m_head == NULL) 1368 break; 1369 1370 /* Pick a descriptor off the free list. */ 1371 cur_tx = sc->my_cdata.my_tx_free; 1372 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc; 1373 1374 /* Pack the data into the descriptor. */ 1375 my_encap(sc, cur_tx, m_head); 1376 1377 if (cur_tx != start_tx) 1378 MY_TXOWN(cur_tx) = MY_OWNByNIC; 1379 BPF_MTAP(ifp, cur_tx->my_mbuf); 1380 } 1381 /* 1382 * If there are no packets queued, bail. 1383 */ 1384 if (cur_tx == NULL) { 1385 crit_exit(); 1386 return; 1387 } 1388 /* 1389 * Place the request for the upload interrupt in the last descriptor 1390 * in the chain. This way, if we're chaining several packets at once, 1391 * we'll only get an interupt once for the whole chain rather than 1392 * once for each packet. 1393 */ 1394 MY_TXCTL(cur_tx) |= MY_TXIC; 1395 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC; 1396 sc->my_cdata.my_tx_tail = cur_tx; 1397 if (sc->my_cdata.my_tx_head == NULL) 1398 sc->my_cdata.my_tx_head = start_tx; 1399 MY_TXOWN(start_tx) = MY_OWNByNIC; 1400 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */ 1401 1402 /* 1403 * Set a timeout in case the chip goes out to lunch. 1404 */ 1405 ifp->if_timer = 5; 1406 1407 crit_exit(); 1408 } 1409 1410 static void 1411 my_init(void *xsc) 1412 { 1413 struct my_softc *sc = xsc; 1414 struct ifnet *ifp = &sc->arpcom.ac_if; 1415 u_int16_t phy_bmcr = 0; 1416 1417 crit_enter(); 1418 if (sc->my_autoneg) { 1419 crit_exit(); 1420 return; 1421 } 1422 if (sc->my_pinfo != NULL) 1423 phy_bmcr = my_phy_readreg(sc, PHY_BMCR); 1424 /* 1425 * Cancel pending I/O and free all RX/TX buffers. 1426 */ 1427 my_stop(sc); 1428 my_reset(sc); 1429 1430 /* 1431 * Set cache alignment and burst length. 1432 */ 1433 #if 0 /* 89/9/1 modify, */ 1434 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512); 1435 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF); 1436 #endif 1437 CSR_WRITE_4(sc, MY_BCR, MY_PBL8); 1438 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512); 1439 /* 1440 * 89/12/29 add, for mtd891, 1441 */ 1442 if (sc->my_info->my_did == MTD891ID) { 1443 MY_SETBIT(sc, MY_BCR, MY_PROG); 1444 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced); 1445 } 1446 my_setcfg(sc, phy_bmcr); 1447 /* Init circular RX list. */ 1448 if (my_list_rx_init(sc) == ENOBUFS) { 1449 printf("my%d: init failed: no memory for rx buffers\n", 1450 sc->my_unit); 1451 my_stop(sc); 1452 crit_exit(); 1453 return; 1454 } 1455 /* Init TX descriptors. */ 1456 my_list_tx_init(sc); 1457 1458 /* If we want promiscuous mode, set the allframes bit. */ 1459 if (ifp->if_flags & IFF_PROMISC) 1460 MY_SETBIT(sc, MY_TCRRCR, MY_PROM); 1461 else 1462 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM); 1463 1464 /* 1465 * Set capture broadcast bit to capture broadcast frames. 1466 */ 1467 if (ifp->if_flags & IFF_BROADCAST) 1468 MY_SETBIT(sc, MY_TCRRCR, MY_AB); 1469 else 1470 MY_CLRBIT(sc, MY_TCRRCR, MY_AB); 1471 1472 /* 1473 * Program the multicast filter, if necessary. 1474 */ 1475 my_setmulti(sc); 1476 1477 /* 1478 * Load the address of the RX list. 1479 */ 1480 MY_CLRBIT(sc, MY_TCRRCR, MY_RE); 1481 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0])); 1482 1483 /* 1484 * Enable interrupts. 1485 */ 1486 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1487 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF); 1488 1489 /* Enable receiver and transmitter. */ 1490 MY_SETBIT(sc, MY_TCRRCR, MY_RE); 1491 MY_CLRBIT(sc, MY_TCRRCR, MY_TE); 1492 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0])); 1493 MY_SETBIT(sc, MY_TCRRCR, MY_TE); 1494 1495 /* Restore state of BMCR */ 1496 if (sc->my_pinfo != NULL) 1497 my_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1498 ifp->if_flags |= IFF_RUNNING; 1499 ifp->if_flags &= ~IFF_OACTIVE; 1500 crit_exit(); 1501 } 1502 1503 /* 1504 * Set media options. 1505 */ 1506 1507 static int 1508 my_ifmedia_upd(struct ifnet * ifp) 1509 { 1510 struct my_softc *sc = ifp->if_softc; 1511 struct ifmedia *ifm = &sc->ifmedia; 1512 1513 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1514 return (EINVAL); 1515 1516 crit_enter(); 1517 1518 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1519 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1520 else 1521 my_setmode_mii(sc, ifm->ifm_media); 1522 1523 crit_exit(); 1524 1525 return (0); 1526 } 1527 1528 /* 1529 * Report current media status. 1530 */ 1531 1532 static void 1533 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr) 1534 { 1535 struct my_softc *sc = ifp->if_softc; 1536 u_int16_t advert = 0, ability = 0; 1537 1538 crit_enter(); 1539 1540 ifmr->ifm_active = IFM_ETHER; 1541 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1542 #if 0 /* this version did not support 1000M, */ 1543 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000) 1544 ifmr->ifm_active = IFM_ETHER | IFM_1000TX; 1545 #endif 1546 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1547 ifmr->ifm_active = IFM_ETHER | IFM_100_TX; 1548 else 1549 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1550 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1551 ifmr->ifm_active |= IFM_FDX; 1552 else 1553 ifmr->ifm_active |= IFM_HDX; 1554 1555 crit_exit(); 1556 1557 return; 1558 } 1559 ability = my_phy_readreg(sc, PHY_LPAR); 1560 advert = my_phy_readreg(sc, PHY_ANAR); 1561 1562 #if 0 /* this version did not support 1000M, */ 1563 if (sc->my_pinfo->my_vid = MarvellPHYID0) { 1564 ability2 = my_phy_readreg(sc, PHY_1000SR); 1565 if (ability2 & PHY_1000SR_1000BTXFULL) { 1566 advert = 0; 1567 ability = 0; 1568 ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_FDX; 1569 } else if (ability & PHY_1000SR_1000BTXHALF) { 1570 advert = 0; 1571 ability = 0; 1572 ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_HDX; 1573 } 1574 } 1575 #endif 1576 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) 1577 ifmr->ifm_active = IFM_ETHER | IFM_100_T4; 1578 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) 1579 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1580 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) 1581 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1582 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) 1583 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1584 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) 1585 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1586 1587 crit_exit(); 1588 } 1589 1590 static int 1591 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data, struct ucred *cr) 1592 { 1593 struct my_softc *sc = ifp->if_softc; 1594 struct ifreq *ifr = (struct ifreq *) data; 1595 int error = 0; 1596 1597 crit_enter(); 1598 switch (command) { 1599 case SIOCSIFFLAGS: 1600 if (ifp->if_flags & IFF_UP) 1601 my_init(sc); 1602 else if (ifp->if_flags & IFF_RUNNING) 1603 my_stop(sc); 1604 error = 0; 1605 break; 1606 case SIOCADDMULTI: 1607 case SIOCDELMULTI: 1608 my_setmulti(sc); 1609 error = 0; 1610 break; 1611 case SIOCGIFMEDIA: 1612 case SIOCSIFMEDIA: 1613 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1614 break; 1615 default: 1616 error = ether_ioctl(ifp, command, data); 1617 break; 1618 } 1619 1620 crit_exit(); 1621 return (error); 1622 } 1623 1624 static void 1625 my_watchdog(struct ifnet * ifp) 1626 { 1627 struct my_softc *sc = ifp->if_softc; 1628 1629 crit_enter(); 1630 1631 if (sc->my_autoneg) { 1632 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1); 1633 crit_exit(); 1634 return; 1635 } 1636 ifp->if_oerrors++; 1637 printf("my%d: watchdog timeout\n", sc->my_unit); 1638 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1639 printf("my%d: no carrier - transceiver cable problem?\n", 1640 sc->my_unit); 1641 my_stop(sc); 1642 my_reset(sc); 1643 my_init(sc); 1644 if (!ifq_is_empty(&ifp->if_snd)) 1645 my_start(ifp); 1646 crit_exit(); 1647 } 1648 1649 1650 /* 1651 * Stop the adapter and free any mbufs allocated to the RX and TX lists. 1652 */ 1653 static void 1654 my_stop(struct my_softc * sc) 1655 { 1656 struct ifnet *ifp = &sc->arpcom.ac_if; 1657 int i; 1658 1659 ifp->if_timer = 0; 1660 1661 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE)); 1662 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1663 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000); 1664 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000); 1665 1666 /* 1667 * Free data in the RX lists. 1668 */ 1669 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1670 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) { 1671 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf); 1672 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL; 1673 } 1674 } 1675 bzero((char *)&sc->my_ldata->my_rx_list, 1676 sizeof(sc->my_ldata->my_rx_list)); 1677 /* 1678 * Free the TX list buffers. 1679 */ 1680 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1681 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) { 1682 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf); 1683 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL; 1684 } 1685 } 1686 bzero((char *)&sc->my_ldata->my_tx_list, 1687 sizeof(sc->my_ldata->my_tx_list)); 1688 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1689 } 1690 1691 /* 1692 * Stop all chip I/O so that the kernel's probe routines don't get confused 1693 * by errant DMAs when rebooting. 1694 */ 1695 static void 1696 my_shutdown(device_t dev) 1697 { 1698 struct my_softc *sc; 1699 1700 sc = device_get_softc(dev); 1701 my_stop(sc); 1702 return; 1703 } 1704