1 /* 2 * Copyright (c) 2002 Myson Technology Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/ 27 * 28 * $FreeBSD: src/sys/dev/my/if_my.c,v 1.2.2.4 2002/04/17 02:05:27 julian Exp $ 29 * $DragonFly: src/sys/dev/netif/my/if_my.c,v 1.27 2006/12/22 23:26:21 swildner Exp $ 30 * 31 * Myson fast ethernet PCI NIC driver 32 * 33 * $Id: if_my.c,v 1.40 2001/11/30 03:55:00 <yen_cw@myson.com.tw> wpaul Exp $ 34 */ 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/queue.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/serialize.h> 46 #include <sys/bus.h> 47 #include <sys/rman.h> 48 49 #include <sys/thread2.h> 50 51 #include <net/if.h> 52 #include <net/ifq_var.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_media.h> 56 #include <net/if_dl.h> 57 #include <net/bpf.h> 58 59 #include <vm/vm.h> /* for vtophys */ 60 #include <vm/pmap.h> /* for vtophys */ 61 #include <machine/clock.h> /* for DELAY */ 62 63 #include <bus/pci/pcireg.h> 64 #include <bus/pci/pcivar.h> 65 66 #include "../mii_layer/mii.h" 67 #include "../mii_layer/miivar.h" 68 69 #include "miibus_if.h" 70 71 /* 72 * #define MY_USEIOSPACE 73 */ 74 75 static int MY_USEIOSPACE = 1; 76 77 #if (MY_USEIOSPACE) 78 #define MY_RES SYS_RES_IOPORT 79 #define MY_RID MY_PCI_LOIO 80 #else 81 #define MY_RES SYS_RES_MEMORY 82 #define MY_RID MY_PCI_LOMEM 83 #endif 84 85 86 #include "if_myreg.h" 87 88 /* 89 * Various supported device vendors/types and their names. 90 */ 91 static struct my_type my_devs[] = { 92 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"}, 93 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"}, 94 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"}, 95 {0, 0, NULL} 96 }; 97 98 /* 99 * Various supported PHY vendors/types and their names. Note that this driver 100 * will work with pretty much any MII-compliant PHY, so failure to positively 101 * identify the chip is not a fatal error. 102 */ 103 static struct my_type my_phys[] = { 104 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"}, 105 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"}, 106 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"}, 107 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"}, 108 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"}, 109 {0, 0, "<MII-compliant physical interface>"} 110 }; 111 112 static int my_probe(device_t); 113 static int my_attach(device_t); 114 static int my_detach(device_t); 115 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *); 116 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *); 117 static void my_rxeof(struct my_softc *); 118 static void my_txeof(struct my_softc *); 119 static void my_txeoc(struct my_softc *); 120 static void my_intr(void *); 121 static void my_start(struct ifnet *); 122 static int my_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 123 static void my_init(void *); 124 static void my_stop(struct my_softc *); 125 static void my_watchdog(struct ifnet *); 126 static void my_shutdown(device_t); 127 static int my_ifmedia_upd(struct ifnet *); 128 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *); 129 static u_int16_t my_phy_readreg(struct my_softc *, int); 130 static void my_phy_writereg(struct my_softc *, int, int); 131 static void my_autoneg_xmit(struct my_softc *); 132 static void my_autoneg_mii(struct my_softc *, int, int); 133 static void my_setmode_mii(struct my_softc *, int); 134 static void my_getmode_mii(struct my_softc *); 135 static void my_setcfg(struct my_softc *, int); 136 static u_int8_t my_calchash(caddr_t); 137 static void my_setmulti(struct my_softc *); 138 static void my_reset(struct my_softc *); 139 static int my_list_rx_init(struct my_softc *); 140 static int my_list_tx_init(struct my_softc *); 141 static long my_send_cmd_to_phy(struct my_softc *, int, int); 142 143 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 144 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 145 146 static device_method_t my_methods[] = { 147 /* Device interface */ 148 DEVMETHOD(device_probe, my_probe), 149 DEVMETHOD(device_attach, my_attach), 150 DEVMETHOD(device_detach, my_detach), 151 DEVMETHOD(device_shutdown, my_shutdown), 152 153 {0, 0} 154 }; 155 156 static driver_t my_driver = { 157 "my", 158 my_methods, 159 sizeof(struct my_softc) 160 }; 161 162 static devclass_t my_devclass; 163 164 DECLARE_DUMMY_MODULE(if_my); 165 DRIVER_MODULE(if_my, pci, my_driver, my_devclass, 0, 0); 166 167 static long 168 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad) 169 { 170 long miir; 171 int i; 172 int mask, data; 173 174 /* enable MII output */ 175 miir = CSR_READ_4(sc, MY_MANAGEMENT); 176 miir &= 0xfffffff0; 177 178 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO; 179 180 /* send 32 1's preamble */ 181 for (i = 0; i < 32; i++) { 182 /* low MDC; MDO is already high (miir) */ 183 miir &= ~MY_MASK_MIIR_MII_MDC; 184 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 185 186 /* high MDC */ 187 miir |= MY_MASK_MIIR_MII_MDC; 188 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 189 } 190 191 /* calculate ST+OP+PHYAD+REGAD+TA */ 192 data = opcode | (sc->my_phy_addr << 7) | (regad << 2); 193 194 /* sent out */ 195 mask = 0x8000; 196 while (mask) { 197 /* low MDC, prepare MDO */ 198 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 199 if (mask & data) 200 miir |= MY_MASK_MIIR_MII_MDO; 201 202 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 203 /* high MDC */ 204 miir |= MY_MASK_MIIR_MII_MDC; 205 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 206 DELAY(30); 207 208 /* next */ 209 mask >>= 1; 210 if (mask == 0x2 && opcode == MY_OP_READ) 211 miir &= ~MY_MASK_MIIR_MII_WRITE; 212 } 213 214 return miir; 215 } 216 217 218 static u_int16_t 219 my_phy_readreg(struct my_softc * sc, int reg) 220 { 221 long miir; 222 int mask, data; 223 224 if (sc->my_info->my_did == MTD803ID) 225 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2); 226 else { 227 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg); 228 229 /* read data */ 230 mask = 0x8000; 231 data = 0; 232 while (mask) { 233 /* low MDC */ 234 miir &= ~MY_MASK_MIIR_MII_MDC; 235 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 236 237 /* read MDI */ 238 miir = CSR_READ_4(sc, MY_MANAGEMENT); 239 if (miir & MY_MASK_MIIR_MII_MDI) 240 data |= mask; 241 242 /* high MDC, and wait */ 243 miir |= MY_MASK_MIIR_MII_MDC; 244 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 245 DELAY(30); 246 247 /* next */ 248 mask >>= 1; 249 } 250 251 /* low MDC */ 252 miir &= ~MY_MASK_MIIR_MII_MDC; 253 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 254 } 255 256 return (u_int16_t) data; 257 } 258 259 260 static void 261 my_phy_writereg(struct my_softc * sc, int reg, int data) 262 { 263 long miir; 264 int mask; 265 266 if (sc->my_info->my_did == MTD803ID) 267 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data); 268 else { 269 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg); 270 271 /* write data */ 272 mask = 0x8000; 273 while (mask) { 274 /* low MDC, prepare MDO */ 275 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 276 if (mask & data) 277 miir |= MY_MASK_MIIR_MII_MDO; 278 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 279 DELAY(1); 280 281 /* high MDC */ 282 miir |= MY_MASK_MIIR_MII_MDC; 283 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 284 DELAY(1); 285 286 /* next */ 287 mask >>= 1; 288 } 289 290 /* low MDC */ 291 miir &= ~MY_MASK_MIIR_MII_MDC; 292 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 293 } 294 } 295 296 static u_int8_t 297 my_calchash(caddr_t addr) 298 { 299 u_int32_t crc, carry; 300 int i, j; 301 u_int8_t c; 302 303 /* Compute CRC for the address value. */ 304 crc = 0xFFFFFFFF; /* initial value */ 305 306 for (i = 0; i < 6; i++) { 307 c = *(addr + i); 308 for (j = 0; j < 8; j++) { 309 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 310 crc <<= 1; 311 c >>= 1; 312 if (carry) 313 crc = (crc ^ 0x04c11db6) | carry; 314 } 315 } 316 317 /* 318 * return the filter bit position Note: I arrived at the following 319 * nonsense through experimentation. It's not the usual way to 320 * generate the bit position but it's the only thing I could come up 321 * with that works. 322 */ 323 return (~(crc >> 26) & 0x0000003F); 324 } 325 326 327 /* 328 * Program the 64-bit multicast hash filter. 329 */ 330 static void 331 my_setmulti(struct my_softc * sc) 332 { 333 struct ifnet *ifp = &sc->arpcom.ac_if; 334 int h = 0; 335 u_int32_t hashes[2] = {0, 0}; 336 struct ifmultiaddr *ifma; 337 u_int32_t rxfilt; 338 int mcnt = 0; 339 340 rxfilt = CSR_READ_4(sc, MY_TCRRCR); 341 342 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 343 rxfilt |= MY_AM; 344 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 345 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF); 346 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF); 347 348 return; 349 } 350 /* first, zot all the existing hash bits */ 351 CSR_WRITE_4(sc, MY_MAR0, 0); 352 CSR_WRITE_4(sc, MY_MAR1, 0); 353 354 /* now program new ones */ 355 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 356 if (ifma->ifma_addr->sa_family != AF_LINK) 357 continue; 358 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr)); 359 if (h < 32) 360 hashes[0] |= (1 << h); 361 else 362 hashes[1] |= (1 << (h - 32)); 363 mcnt++; 364 } 365 366 if (mcnt) 367 rxfilt |= MY_AM; 368 else 369 rxfilt &= ~MY_AM; 370 CSR_WRITE_4(sc, MY_MAR0, hashes[0]); 371 CSR_WRITE_4(sc, MY_MAR1, hashes[1]); 372 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 373 } 374 375 /* 376 * Initiate an autonegotiation session. 377 */ 378 static void 379 my_autoneg_xmit(struct my_softc * sc) 380 { 381 u_int16_t phy_sts = 0; 382 383 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 384 DELAY(500); 385 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 386 387 phy_sts = my_phy_readreg(sc, PHY_BMCR); 388 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR; 389 my_phy_writereg(sc, PHY_BMCR, phy_sts); 390 } 391 392 393 /* 394 * Invoke autonegotiation on a PHY. 395 */ 396 static void 397 my_autoneg_mii(struct my_softc * sc, int flag, int verbose) 398 { 399 u_int16_t phy_sts = 0, media, advert, ability; 400 u_int16_t ability2 = 0; 401 struct ifnet *ifp = &sc->arpcom.ac_if; 402 struct ifmedia *ifm = &sc->ifmedia; 403 404 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 405 406 #ifndef FORCE_AUTONEG_TFOUR 407 /* 408 * First, see if autoneg is supported. If not, there's no point in 409 * continuing. 410 */ 411 phy_sts = my_phy_readreg(sc, PHY_BMSR); 412 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 413 if (verbose) 414 kprintf("my%d: autonegotiation not supported\n", 415 sc->my_unit); 416 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 417 return; 418 } 419 #endif 420 switch (flag) { 421 case MY_FLAG_FORCEDELAY: 422 /* 423 * XXX Never use this option anywhere but in the probe 424 * routine: making the kernel stop dead in its tracks for 425 * three whole seconds after we've gone multi-user is really 426 * bad manners. 427 */ 428 my_autoneg_xmit(sc); 429 DELAY(5000000); 430 break; 431 case MY_FLAG_SCHEDDELAY: 432 /* 433 * Wait for the transmitter to go idle before starting an 434 * autoneg session, otherwise my_start() may clobber our 435 * timeout, and we don't want to allow transmission during an 436 * autoneg session since that can screw it up. 437 */ 438 if (sc->my_cdata.my_tx_head != NULL) { 439 sc->my_want_auto = 1; 440 return; 441 } 442 my_autoneg_xmit(sc); 443 ifp->if_timer = 5; 444 sc->my_autoneg = 1; 445 sc->my_want_auto = 0; 446 return; 447 case MY_FLAG_DELAYTIMEO: 448 ifp->if_timer = 0; 449 sc->my_autoneg = 0; 450 break; 451 default: 452 kprintf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag); 453 return; 454 } 455 456 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 457 if (verbose) 458 kprintf("my%d: autoneg complete, ", sc->my_unit); 459 phy_sts = my_phy_readreg(sc, PHY_BMSR); 460 } else { 461 if (verbose) 462 kprintf("my%d: autoneg not complete, ", sc->my_unit); 463 } 464 465 media = my_phy_readreg(sc, PHY_BMCR); 466 467 /* Link is good. Report modes and set duplex mode. */ 468 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 469 if (verbose) 470 kprintf("my%d: link status good. ", sc->my_unit); 471 advert = my_phy_readreg(sc, PHY_ANAR); 472 ability = my_phy_readreg(sc, PHY_LPAR); 473 if ((sc->my_pinfo->my_vid == MarvellPHYID0) || 474 (sc->my_pinfo->my_vid == LevelOnePHYID0)) { 475 ability2 = my_phy_readreg(sc, PHY_1000SR); 476 if (ability2 & PHY_1000SR_1000BTXFULL) { 477 advert = 0; 478 ability = 0; 479 /* 480 * this version did not support 1000M, 481 * ifm->ifm_media = 482 * IFM_ETHER | IFM_1000_T | IFM_FDX; 483 */ 484 ifm->ifm_media = 485 IFM_ETHER | IFM_100_TX | IFM_FDX; 486 media &= ~PHY_BMCR_SPEEDSEL; 487 media |= PHY_BMCR_1000; 488 media |= PHY_BMCR_DUPLEX; 489 kprintf("(full-duplex, 1000Mbps)\n"); 490 } else if (ability2 & PHY_1000SR_1000BTXHALF) { 491 advert = 0; 492 ability = 0; 493 /* 494 * this version did not support 1000M, 495 * ifm->ifm_media = IFM_ETHER | IFM_1000_T; 496 */ 497 ifm->ifm_media = IFM_ETHER | IFM_100_TX; 498 media &= ~PHY_BMCR_SPEEDSEL; 499 media &= ~PHY_BMCR_DUPLEX; 500 media |= PHY_BMCR_1000; 501 kprintf("(half-duplex, 1000Mbps)\n"); 502 } 503 } 504 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 505 ifm->ifm_media = IFM_ETHER | IFM_100_T4; 506 media |= PHY_BMCR_SPEEDSEL; 507 media &= ~PHY_BMCR_DUPLEX; 508 kprintf("(100baseT4)\n"); 509 } else if (advert & PHY_ANAR_100BTXFULL && 510 ability & PHY_ANAR_100BTXFULL) { 511 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 512 media |= PHY_BMCR_SPEEDSEL; 513 media |= PHY_BMCR_DUPLEX; 514 kprintf("(full-duplex, 100Mbps)\n"); 515 } else if (advert & PHY_ANAR_100BTXHALF && 516 ability & PHY_ANAR_100BTXHALF) { 517 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 518 media |= PHY_BMCR_SPEEDSEL; 519 media &= ~PHY_BMCR_DUPLEX; 520 kprintf("(half-duplex, 100Mbps)\n"); 521 } else if (advert & PHY_ANAR_10BTFULL && 522 ability & PHY_ANAR_10BTFULL) { 523 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 524 media &= ~PHY_BMCR_SPEEDSEL; 525 media |= PHY_BMCR_DUPLEX; 526 kprintf("(full-duplex, 10Mbps)\n"); 527 } else if (advert) { 528 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 529 media &= ~PHY_BMCR_SPEEDSEL; 530 media &= ~PHY_BMCR_DUPLEX; 531 kprintf("(half-duplex, 10Mbps)\n"); 532 } 533 media &= ~PHY_BMCR_AUTONEGENBL; 534 535 /* Set ASIC's duplex mode to match the PHY. */ 536 my_phy_writereg(sc, PHY_BMCR, media); 537 my_setcfg(sc, media); 538 } else { 539 if (verbose) 540 kprintf("my%d: no carrier\n", sc->my_unit); 541 } 542 543 my_init(sc); 544 if (sc->my_tx_pend) { 545 sc->my_autoneg = 0; 546 sc->my_tx_pend = 0; 547 my_start(ifp); 548 } 549 } 550 551 /* 552 * To get PHY ability. 553 */ 554 static void 555 my_getmode_mii(struct my_softc * sc) 556 { 557 struct ifnet *ifp = &sc->arpcom.ac_if; 558 u_int16_t bmsr; 559 560 bmsr = my_phy_readreg(sc, PHY_BMSR); 561 if (bootverbose) 562 kprintf("my%d: PHY status word: %x\n", sc->my_unit, bmsr); 563 564 /* fallback */ 565 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 566 567 if (bmsr & PHY_BMSR_10BTHALF) { 568 if (bootverbose) 569 kprintf("my%d: 10Mbps half-duplex mode supported\n", 570 sc->my_unit); 571 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 572 0, NULL); 573 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 574 } 575 if (bmsr & PHY_BMSR_10BTFULL) { 576 if (bootverbose) 577 kprintf("my%d: 10Mbps full-duplex mode supported\n", 578 sc->my_unit); 579 580 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 581 0, NULL); 582 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 583 } 584 if (bmsr & PHY_BMSR_100BTXHALF) { 585 if (bootverbose) 586 kprintf("my%d: 100Mbps half-duplex mode supported\n", 587 sc->my_unit); 588 ifp->if_baudrate = 100000000; 589 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 590 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 591 0, NULL); 592 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 593 } 594 if (bmsr & PHY_BMSR_100BTXFULL) { 595 if (bootverbose) 596 kprintf("my%d: 100Mbps full-duplex mode supported\n", 597 sc->my_unit); 598 ifp->if_baudrate = 100000000; 599 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 600 0, NULL); 601 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 602 } 603 /* Some also support 100BaseT4. */ 604 if (bmsr & PHY_BMSR_100BT4) { 605 if (bootverbose) 606 kprintf("my%d: 100baseT4 mode supported\n", sc->my_unit); 607 ifp->if_baudrate = 100000000; 608 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL); 609 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4; 610 #ifdef FORCE_AUTONEG_TFOUR 611 if (bootverbose) 612 kprintf("my%d: forcing on autoneg support for BT4\n", 613 sc->my_unit); 614 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL): 615 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 616 #endif 617 } 618 #if 0 /* this version did not support 1000M, */ 619 if (sc->my_pinfo->my_vid == MarvellPHYID0) { 620 if (bootverbose) 621 kprintf("my%d: 1000Mbps half-duplex mode supported\n", 622 sc->my_unit); 623 624 ifp->if_baudrate = 1000000000; 625 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 626 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX, 627 0, NULL); 628 if (bootverbose) 629 kprintf("my%d: 1000Mbps full-duplex mode supported\n", 630 sc->my_unit); 631 ifp->if_baudrate = 1000000000; 632 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 633 0, NULL); 634 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX; 635 } 636 #endif 637 if (bmsr & PHY_BMSR_CANAUTONEG) { 638 if (bootverbose) 639 kprintf("my%d: autoneg supported\n", sc->my_unit); 640 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 641 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 642 } 643 } 644 645 /* 646 * Set speed and duplex mode. 647 */ 648 static void 649 my_setmode_mii(struct my_softc * sc, int media) 650 { 651 struct ifnet *ifp = &sc->arpcom.ac_if; 652 u_int16_t bmcr; 653 654 /* 655 * If an autoneg session is in progress, stop it. 656 */ 657 if (sc->my_autoneg) { 658 kprintf("my%d: canceling autoneg session\n", sc->my_unit); 659 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0; 660 bmcr = my_phy_readreg(sc, PHY_BMCR); 661 bmcr &= ~PHY_BMCR_AUTONEGENBL; 662 my_phy_writereg(sc, PHY_BMCR, bmcr); 663 } 664 kprintf("my%d: selecting MII, ", sc->my_unit); 665 bmcr = my_phy_readreg(sc, PHY_BMCR); 666 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 | 667 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK); 668 669 #if 0 /* this version did not support 1000M, */ 670 if (IFM_SUBTYPE(media) == IFM_1000_T) { 671 kprintf("1000Mbps/T4, half-duplex\n"); 672 bmcr &= ~PHY_BMCR_SPEEDSEL; 673 bmcr &= ~PHY_BMCR_DUPLEX; 674 bmcr |= PHY_BMCR_1000; 675 } 676 #endif 677 if (IFM_SUBTYPE(media) == IFM_100_T4) { 678 kprintf("100Mbps/T4, half-duplex\n"); 679 bmcr |= PHY_BMCR_SPEEDSEL; 680 bmcr &= ~PHY_BMCR_DUPLEX; 681 } 682 if (IFM_SUBTYPE(media) == IFM_100_TX) { 683 kprintf("100Mbps, "); 684 bmcr |= PHY_BMCR_SPEEDSEL; 685 } 686 if (IFM_SUBTYPE(media) == IFM_10_T) { 687 kprintf("10Mbps, "); 688 bmcr &= ~PHY_BMCR_SPEEDSEL; 689 } 690 if ((media & IFM_GMASK) == IFM_FDX) { 691 kprintf("full duplex\n"); 692 bmcr |= PHY_BMCR_DUPLEX; 693 } else { 694 kprintf("half duplex\n"); 695 bmcr &= ~PHY_BMCR_DUPLEX; 696 } 697 my_phy_writereg(sc, PHY_BMCR, bmcr); 698 my_setcfg(sc, bmcr); 699 } 700 701 /* 702 * The Myson manual states that in order to fiddle with the 'full-duplex' and 703 * '100Mbps' bits in the netconfig register, we first have to put the 704 * transmit and/or receive logic in the idle state. 705 */ 706 static void 707 my_setcfg(struct my_softc * sc, int bmcr) 708 { 709 int i, restart = 0; 710 711 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { 712 restart = 1; 713 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE)); 714 for (i = 0; i < MY_TIMEOUT; i++) { 715 DELAY(10); 716 if (!(CSR_READ_4(sc, MY_TCRRCR) & 717 (MY_TXRUN | MY_RXRUN))) 718 break; 719 } 720 if (i == MY_TIMEOUT) 721 kprintf("my%d: failed to force tx and rx to idle \n", 722 sc->my_unit); 723 } 724 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000); 725 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10); 726 if (bmcr & PHY_BMCR_1000) 727 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000); 728 else if (!(bmcr & PHY_BMCR_SPEEDSEL)) 729 MY_SETBIT(sc, MY_TCRRCR, MY_PS10); 730 if (bmcr & PHY_BMCR_DUPLEX) 731 MY_SETBIT(sc, MY_TCRRCR, MY_FD); 732 else 733 MY_CLRBIT(sc, MY_TCRRCR, MY_FD); 734 if (restart) 735 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE); 736 } 737 738 static void 739 my_reset(struct my_softc * sc) 740 { 741 int i; 742 743 MY_SETBIT(sc, MY_BCR, MY_SWR); 744 for (i = 0; i < MY_TIMEOUT; i++) { 745 DELAY(10); 746 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) 747 break; 748 } 749 if (i == MY_TIMEOUT) 750 kprintf("m0x%d: reset never completed!\n", sc->my_unit); 751 752 /* Wait a little while for the chip to get its brains in order. */ 753 DELAY(1000); 754 } 755 756 /* 757 * Probe for a Myson chip. Check the PCI vendor and device IDs against our 758 * list and return a device name if we find a match. 759 */ 760 static int 761 my_probe(device_t dev) 762 { 763 struct my_type *t; 764 uint16_t vendor, product; 765 766 vendor = pci_get_vendor(dev); 767 product = pci_get_device(dev); 768 769 for (t = my_devs; t->my_name != NULL; t++) { 770 if (vendor == t->my_vid && product == t->my_did) { 771 device_set_desc(dev, t->my_name); 772 return (0); 773 } 774 } 775 776 return (ENXIO); 777 } 778 779 /* 780 * Attach the interface. Allocate softc structures, do ifmedia setup and 781 * ethernet/BPF attach. 782 */ 783 static int 784 my_attach(device_t dev) 785 { 786 int i; 787 u_char eaddr[ETHER_ADDR_LEN]; 788 u_int32_t command, iobase; 789 struct my_softc *sc; 790 struct ifnet *ifp; 791 int media = IFM_ETHER | IFM_100_TX | IFM_FDX; 792 unsigned int round; 793 caddr_t roundptr; 794 struct my_type *p; 795 u_int16_t phy_vid, phy_did, phy_sts = 0; 796 int rid, unit, error = 0; 797 struct my_type *t; 798 uint16_t vendor, product; 799 800 vendor = pci_get_vendor(dev); 801 product = pci_get_device(dev); 802 803 for (t = my_devs; t->my_name != NULL; t++) { 804 if (vendor == t->my_vid && product == t->my_did) 805 break; 806 } 807 808 if (t->my_name == NULL) 809 return(ENXIO); 810 811 sc = device_get_softc(dev); 812 unit = device_get_unit(dev); 813 814 /* 815 * Map control/status registers. 816 */ 817 command = pci_read_config(dev, PCIR_COMMAND, 4); 818 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 819 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4); 820 command = pci_read_config(dev, PCIR_COMMAND, 4); 821 822 if (t->my_did == MTD800ID) { 823 iobase = pci_read_config(dev, MY_PCI_LOIO, 4); 824 if (iobase & 0x300) 825 MY_USEIOSPACE = 0; 826 } 827 if (MY_USEIOSPACE) { 828 if (!(command & PCIM_CMD_PORTEN)) { 829 kprintf("my%d: failed to enable I/O ports!\n", unit); 830 error = ENXIO; 831 return(error); 832 } 833 } else { 834 if (!(command & PCIM_CMD_MEMEN)) { 835 kprintf("my%d: failed to enable memory mapping!\n", 836 unit); 837 error = ENXIO; 838 return(error); 839 } 840 } 841 842 rid = MY_RID; 843 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE); 844 845 if (sc->my_res == NULL) { 846 kprintf("my%d: couldn't map ports/memory\n", unit); 847 error = ENXIO; 848 goto fail; 849 } 850 sc->my_btag = rman_get_bustag(sc->my_res); 851 sc->my_bhandle = rman_get_bushandle(sc->my_res); 852 853 rid = 0; 854 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 855 RF_SHAREABLE | RF_ACTIVE); 856 857 if (sc->my_irq == NULL) { 858 kprintf("my%d: couldn't map interrupt\n", unit); 859 error = ENXIO; 860 goto fail; 861 } 862 863 sc->my_info = t; 864 865 /* Reset the adapter. */ 866 my_reset(sc); 867 868 /* 869 * Get station address 870 */ 871 for (i = 0; i < ETHER_ADDR_LEN; ++i) 872 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); 873 874 sc->my_unit = unit; 875 876 sc->my_ldata_ptr = kmalloc(sizeof(struct my_list_data) + 8, 877 M_DEVBUF, M_WAITOK); 878 if (sc->my_ldata_ptr == NULL) { 879 kprintf("my%d: no memory for list buffers!\n", unit); 880 error = ENXIO; 881 goto fail; 882 } 883 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr; 884 round = (unsigned int)sc->my_ldata_ptr & 0xF; 885 roundptr = sc->my_ldata_ptr; 886 for (i = 0; i < 8; i++) { 887 if (round % 8) { 888 round++; 889 roundptr++; 890 } else 891 break; 892 } 893 sc->my_ldata = (struct my_list_data *) roundptr; 894 bzero(sc->my_ldata, sizeof(struct my_list_data)); 895 896 ifp = &sc->arpcom.ac_if; 897 ifp->if_softc = sc; 898 if_initname(ifp, "my", unit); 899 ifp->if_mtu = ETHERMTU; 900 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 901 ifp->if_ioctl = my_ioctl; 902 ifp->if_start = my_start; 903 ifp->if_watchdog = my_watchdog; 904 ifp->if_init = my_init; 905 ifp->if_baudrate = 10000000; 906 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 907 ifq_set_ready(&ifp->if_snd); 908 909 if (sc->my_info->my_did == MTD803ID) 910 sc->my_pinfo = my_phys; 911 else { 912 if (bootverbose) 913 kprintf("my%d: probing for a PHY\n", sc->my_unit); 914 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) { 915 if (bootverbose) 916 kprintf("my%d: checking address: %d\n", 917 sc->my_unit, i); 918 sc->my_phy_addr = i; 919 phy_sts = my_phy_readreg(sc, PHY_BMSR); 920 if ((phy_sts != 0) && (phy_sts != 0xffff)) 921 break; 922 else 923 phy_sts = 0; 924 } 925 if (phy_sts) { 926 phy_vid = my_phy_readreg(sc, PHY_VENID); 927 phy_did = my_phy_readreg(sc, PHY_DEVID); 928 if (bootverbose) { 929 kprintf("my%d: found PHY at address %d, ", 930 sc->my_unit, sc->my_phy_addr); 931 kprintf("vendor id: %x device id: %x\n", 932 phy_vid, phy_did); 933 } 934 p = my_phys; 935 while (p->my_vid) { 936 if (phy_vid == p->my_vid) { 937 sc->my_pinfo = p; 938 break; 939 } 940 p++; 941 } 942 if (sc->my_pinfo == NULL) 943 sc->my_pinfo = &my_phys[PHY_UNKNOWN]; 944 if (bootverbose) 945 kprintf("my%d: PHY type: %s\n", 946 sc->my_unit, sc->my_pinfo->my_name); 947 } else { 948 kprintf("my%d: MII without any phy!\n", sc->my_unit); 949 error = ENXIO; 950 goto fail; 951 } 952 } 953 954 /* Do ifmedia setup. */ 955 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts); 956 my_getmode_mii(sc); 957 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1); 958 media = sc->ifmedia.ifm_media; 959 my_stop(sc); 960 ifmedia_set(&sc->ifmedia, media); 961 962 ether_ifattach(ifp, eaddr, NULL); 963 964 error = bus_setup_intr(dev, sc->my_irq, INTR_NETSAFE, 965 my_intr, sc, &sc->my_intrhand, 966 ifp->if_serializer); 967 if (error) { 968 ether_ifdetach(ifp); 969 kprintf("my%d: couldn't set up irq\n", unit); 970 goto fail; 971 } 972 973 return (0); 974 975 fail: 976 my_detach(dev); 977 return (error); 978 } 979 980 static int 981 my_detach(device_t dev) 982 { 983 struct my_softc *sc = device_get_softc(dev); 984 struct ifnet *ifp = &sc->arpcom.ac_if; 985 986 if (device_is_attached(dev)) { 987 lwkt_serialize_enter(ifp->if_serializer); 988 my_stop(sc); 989 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand); 990 lwkt_serialize_exit(ifp->if_serializer); 991 992 ether_ifdetach(ifp); 993 } 994 995 if (sc->my_irq) 996 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 997 if (sc->my_res) 998 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 999 1000 return (0); 1001 } 1002 1003 1004 /* 1005 * Initialize the transmit descriptors. 1006 */ 1007 static int 1008 my_list_tx_init(struct my_softc * sc) 1009 { 1010 struct my_chain_data *cd; 1011 struct my_list_data *ld; 1012 int i; 1013 1014 cd = &sc->my_cdata; 1015 ld = sc->my_ldata; 1016 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1017 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i]; 1018 if (i == (MY_TX_LIST_CNT - 1)) 1019 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0]; 1020 else 1021 cd->my_tx_chain[i].my_nextdesc = 1022 &cd->my_tx_chain[i + 1]; 1023 } 1024 cd->my_tx_free = &cd->my_tx_chain[0]; 1025 cd->my_tx_tail = cd->my_tx_head = NULL; 1026 return (0); 1027 } 1028 1029 /* 1030 * Initialize the RX descriptors and allocate mbufs for them. Note that we 1031 * arrange the descriptors in a closed ring, so that the last descriptor 1032 * points back to the first. 1033 */ 1034 static int 1035 my_list_rx_init(struct my_softc * sc) 1036 { 1037 struct my_chain_data *cd; 1038 struct my_list_data *ld; 1039 int i; 1040 1041 cd = &sc->my_cdata; 1042 ld = sc->my_ldata; 1043 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1044 cd->my_rx_chain[i].my_ptr = 1045 (struct my_desc *) & ld->my_rx_list[i]; 1046 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) 1047 return (ENOBUFS); 1048 if (i == (MY_RX_LIST_CNT - 1)) { 1049 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0]; 1050 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]); 1051 } else { 1052 cd->my_rx_chain[i].my_nextdesc = 1053 &cd->my_rx_chain[i + 1]; 1054 ld->my_rx_list[i].my_next = 1055 vtophys(&ld->my_rx_list[i + 1]); 1056 } 1057 } 1058 cd->my_rx_head = &cd->my_rx_chain[0]; 1059 return (0); 1060 } 1061 1062 /* 1063 * Initialize an RX descriptor and attach an MBUF cluster. 1064 */ 1065 static int 1066 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c) 1067 { 1068 struct mbuf *m_new = NULL; 1069 1070 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1071 if (m_new == NULL) { 1072 kprintf("my%d: no memory for rx list -- packet dropped!\n", 1073 sc->my_unit); 1074 return (ENOBUFS); 1075 } 1076 MCLGET(m_new, MB_DONTWAIT); 1077 if (!(m_new->m_flags & M_EXT)) { 1078 kprintf("my%d: no memory for rx list -- packet dropped!\n", 1079 sc->my_unit); 1080 m_freem(m_new); 1081 return (ENOBUFS); 1082 } 1083 c->my_mbuf = m_new; 1084 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t)); 1085 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift; 1086 c->my_ptr->my_status = MY_OWNByNIC; 1087 return (0); 1088 } 1089 1090 /* 1091 * A frame has been uploaded: pass the resulting mbuf chain up to the higher 1092 * level protocols. 1093 */ 1094 static void 1095 my_rxeof(struct my_softc * sc) 1096 { 1097 struct mbuf *m; 1098 struct ifnet *ifp = &sc->arpcom.ac_if; 1099 struct my_chain_onefrag *cur_rx; 1100 int total_len = 0; 1101 u_int32_t rxstat; 1102 1103 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status) 1104 & MY_OWNByNIC)) { 1105 cur_rx = sc->my_cdata.my_rx_head; 1106 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc; 1107 1108 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */ 1109 ifp->if_ierrors++; 1110 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1111 continue; 1112 } 1113 /* No errors; receive the packet. */ 1114 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift; 1115 total_len -= ETHER_CRC_LEN; 1116 1117 if (total_len < MINCLSIZE) { 1118 m = m_devget(mtod(cur_rx->my_mbuf, char *), 1119 total_len, 0, ifp, NULL); 1120 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1121 if (m == NULL) { 1122 ifp->if_ierrors++; 1123 continue; 1124 } 1125 } else { 1126 m = cur_rx->my_mbuf; 1127 /* 1128 * Try to conjure up a new mbuf cluster. If that 1129 * fails, it means we have an out of memory condition 1130 * and should leave the buffer in place and continue. 1131 * This will result in a lost packet, but there's 1132 * little else we can do in this situation. 1133 */ 1134 if (my_newbuf(sc, cur_rx) == ENOBUFS) { 1135 ifp->if_ierrors++; 1136 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1137 continue; 1138 } 1139 m->m_pkthdr.rcvif = ifp; 1140 m->m_pkthdr.len = m->m_len = total_len; 1141 } 1142 ifp->if_ipackets++; 1143 ifp->if_input(ifp, m); 1144 } 1145 } 1146 1147 1148 /* 1149 * A frame was downloaded to the chip. It's safe for us to clean up the list 1150 * buffers. 1151 */ 1152 static void 1153 my_txeof(struct my_softc * sc) 1154 { 1155 struct ifnet *ifp = &sc->arpcom.ac_if; 1156 struct my_chain *cur_tx; 1157 1158 /* Clear the timeout timer. */ 1159 ifp->if_timer = 0; 1160 if (sc->my_cdata.my_tx_head == NULL) 1161 return; 1162 /* 1163 * Go through our tx list and free mbufs for those frames that have 1164 * been transmitted. 1165 */ 1166 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) { 1167 u_int32_t txstat; 1168 1169 cur_tx = sc->my_cdata.my_tx_head; 1170 txstat = MY_TXSTATUS(cur_tx); 1171 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT) 1172 break; 1173 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { 1174 if (txstat & MY_TXERR) { 1175 ifp->if_oerrors++; 1176 if (txstat & MY_EC) /* excessive collision */ 1177 ifp->if_collisions++; 1178 if (txstat & MY_LC) /* late collision */ 1179 ifp->if_collisions++; 1180 } 1181 ifp->if_collisions += (txstat & MY_NCRMASK) >> 1182 MY_NCRShift; 1183 } 1184 ifp->if_opackets++; 1185 m_freem(cur_tx->my_mbuf); 1186 cur_tx->my_mbuf = NULL; 1187 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) { 1188 sc->my_cdata.my_tx_head = NULL; 1189 sc->my_cdata.my_tx_tail = NULL; 1190 break; 1191 } 1192 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc; 1193 } 1194 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { 1195 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask); 1196 } 1197 } 1198 1199 /* 1200 * TX 'end of channel' interrupt handler. 1201 */ 1202 static void 1203 my_txeoc(struct my_softc * sc) 1204 { 1205 struct ifnet *ifp = &sc->arpcom.ac_if; 1206 1207 ifp->if_timer = 0; 1208 if (sc->my_cdata.my_tx_head == NULL) { 1209 ifp->if_flags &= ~IFF_OACTIVE; 1210 sc->my_cdata.my_tx_tail = NULL; 1211 if (sc->my_want_auto) 1212 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1213 } else { 1214 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) { 1215 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC; 1216 ifp->if_timer = 5; 1217 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); 1218 } 1219 } 1220 } 1221 1222 static void 1223 my_intr(void *arg) 1224 { 1225 struct my_softc *sc = arg; 1226 struct ifnet *ifp = &sc->arpcom.ac_if; 1227 u_int32_t status; 1228 1229 if (!(ifp->if_flags & IFF_UP)) 1230 return; 1231 1232 /* Disable interrupts. */ 1233 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1234 1235 for (;;) { 1236 status = CSR_READ_4(sc, MY_ISR); 1237 status &= MY_INTRS; 1238 if (status) 1239 CSR_WRITE_4(sc, MY_ISR, status); 1240 else 1241 break; 1242 1243 if (status & MY_RI) /* receive interrupt */ 1244 my_rxeof(sc); 1245 1246 if ((status & MY_RBU) || (status & MY_RxErr)) { 1247 /* rx buffer unavailable or rx error */ 1248 ifp->if_ierrors++; 1249 #ifdef foo 1250 my_stop(sc); 1251 my_reset(sc); 1252 my_init(sc); 1253 #endif 1254 } 1255 if (status & MY_TI) /* tx interrupt */ 1256 my_txeof(sc); 1257 if (status & MY_ETI) /* tx early interrupt */ 1258 my_txeof(sc); 1259 if (status & MY_TBU) /* tx buffer unavailable */ 1260 my_txeoc(sc); 1261 1262 #if 0 /* 90/1/18 delete */ 1263 if (status & MY_FBE) { 1264 my_reset(sc); 1265 my_init(sc); 1266 } 1267 #endif 1268 1269 } 1270 1271 /* Re-enable interrupts. */ 1272 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1273 if (!ifq_is_empty(&ifp->if_snd)) 1274 my_start(ifp); 1275 } 1276 1277 /* 1278 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1279 * pointers to the fragment pointers. 1280 */ 1281 static int 1282 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head) 1283 { 1284 struct my_desc *f = NULL; 1285 int total_len; 1286 struct mbuf *m, *m_new = NULL; 1287 1288 /* calculate the total tx pkt length */ 1289 total_len = 0; 1290 for (m = m_head; m != NULL; m = m->m_next) 1291 total_len += m->m_len; 1292 /* 1293 * Start packing the mbufs in this chain into the fragment pointers. 1294 * Stop when we run out of fragments or hit the end of the mbuf 1295 * chain. 1296 */ 1297 m = m_head; 1298 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1299 if (m_new == NULL) { 1300 kprintf("my%d: no memory for tx list", sc->my_unit); 1301 return (1); 1302 } 1303 if (m_head->m_pkthdr.len > MHLEN) { 1304 MCLGET(m_new, MB_DONTWAIT); 1305 if (!(m_new->m_flags & M_EXT)) { 1306 m_freem(m_new); 1307 kprintf("my%d: no memory for tx list", sc->my_unit); 1308 return (1); 1309 } 1310 } 1311 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1312 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1313 m_freem(m_head); 1314 m_head = m_new; 1315 f = &c->my_ptr->my_frag[0]; 1316 f->my_status = 0; 1317 f->my_data = vtophys(mtod(m_new, caddr_t)); 1318 total_len = m_new->m_len; 1319 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable; 1320 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */ 1321 f->my_ctl |= total_len; /* buffer size */ 1322 /* 89/12/29 add, for mtd891 *//* [ 89? ] */ 1323 if (sc->my_info->my_did == MTD891ID) 1324 f->my_ctl |= MY_ETIControl | MY_RetryTxLC; 1325 c->my_mbuf = m_head; 1326 c->my_lastdesc = 0; 1327 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]); 1328 return (0); 1329 } 1330 1331 /* 1332 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1333 * to the mbuf data regions directly in the transmit lists. We also save a 1334 * copy of the pointers since the transmit list fragment pointers are 1335 * physical addresses. 1336 */ 1337 static void 1338 my_start(struct ifnet * ifp) 1339 { 1340 struct my_softc *sc = ifp->if_softc; 1341 struct mbuf *m_head = NULL; 1342 struct my_chain *cur_tx = NULL, *start_tx; 1343 1344 crit_enter(); 1345 1346 if (sc->my_autoneg) { 1347 sc->my_tx_pend = 1; 1348 crit_exit(); 1349 return; 1350 } 1351 /* 1352 * Check for an available queue slot. If there are none, punt. 1353 */ 1354 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) { 1355 ifp->if_flags |= IFF_OACTIVE; 1356 crit_exit(); 1357 return; 1358 } 1359 1360 start_tx = sc->my_cdata.my_tx_free; 1361 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) { 1362 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1363 if (m_head == NULL) 1364 break; 1365 1366 /* Pick a descriptor off the free list. */ 1367 cur_tx = sc->my_cdata.my_tx_free; 1368 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc; 1369 1370 /* Pack the data into the descriptor. */ 1371 my_encap(sc, cur_tx, m_head); 1372 1373 if (cur_tx != start_tx) 1374 MY_TXOWN(cur_tx) = MY_OWNByNIC; 1375 BPF_MTAP(ifp, cur_tx->my_mbuf); 1376 } 1377 /* 1378 * If there are no packets queued, bail. 1379 */ 1380 if (cur_tx == NULL) { 1381 crit_exit(); 1382 return; 1383 } 1384 /* 1385 * Place the request for the upload interrupt in the last descriptor 1386 * in the chain. This way, if we're chaining several packets at once, 1387 * we'll only get an interupt once for the whole chain rather than 1388 * once for each packet. 1389 */ 1390 MY_TXCTL(cur_tx) |= MY_TXIC; 1391 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC; 1392 sc->my_cdata.my_tx_tail = cur_tx; 1393 if (sc->my_cdata.my_tx_head == NULL) 1394 sc->my_cdata.my_tx_head = start_tx; 1395 MY_TXOWN(start_tx) = MY_OWNByNIC; 1396 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */ 1397 1398 /* 1399 * Set a timeout in case the chip goes out to lunch. 1400 */ 1401 ifp->if_timer = 5; 1402 1403 crit_exit(); 1404 } 1405 1406 static void 1407 my_init(void *xsc) 1408 { 1409 struct my_softc *sc = xsc; 1410 struct ifnet *ifp = &sc->arpcom.ac_if; 1411 u_int16_t phy_bmcr = 0; 1412 1413 crit_enter(); 1414 if (sc->my_autoneg) { 1415 crit_exit(); 1416 return; 1417 } 1418 if (sc->my_pinfo != NULL) 1419 phy_bmcr = my_phy_readreg(sc, PHY_BMCR); 1420 /* 1421 * Cancel pending I/O and free all RX/TX buffers. 1422 */ 1423 my_stop(sc); 1424 my_reset(sc); 1425 1426 /* 1427 * Set cache alignment and burst length. 1428 */ 1429 #if 0 /* 89/9/1 modify, */ 1430 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512); 1431 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF); 1432 #endif 1433 CSR_WRITE_4(sc, MY_BCR, MY_PBL8); 1434 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512); 1435 /* 1436 * 89/12/29 add, for mtd891, 1437 */ 1438 if (sc->my_info->my_did == MTD891ID) { 1439 MY_SETBIT(sc, MY_BCR, MY_PROG); 1440 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced); 1441 } 1442 my_setcfg(sc, phy_bmcr); 1443 /* Init circular RX list. */ 1444 if (my_list_rx_init(sc) == ENOBUFS) { 1445 kprintf("my%d: init failed: no memory for rx buffers\n", 1446 sc->my_unit); 1447 my_stop(sc); 1448 crit_exit(); 1449 return; 1450 } 1451 /* Init TX descriptors. */ 1452 my_list_tx_init(sc); 1453 1454 /* If we want promiscuous mode, set the allframes bit. */ 1455 if (ifp->if_flags & IFF_PROMISC) 1456 MY_SETBIT(sc, MY_TCRRCR, MY_PROM); 1457 else 1458 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM); 1459 1460 /* 1461 * Set capture broadcast bit to capture broadcast frames. 1462 */ 1463 if (ifp->if_flags & IFF_BROADCAST) 1464 MY_SETBIT(sc, MY_TCRRCR, MY_AB); 1465 else 1466 MY_CLRBIT(sc, MY_TCRRCR, MY_AB); 1467 1468 /* 1469 * Program the multicast filter, if necessary. 1470 */ 1471 my_setmulti(sc); 1472 1473 /* 1474 * Load the address of the RX list. 1475 */ 1476 MY_CLRBIT(sc, MY_TCRRCR, MY_RE); 1477 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0])); 1478 1479 /* 1480 * Enable interrupts. 1481 */ 1482 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1483 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF); 1484 1485 /* Enable receiver and transmitter. */ 1486 MY_SETBIT(sc, MY_TCRRCR, MY_RE); 1487 MY_CLRBIT(sc, MY_TCRRCR, MY_TE); 1488 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0])); 1489 MY_SETBIT(sc, MY_TCRRCR, MY_TE); 1490 1491 /* Restore state of BMCR */ 1492 if (sc->my_pinfo != NULL) 1493 my_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1494 ifp->if_flags |= IFF_RUNNING; 1495 ifp->if_flags &= ~IFF_OACTIVE; 1496 crit_exit(); 1497 } 1498 1499 /* 1500 * Set media options. 1501 */ 1502 1503 static int 1504 my_ifmedia_upd(struct ifnet * ifp) 1505 { 1506 struct my_softc *sc = ifp->if_softc; 1507 struct ifmedia *ifm = &sc->ifmedia; 1508 1509 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1510 return (EINVAL); 1511 1512 crit_enter(); 1513 1514 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1515 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1516 else 1517 my_setmode_mii(sc, ifm->ifm_media); 1518 1519 crit_exit(); 1520 1521 return (0); 1522 } 1523 1524 /* 1525 * Report current media status. 1526 */ 1527 1528 static void 1529 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr) 1530 { 1531 struct my_softc *sc = ifp->if_softc; 1532 u_int16_t advert = 0, ability = 0; 1533 1534 crit_enter(); 1535 1536 ifmr->ifm_active = IFM_ETHER; 1537 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1538 #if 0 /* this version did not support 1000M, */ 1539 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000) 1540 ifmr->ifm_active = IFM_ETHER | IFM_1000TX; 1541 #endif 1542 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1543 ifmr->ifm_active = IFM_ETHER | IFM_100_TX; 1544 else 1545 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1546 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1547 ifmr->ifm_active |= IFM_FDX; 1548 else 1549 ifmr->ifm_active |= IFM_HDX; 1550 1551 crit_exit(); 1552 1553 return; 1554 } 1555 ability = my_phy_readreg(sc, PHY_LPAR); 1556 advert = my_phy_readreg(sc, PHY_ANAR); 1557 1558 #if 0 /* this version did not support 1000M, */ 1559 if (sc->my_pinfo->my_vid = MarvellPHYID0) { 1560 ability2 = my_phy_readreg(sc, PHY_1000SR); 1561 if (ability2 & PHY_1000SR_1000BTXFULL) { 1562 advert = 0; 1563 ability = 0; 1564 ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_FDX; 1565 } else if (ability & PHY_1000SR_1000BTXHALF) { 1566 advert = 0; 1567 ability = 0; 1568 ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_HDX; 1569 } 1570 } 1571 #endif 1572 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) 1573 ifmr->ifm_active = IFM_ETHER | IFM_100_T4; 1574 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) 1575 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1576 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) 1577 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1578 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) 1579 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1580 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) 1581 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1582 1583 crit_exit(); 1584 } 1585 1586 static int 1587 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data, struct ucred *cr) 1588 { 1589 struct my_softc *sc = ifp->if_softc; 1590 struct ifreq *ifr = (struct ifreq *) data; 1591 int error = 0; 1592 1593 crit_enter(); 1594 switch (command) { 1595 case SIOCSIFFLAGS: 1596 if (ifp->if_flags & IFF_UP) 1597 my_init(sc); 1598 else if (ifp->if_flags & IFF_RUNNING) 1599 my_stop(sc); 1600 error = 0; 1601 break; 1602 case SIOCADDMULTI: 1603 case SIOCDELMULTI: 1604 my_setmulti(sc); 1605 error = 0; 1606 break; 1607 case SIOCGIFMEDIA: 1608 case SIOCSIFMEDIA: 1609 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1610 break; 1611 default: 1612 error = ether_ioctl(ifp, command, data); 1613 break; 1614 } 1615 1616 crit_exit(); 1617 return (error); 1618 } 1619 1620 static void 1621 my_watchdog(struct ifnet * ifp) 1622 { 1623 struct my_softc *sc = ifp->if_softc; 1624 1625 crit_enter(); 1626 1627 if (sc->my_autoneg) { 1628 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1); 1629 crit_exit(); 1630 return; 1631 } 1632 ifp->if_oerrors++; 1633 kprintf("my%d: watchdog timeout\n", sc->my_unit); 1634 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1635 kprintf("my%d: no carrier - transceiver cable problem?\n", 1636 sc->my_unit); 1637 my_stop(sc); 1638 my_reset(sc); 1639 my_init(sc); 1640 if (!ifq_is_empty(&ifp->if_snd)) 1641 my_start(ifp); 1642 crit_exit(); 1643 } 1644 1645 1646 /* 1647 * Stop the adapter and free any mbufs allocated to the RX and TX lists. 1648 */ 1649 static void 1650 my_stop(struct my_softc * sc) 1651 { 1652 struct ifnet *ifp = &sc->arpcom.ac_if; 1653 int i; 1654 1655 ifp->if_timer = 0; 1656 1657 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE)); 1658 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1659 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000); 1660 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000); 1661 1662 /* 1663 * Free data in the RX lists. 1664 */ 1665 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1666 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) { 1667 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf); 1668 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL; 1669 } 1670 } 1671 bzero((char *)&sc->my_ldata->my_rx_list, 1672 sizeof(sc->my_ldata->my_rx_list)); 1673 /* 1674 * Free the TX list buffers. 1675 */ 1676 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1677 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) { 1678 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf); 1679 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL; 1680 } 1681 } 1682 bzero((char *)&sc->my_ldata->my_tx_list, 1683 sizeof(sc->my_ldata->my_tx_list)); 1684 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1685 } 1686 1687 /* 1688 * Stop all chip I/O so that the kernel's probe routines don't get confused 1689 * by errant DMAs when rebooting. 1690 */ 1691 static void 1692 my_shutdown(device_t dev) 1693 { 1694 struct my_softc *sc; 1695 1696 sc = device_get_softc(dev); 1697 my_stop(sc); 1698 return; 1699 } 1700