1 /* 2 * Copyright (c) 2002 Myson Technology Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/ 27 * 28 * $FreeBSD: src/sys/dev/my/if_my.c,v 1.2.2.4 2002/04/17 02:05:27 julian Exp $ 29 * 30 * Myson fast ethernet PCI NIC driver 31 * 32 * $Id: if_my.c,v 1.40 2001/11/30 03:55:00 <yen_cw@myson.com.tw> wpaul Exp $ 33 */ 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/sockio.h> 37 #include <sys/mbuf.h> 38 #include <sys/malloc.h> 39 #include <sys/kernel.h> 40 #include <sys/interrupt.h> 41 #include <sys/socket.h> 42 #include <sys/queue.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/serialize.h> 46 #include <sys/bus.h> 47 #include <sys/rman.h> 48 49 #include <sys/thread2.h> 50 51 #include <net/if.h> 52 #include <net/ifq_var.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_media.h> 56 #include <net/if_dl.h> 57 #include <net/bpf.h> 58 59 #include <vm/vm.h> /* for vtophys */ 60 #include <vm/pmap.h> /* for vtophys */ 61 #include <machine/clock.h> /* for DELAY */ 62 63 #include <bus/pci/pcireg.h> 64 #include <bus/pci/pcivar.h> 65 66 /* 67 * #define MY_USEIOSPACE 68 */ 69 70 static int MY_USEIOSPACE = 1; 71 72 #if (MY_USEIOSPACE) 73 #define MY_RES SYS_RES_IOPORT 74 #define MY_RID MY_PCI_LOIO 75 #else 76 #define MY_RES SYS_RES_MEMORY 77 #define MY_RID MY_PCI_LOMEM 78 #endif 79 80 81 #include "if_myreg.h" 82 83 /* 84 * Various supported device vendors/types and their names. 85 */ 86 static struct my_type my_devs[] = { 87 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"}, 88 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"}, 89 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"}, 90 {0, 0, NULL} 91 }; 92 93 /* 94 * Various supported PHY vendors/types and their names. Note that this driver 95 * will work with pretty much any MII-compliant PHY, so failure to positively 96 * identify the chip is not a fatal error. 97 */ 98 static struct my_type my_phys[] = { 99 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"}, 100 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"}, 101 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"}, 102 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"}, 103 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"}, 104 {0, 0, "<MII-compliant physical interface>"} 105 }; 106 107 static int my_probe(device_t); 108 static int my_attach(device_t); 109 static int my_detach(device_t); 110 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *); 111 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *); 112 static void my_rxeof(struct my_softc *); 113 static void my_txeof(struct my_softc *); 114 static void my_txeoc(struct my_softc *); 115 static void my_intr(void *); 116 static void my_start(struct ifnet *, struct ifaltq_subque *); 117 static int my_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 118 static void my_init(void *); 119 static void my_stop(struct my_softc *); 120 static void my_watchdog(struct ifnet *); 121 static void my_shutdown(device_t); 122 static int my_ifmedia_upd(struct ifnet *); 123 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *); 124 static u_int16_t my_phy_readreg(struct my_softc *, int); 125 static void my_phy_writereg(struct my_softc *, int, int); 126 static void my_autoneg_xmit(struct my_softc *); 127 static void my_autoneg_mii(struct my_softc *, int, int); 128 static void my_setmode_mii(struct my_softc *, int); 129 static void my_getmode_mii(struct my_softc *); 130 static void my_setcfg(struct my_softc *, int); 131 static u_int8_t my_calchash(caddr_t); 132 static void my_setmulti(struct my_softc *); 133 static void my_reset(struct my_softc *); 134 static int my_list_rx_init(struct my_softc *); 135 static int my_list_tx_init(struct my_softc *); 136 static long my_send_cmd_to_phy(struct my_softc *, int, int); 137 138 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 139 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 140 141 static device_method_t my_methods[] = { 142 /* Device interface */ 143 DEVMETHOD(device_probe, my_probe), 144 DEVMETHOD(device_attach, my_attach), 145 DEVMETHOD(device_detach, my_detach), 146 DEVMETHOD(device_shutdown, my_shutdown), 147 148 DEVMETHOD_END 149 }; 150 151 static driver_t my_driver = { 152 "my", 153 my_methods, 154 sizeof(struct my_softc) 155 }; 156 157 static devclass_t my_devclass; 158 159 DECLARE_DUMMY_MODULE(if_my); 160 DRIVER_MODULE(if_my, pci, my_driver, my_devclass, NULL, NULL); 161 162 static long 163 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad) 164 { 165 long miir; 166 int i; 167 int mask, data; 168 169 /* enable MII output */ 170 miir = CSR_READ_4(sc, MY_MANAGEMENT); 171 miir &= 0xfffffff0; 172 173 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO; 174 175 /* send 32 1's preamble */ 176 for (i = 0; i < 32; i++) { 177 /* low MDC; MDO is already high (miir) */ 178 miir &= ~MY_MASK_MIIR_MII_MDC; 179 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 180 181 /* high MDC */ 182 miir |= MY_MASK_MIIR_MII_MDC; 183 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 184 } 185 186 /* calculate ST+OP+PHYAD+REGAD+TA */ 187 data = opcode | (sc->my_phy_addr << 7) | (regad << 2); 188 189 /* sent out */ 190 mask = 0x8000; 191 while (mask) { 192 /* low MDC, prepare MDO */ 193 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 194 if (mask & data) 195 miir |= MY_MASK_MIIR_MII_MDO; 196 197 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 198 /* high MDC */ 199 miir |= MY_MASK_MIIR_MII_MDC; 200 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 201 DELAY(30); 202 203 /* next */ 204 mask >>= 1; 205 if (mask == 0x2 && opcode == MY_OP_READ) 206 miir &= ~MY_MASK_MIIR_MII_WRITE; 207 } 208 209 return miir; 210 } 211 212 213 static u_int16_t 214 my_phy_readreg(struct my_softc * sc, int reg) 215 { 216 long miir; 217 int mask, data; 218 219 if (sc->my_info->my_did == MTD803ID) 220 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2); 221 else { 222 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg); 223 224 /* read data */ 225 mask = 0x8000; 226 data = 0; 227 while (mask) { 228 /* low MDC */ 229 miir &= ~MY_MASK_MIIR_MII_MDC; 230 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 231 232 /* read MDI */ 233 miir = CSR_READ_4(sc, MY_MANAGEMENT); 234 if (miir & MY_MASK_MIIR_MII_MDI) 235 data |= mask; 236 237 /* high MDC, and wait */ 238 miir |= MY_MASK_MIIR_MII_MDC; 239 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 240 DELAY(30); 241 242 /* next */ 243 mask >>= 1; 244 } 245 246 /* low MDC */ 247 miir &= ~MY_MASK_MIIR_MII_MDC; 248 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 249 } 250 251 return (u_int16_t) data; 252 } 253 254 255 static void 256 my_phy_writereg(struct my_softc * sc, int reg, int data) 257 { 258 long miir; 259 int mask; 260 261 if (sc->my_info->my_did == MTD803ID) 262 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data); 263 else { 264 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg); 265 266 /* write data */ 267 mask = 0x8000; 268 while (mask) { 269 /* low MDC, prepare MDO */ 270 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 271 if (mask & data) 272 miir |= MY_MASK_MIIR_MII_MDO; 273 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 274 DELAY(1); 275 276 /* high MDC */ 277 miir |= MY_MASK_MIIR_MII_MDC; 278 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 279 DELAY(1); 280 281 /* next */ 282 mask >>= 1; 283 } 284 285 /* low MDC */ 286 miir &= ~MY_MASK_MIIR_MII_MDC; 287 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 288 } 289 } 290 291 static u_int8_t 292 my_calchash(caddr_t addr) 293 { 294 u_int32_t crc, carry; 295 int i, j; 296 u_int8_t c; 297 298 /* Compute CRC for the address value. */ 299 crc = 0xFFFFFFFF; /* initial value */ 300 301 for (i = 0; i < 6; i++) { 302 c = *(addr + i); 303 for (j = 0; j < 8; j++) { 304 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 305 crc <<= 1; 306 c >>= 1; 307 if (carry) 308 crc = (crc ^ 0x04c11db6) | carry; 309 } 310 } 311 312 /* 313 * return the filter bit position Note: I arrived at the following 314 * nonsense through experimentation. It's not the usual way to 315 * generate the bit position but it's the only thing I could come up 316 * with that works. 317 */ 318 return (~(crc >> 26) & 0x0000003F); 319 } 320 321 322 /* 323 * Program the 64-bit multicast hash filter. 324 */ 325 static void 326 my_setmulti(struct my_softc * sc) 327 { 328 struct ifnet *ifp = &sc->arpcom.ac_if; 329 int h = 0; 330 u_int32_t hashes[2] = {0, 0}; 331 struct ifmultiaddr *ifma; 332 u_int32_t rxfilt; 333 int mcnt = 0; 334 335 rxfilt = CSR_READ_4(sc, MY_TCRRCR); 336 337 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 338 rxfilt |= MY_AM; 339 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 340 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF); 341 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF); 342 343 return; 344 } 345 /* first, zot all the existing hash bits */ 346 CSR_WRITE_4(sc, MY_MAR0, 0); 347 CSR_WRITE_4(sc, MY_MAR1, 0); 348 349 /* now program new ones */ 350 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 351 if (ifma->ifma_addr->sa_family != AF_LINK) 352 continue; 353 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr)); 354 if (h < 32) 355 hashes[0] |= (1 << h); 356 else 357 hashes[1] |= (1 << (h - 32)); 358 mcnt++; 359 } 360 361 if (mcnt) 362 rxfilt |= MY_AM; 363 else 364 rxfilt &= ~MY_AM; 365 CSR_WRITE_4(sc, MY_MAR0, hashes[0]); 366 CSR_WRITE_4(sc, MY_MAR1, hashes[1]); 367 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 368 } 369 370 /* 371 * Initiate an autonegotiation session. 372 */ 373 static void 374 my_autoneg_xmit(struct my_softc * sc) 375 { 376 u_int16_t phy_sts = 0; 377 378 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 379 DELAY(500); 380 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 381 382 phy_sts = my_phy_readreg(sc, PHY_BMCR); 383 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR; 384 my_phy_writereg(sc, PHY_BMCR, phy_sts); 385 } 386 387 388 /* 389 * Invoke autonegotiation on a PHY. 390 */ 391 static void 392 my_autoneg_mii(struct my_softc * sc, int flag, int verbose) 393 { 394 u_int16_t phy_sts = 0, media, advert, ability; 395 u_int16_t ability2 = 0; 396 struct ifnet *ifp = &sc->arpcom.ac_if; 397 struct ifmedia *ifm = &sc->ifmedia; 398 399 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 400 401 #ifndef FORCE_AUTONEG_TFOUR 402 /* 403 * First, see if autoneg is supported. If not, there's no point in 404 * continuing. 405 */ 406 phy_sts = my_phy_readreg(sc, PHY_BMSR); 407 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 408 if (verbose) 409 kprintf("my%d: autonegotiation not supported\n", 410 sc->my_unit); 411 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 412 return; 413 } 414 #endif 415 switch (flag) { 416 case MY_FLAG_FORCEDELAY: 417 /* 418 * XXX Never use this option anywhere but in the probe 419 * routine: making the kernel stop dead in its tracks for 420 * three whole seconds after we've gone multi-user is really 421 * bad manners. 422 */ 423 my_autoneg_xmit(sc); 424 DELAY(5000000); 425 break; 426 case MY_FLAG_SCHEDDELAY: 427 /* 428 * Wait for the transmitter to go idle before starting an 429 * autoneg session, otherwise my_start() may clobber our 430 * timeout, and we don't want to allow transmission during an 431 * autoneg session since that can screw it up. 432 */ 433 if (sc->my_cdata.my_tx_head != NULL) { 434 sc->my_want_auto = 1; 435 return; 436 } 437 my_autoneg_xmit(sc); 438 ifp->if_timer = 5; 439 sc->my_autoneg = 1; 440 sc->my_want_auto = 0; 441 return; 442 case MY_FLAG_DELAYTIMEO: 443 ifp->if_timer = 0; 444 sc->my_autoneg = 0; 445 break; 446 default: 447 kprintf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag); 448 return; 449 } 450 451 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 452 if (verbose) 453 kprintf("my%d: autoneg complete, ", sc->my_unit); 454 phy_sts = my_phy_readreg(sc, PHY_BMSR); 455 } else { 456 if (verbose) 457 kprintf("my%d: autoneg not complete, ", sc->my_unit); 458 } 459 460 media = my_phy_readreg(sc, PHY_BMCR); 461 462 /* Link is good. Report modes and set duplex mode. */ 463 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 464 if (verbose) 465 kprintf("my%d: link status good. ", sc->my_unit); 466 advert = my_phy_readreg(sc, PHY_ANAR); 467 ability = my_phy_readreg(sc, PHY_LPAR); 468 if ((sc->my_pinfo->my_vid == MarvellPHYID0) || 469 (sc->my_pinfo->my_vid == LevelOnePHYID0)) { 470 ability2 = my_phy_readreg(sc, PHY_1000SR); 471 if (ability2 & PHY_1000SR_1000BTXFULL) { 472 advert = 0; 473 ability = 0; 474 /* 475 * this version did not support 1000M, 476 * ifm->ifm_media = 477 * IFM_ETHER | IFM_1000_T | IFM_FDX; 478 */ 479 ifm->ifm_media = 480 IFM_ETHER | IFM_100_TX | IFM_FDX; 481 media &= ~PHY_BMCR_SPEEDSEL; 482 media |= PHY_BMCR_1000; 483 media |= PHY_BMCR_DUPLEX; 484 kprintf("(full-duplex, 1000Mbps)\n"); 485 } else if (ability2 & PHY_1000SR_1000BTXHALF) { 486 advert = 0; 487 ability = 0; 488 /* 489 * this version did not support 1000M, 490 * ifm->ifm_media = IFM_ETHER | IFM_1000_T; 491 */ 492 ifm->ifm_media = IFM_ETHER | IFM_100_TX; 493 media &= ~PHY_BMCR_SPEEDSEL; 494 media &= ~PHY_BMCR_DUPLEX; 495 media |= PHY_BMCR_1000; 496 kprintf("(half-duplex, 1000Mbps)\n"); 497 } 498 } 499 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 500 ifm->ifm_media = IFM_ETHER | IFM_100_T4; 501 media |= PHY_BMCR_SPEEDSEL; 502 media &= ~PHY_BMCR_DUPLEX; 503 kprintf("(100baseT4)\n"); 504 } else if (advert & PHY_ANAR_100BTXFULL && 505 ability & PHY_ANAR_100BTXFULL) { 506 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 507 media |= PHY_BMCR_SPEEDSEL; 508 media |= PHY_BMCR_DUPLEX; 509 kprintf("(full-duplex, 100Mbps)\n"); 510 } else if (advert & PHY_ANAR_100BTXHALF && 511 ability & PHY_ANAR_100BTXHALF) { 512 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 513 media |= PHY_BMCR_SPEEDSEL; 514 media &= ~PHY_BMCR_DUPLEX; 515 kprintf("(half-duplex, 100Mbps)\n"); 516 } else if (advert & PHY_ANAR_10BTFULL && 517 ability & PHY_ANAR_10BTFULL) { 518 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 519 media &= ~PHY_BMCR_SPEEDSEL; 520 media |= PHY_BMCR_DUPLEX; 521 kprintf("(full-duplex, 10Mbps)\n"); 522 } else if (advert) { 523 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 524 media &= ~PHY_BMCR_SPEEDSEL; 525 media &= ~PHY_BMCR_DUPLEX; 526 kprintf("(half-duplex, 10Mbps)\n"); 527 } 528 media &= ~PHY_BMCR_AUTONEGENBL; 529 530 /* Set ASIC's duplex mode to match the PHY. */ 531 my_phy_writereg(sc, PHY_BMCR, media); 532 my_setcfg(sc, media); 533 } else { 534 if (verbose) 535 kprintf("my%d: no carrier\n", sc->my_unit); 536 } 537 538 my_init(sc); 539 if (sc->my_tx_pend) { 540 sc->my_autoneg = 0; 541 sc->my_tx_pend = 0; 542 if_devstart(ifp); 543 } 544 } 545 546 /* 547 * To get PHY ability. 548 */ 549 static void 550 my_getmode_mii(struct my_softc * sc) 551 { 552 struct ifnet *ifp = &sc->arpcom.ac_if; 553 u_int16_t bmsr; 554 555 bmsr = my_phy_readreg(sc, PHY_BMSR); 556 if (bootverbose) 557 kprintf("my%d: PHY status word: %x\n", sc->my_unit, bmsr); 558 559 /* fallback */ 560 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 561 562 if (bmsr & PHY_BMSR_10BTHALF) { 563 if (bootverbose) 564 kprintf("my%d: 10Mbps half-duplex mode supported\n", 565 sc->my_unit); 566 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 567 0, NULL); 568 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 569 } 570 if (bmsr & PHY_BMSR_10BTFULL) { 571 if (bootverbose) 572 kprintf("my%d: 10Mbps full-duplex mode supported\n", 573 sc->my_unit); 574 575 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 576 0, NULL); 577 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 578 } 579 if (bmsr & PHY_BMSR_100BTXHALF) { 580 if (bootverbose) 581 kprintf("my%d: 100Mbps half-duplex mode supported\n", 582 sc->my_unit); 583 ifp->if_baudrate = 100000000; 584 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 585 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 586 0, NULL); 587 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 588 } 589 if (bmsr & PHY_BMSR_100BTXFULL) { 590 if (bootverbose) 591 kprintf("my%d: 100Mbps full-duplex mode supported\n", 592 sc->my_unit); 593 ifp->if_baudrate = 100000000; 594 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 595 0, NULL); 596 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 597 } 598 /* Some also support 100BaseT4. */ 599 if (bmsr & PHY_BMSR_100BT4) { 600 if (bootverbose) 601 kprintf("my%d: 100baseT4 mode supported\n", sc->my_unit); 602 ifp->if_baudrate = 100000000; 603 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL); 604 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4; 605 #ifdef FORCE_AUTONEG_TFOUR 606 if (bootverbose) 607 kprintf("my%d: forcing on autoneg support for BT4\n", 608 sc->my_unit); 609 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL): 610 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 611 #endif 612 } 613 #if 0 /* this version did not support 1000M, */ 614 if (sc->my_pinfo->my_vid == MarvellPHYID0) { 615 if (bootverbose) 616 kprintf("my%d: 1000Mbps half-duplex mode supported\n", 617 sc->my_unit); 618 619 ifp->if_baudrate = 1000000000; 620 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 621 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX, 622 0, NULL); 623 if (bootverbose) 624 kprintf("my%d: 1000Mbps full-duplex mode supported\n", 625 sc->my_unit); 626 ifp->if_baudrate = 1000000000; 627 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 628 0, NULL); 629 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX; 630 } 631 #endif 632 if (bmsr & PHY_BMSR_CANAUTONEG) { 633 if (bootverbose) 634 kprintf("my%d: autoneg supported\n", sc->my_unit); 635 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 636 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 637 } 638 } 639 640 /* 641 * Set speed and duplex mode. 642 */ 643 static void 644 my_setmode_mii(struct my_softc * sc, int media) 645 { 646 struct ifnet *ifp = &sc->arpcom.ac_if; 647 u_int16_t bmcr; 648 649 /* 650 * If an autoneg session is in progress, stop it. 651 */ 652 if (sc->my_autoneg) { 653 kprintf("my%d: canceling autoneg session\n", sc->my_unit); 654 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0; 655 bmcr = my_phy_readreg(sc, PHY_BMCR); 656 bmcr &= ~PHY_BMCR_AUTONEGENBL; 657 my_phy_writereg(sc, PHY_BMCR, bmcr); 658 } 659 kprintf("my%d: selecting MII, ", sc->my_unit); 660 bmcr = my_phy_readreg(sc, PHY_BMCR); 661 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 | 662 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK); 663 664 #if 0 /* this version did not support 1000M, */ 665 if (IFM_SUBTYPE(media) == IFM_1000_T) { 666 kprintf("1000Mbps/T4, half-duplex\n"); 667 bmcr &= ~PHY_BMCR_SPEEDSEL; 668 bmcr &= ~PHY_BMCR_DUPLEX; 669 bmcr |= PHY_BMCR_1000; 670 } 671 #endif 672 if (IFM_SUBTYPE(media) == IFM_100_T4) { 673 kprintf("100Mbps/T4, half-duplex\n"); 674 bmcr |= PHY_BMCR_SPEEDSEL; 675 bmcr &= ~PHY_BMCR_DUPLEX; 676 } 677 if (IFM_SUBTYPE(media) == IFM_100_TX) { 678 kprintf("100Mbps, "); 679 bmcr |= PHY_BMCR_SPEEDSEL; 680 } 681 if (IFM_SUBTYPE(media) == IFM_10_T) { 682 kprintf("10Mbps, "); 683 bmcr &= ~PHY_BMCR_SPEEDSEL; 684 } 685 if ((media & IFM_GMASK) == IFM_FDX) { 686 kprintf("full duplex\n"); 687 bmcr |= PHY_BMCR_DUPLEX; 688 } else { 689 kprintf("half duplex\n"); 690 bmcr &= ~PHY_BMCR_DUPLEX; 691 } 692 my_phy_writereg(sc, PHY_BMCR, bmcr); 693 my_setcfg(sc, bmcr); 694 } 695 696 /* 697 * The Myson manual states that in order to fiddle with the 'full-duplex' and 698 * '100Mbps' bits in the netconfig register, we first have to put the 699 * transmit and/or receive logic in the idle state. 700 */ 701 static void 702 my_setcfg(struct my_softc * sc, int bmcr) 703 { 704 int i, restart = 0; 705 706 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { 707 restart = 1; 708 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE)); 709 for (i = 0; i < MY_TIMEOUT; i++) { 710 DELAY(10); 711 if (!(CSR_READ_4(sc, MY_TCRRCR) & 712 (MY_TXRUN | MY_RXRUN))) 713 break; 714 } 715 if (i == MY_TIMEOUT) 716 kprintf("my%d: failed to force tx and rx to idle \n", 717 sc->my_unit); 718 } 719 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000); 720 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10); 721 if (bmcr & PHY_BMCR_1000) 722 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000); 723 else if (!(bmcr & PHY_BMCR_SPEEDSEL)) 724 MY_SETBIT(sc, MY_TCRRCR, MY_PS10); 725 if (bmcr & PHY_BMCR_DUPLEX) 726 MY_SETBIT(sc, MY_TCRRCR, MY_FD); 727 else 728 MY_CLRBIT(sc, MY_TCRRCR, MY_FD); 729 if (restart) 730 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE); 731 } 732 733 static void 734 my_reset(struct my_softc * sc) 735 { 736 int i; 737 738 MY_SETBIT(sc, MY_BCR, MY_SWR); 739 for (i = 0; i < MY_TIMEOUT; i++) { 740 DELAY(10); 741 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) 742 break; 743 } 744 if (i == MY_TIMEOUT) 745 kprintf("m0x%d: reset never completed!\n", sc->my_unit); 746 747 /* Wait a little while for the chip to get its brains in order. */ 748 DELAY(1000); 749 } 750 751 /* 752 * Probe for a Myson chip. Check the PCI vendor and device IDs against our 753 * list and return a device name if we find a match. 754 */ 755 static int 756 my_probe(device_t dev) 757 { 758 struct my_type *t; 759 uint16_t vendor, product; 760 761 vendor = pci_get_vendor(dev); 762 product = pci_get_device(dev); 763 764 for (t = my_devs; t->my_name != NULL; t++) { 765 if (vendor == t->my_vid && product == t->my_did) { 766 device_set_desc(dev, t->my_name); 767 return (0); 768 } 769 } 770 771 return (ENXIO); 772 } 773 774 /* 775 * Attach the interface. Allocate softc structures, do ifmedia setup and 776 * ethernet/BPF attach. 777 */ 778 static int 779 my_attach(device_t dev) 780 { 781 int i; 782 u_char eaddr[ETHER_ADDR_LEN]; 783 u_int32_t command, iobase; 784 struct my_softc *sc; 785 struct ifnet *ifp; 786 int media = IFM_ETHER | IFM_100_TX | IFM_FDX; 787 unsigned int round; 788 caddr_t roundptr; 789 struct my_type *p; 790 u_int16_t phy_vid, phy_did, phy_sts = 0; 791 int rid, unit, error = 0; 792 struct my_type *t; 793 uint16_t vendor, product; 794 795 vendor = pci_get_vendor(dev); 796 product = pci_get_device(dev); 797 798 for (t = my_devs; t->my_name != NULL; t++) { 799 if (vendor == t->my_vid && product == t->my_did) 800 break; 801 } 802 803 if (t->my_name == NULL) 804 return(ENXIO); 805 806 sc = device_get_softc(dev); 807 unit = device_get_unit(dev); 808 809 /* 810 * Map control/status registers. 811 */ 812 command = pci_read_config(dev, PCIR_COMMAND, 4); 813 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 814 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4); 815 command = pci_read_config(dev, PCIR_COMMAND, 4); 816 817 if (t->my_did == MTD800ID) { 818 iobase = pci_read_config(dev, MY_PCI_LOIO, 4); 819 if (iobase & 0x300) 820 MY_USEIOSPACE = 0; 821 } 822 if (MY_USEIOSPACE) { 823 if (!(command & PCIM_CMD_PORTEN)) { 824 kprintf("my%d: failed to enable I/O ports!\n", unit); 825 error = ENXIO; 826 return(error); 827 } 828 } else { 829 if (!(command & PCIM_CMD_MEMEN)) { 830 kprintf("my%d: failed to enable memory mapping!\n", 831 unit); 832 error = ENXIO; 833 return(error); 834 } 835 } 836 837 rid = MY_RID; 838 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE); 839 840 if (sc->my_res == NULL) { 841 kprintf("my%d: couldn't map ports/memory\n", unit); 842 error = ENXIO; 843 goto fail; 844 } 845 sc->my_btag = rman_get_bustag(sc->my_res); 846 sc->my_bhandle = rman_get_bushandle(sc->my_res); 847 848 rid = 0; 849 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 850 RF_SHAREABLE | RF_ACTIVE); 851 852 if (sc->my_irq == NULL) { 853 kprintf("my%d: couldn't map interrupt\n", unit); 854 error = ENXIO; 855 goto fail; 856 } 857 858 sc->my_info = t; 859 860 /* Reset the adapter. */ 861 my_reset(sc); 862 863 /* 864 * Get station address 865 */ 866 for (i = 0; i < ETHER_ADDR_LEN; ++i) 867 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); 868 869 sc->my_unit = unit; 870 871 sc->my_ldata_ptr = kmalloc(sizeof(struct my_list_data) + 8, 872 M_DEVBUF, M_WAITOK); 873 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr; 874 round = (uintptr_t)sc->my_ldata_ptr & 0xF; 875 roundptr = sc->my_ldata_ptr; 876 for (i = 0; i < 8; i++) { 877 if (round % 8) { 878 round++; 879 roundptr++; 880 } else 881 break; 882 } 883 sc->my_ldata = (struct my_list_data *) roundptr; 884 bzero(sc->my_ldata, sizeof(struct my_list_data)); 885 886 ifp = &sc->arpcom.ac_if; 887 ifp->if_softc = sc; 888 if_initname(ifp, "my", unit); 889 ifp->if_mtu = ETHERMTU; 890 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 891 ifp->if_ioctl = my_ioctl; 892 ifp->if_start = my_start; 893 ifp->if_watchdog = my_watchdog; 894 ifp->if_init = my_init; 895 ifp->if_baudrate = 10000000; 896 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 897 ifq_set_ready(&ifp->if_snd); 898 899 if (sc->my_info->my_did == MTD803ID) 900 sc->my_pinfo = my_phys; 901 else { 902 if (bootverbose) 903 kprintf("my%d: probing for a PHY\n", sc->my_unit); 904 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) { 905 if (bootverbose) 906 kprintf("my%d: checking address: %d\n", 907 sc->my_unit, i); 908 sc->my_phy_addr = i; 909 phy_sts = my_phy_readreg(sc, PHY_BMSR); 910 if ((phy_sts != 0) && (phy_sts != 0xffff)) 911 break; 912 else 913 phy_sts = 0; 914 } 915 if (phy_sts) { 916 phy_vid = my_phy_readreg(sc, PHY_VENID); 917 phy_did = my_phy_readreg(sc, PHY_DEVID); 918 if (bootverbose) { 919 kprintf("my%d: found PHY at address %d, ", 920 sc->my_unit, sc->my_phy_addr); 921 kprintf("vendor id: %x device id: %x\n", 922 phy_vid, phy_did); 923 } 924 p = my_phys; 925 while (p->my_vid) { 926 if (phy_vid == p->my_vid) { 927 sc->my_pinfo = p; 928 break; 929 } 930 p++; 931 } 932 if (sc->my_pinfo == NULL) 933 sc->my_pinfo = &my_phys[PHY_UNKNOWN]; 934 if (bootverbose) 935 kprintf("my%d: PHY type: %s\n", 936 sc->my_unit, sc->my_pinfo->my_name); 937 } else { 938 kprintf("my%d: MII without any phy!\n", sc->my_unit); 939 error = ENXIO; 940 goto fail; 941 } 942 } 943 944 /* Do ifmedia setup. */ 945 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts); 946 my_getmode_mii(sc); 947 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1); 948 media = sc->ifmedia.ifm_media; 949 my_stop(sc); 950 ifmedia_set(&sc->ifmedia, media); 951 952 ether_ifattach(ifp, eaddr, NULL); 953 954 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->my_irq)); 955 956 error = bus_setup_intr(dev, sc->my_irq, INTR_MPSAFE, 957 my_intr, sc, &sc->my_intrhand, 958 ifp->if_serializer); 959 if (error) { 960 ether_ifdetach(ifp); 961 kprintf("my%d: couldn't set up irq\n", unit); 962 goto fail; 963 } 964 965 return (0); 966 967 fail: 968 my_detach(dev); 969 return (error); 970 } 971 972 static int 973 my_detach(device_t dev) 974 { 975 struct my_softc *sc = device_get_softc(dev); 976 struct ifnet *ifp = &sc->arpcom.ac_if; 977 978 if (device_is_attached(dev)) { 979 lwkt_serialize_enter(ifp->if_serializer); 980 my_stop(sc); 981 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand); 982 lwkt_serialize_exit(ifp->if_serializer); 983 984 ether_ifdetach(ifp); 985 } 986 987 if (sc->my_irq) 988 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 989 if (sc->my_res) 990 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 991 992 return (0); 993 } 994 995 996 /* 997 * Initialize the transmit descriptors. 998 */ 999 static int 1000 my_list_tx_init(struct my_softc * sc) 1001 { 1002 struct my_chain_data *cd; 1003 struct my_list_data *ld; 1004 int i; 1005 1006 cd = &sc->my_cdata; 1007 ld = sc->my_ldata; 1008 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1009 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i]; 1010 if (i == (MY_TX_LIST_CNT - 1)) 1011 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0]; 1012 else 1013 cd->my_tx_chain[i].my_nextdesc = 1014 &cd->my_tx_chain[i + 1]; 1015 } 1016 cd->my_tx_free = &cd->my_tx_chain[0]; 1017 cd->my_tx_tail = cd->my_tx_head = NULL; 1018 return (0); 1019 } 1020 1021 /* 1022 * Initialize the RX descriptors and allocate mbufs for them. Note that we 1023 * arrange the descriptors in a closed ring, so that the last descriptor 1024 * points back to the first. 1025 */ 1026 static int 1027 my_list_rx_init(struct my_softc * sc) 1028 { 1029 struct my_chain_data *cd; 1030 struct my_list_data *ld; 1031 int i; 1032 1033 cd = &sc->my_cdata; 1034 ld = sc->my_ldata; 1035 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1036 cd->my_rx_chain[i].my_ptr = 1037 (struct my_desc *) & ld->my_rx_list[i]; 1038 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) 1039 return (ENOBUFS); 1040 if (i == (MY_RX_LIST_CNT - 1)) { 1041 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0]; 1042 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]); 1043 } else { 1044 cd->my_rx_chain[i].my_nextdesc = 1045 &cd->my_rx_chain[i + 1]; 1046 ld->my_rx_list[i].my_next = 1047 vtophys(&ld->my_rx_list[i + 1]); 1048 } 1049 } 1050 cd->my_rx_head = &cd->my_rx_chain[0]; 1051 return (0); 1052 } 1053 1054 /* 1055 * Initialize an RX descriptor and attach an MBUF cluster. 1056 */ 1057 static int 1058 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c) 1059 { 1060 struct mbuf *m_new = NULL; 1061 1062 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1063 if (m_new == NULL) { 1064 kprintf("my%d: no memory for rx list -- packet dropped!\n", 1065 sc->my_unit); 1066 return (ENOBUFS); 1067 } 1068 MCLGET(m_new, MB_DONTWAIT); 1069 if (!(m_new->m_flags & M_EXT)) { 1070 kprintf("my%d: no memory for rx list -- packet dropped!\n", 1071 sc->my_unit); 1072 m_freem(m_new); 1073 return (ENOBUFS); 1074 } 1075 c->my_mbuf = m_new; 1076 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t)); 1077 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift; 1078 c->my_ptr->my_status = MY_OWNByNIC; 1079 return (0); 1080 } 1081 1082 /* 1083 * A frame has been uploaded: pass the resulting mbuf chain up to the higher 1084 * level protocols. 1085 */ 1086 static void 1087 my_rxeof(struct my_softc * sc) 1088 { 1089 struct mbuf *m; 1090 struct ifnet *ifp = &sc->arpcom.ac_if; 1091 struct my_chain_onefrag *cur_rx; 1092 int total_len = 0; 1093 u_int32_t rxstat; 1094 1095 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status) 1096 & MY_OWNByNIC)) { 1097 cur_rx = sc->my_cdata.my_rx_head; 1098 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc; 1099 1100 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */ 1101 IFNET_STAT_INC(ifp, ierrors, 1); 1102 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1103 continue; 1104 } 1105 /* No errors; receive the packet. */ 1106 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift; 1107 total_len -= ETHER_CRC_LEN; 1108 1109 if (total_len < MINCLSIZE) { 1110 m = m_devget(mtod(cur_rx->my_mbuf, char *), 1111 total_len, 0, ifp, NULL); 1112 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1113 if (m == NULL) { 1114 IFNET_STAT_INC(ifp, ierrors, 1); 1115 continue; 1116 } 1117 } else { 1118 m = cur_rx->my_mbuf; 1119 /* 1120 * Try to conjure up a new mbuf cluster. If that 1121 * fails, it means we have an out of memory condition 1122 * and should leave the buffer in place and continue. 1123 * This will result in a lost packet, but there's 1124 * little else we can do in this situation. 1125 */ 1126 if (my_newbuf(sc, cur_rx) == ENOBUFS) { 1127 IFNET_STAT_INC(ifp, ierrors, 1); 1128 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1129 continue; 1130 } 1131 m->m_pkthdr.rcvif = ifp; 1132 m->m_pkthdr.len = m->m_len = total_len; 1133 } 1134 IFNET_STAT_INC(ifp, ipackets, 1); 1135 ifp->if_input(ifp, m); 1136 } 1137 } 1138 1139 1140 /* 1141 * A frame was downloaded to the chip. It's safe for us to clean up the list 1142 * buffers. 1143 */ 1144 static void 1145 my_txeof(struct my_softc * sc) 1146 { 1147 struct ifnet *ifp = &sc->arpcom.ac_if; 1148 struct my_chain *cur_tx; 1149 1150 /* Clear the timeout timer. */ 1151 ifp->if_timer = 0; 1152 if (sc->my_cdata.my_tx_head == NULL) 1153 return; 1154 /* 1155 * Go through our tx list and free mbufs for those frames that have 1156 * been transmitted. 1157 */ 1158 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) { 1159 u_int32_t txstat; 1160 1161 cur_tx = sc->my_cdata.my_tx_head; 1162 txstat = MY_TXSTATUS(cur_tx); 1163 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT) 1164 break; 1165 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { 1166 if (txstat & MY_TXERR) { 1167 IFNET_STAT_INC(ifp, oerrors, 1); 1168 if (txstat & MY_EC) /* excessive collision */ 1169 IFNET_STAT_INC(ifp, collisions, 1); 1170 if (txstat & MY_LC) /* late collision */ 1171 IFNET_STAT_INC(ifp, collisions, 1); 1172 } 1173 IFNET_STAT_INC(ifp, collisions, 1174 (txstat & MY_NCRMASK) >> MY_NCRShift); 1175 } 1176 IFNET_STAT_INC(ifp, opackets, 1); 1177 m_freem(cur_tx->my_mbuf); 1178 cur_tx->my_mbuf = NULL; 1179 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) { 1180 sc->my_cdata.my_tx_head = NULL; 1181 sc->my_cdata.my_tx_tail = NULL; 1182 break; 1183 } 1184 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc; 1185 } 1186 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { 1187 IFNET_STAT_INC(ifp, collisions, 1188 (CSR_READ_4(sc, MY_TSR) & MY_NCRMask)); 1189 } 1190 } 1191 1192 /* 1193 * TX 'end of channel' interrupt handler. 1194 */ 1195 static void 1196 my_txeoc(struct my_softc * sc) 1197 { 1198 struct ifnet *ifp = &sc->arpcom.ac_if; 1199 1200 ifp->if_timer = 0; 1201 if (sc->my_cdata.my_tx_head == NULL) { 1202 ifq_clr_oactive(&ifp->if_snd); 1203 sc->my_cdata.my_tx_tail = NULL; 1204 if (sc->my_want_auto) 1205 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1206 } else { 1207 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) { 1208 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC; 1209 ifp->if_timer = 5; 1210 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); 1211 } 1212 } 1213 } 1214 1215 static void 1216 my_intr(void *arg) 1217 { 1218 struct my_softc *sc = arg; 1219 struct ifnet *ifp = &sc->arpcom.ac_if; 1220 u_int32_t status; 1221 1222 if (!(ifp->if_flags & IFF_UP)) 1223 return; 1224 1225 /* Disable interrupts. */ 1226 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1227 1228 for (;;) { 1229 status = CSR_READ_4(sc, MY_ISR); 1230 status &= MY_INTRS; 1231 if (status) 1232 CSR_WRITE_4(sc, MY_ISR, status); 1233 else 1234 break; 1235 1236 if (status & MY_RI) /* receive interrupt */ 1237 my_rxeof(sc); 1238 1239 if ((status & MY_RBU) || (status & MY_RxErr)) { 1240 /* rx buffer unavailable or rx error */ 1241 IFNET_STAT_INC(ifp, ierrors, 1); 1242 #ifdef foo 1243 my_stop(sc); 1244 my_reset(sc); 1245 my_init(sc); 1246 #endif 1247 } 1248 if (status & MY_TI) /* tx interrupt */ 1249 my_txeof(sc); 1250 if (status & MY_ETI) /* tx early interrupt */ 1251 my_txeof(sc); 1252 if (status & MY_TBU) /* tx buffer unavailable */ 1253 my_txeoc(sc); 1254 1255 #if 0 /* 90/1/18 delete */ 1256 if (status & MY_FBE) { 1257 my_reset(sc); 1258 my_init(sc); 1259 } 1260 #endif 1261 1262 } 1263 1264 /* Re-enable interrupts. */ 1265 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1266 if (!ifq_is_empty(&ifp->if_snd)) 1267 if_devstart(ifp); 1268 } 1269 1270 /* 1271 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1272 * pointers to the fragment pointers. 1273 */ 1274 static int 1275 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head) 1276 { 1277 struct my_desc *f = NULL; 1278 int total_len; 1279 struct mbuf *m, *m_new = NULL; 1280 1281 /* calculate the total tx pkt length */ 1282 total_len = 0; 1283 for (m = m_head; m != NULL; m = m->m_next) 1284 total_len += m->m_len; 1285 /* 1286 * Start packing the mbufs in this chain into the fragment pointers. 1287 * Stop when we run out of fragments or hit the end of the mbuf 1288 * chain. 1289 */ 1290 m = m_head; 1291 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1292 if (m_new == NULL) { 1293 kprintf("my%d: no memory for tx list", sc->my_unit); 1294 return (1); 1295 } 1296 if (m_head->m_pkthdr.len > MHLEN) { 1297 MCLGET(m_new, MB_DONTWAIT); 1298 if (!(m_new->m_flags & M_EXT)) { 1299 m_freem(m_new); 1300 kprintf("my%d: no memory for tx list", sc->my_unit); 1301 return (1); 1302 } 1303 } 1304 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1305 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1306 m_freem(m_head); 1307 m_head = m_new; 1308 f = &c->my_ptr->my_frag[0]; 1309 f->my_status = 0; 1310 f->my_data = vtophys(mtod(m_new, caddr_t)); 1311 total_len = m_new->m_len; 1312 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable; 1313 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */ 1314 f->my_ctl |= total_len; /* buffer size */ 1315 /* 89/12/29 add, for mtd891 *//* [ 89? ] */ 1316 if (sc->my_info->my_did == MTD891ID) 1317 f->my_ctl |= MY_ETIControl | MY_RetryTxLC; 1318 c->my_mbuf = m_head; 1319 c->my_lastdesc = 0; 1320 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]); 1321 return (0); 1322 } 1323 1324 /* 1325 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1326 * to the mbuf data regions directly in the transmit lists. We also save a 1327 * copy of the pointers since the transmit list fragment pointers are 1328 * physical addresses. 1329 */ 1330 static void 1331 my_start(struct ifnet * ifp, struct ifaltq_subque *ifsq) 1332 { 1333 struct my_softc *sc = ifp->if_softc; 1334 struct mbuf *m_head = NULL; 1335 struct my_chain *cur_tx = NULL, *start_tx; 1336 1337 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1338 crit_enter(); 1339 1340 if (sc->my_autoneg) { 1341 ifq_purge(&ifp->if_snd); 1342 sc->my_tx_pend = 1; 1343 crit_exit(); 1344 return; 1345 } 1346 /* 1347 * Check for an available queue slot. If there are none, punt. 1348 */ 1349 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) { 1350 ifq_set_oactive(&ifp->if_snd); 1351 crit_exit(); 1352 return; 1353 } 1354 1355 start_tx = sc->my_cdata.my_tx_free; 1356 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) { 1357 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1358 if (m_head == NULL) 1359 break; 1360 1361 /* Pick a descriptor off the free list. */ 1362 cur_tx = sc->my_cdata.my_tx_free; 1363 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc; 1364 1365 /* Pack the data into the descriptor. */ 1366 my_encap(sc, cur_tx, m_head); 1367 1368 if (cur_tx != start_tx) 1369 MY_TXOWN(cur_tx) = MY_OWNByNIC; 1370 BPF_MTAP(ifp, cur_tx->my_mbuf); 1371 } 1372 /* 1373 * If there are no packets queued, bail. 1374 */ 1375 if (cur_tx == NULL) { 1376 crit_exit(); 1377 return; 1378 } 1379 /* 1380 * Place the request for the upload interrupt in the last descriptor 1381 * in the chain. This way, if we're chaining several packets at once, 1382 * we'll only get an interupt once for the whole chain rather than 1383 * once for each packet. 1384 */ 1385 MY_TXCTL(cur_tx) |= MY_TXIC; 1386 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC; 1387 sc->my_cdata.my_tx_tail = cur_tx; 1388 if (sc->my_cdata.my_tx_head == NULL) 1389 sc->my_cdata.my_tx_head = start_tx; 1390 MY_TXOWN(start_tx) = MY_OWNByNIC; 1391 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */ 1392 1393 /* 1394 * Set a timeout in case the chip goes out to lunch. 1395 */ 1396 ifp->if_timer = 5; 1397 1398 crit_exit(); 1399 } 1400 1401 static void 1402 my_init(void *xsc) 1403 { 1404 struct my_softc *sc = xsc; 1405 struct ifnet *ifp = &sc->arpcom.ac_if; 1406 u_int16_t phy_bmcr = 0; 1407 1408 crit_enter(); 1409 if (sc->my_autoneg) { 1410 crit_exit(); 1411 return; 1412 } 1413 if (sc->my_pinfo != NULL) 1414 phy_bmcr = my_phy_readreg(sc, PHY_BMCR); 1415 /* 1416 * Cancel pending I/O and free all RX/TX buffers. 1417 */ 1418 my_stop(sc); 1419 my_reset(sc); 1420 1421 /* 1422 * Set cache alignment and burst length. 1423 */ 1424 #if 0 /* 89/9/1 modify, */ 1425 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512); 1426 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF); 1427 #endif 1428 CSR_WRITE_4(sc, MY_BCR, MY_PBL8); 1429 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512); 1430 /* 1431 * 89/12/29 add, for mtd891, 1432 */ 1433 if (sc->my_info->my_did == MTD891ID) { 1434 MY_SETBIT(sc, MY_BCR, MY_PROG); 1435 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced); 1436 } 1437 my_setcfg(sc, phy_bmcr); 1438 /* Init circular RX list. */ 1439 if (my_list_rx_init(sc) == ENOBUFS) { 1440 kprintf("my%d: init failed: no memory for rx buffers\n", 1441 sc->my_unit); 1442 my_stop(sc); 1443 crit_exit(); 1444 return; 1445 } 1446 /* Init TX descriptors. */ 1447 my_list_tx_init(sc); 1448 1449 /* If we want promiscuous mode, set the allframes bit. */ 1450 if (ifp->if_flags & IFF_PROMISC) 1451 MY_SETBIT(sc, MY_TCRRCR, MY_PROM); 1452 else 1453 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM); 1454 1455 /* 1456 * Set capture broadcast bit to capture broadcast frames. 1457 */ 1458 if (ifp->if_flags & IFF_BROADCAST) 1459 MY_SETBIT(sc, MY_TCRRCR, MY_AB); 1460 else 1461 MY_CLRBIT(sc, MY_TCRRCR, MY_AB); 1462 1463 /* 1464 * Program the multicast filter, if necessary. 1465 */ 1466 my_setmulti(sc); 1467 1468 /* 1469 * Load the address of the RX list. 1470 */ 1471 MY_CLRBIT(sc, MY_TCRRCR, MY_RE); 1472 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0])); 1473 1474 /* 1475 * Enable interrupts. 1476 */ 1477 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1478 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF); 1479 1480 /* Enable receiver and transmitter. */ 1481 MY_SETBIT(sc, MY_TCRRCR, MY_RE); 1482 MY_CLRBIT(sc, MY_TCRRCR, MY_TE); 1483 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0])); 1484 MY_SETBIT(sc, MY_TCRRCR, MY_TE); 1485 1486 /* Restore state of BMCR */ 1487 if (sc->my_pinfo != NULL) 1488 my_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1489 ifp->if_flags |= IFF_RUNNING; 1490 ifq_clr_oactive(&ifp->if_snd); 1491 crit_exit(); 1492 } 1493 1494 /* 1495 * Set media options. 1496 */ 1497 1498 static int 1499 my_ifmedia_upd(struct ifnet * ifp) 1500 { 1501 struct my_softc *sc = ifp->if_softc; 1502 struct ifmedia *ifm = &sc->ifmedia; 1503 1504 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1505 return (EINVAL); 1506 1507 crit_enter(); 1508 1509 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1510 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1511 else 1512 my_setmode_mii(sc, ifm->ifm_media); 1513 1514 crit_exit(); 1515 1516 return (0); 1517 } 1518 1519 /* 1520 * Report current media status. 1521 */ 1522 1523 static void 1524 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr) 1525 { 1526 struct my_softc *sc = ifp->if_softc; 1527 u_int16_t advert = 0, ability = 0; 1528 1529 crit_enter(); 1530 1531 ifmr->ifm_active = IFM_ETHER; 1532 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1533 #if 0 /* this version did not support 1000M, */ 1534 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000) 1535 ifmr->ifm_active = IFM_ETHER | IFM_1000TX; 1536 #endif 1537 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1538 ifmr->ifm_active = IFM_ETHER | IFM_100_TX; 1539 else 1540 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1541 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1542 ifmr->ifm_active |= IFM_FDX; 1543 else 1544 ifmr->ifm_active |= IFM_HDX; 1545 1546 crit_exit(); 1547 1548 return; 1549 } 1550 ability = my_phy_readreg(sc, PHY_LPAR); 1551 advert = my_phy_readreg(sc, PHY_ANAR); 1552 1553 #if 0 /* this version did not support 1000M, */ 1554 if (sc->my_pinfo->my_vid == MarvellPHYID0) { 1555 ability2 = my_phy_readreg(sc, PHY_1000SR); 1556 if (ability2 & PHY_1000SR_1000BTXFULL) { 1557 advert = 0; 1558 ability = 0; 1559 ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_FDX; 1560 } else if (ability & PHY_1000SR_1000BTXHALF) { 1561 advert = 0; 1562 ability = 0; 1563 ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_HDX; 1564 } 1565 } 1566 #endif 1567 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) 1568 ifmr->ifm_active = IFM_ETHER | IFM_100_T4; 1569 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) 1570 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1571 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) 1572 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1573 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) 1574 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1575 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) 1576 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1577 1578 crit_exit(); 1579 } 1580 1581 static int 1582 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data, struct ucred *cr) 1583 { 1584 struct my_softc *sc = ifp->if_softc; 1585 struct ifreq *ifr = (struct ifreq *) data; 1586 int error = 0; 1587 1588 crit_enter(); 1589 switch (command) { 1590 case SIOCSIFFLAGS: 1591 if (ifp->if_flags & IFF_UP) 1592 my_init(sc); 1593 else if (ifp->if_flags & IFF_RUNNING) 1594 my_stop(sc); 1595 error = 0; 1596 break; 1597 case SIOCADDMULTI: 1598 case SIOCDELMULTI: 1599 my_setmulti(sc); 1600 error = 0; 1601 break; 1602 case SIOCGIFMEDIA: 1603 case SIOCSIFMEDIA: 1604 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1605 break; 1606 default: 1607 error = ether_ioctl(ifp, command, data); 1608 break; 1609 } 1610 1611 crit_exit(); 1612 return (error); 1613 } 1614 1615 static void 1616 my_watchdog(struct ifnet * ifp) 1617 { 1618 struct my_softc *sc = ifp->if_softc; 1619 1620 crit_enter(); 1621 1622 if (sc->my_autoneg) { 1623 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1); 1624 crit_exit(); 1625 return; 1626 } 1627 IFNET_STAT_INC(ifp, oerrors, 1); 1628 kprintf("my%d: watchdog timeout\n", sc->my_unit); 1629 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1630 kprintf("my%d: no carrier - transceiver cable problem?\n", 1631 sc->my_unit); 1632 my_stop(sc); 1633 my_reset(sc); 1634 my_init(sc); 1635 if (!ifq_is_empty(&ifp->if_snd)) 1636 if_devstart(ifp); 1637 crit_exit(); 1638 } 1639 1640 1641 /* 1642 * Stop the adapter and free any mbufs allocated to the RX and TX lists. 1643 */ 1644 static void 1645 my_stop(struct my_softc * sc) 1646 { 1647 struct ifnet *ifp = &sc->arpcom.ac_if; 1648 int i; 1649 1650 ifp->if_timer = 0; 1651 1652 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE)); 1653 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1654 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000); 1655 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000); 1656 1657 /* 1658 * Free data in the RX lists. 1659 */ 1660 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1661 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) { 1662 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf); 1663 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL; 1664 } 1665 } 1666 bzero((char *)&sc->my_ldata->my_rx_list, 1667 sizeof(sc->my_ldata->my_rx_list)); 1668 /* 1669 * Free the TX list buffers. 1670 */ 1671 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1672 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) { 1673 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf); 1674 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL; 1675 } 1676 } 1677 bzero((char *)&sc->my_ldata->my_tx_list, 1678 sizeof(sc->my_ldata->my_tx_list)); 1679 ifp->if_flags &= ~IFF_RUNNING; 1680 ifq_clr_oactive(&ifp->if_snd); 1681 } 1682 1683 /* 1684 * Stop all chip I/O so that the kernel's probe routines don't get confused 1685 * by errant DMAs when rebooting. 1686 */ 1687 static void 1688 my_shutdown(device_t dev) 1689 { 1690 struct my_softc *sc; 1691 1692 sc = device_get_softc(dev); 1693 my_stop(sc); 1694 return; 1695 } 1696