1 /* 2 * Copyright (c) 2002 Myson Technology Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/ 27 * 28 * $FreeBSD: src/sys/dev/my/if_my.c,v 1.2.2.4 2002/04/17 02:05:27 julian Exp $ 29 * $DragonFly: src/sys/dev/netif/my/if_my.c,v 1.3 2003/07/26 14:25:22 rob Exp $ 30 * 31 * Myson fast ethernet PCI NIC driver 32 * 33 * $Id: if_my.c,v 1.40 2001/11/30 03:55:00 <yen_cw@myson.com.tw> wpaul Exp $ 34 */ 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/queue.h> 43 #include <sys/types.h> 44 #include <sys/bus.h> 45 #include <sys/module.h> 46 47 #define NBPFILTER 1 48 49 #include <net/if.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_media.h> 53 #include <net/if_dl.h> 54 #include <net/bpf.h> 55 56 #include <vm/vm.h> /* for vtophys */ 57 #include <vm/pmap.h> /* for vtophys */ 58 #include <machine/clock.h> /* for DELAY */ 59 #include <machine/bus_memio.h> 60 #include <machine/bus_pio.h> 61 #include <machine/bus.h> 62 #include <machine/resource.h> 63 #include <sys/bus.h> 64 #include <sys/rman.h> 65 66 #include <pci/pcireg.h> 67 #include <pci/pcivar.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 72 #include "miibus_if.h" 73 74 /* 75 * #define MY_USEIOSPACE 76 */ 77 78 static int MY_USEIOSPACE = 1; 79 80 #if (MY_USEIOSPACE) 81 #define MY_RES SYS_RES_IOPORT 82 #define MY_RID MY_PCI_LOIO 83 #else 84 #define MY_RES SYS_RES_MEMORY 85 #define MY_RID MY_PCI_LOMEM 86 #endif 87 88 89 #include <dev/my/if_myreg.h> 90 91 /* 92 * Various supported device vendors/types and their names. 93 */ 94 struct my_type *my_info_tmp; 95 static struct my_type my_devs[] = { 96 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"}, 97 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"}, 98 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"}, 99 {0, 0, NULL} 100 }; 101 102 /* 103 * Various supported PHY vendors/types and their names. Note that this driver 104 * will work with pretty much any MII-compliant PHY, so failure to positively 105 * identify the chip is not a fatal error. 106 */ 107 static struct my_type my_phys[] = { 108 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"}, 109 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"}, 110 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"}, 111 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"}, 112 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"}, 113 {0, 0, "<MII-compliant physical interface>"} 114 }; 115 116 static int my_probe(device_t); 117 static int my_attach(device_t); 118 static int my_detach(device_t); 119 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *); 120 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *); 121 static void my_rxeof(struct my_softc *); 122 static void my_txeof(struct my_softc *); 123 static void my_txeoc(struct my_softc *); 124 static void my_intr(void *); 125 static void my_start(struct ifnet *); 126 static int my_ioctl(struct ifnet *, u_long, caddr_t); 127 static void my_init(void *); 128 static void my_stop(struct my_softc *); 129 static void my_watchdog(struct ifnet *); 130 static void my_shutdown(device_t); 131 static int my_ifmedia_upd(struct ifnet *); 132 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *); 133 static u_int16_t my_phy_readreg(struct my_softc *, int); 134 static void my_phy_writereg(struct my_softc *, int, int); 135 static void my_autoneg_xmit(struct my_softc *); 136 static void my_autoneg_mii(struct my_softc *, int, int); 137 static void my_setmode_mii(struct my_softc *, int); 138 static void my_getmode_mii(struct my_softc *); 139 static void my_setcfg(struct my_softc *, int); 140 static u_int8_t my_calchash(caddr_t); 141 static void my_setmulti(struct my_softc *); 142 static void my_reset(struct my_softc *); 143 static int my_list_rx_init(struct my_softc *); 144 static int my_list_tx_init(struct my_softc *); 145 static long my_send_cmd_to_phy(struct my_softc *, int, int); 146 147 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 148 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 149 150 static device_method_t my_methods[] = { 151 /* Device interface */ 152 DEVMETHOD(device_probe, my_probe), 153 DEVMETHOD(device_attach, my_attach), 154 DEVMETHOD(device_detach, my_detach), 155 DEVMETHOD(device_shutdown, my_shutdown), 156 157 {0, 0} 158 }; 159 160 static driver_t my_driver = { 161 "my", 162 my_methods, 163 sizeof(struct my_softc) 164 }; 165 166 static devclass_t my_devclass; 167 168 DRIVER_MODULE(if_my, pci, my_driver, my_devclass, 0, 0); 169 170 static long 171 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad) 172 { 173 long miir; 174 int i; 175 int mask, data; 176 177 MY_LOCK(sc); 178 179 /* enable MII output */ 180 miir = CSR_READ_4(sc, MY_MANAGEMENT); 181 miir &= 0xfffffff0; 182 183 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO; 184 185 /* send 32 1's preamble */ 186 for (i = 0; i < 32; i++) { 187 /* low MDC; MDO is already high (miir) */ 188 miir &= ~MY_MASK_MIIR_MII_MDC; 189 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 190 191 /* high MDC */ 192 miir |= MY_MASK_MIIR_MII_MDC; 193 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 194 } 195 196 /* calculate ST+OP+PHYAD+REGAD+TA */ 197 data = opcode | (sc->my_phy_addr << 7) | (regad << 2); 198 199 /* sent out */ 200 mask = 0x8000; 201 while (mask) { 202 /* low MDC, prepare MDO */ 203 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 204 if (mask & data) 205 miir |= MY_MASK_MIIR_MII_MDO; 206 207 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 208 /* high MDC */ 209 miir |= MY_MASK_MIIR_MII_MDC; 210 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 211 DELAY(30); 212 213 /* next */ 214 mask >>= 1; 215 if (mask == 0x2 && opcode == MY_OP_READ) 216 miir &= ~MY_MASK_MIIR_MII_WRITE; 217 } 218 219 MY_UNLOCK(sc); 220 return miir; 221 } 222 223 224 static u_int16_t 225 my_phy_readreg(struct my_softc * sc, int reg) 226 { 227 long miir; 228 int mask, data; 229 230 MY_LOCK(sc); 231 232 if (sc->my_info->my_did == MTD803ID) 233 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2); 234 else { 235 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg); 236 237 /* read data */ 238 mask = 0x8000; 239 data = 0; 240 while (mask) { 241 /* low MDC */ 242 miir &= ~MY_MASK_MIIR_MII_MDC; 243 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 244 245 /* read MDI */ 246 miir = CSR_READ_4(sc, MY_MANAGEMENT); 247 if (miir & MY_MASK_MIIR_MII_MDI) 248 data |= mask; 249 250 /* high MDC, and wait */ 251 miir |= MY_MASK_MIIR_MII_MDC; 252 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 253 DELAY(30); 254 255 /* next */ 256 mask >>= 1; 257 } 258 259 /* low MDC */ 260 miir &= ~MY_MASK_MIIR_MII_MDC; 261 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 262 } 263 264 MY_UNLOCK(sc); 265 return (u_int16_t) data; 266 } 267 268 269 static void 270 my_phy_writereg(struct my_softc * sc, int reg, int data) 271 { 272 long miir; 273 int mask; 274 275 MY_LOCK(sc); 276 277 if (sc->my_info->my_did == MTD803ID) 278 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data); 279 else { 280 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg); 281 282 /* write data */ 283 mask = 0x8000; 284 while (mask) { 285 /* low MDC, prepare MDO */ 286 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 287 if (mask & data) 288 miir |= MY_MASK_MIIR_MII_MDO; 289 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 290 DELAY(1); 291 292 /* high MDC */ 293 miir |= MY_MASK_MIIR_MII_MDC; 294 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 295 DELAY(1); 296 297 /* next */ 298 mask >>= 1; 299 } 300 301 /* low MDC */ 302 miir &= ~MY_MASK_MIIR_MII_MDC; 303 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 304 } 305 MY_UNLOCK(sc); 306 return; 307 } 308 309 static u_int8_t 310 my_calchash(caddr_t addr) 311 { 312 u_int32_t crc, carry; 313 int i, j; 314 u_int8_t c; 315 316 /* Compute CRC for the address value. */ 317 crc = 0xFFFFFFFF; /* initial value */ 318 319 for (i = 0; i < 6; i++) { 320 c = *(addr + i); 321 for (j = 0; j < 8; j++) { 322 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 323 crc <<= 1; 324 c >>= 1; 325 if (carry) 326 crc = (crc ^ 0x04c11db6) | carry; 327 } 328 } 329 330 /* 331 * return the filter bit position Note: I arrived at the following 332 * nonsense through experimentation. It's not the usual way to 333 * generate the bit position but it's the only thing I could come up 334 * with that works. 335 */ 336 return (~(crc >> 26) & 0x0000003F); 337 } 338 339 340 /* 341 * Program the 64-bit multicast hash filter. 342 */ 343 static void 344 my_setmulti(struct my_softc * sc) 345 { 346 struct ifnet *ifp; 347 int h = 0; 348 u_int32_t hashes[2] = {0, 0}; 349 struct ifmultiaddr *ifma; 350 u_int32_t rxfilt; 351 int mcnt = 0; 352 353 MY_LOCK(sc); 354 355 ifp = &sc->arpcom.ac_if; 356 357 rxfilt = CSR_READ_4(sc, MY_TCRRCR); 358 359 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 360 rxfilt |= MY_AM; 361 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 362 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF); 363 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF); 364 365 MY_UNLOCK(sc); 366 367 return; 368 } 369 /* first, zot all the existing hash bits */ 370 CSR_WRITE_4(sc, MY_MAR0, 0); 371 CSR_WRITE_4(sc, MY_MAR1, 0); 372 373 /* now program new ones */ 374 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 375 if (ifma->ifma_addr->sa_family != AF_LINK) 376 continue; 377 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr)); 378 if (h < 32) 379 hashes[0] |= (1 << h); 380 else 381 hashes[1] |= (1 << (h - 32)); 382 mcnt++; 383 } 384 385 if (mcnt) 386 rxfilt |= MY_AM; 387 else 388 rxfilt &= ~MY_AM; 389 CSR_WRITE_4(sc, MY_MAR0, hashes[0]); 390 CSR_WRITE_4(sc, MY_MAR1, hashes[1]); 391 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 392 MY_UNLOCK(sc); 393 return; 394 } 395 396 /* 397 * Initiate an autonegotiation session. 398 */ 399 static void 400 my_autoneg_xmit(struct my_softc * sc) 401 { 402 u_int16_t phy_sts = 0; 403 404 MY_LOCK(sc); 405 406 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 407 DELAY(500); 408 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 409 410 phy_sts = my_phy_readreg(sc, PHY_BMCR); 411 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR; 412 my_phy_writereg(sc, PHY_BMCR, phy_sts); 413 414 MY_UNLOCK(sc); 415 return; 416 } 417 418 419 /* 420 * Invoke autonegotiation on a PHY. 421 */ 422 static void 423 my_autoneg_mii(struct my_softc * sc, int flag, int verbose) 424 { 425 u_int16_t phy_sts = 0, media, advert, ability; 426 u_int16_t ability2 = 0; 427 struct ifnet *ifp; 428 struct ifmedia *ifm; 429 430 MY_LOCK(sc); 431 432 ifm = &sc->ifmedia; 433 ifp = &sc->arpcom.ac_if; 434 435 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 436 437 #ifndef FORCE_AUTONEG_TFOUR 438 /* 439 * First, see if autoneg is supported. If not, there's no point in 440 * continuing. 441 */ 442 phy_sts = my_phy_readreg(sc, PHY_BMSR); 443 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 444 if (verbose) 445 printf("my%d: autonegotiation not supported\n", 446 sc->my_unit); 447 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 448 MY_UNLOCK(sc); 449 return; 450 } 451 #endif 452 switch (flag) { 453 case MY_FLAG_FORCEDELAY: 454 /* 455 * XXX Never use this option anywhere but in the probe 456 * routine: making the kernel stop dead in its tracks for 457 * three whole seconds after we've gone multi-user is really 458 * bad manners. 459 */ 460 my_autoneg_xmit(sc); 461 DELAY(5000000); 462 break; 463 case MY_FLAG_SCHEDDELAY: 464 /* 465 * Wait for the transmitter to go idle before starting an 466 * autoneg session, otherwise my_start() may clobber our 467 * timeout, and we don't want to allow transmission during an 468 * autoneg session since that can screw it up. 469 */ 470 if (sc->my_cdata.my_tx_head != NULL) { 471 sc->my_want_auto = 1; 472 MY_UNLOCK(sc); 473 return; 474 } 475 my_autoneg_xmit(sc); 476 ifp->if_timer = 5; 477 sc->my_autoneg = 1; 478 sc->my_want_auto = 0; 479 MY_UNLOCK(sc); 480 return; 481 case MY_FLAG_DELAYTIMEO: 482 ifp->if_timer = 0; 483 sc->my_autoneg = 0; 484 break; 485 default: 486 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag); 487 MY_UNLOCK(sc); 488 return; 489 } 490 491 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 492 if (verbose) 493 printf("my%d: autoneg complete, ", sc->my_unit); 494 phy_sts = my_phy_readreg(sc, PHY_BMSR); 495 } else { 496 if (verbose) 497 printf("my%d: autoneg not complete, ", sc->my_unit); 498 } 499 500 media = my_phy_readreg(sc, PHY_BMCR); 501 502 /* Link is good. Report modes and set duplex mode. */ 503 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 504 if (verbose) 505 printf("my%d: link status good. ", sc->my_unit); 506 advert = my_phy_readreg(sc, PHY_ANAR); 507 ability = my_phy_readreg(sc, PHY_LPAR); 508 if ((sc->my_pinfo->my_vid == MarvellPHYID0) || 509 (sc->my_pinfo->my_vid == LevelOnePHYID0)) { 510 ability2 = my_phy_readreg(sc, PHY_1000SR); 511 if (ability2 & PHY_1000SR_1000BTXFULL) { 512 advert = 0; 513 ability = 0; 514 /* 515 * this version did not support 1000M, 516 * ifm->ifm_media = 517 * IFM_ETHER|IFM_1000_TX|IFM_FDX; 518 */ 519 ifm->ifm_media = 520 IFM_ETHER | IFM_100_TX | IFM_FDX; 521 media &= ~PHY_BMCR_SPEEDSEL; 522 media |= PHY_BMCR_1000; 523 media |= PHY_BMCR_DUPLEX; 524 printf("(full-duplex, 1000Mbps)\n"); 525 } else if (ability2 & PHY_1000SR_1000BTXHALF) { 526 advert = 0; 527 ability = 0; 528 /* 529 * this version did not support 1000M, 530 * ifm->ifm_media = IFM_ETHER|IFM_1000_TX; 531 */ 532 ifm->ifm_media = IFM_ETHER | IFM_100_TX; 533 media &= ~PHY_BMCR_SPEEDSEL; 534 media &= ~PHY_BMCR_DUPLEX; 535 media |= PHY_BMCR_1000; 536 printf("(half-duplex, 1000Mbps)\n"); 537 } 538 } 539 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 540 ifm->ifm_media = IFM_ETHER | IFM_100_T4; 541 media |= PHY_BMCR_SPEEDSEL; 542 media &= ~PHY_BMCR_DUPLEX; 543 printf("(100baseT4)\n"); 544 } else if (advert & PHY_ANAR_100BTXFULL && 545 ability & PHY_ANAR_100BTXFULL) { 546 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 547 media |= PHY_BMCR_SPEEDSEL; 548 media |= PHY_BMCR_DUPLEX; 549 printf("(full-duplex, 100Mbps)\n"); 550 } else if (advert & PHY_ANAR_100BTXHALF && 551 ability & PHY_ANAR_100BTXHALF) { 552 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 553 media |= PHY_BMCR_SPEEDSEL; 554 media &= ~PHY_BMCR_DUPLEX; 555 printf("(half-duplex, 100Mbps)\n"); 556 } else if (advert & PHY_ANAR_10BTFULL && 557 ability & PHY_ANAR_10BTFULL) { 558 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 559 media &= ~PHY_BMCR_SPEEDSEL; 560 media |= PHY_BMCR_DUPLEX; 561 printf("(full-duplex, 10Mbps)\n"); 562 } else if (advert) { 563 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 564 media &= ~PHY_BMCR_SPEEDSEL; 565 media &= ~PHY_BMCR_DUPLEX; 566 printf("(half-duplex, 10Mbps)\n"); 567 } 568 media &= ~PHY_BMCR_AUTONEGENBL; 569 570 /* Set ASIC's duplex mode to match the PHY. */ 571 my_phy_writereg(sc, PHY_BMCR, media); 572 my_setcfg(sc, media); 573 } else { 574 if (verbose) 575 printf("my%d: no carrier\n", sc->my_unit); 576 } 577 578 my_init(sc); 579 if (sc->my_tx_pend) { 580 sc->my_autoneg = 0; 581 sc->my_tx_pend = 0; 582 my_start(ifp); 583 } 584 MY_UNLOCK(sc); 585 return; 586 } 587 588 /* 589 * To get PHY ability. 590 */ 591 static void 592 my_getmode_mii(struct my_softc * sc) 593 { 594 u_int16_t bmsr; 595 struct ifnet *ifp; 596 597 MY_LOCK(sc); 598 ifp = &sc->arpcom.ac_if; 599 bmsr = my_phy_readreg(sc, PHY_BMSR); 600 if (bootverbose) 601 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr); 602 603 /* fallback */ 604 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 605 606 if (bmsr & PHY_BMSR_10BTHALF) { 607 if (bootverbose) 608 printf("my%d: 10Mbps half-duplex mode supported\n", 609 sc->my_unit); 610 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 611 0, NULL); 612 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 613 } 614 if (bmsr & PHY_BMSR_10BTFULL) { 615 if (bootverbose) 616 printf("my%d: 10Mbps full-duplex mode supported\n", 617 sc->my_unit); 618 619 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 620 0, NULL); 621 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 622 } 623 if (bmsr & PHY_BMSR_100BTXHALF) { 624 if (bootverbose) 625 printf("my%d: 100Mbps half-duplex mode supported\n", 626 sc->my_unit); 627 ifp->if_baudrate = 100000000; 628 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 629 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 630 0, NULL); 631 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 632 } 633 if (bmsr & PHY_BMSR_100BTXFULL) { 634 if (bootverbose) 635 printf("my%d: 100Mbps full-duplex mode supported\n", 636 sc->my_unit); 637 ifp->if_baudrate = 100000000; 638 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 639 0, NULL); 640 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 641 } 642 /* Some also support 100BaseT4. */ 643 if (bmsr & PHY_BMSR_100BT4) { 644 if (bootverbose) 645 printf("my%d: 100baseT4 mode supported\n", sc->my_unit); 646 ifp->if_baudrate = 100000000; 647 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL); 648 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4; 649 #ifdef FORCE_AUTONEG_TFOUR 650 if (bootverbose) 651 printf("my%d: forcing on autoneg support for BT4\n", 652 sc->my_unit); 653 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL): 654 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 655 #endif 656 } 657 #if 0 /* this version did not support 1000M, */ 658 if (sc->my_pinfo->my_vid == MarvellPHYID0) { 659 if (bootverbose) 660 printf("my%d: 1000Mbps half-duplex mode supported\n", 661 sc->my_unit); 662 663 ifp->if_baudrate = 1000000000; 664 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_TX, 0, NULL); 665 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_TX | IFM_HDX, 666 0, NULL); 667 if (bootverbose) 668 printf("my%d: 1000Mbps full-duplex mode supported\n", 669 sc->my_unit); 670 ifp->if_baudrate = 1000000000; 671 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_TX | IFM_FDX, 672 0, NULL); 673 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_TX | IFM_FDX; 674 } 675 #endif 676 if (bmsr & PHY_BMSR_CANAUTONEG) { 677 if (bootverbose) 678 printf("my%d: autoneg supported\n", sc->my_unit); 679 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 680 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 681 } 682 MY_UNLOCK(sc); 683 return; 684 } 685 686 /* 687 * Set speed and duplex mode. 688 */ 689 static void 690 my_setmode_mii(struct my_softc * sc, int media) 691 { 692 u_int16_t bmcr; 693 struct ifnet *ifp; 694 695 MY_LOCK(sc); 696 ifp = &sc->arpcom.ac_if; 697 /* 698 * If an autoneg session is in progress, stop it. 699 */ 700 if (sc->my_autoneg) { 701 printf("my%d: canceling autoneg session\n", sc->my_unit); 702 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0; 703 bmcr = my_phy_readreg(sc, PHY_BMCR); 704 bmcr &= ~PHY_BMCR_AUTONEGENBL; 705 my_phy_writereg(sc, PHY_BMCR, bmcr); 706 } 707 printf("my%d: selecting MII, ", sc->my_unit); 708 bmcr = my_phy_readreg(sc, PHY_BMCR); 709 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 | 710 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK); 711 712 #if 0 /* this version did not support 1000M, */ 713 if (IFM_SUBTYPE(media) == IFM_1000_TX) { 714 printf("1000Mbps/T4, half-duplex\n"); 715 bmcr &= ~PHY_BMCR_SPEEDSEL; 716 bmcr &= ~PHY_BMCR_DUPLEX; 717 bmcr |= PHY_BMCR_1000; 718 } 719 #endif 720 if (IFM_SUBTYPE(media) == IFM_100_T4) { 721 printf("100Mbps/T4, half-duplex\n"); 722 bmcr |= PHY_BMCR_SPEEDSEL; 723 bmcr &= ~PHY_BMCR_DUPLEX; 724 } 725 if (IFM_SUBTYPE(media) == IFM_100_TX) { 726 printf("100Mbps, "); 727 bmcr |= PHY_BMCR_SPEEDSEL; 728 } 729 if (IFM_SUBTYPE(media) == IFM_10_T) { 730 printf("10Mbps, "); 731 bmcr &= ~PHY_BMCR_SPEEDSEL; 732 } 733 if ((media & IFM_GMASK) == IFM_FDX) { 734 printf("full duplex\n"); 735 bmcr |= PHY_BMCR_DUPLEX; 736 } else { 737 printf("half duplex\n"); 738 bmcr &= ~PHY_BMCR_DUPLEX; 739 } 740 my_phy_writereg(sc, PHY_BMCR, bmcr); 741 my_setcfg(sc, bmcr); 742 MY_UNLOCK(sc); 743 return; 744 } 745 746 /* 747 * The Myson manual states that in order to fiddle with the 'full-duplex' and 748 * '100Mbps' bits in the netconfig register, we first have to put the 749 * transmit and/or receive logic in the idle state. 750 */ 751 static void 752 my_setcfg(struct my_softc * sc, int bmcr) 753 { 754 int i, restart = 0; 755 756 MY_LOCK(sc); 757 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { 758 restart = 1; 759 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE)); 760 for (i = 0; i < MY_TIMEOUT; i++) { 761 DELAY(10); 762 if (!(CSR_READ_4(sc, MY_TCRRCR) & 763 (MY_TXRUN | MY_RXRUN))) 764 break; 765 } 766 if (i == MY_TIMEOUT) 767 printf("my%d: failed to force tx and rx to idle \n", 768 sc->my_unit); 769 } 770 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000); 771 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10); 772 if (bmcr & PHY_BMCR_1000) 773 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000); 774 else if (!(bmcr & PHY_BMCR_SPEEDSEL)) 775 MY_SETBIT(sc, MY_TCRRCR, MY_PS10); 776 if (bmcr & PHY_BMCR_DUPLEX) 777 MY_SETBIT(sc, MY_TCRRCR, MY_FD); 778 else 779 MY_CLRBIT(sc, MY_TCRRCR, MY_FD); 780 if (restart) 781 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE); 782 MY_UNLOCK(sc); 783 return; 784 } 785 786 static void 787 my_reset(struct my_softc * sc) 788 { 789 int i; 790 791 MY_LOCK(sc); 792 MY_SETBIT(sc, MY_BCR, MY_SWR); 793 for (i = 0; i < MY_TIMEOUT; i++) { 794 DELAY(10); 795 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) 796 break; 797 } 798 if (i == MY_TIMEOUT) 799 printf("m0x%d: reset never completed!\n", sc->my_unit); 800 801 /* Wait a little while for the chip to get its brains in order. */ 802 DELAY(1000); 803 MY_UNLOCK(sc); 804 return; 805 } 806 807 /* 808 * Probe for a Myson chip. Check the PCI vendor and device IDs against our 809 * list and return a device name if we find a match. 810 */ 811 static int 812 my_probe(device_t dev) 813 { 814 struct my_type *t; 815 816 t = my_devs; 817 while (t->my_name != NULL) { 818 if ((pci_get_vendor(dev) == t->my_vid) && 819 (pci_get_device(dev) == t->my_did)) { 820 device_set_desc(dev, t->my_name); 821 my_info_tmp = t; 822 return (0); 823 } 824 t++; 825 } 826 return (ENXIO); 827 } 828 829 /* 830 * Attach the interface. Allocate softc structures, do ifmedia setup and 831 * ethernet/BPF attach. 832 */ 833 static int 834 my_attach(device_t dev) 835 { 836 int s, i; 837 u_char eaddr[ETHER_ADDR_LEN]; 838 u_int32_t command, iobase; 839 struct my_softc *sc; 840 struct ifnet *ifp; 841 int media = IFM_ETHER | IFM_100_TX | IFM_FDX; 842 unsigned int round; 843 caddr_t roundptr; 844 struct my_type *p; 845 u_int16_t phy_vid, phy_did, phy_sts = 0; 846 int rid, unit, error = 0; 847 848 s = splimp(); 849 sc = device_get_softc(dev); 850 unit = device_get_unit(dev); 851 if (sc == NULL) { 852 printf("my%d: no memory for softc struct!\n", unit); 853 error = ENXIO; 854 goto fail; 855 856 } 857 bzero(sc, sizeof(struct my_softc)); 858 /*mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);*/ 859 MY_LOCK(sc); 860 861 /* 862 * Map control/status registers. 863 */ 864 #if 0 865 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 866 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 867 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command & 0x000000ff, 4); 868 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 869 #endif 870 command = pci_read_config(dev, PCIR_COMMAND, 4); 871 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 872 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4); 873 command = pci_read_config(dev, PCIR_COMMAND, 4); 874 875 if (my_info_tmp->my_did == MTD800ID) { 876 iobase = pci_read_config(dev, MY_PCI_LOIO, 4); 877 if (iobase & 0x300) 878 MY_USEIOSPACE = 0; 879 } 880 if (MY_USEIOSPACE) { 881 if (!(command & PCIM_CMD_PORTEN)) { 882 printf("my%d: failed to enable I/O ports!\n", unit); 883 free(sc, M_DEVBUF); 884 error = ENXIO; 885 goto fail; 886 } 887 #if 0 888 if (!pci_map_port(config_id, MY_PCI_LOIO, (u_int16_t *) & (sc->my_bhandle))) { 889 printf("my%d: couldn't map ports\n", unit); 890 error = ENXIO; 891 goto fail; 892 } 893 894 sc->my_btag = I386_BUS_SPACE_IO; 895 #endif 896 } else { 897 if (!(command & PCIM_CMD_MEMEN)) { 898 printf("my%d: failed to enable memory mapping!\n", 899 unit); 900 error = ENXIO; 901 goto fail; 902 } 903 #if 0 904 if (!pci_map_mem(config_id, MY_PCI_LOMEM, &vbase, &pbase)) { 905 printf ("my%d: couldn't map memory\n", unit); 906 error = ENXIO; 907 goto fail; 908 } 909 sc->my_btag = I386_BUS_SPACE_MEM; 910 sc->my_bhandle = vbase; 911 #endif 912 } 913 914 rid = MY_RID; 915 sc->my_res = bus_alloc_resource(dev, MY_RES, &rid, 916 0, ~0, 1, RF_ACTIVE); 917 918 if (sc->my_res == NULL) { 919 printf("my%d: couldn't map ports/memory\n", unit); 920 error = ENXIO; 921 goto fail; 922 } 923 sc->my_btag = rman_get_bustag(sc->my_res); 924 sc->my_bhandle = rman_get_bushandle(sc->my_res); 925 926 rid = 0; 927 sc->my_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 928 RF_SHAREABLE | RF_ACTIVE); 929 930 if (sc->my_irq == NULL) { 931 printf("my%d: couldn't map interrupt\n", unit); 932 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 933 error = ENXIO; 934 goto fail; 935 } 936 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET, 937 my_intr, sc, &sc->my_intrhand); 938 939 if (error) { 940 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 941 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 942 printf("my%d: couldn't set up irq\n", unit); 943 goto fail; 944 } 945 callout_handle_init(&sc->my_stat_ch); 946 947 sc->my_info = my_info_tmp; 948 949 /* Reset the adapter. */ 950 my_reset(sc); 951 952 /* 953 * Get station address 954 */ 955 for (i = 0; i < ETHER_ADDR_LEN; ++i) 956 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); 957 958 /* 959 * A Myson chip was detected. Inform the world. 960 */ 961 printf("my%d: Ethernet address: %6D\n", unit, eaddr, ":"); 962 963 sc->my_unit = unit; 964 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 965 966 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8, 967 M_DEVBUF, M_NOWAIT); 968 if (sc->my_ldata_ptr == NULL) { 969 free(sc, M_DEVBUF); 970 printf("my%d: no memory for list buffers!\n", unit); 971 error = ENXIO; 972 goto fail; 973 } 974 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr; 975 round = (unsigned int)sc->my_ldata_ptr & 0xF; 976 roundptr = sc->my_ldata_ptr; 977 for (i = 0; i < 8; i++) { 978 if (round % 8) { 979 round++; 980 roundptr++; 981 } else 982 break; 983 } 984 sc->my_ldata = (struct my_list_data *) roundptr; 985 bzero(sc->my_ldata, sizeof(struct my_list_data)); 986 987 ifp = &sc->arpcom.ac_if; 988 ifp->if_softc = sc; 989 ifp->if_unit = unit; 990 ifp->if_name = "my"; 991 ifp->if_mtu = ETHERMTU; 992 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 993 ifp->if_ioctl = my_ioctl; 994 ifp->if_output = ether_output; 995 ifp->if_start = my_start; 996 ifp->if_watchdog = my_watchdog; 997 ifp->if_init = my_init; 998 ifp->if_baudrate = 10000000; 999 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1000 1001 if (sc->my_info->my_did == MTD803ID) 1002 sc->my_pinfo = my_phys; 1003 else { 1004 if (bootverbose) 1005 printf("my%d: probing for a PHY\n", sc->my_unit); 1006 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) { 1007 if (bootverbose) 1008 printf("my%d: checking address: %d\n", 1009 sc->my_unit, i); 1010 sc->my_phy_addr = i; 1011 phy_sts = my_phy_readreg(sc, PHY_BMSR); 1012 if ((phy_sts != 0) && (phy_sts != 0xffff)) 1013 break; 1014 else 1015 phy_sts = 0; 1016 } 1017 if (phy_sts) { 1018 phy_vid = my_phy_readreg(sc, PHY_VENID); 1019 phy_did = my_phy_readreg(sc, PHY_DEVID); 1020 if (bootverbose) { 1021 printf("my%d: found PHY at address %d, ", 1022 sc->my_unit, sc->my_phy_addr); 1023 printf("vendor id: %x device id: %x\n", 1024 phy_vid, phy_did); 1025 } 1026 p = my_phys; 1027 while (p->my_vid) { 1028 if (phy_vid == p->my_vid) { 1029 sc->my_pinfo = p; 1030 break; 1031 } 1032 p++; 1033 } 1034 if (sc->my_pinfo == NULL) 1035 sc->my_pinfo = &my_phys[PHY_UNKNOWN]; 1036 if (bootverbose) 1037 printf("my%d: PHY type: %s\n", 1038 sc->my_unit, sc->my_pinfo->my_name); 1039 } else { 1040 printf("my%d: MII without any phy!\n", sc->my_unit); 1041 error = ENXIO; 1042 goto fail; 1043 } 1044 } 1045 1046 /* Do ifmedia setup. */ 1047 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts); 1048 my_getmode_mii(sc); 1049 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1); 1050 media = sc->ifmedia.ifm_media; 1051 my_stop(sc); 1052 ifmedia_set(&sc->ifmedia, media); 1053 1054 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1055 1056 #if 0 1057 at_shutdown(my_shutdown, sc, SHUTDOWN_POST_SYNC); 1058 shutdownhook_establish(my_shutdown, sc); 1059 #endif 1060 1061 MY_UNLOCK(sc); 1062 return (0); 1063 1064 fail: 1065 MY_UNLOCK(sc); 1066 /*mtx_destroy(&sc->my_mtx);*/ 1067 splx(s); 1068 return (error); 1069 } 1070 1071 static int 1072 my_detach(device_t dev) 1073 { 1074 struct my_softc *sc; 1075 struct ifnet *ifp; 1076 int s; 1077 1078 s = splimp(); 1079 sc = device_get_softc(dev); 1080 MY_LOCK(sc); 1081 ifp = &sc->arpcom.ac_if; 1082 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1083 my_stop(sc); 1084 1085 #if 0 1086 bus_generic_detach(dev); 1087 device_delete_child(dev, sc->rl_miibus); 1088 #endif 1089 1090 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand); 1091 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 1092 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 1093 #if 0 1094 contigfree(sc->my_cdata.my_rx_buf, MY_RXBUFLEN + 32, M_DEVBUF); 1095 #endif 1096 free(sc, M_DEVBUF); 1097 MY_UNLOCK(sc); 1098 splx(s); 1099 /*mtx_destroy(&sc->my_mtx);*/ 1100 return (0); 1101 } 1102 1103 1104 /* 1105 * Initialize the transmit descriptors. 1106 */ 1107 static int 1108 my_list_tx_init(struct my_softc * sc) 1109 { 1110 struct my_chain_data *cd; 1111 struct my_list_data *ld; 1112 int i; 1113 1114 MY_LOCK(sc); 1115 cd = &sc->my_cdata; 1116 ld = sc->my_ldata; 1117 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1118 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i]; 1119 if (i == (MY_TX_LIST_CNT - 1)) 1120 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0]; 1121 else 1122 cd->my_tx_chain[i].my_nextdesc = 1123 &cd->my_tx_chain[i + 1]; 1124 } 1125 cd->my_tx_free = &cd->my_tx_chain[0]; 1126 cd->my_tx_tail = cd->my_tx_head = NULL; 1127 MY_UNLOCK(sc); 1128 return (0); 1129 } 1130 1131 /* 1132 * Initialize the RX descriptors and allocate mbufs for them. Note that we 1133 * arrange the descriptors in a closed ring, so that the last descriptor 1134 * points back to the first. 1135 */ 1136 static int 1137 my_list_rx_init(struct my_softc * sc) 1138 { 1139 struct my_chain_data *cd; 1140 struct my_list_data *ld; 1141 int i; 1142 1143 MY_LOCK(sc); 1144 cd = &sc->my_cdata; 1145 ld = sc->my_ldata; 1146 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1147 cd->my_rx_chain[i].my_ptr = 1148 (struct my_desc *) & ld->my_rx_list[i]; 1149 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) 1150 return (ENOBUFS); 1151 if (i == (MY_RX_LIST_CNT - 1)) { 1152 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0]; 1153 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]); 1154 } else { 1155 cd->my_rx_chain[i].my_nextdesc = 1156 &cd->my_rx_chain[i + 1]; 1157 ld->my_rx_list[i].my_next = 1158 vtophys(&ld->my_rx_list[i + 1]); 1159 } 1160 } 1161 cd->my_rx_head = &cd->my_rx_chain[0]; 1162 MY_UNLOCK(sc); 1163 return (0); 1164 } 1165 1166 /* 1167 * Initialize an RX descriptor and attach an MBUF cluster. 1168 */ 1169 static int 1170 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c) 1171 { 1172 struct mbuf *m_new = NULL; 1173 1174 MY_LOCK(sc); 1175 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1176 if (m_new == NULL) { 1177 printf("my%d: no memory for rx list -- packet dropped!\n", 1178 sc->my_unit); 1179 return (ENOBUFS); 1180 } 1181 MCLGET(m_new, M_DONTWAIT); 1182 if (!(m_new->m_flags & M_EXT)) { 1183 printf("my%d: no memory for rx list -- packet dropped!\n", 1184 sc->my_unit); 1185 m_freem(m_new); 1186 return (ENOBUFS); 1187 } 1188 c->my_mbuf = m_new; 1189 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t)); 1190 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift; 1191 c->my_ptr->my_status = MY_OWNByNIC; 1192 MY_UNLOCK(sc); 1193 return (0); 1194 } 1195 1196 /* 1197 * A frame has been uploaded: pass the resulting mbuf chain up to the higher 1198 * level protocols. 1199 */ 1200 static void 1201 my_rxeof(struct my_softc * sc) 1202 { 1203 struct ether_header *eh; 1204 struct mbuf *m; 1205 struct ifnet *ifp; 1206 struct my_chain_onefrag *cur_rx; 1207 int total_len = 0; 1208 u_int32_t rxstat; 1209 1210 MY_LOCK(sc); 1211 ifp = &sc->arpcom.ac_if; 1212 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status) 1213 & MY_OWNByNIC)) { 1214 cur_rx = sc->my_cdata.my_rx_head; 1215 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc; 1216 1217 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */ 1218 ifp->if_ierrors++; 1219 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1220 continue; 1221 } 1222 /* No errors; receive the packet. */ 1223 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift; 1224 total_len -= ETHER_CRC_LEN; 1225 1226 if (total_len < MINCLSIZE) { 1227 m = m_devget(mtod(cur_rx->my_mbuf, char *), 1228 total_len, 0, ifp, NULL); 1229 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1230 if (m == NULL) { 1231 ifp->if_ierrors++; 1232 continue; 1233 } 1234 } else { 1235 m = cur_rx->my_mbuf; 1236 /* 1237 * Try to conjure up a new mbuf cluster. If that 1238 * fails, it means we have an out of memory condition 1239 * and should leave the buffer in place and continue. 1240 * This will result in a lost packet, but there's 1241 * little else we can do in this situation. 1242 */ 1243 if (my_newbuf(sc, cur_rx) == ENOBUFS) { 1244 ifp->if_ierrors++; 1245 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1246 continue; 1247 } 1248 m->m_pkthdr.rcvif = ifp; 1249 m->m_pkthdr.len = m->m_len = total_len; 1250 } 1251 ifp->if_ipackets++; 1252 eh = mtod(m, struct ether_header *); 1253 #if NBPFILTER > 0 1254 /* 1255 * Handle BPF listeners. Let the BPF user see the packet, but 1256 * don't pass it up to the ether_input() layer unless it's a 1257 * broadcast packet, multicast packet, matches our ethernet 1258 * address or the interface is in promiscuous mode. 1259 */ 1260 if (ifp->if_bpf) { 1261 bpf_mtap(ifp, m); 1262 if (ifp->if_flags & IFF_PROMISC && 1263 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1264 ETHER_ADDR_LEN) && 1265 (eh->ether_dhost[0] & 1) == 0)) { 1266 m_freem(m); 1267 continue; 1268 } 1269 } 1270 #endif 1271 /* Remove header from mbuf and pass it on. */ 1272 m_adj(m, sizeof(struct ether_header)); 1273 ether_input(ifp, eh, m); 1274 } 1275 MY_UNLOCK(sc); 1276 return; 1277 } 1278 1279 1280 /* 1281 * A frame was downloaded to the chip. It's safe for us to clean up the list 1282 * buffers. 1283 */ 1284 static void 1285 my_txeof(struct my_softc * sc) 1286 { 1287 struct my_chain *cur_tx; 1288 struct ifnet *ifp; 1289 1290 MY_LOCK(sc); 1291 ifp = &sc->arpcom.ac_if; 1292 /* Clear the timeout timer. */ 1293 ifp->if_timer = 0; 1294 if (sc->my_cdata.my_tx_head == NULL) 1295 return; 1296 /* 1297 * Go through our tx list and free mbufs for those frames that have 1298 * been transmitted. 1299 */ 1300 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) { 1301 u_int32_t txstat; 1302 1303 cur_tx = sc->my_cdata.my_tx_head; 1304 txstat = MY_TXSTATUS(cur_tx); 1305 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT) 1306 break; 1307 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { 1308 if (txstat & MY_TXERR) { 1309 ifp->if_oerrors++; 1310 if (txstat & MY_EC) /* excessive collision */ 1311 ifp->if_collisions++; 1312 if (txstat & MY_LC) /* late collision */ 1313 ifp->if_collisions++; 1314 } 1315 ifp->if_collisions += (txstat & MY_NCRMASK) >> 1316 MY_NCRShift; 1317 } 1318 ifp->if_opackets++; 1319 m_freem(cur_tx->my_mbuf); 1320 cur_tx->my_mbuf = NULL; 1321 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) { 1322 sc->my_cdata.my_tx_head = NULL; 1323 sc->my_cdata.my_tx_tail = NULL; 1324 break; 1325 } 1326 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc; 1327 } 1328 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { 1329 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask); 1330 } 1331 MY_UNLOCK(sc); 1332 return; 1333 } 1334 1335 /* 1336 * TX 'end of channel' interrupt handler. 1337 */ 1338 static void 1339 my_txeoc(struct my_softc * sc) 1340 { 1341 struct ifnet *ifp; 1342 1343 MY_LOCK(sc); 1344 ifp = &sc->arpcom.ac_if; 1345 ifp->if_timer = 0; 1346 if (sc->my_cdata.my_tx_head == NULL) { 1347 ifp->if_flags &= ~IFF_OACTIVE; 1348 sc->my_cdata.my_tx_tail = NULL; 1349 if (sc->my_want_auto) 1350 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1351 } else { 1352 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) { 1353 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC; 1354 ifp->if_timer = 5; 1355 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); 1356 } 1357 } 1358 MY_UNLOCK(sc); 1359 return; 1360 } 1361 1362 static void 1363 my_intr(void *arg) 1364 { 1365 struct my_softc *sc; 1366 struct ifnet *ifp; 1367 u_int32_t status; 1368 1369 sc = arg; 1370 MY_LOCK(sc); 1371 ifp = &sc->arpcom.ac_if; 1372 if (!(ifp->if_flags & IFF_UP)) { 1373 MY_UNLOCK(sc); 1374 return; 1375 } 1376 /* Disable interrupts. */ 1377 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1378 1379 for (;;) { 1380 status = CSR_READ_4(sc, MY_ISR); 1381 status &= MY_INTRS; 1382 if (status) 1383 CSR_WRITE_4(sc, MY_ISR, status); 1384 else 1385 break; 1386 1387 if (status & MY_RI) /* receive interrupt */ 1388 my_rxeof(sc); 1389 1390 if ((status & MY_RBU) || (status & MY_RxErr)) { 1391 /* rx buffer unavailable or rx error */ 1392 ifp->if_ierrors++; 1393 #ifdef foo 1394 my_stop(sc); 1395 my_reset(sc); 1396 my_init(sc); 1397 #endif 1398 } 1399 if (status & MY_TI) /* tx interrupt */ 1400 my_txeof(sc); 1401 if (status & MY_ETI) /* tx early interrupt */ 1402 my_txeof(sc); 1403 if (status & MY_TBU) /* tx buffer unavailable */ 1404 my_txeoc(sc); 1405 1406 #if 0 /* 90/1/18 delete */ 1407 if (status & MY_FBE) { 1408 my_reset(sc); 1409 my_init(sc); 1410 } 1411 #endif 1412 1413 } 1414 1415 /* Re-enable interrupts. */ 1416 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1417 if (ifp->if_snd.ifq_head != NULL) 1418 my_start(ifp); 1419 MY_UNLOCK(sc); 1420 return; 1421 } 1422 1423 /* 1424 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1425 * pointers to the fragment pointers. 1426 */ 1427 static int 1428 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head) 1429 { 1430 struct my_desc *f = NULL; 1431 int total_len; 1432 struct mbuf *m, *m_new = NULL; 1433 1434 MY_LOCK(sc); 1435 /* calculate the total tx pkt length */ 1436 total_len = 0; 1437 for (m = m_head; m != NULL; m = m->m_next) 1438 total_len += m->m_len; 1439 /* 1440 * Start packing the mbufs in this chain into the fragment pointers. 1441 * Stop when we run out of fragments or hit the end of the mbuf 1442 * chain. 1443 */ 1444 m = m_head; 1445 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1446 if (m_new == NULL) { 1447 printf("my%d: no memory for tx list", sc->my_unit); 1448 return (1); 1449 } 1450 if (m_head->m_pkthdr.len > MHLEN) { 1451 MCLGET(m_new, M_DONTWAIT); 1452 if (!(m_new->m_flags & M_EXT)) { 1453 m_freem(m_new); 1454 printf("my%d: no memory for tx list", sc->my_unit); 1455 return (1); 1456 } 1457 } 1458 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1459 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1460 m_freem(m_head); 1461 m_head = m_new; 1462 f = &c->my_ptr->my_frag[0]; 1463 f->my_status = 0; 1464 f->my_data = vtophys(mtod(m_new, caddr_t)); 1465 total_len = m_new->m_len; 1466 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable; 1467 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */ 1468 f->my_ctl |= total_len; /* buffer size */ 1469 /* 89/12/29 add, for mtd891 *//* [ 89? ] */ 1470 if (sc->my_info->my_did == MTD891ID) 1471 f->my_ctl |= MY_ETIControl | MY_RetryTxLC; 1472 c->my_mbuf = m_head; 1473 c->my_lastdesc = 0; 1474 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]); 1475 MY_UNLOCK(sc); 1476 return (0); 1477 } 1478 1479 /* 1480 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1481 * to the mbuf data regions directly in the transmit lists. We also save a 1482 * copy of the pointers since the transmit list fragment pointers are 1483 * physical addresses. 1484 */ 1485 static void 1486 my_start(struct ifnet * ifp) 1487 { 1488 struct my_softc *sc; 1489 struct mbuf *m_head = NULL; 1490 struct my_chain *cur_tx = NULL, *start_tx; 1491 1492 sc = ifp->if_softc; 1493 MY_LOCK(sc); 1494 if (sc->my_autoneg) { 1495 sc->my_tx_pend = 1; 1496 MY_UNLOCK(sc); 1497 return; 1498 } 1499 /* 1500 * Check for an available queue slot. If there are none, punt. 1501 */ 1502 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) { 1503 ifp->if_flags |= IFF_OACTIVE; 1504 MY_UNLOCK(sc); 1505 return; 1506 } 1507 start_tx = sc->my_cdata.my_tx_free; 1508 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) { 1509 IF_DEQUEUE(&ifp->if_snd, m_head); 1510 if (m_head == NULL) 1511 break; 1512 1513 /* Pick a descriptor off the free list. */ 1514 cur_tx = sc->my_cdata.my_tx_free; 1515 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc; 1516 1517 /* Pack the data into the descriptor. */ 1518 my_encap(sc, cur_tx, m_head); 1519 1520 if (cur_tx != start_tx) 1521 MY_TXOWN(cur_tx) = MY_OWNByNIC; 1522 #if NBPFILTER > 0 1523 /* 1524 * If there's a BPF listener, bounce a copy of this frame to 1525 * him. 1526 */ 1527 if (ifp->if_bpf) 1528 bpf_mtap(ifp, cur_tx->my_mbuf); 1529 #endif 1530 } 1531 /* 1532 * If there are no packets queued, bail. 1533 */ 1534 if (cur_tx == NULL) { 1535 MY_UNLOCK(sc); 1536 return; 1537 } 1538 /* 1539 * Place the request for the upload interrupt in the last descriptor 1540 * in the chain. This way, if we're chaining several packets at once, 1541 * we'll only get an interupt once for the whole chain rather than 1542 * once for each packet. 1543 */ 1544 MY_TXCTL(cur_tx) |= MY_TXIC; 1545 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC; 1546 sc->my_cdata.my_tx_tail = cur_tx; 1547 if (sc->my_cdata.my_tx_head == NULL) 1548 sc->my_cdata.my_tx_head = start_tx; 1549 MY_TXOWN(start_tx) = MY_OWNByNIC; 1550 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */ 1551 1552 /* 1553 * Set a timeout in case the chip goes out to lunch. 1554 */ 1555 ifp->if_timer = 5; 1556 MY_UNLOCK(sc); 1557 return; 1558 } 1559 1560 static void 1561 my_init(void *xsc) 1562 { 1563 struct my_softc *sc = xsc; 1564 struct ifnet *ifp = &sc->arpcom.ac_if; 1565 int s; 1566 u_int16_t phy_bmcr = 0; 1567 1568 MY_LOCK(sc); 1569 if (sc->my_autoneg) { 1570 MY_UNLOCK(sc); 1571 return; 1572 } 1573 s = splimp(); 1574 if (sc->my_pinfo != NULL) 1575 phy_bmcr = my_phy_readreg(sc, PHY_BMCR); 1576 /* 1577 * Cancel pending I/O and free all RX/TX buffers. 1578 */ 1579 my_stop(sc); 1580 my_reset(sc); 1581 1582 /* 1583 * Set cache alignment and burst length. 1584 */ 1585 #if 0 /* 89/9/1 modify, */ 1586 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512); 1587 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF); 1588 #endif 1589 CSR_WRITE_4(sc, MY_BCR, MY_PBL8); 1590 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512); 1591 /* 1592 * 89/12/29 add, for mtd891, 1593 */ 1594 if (sc->my_info->my_did == MTD891ID) { 1595 MY_SETBIT(sc, MY_BCR, MY_PROG); 1596 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced); 1597 } 1598 my_setcfg(sc, phy_bmcr); 1599 /* Init circular RX list. */ 1600 if (my_list_rx_init(sc) == ENOBUFS) { 1601 printf("my%d: init failed: no memory for rx buffers\n", 1602 sc->my_unit); 1603 my_stop(sc); 1604 (void)splx(s); 1605 MY_UNLOCK(sc); 1606 return; 1607 } 1608 /* Init TX descriptors. */ 1609 my_list_tx_init(sc); 1610 1611 /* If we want promiscuous mode, set the allframes bit. */ 1612 if (ifp->if_flags & IFF_PROMISC) 1613 MY_SETBIT(sc, MY_TCRRCR, MY_PROM); 1614 else 1615 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM); 1616 1617 /* 1618 * Set capture broadcast bit to capture broadcast frames. 1619 */ 1620 if (ifp->if_flags & IFF_BROADCAST) 1621 MY_SETBIT(sc, MY_TCRRCR, MY_AB); 1622 else 1623 MY_CLRBIT(sc, MY_TCRRCR, MY_AB); 1624 1625 /* 1626 * Program the multicast filter, if necessary. 1627 */ 1628 my_setmulti(sc); 1629 1630 /* 1631 * Load the address of the RX list. 1632 */ 1633 MY_CLRBIT(sc, MY_TCRRCR, MY_RE); 1634 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0])); 1635 1636 /* 1637 * Enable interrupts. 1638 */ 1639 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1640 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF); 1641 1642 /* Enable receiver and transmitter. */ 1643 MY_SETBIT(sc, MY_TCRRCR, MY_RE); 1644 MY_CLRBIT(sc, MY_TCRRCR, MY_TE); 1645 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0])); 1646 MY_SETBIT(sc, MY_TCRRCR, MY_TE); 1647 1648 /* Restore state of BMCR */ 1649 if (sc->my_pinfo != NULL) 1650 my_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1651 ifp->if_flags |= IFF_RUNNING; 1652 ifp->if_flags &= ~IFF_OACTIVE; 1653 (void)splx(s); 1654 MY_UNLOCK(sc); 1655 return; 1656 } 1657 1658 /* 1659 * Set media options. 1660 */ 1661 1662 static int 1663 my_ifmedia_upd(struct ifnet * ifp) 1664 { 1665 struct my_softc *sc; 1666 struct ifmedia *ifm; 1667 1668 sc = ifp->if_softc; 1669 MY_LOCK(sc); 1670 ifm = &sc->ifmedia; 1671 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) { 1672 MY_UNLOCK(sc); 1673 return (EINVAL); 1674 } 1675 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1676 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1677 else 1678 my_setmode_mii(sc, ifm->ifm_media); 1679 MY_UNLOCK(sc); 1680 return (0); 1681 } 1682 1683 /* 1684 * Report current media status. 1685 */ 1686 1687 static void 1688 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr) 1689 { 1690 struct my_softc *sc; 1691 u_int16_t advert = 0, ability = 0; 1692 1693 sc = ifp->if_softc; 1694 MY_LOCK(sc); 1695 ifmr->ifm_active = IFM_ETHER; 1696 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1697 #if 0 /* this version did not support 1000M, */ 1698 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000) 1699 ifmr->ifm_active = IFM_ETHER | IFM_1000TX; 1700 #endif 1701 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1702 ifmr->ifm_active = IFM_ETHER | IFM_100_TX; 1703 else 1704 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1705 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1706 ifmr->ifm_active |= IFM_FDX; 1707 else 1708 ifmr->ifm_active |= IFM_HDX; 1709 1710 MY_UNLOCK(sc); 1711 return; 1712 } 1713 ability = my_phy_readreg(sc, PHY_LPAR); 1714 advert = my_phy_readreg(sc, PHY_ANAR); 1715 1716 #if 0 /* this version did not support 1000M, */ 1717 if (sc->my_pinfo->my_vid = MarvellPHYID0) { 1718 ability2 = my_phy_readreg(sc, PHY_1000SR); 1719 if (ability2 & PHY_1000SR_1000BTXFULL) { 1720 advert = 0; 1721 ability = 0; 1722 ifmr->ifm_active = IFM_ETHER|IFM_1000_TX|IFM_FDX; 1723 } else if (ability & PHY_1000SR_1000BTXHALF) { 1724 advert = 0; 1725 ability = 0; 1726 ifmr->ifm_active = IFM_ETHER|IFM_1000_TX|IFM_HDX; 1727 } 1728 } 1729 #endif 1730 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) 1731 ifmr->ifm_active = IFM_ETHER | IFM_100_T4; 1732 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) 1733 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1734 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) 1735 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1736 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) 1737 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1738 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) 1739 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1740 MY_UNLOCK(sc); 1741 return; 1742 } 1743 1744 static int 1745 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data) 1746 { 1747 struct my_softc *sc = ifp->if_softc; 1748 struct ifreq *ifr = (struct ifreq *) data; 1749 int s, error = 0; 1750 1751 s = splimp(); 1752 MY_LOCK(sc); 1753 switch (command) { 1754 case SIOCSIFADDR: 1755 case SIOCGIFADDR: 1756 case SIOCSIFMTU: 1757 error = ether_ioctl(ifp, command, data); 1758 break; 1759 case SIOCSIFFLAGS: 1760 if (ifp->if_flags & IFF_UP) 1761 my_init(sc); 1762 else if (ifp->if_flags & IFF_RUNNING) 1763 my_stop(sc); 1764 error = 0; 1765 break; 1766 case SIOCADDMULTI: 1767 case SIOCDELMULTI: 1768 my_setmulti(sc); 1769 error = 0; 1770 break; 1771 case SIOCGIFMEDIA: 1772 case SIOCSIFMEDIA: 1773 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1774 break; 1775 default: 1776 error = EINVAL; 1777 break; 1778 } 1779 MY_UNLOCK(sc); 1780 (void)splx(s); 1781 return (error); 1782 } 1783 1784 static void 1785 my_watchdog(struct ifnet * ifp) 1786 { 1787 struct my_softc *sc; 1788 1789 sc = ifp->if_softc; 1790 MY_LOCK(sc); 1791 if (sc->my_autoneg) { 1792 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1); 1793 MY_UNLOCK(sc); 1794 return; 1795 } 1796 ifp->if_oerrors++; 1797 printf("my%d: watchdog timeout\n", sc->my_unit); 1798 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1799 printf("my%d: no carrier - transceiver cable problem?\n", 1800 sc->my_unit); 1801 my_stop(sc); 1802 my_reset(sc); 1803 my_init(sc); 1804 if (ifp->if_snd.ifq_head != NULL) 1805 my_start(ifp); 1806 MY_LOCK(sc); 1807 return; 1808 } 1809 1810 1811 /* 1812 * Stop the adapter and free any mbufs allocated to the RX and TX lists. 1813 */ 1814 static void 1815 my_stop(struct my_softc * sc) 1816 { 1817 int i; 1818 struct ifnet *ifp; 1819 1820 MY_LOCK(sc); 1821 ifp = &sc->arpcom.ac_if; 1822 ifp->if_timer = 0; 1823 1824 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE)); 1825 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1826 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000); 1827 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000); 1828 1829 /* 1830 * Free data in the RX lists. 1831 */ 1832 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1833 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) { 1834 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf); 1835 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL; 1836 } 1837 } 1838 bzero((char *)&sc->my_ldata->my_rx_list, 1839 sizeof(sc->my_ldata->my_rx_list)); 1840 /* 1841 * Free the TX list buffers. 1842 */ 1843 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1844 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) { 1845 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf); 1846 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL; 1847 } 1848 } 1849 bzero((char *)&sc->my_ldata->my_tx_list, 1850 sizeof(sc->my_ldata->my_tx_list)); 1851 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1852 MY_UNLOCK(sc); 1853 return; 1854 } 1855 1856 /* 1857 * Stop all chip I/O so that the kernel's probe routines don't get confused 1858 * by errant DMAs when rebooting. 1859 */ 1860 static void 1861 my_shutdown(device_t dev) 1862 { 1863 struct my_softc *sc; 1864 1865 sc = device_get_softc(dev); 1866 my_stop(sc); 1867 return; 1868 } 1869