1 /* 2 * Copyright (c) 2002 Myson Technology Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/ 27 * 28 * $FreeBSD: src/sys/dev/my/if_my.c,v 1.2.2.4 2002/04/17 02:05:27 julian Exp $ 29 * $DragonFly: src/sys/dev/netif/my/if_my.c,v 1.16 2005/02/19 00:40:45 joerg Exp $ 30 * 31 * Myson fast ethernet PCI NIC driver 32 * 33 * $Id: if_my.c,v 1.40 2001/11/30 03:55:00 <yen_cw@myson.com.tw> wpaul Exp $ 34 */ 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/queue.h> 43 #include <sys/types.h> 44 #include <sys/bus.h> 45 #include <sys/module.h> 46 47 #define NBPFILTER 1 48 49 #include <net/if.h> 50 #include <net/ifq_var.h> 51 #include <net/if_arp.h> 52 #include <net/ethernet.h> 53 #include <net/if_media.h> 54 #include <net/if_dl.h> 55 #include <net/bpf.h> 56 57 #include <vm/vm.h> /* for vtophys */ 58 #include <vm/pmap.h> /* for vtophys */ 59 #include <machine/clock.h> /* for DELAY */ 60 #include <machine/bus_memio.h> 61 #include <machine/bus_pio.h> 62 #include <machine/bus.h> 63 #include <machine/resource.h> 64 #include <sys/bus.h> 65 #include <sys/rman.h> 66 67 #include <bus/pci/pcireg.h> 68 #include <bus/pci/pcivar.h> 69 70 #include "../mii_layer/mii.h" 71 #include "../mii_layer/miivar.h" 72 73 #include "miibus_if.h" 74 75 /* 76 * #define MY_USEIOSPACE 77 */ 78 79 static int MY_USEIOSPACE = 1; 80 81 #if (MY_USEIOSPACE) 82 #define MY_RES SYS_RES_IOPORT 83 #define MY_RID MY_PCI_LOIO 84 #else 85 #define MY_RES SYS_RES_MEMORY 86 #define MY_RID MY_PCI_LOMEM 87 #endif 88 89 90 #include "if_myreg.h" 91 92 /* 93 * Various supported device vendors/types and their names. 94 */ 95 struct my_type *my_info_tmp; 96 static struct my_type my_devs[] = { 97 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"}, 98 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"}, 99 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"}, 100 {0, 0, NULL} 101 }; 102 103 /* 104 * Various supported PHY vendors/types and their names. Note that this driver 105 * will work with pretty much any MII-compliant PHY, so failure to positively 106 * identify the chip is not a fatal error. 107 */ 108 static struct my_type my_phys[] = { 109 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"}, 110 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"}, 111 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"}, 112 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"}, 113 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"}, 114 {0, 0, "<MII-compliant physical interface>"} 115 }; 116 117 static int my_probe(device_t); 118 static int my_attach(device_t); 119 static int my_detach(device_t); 120 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *); 121 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *); 122 static void my_rxeof(struct my_softc *); 123 static void my_txeof(struct my_softc *); 124 static void my_txeoc(struct my_softc *); 125 static void my_intr(void *); 126 static void my_start(struct ifnet *); 127 static int my_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 128 static void my_init(void *); 129 static void my_stop(struct my_softc *); 130 static void my_watchdog(struct ifnet *); 131 static void my_shutdown(device_t); 132 static int my_ifmedia_upd(struct ifnet *); 133 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *); 134 static u_int16_t my_phy_readreg(struct my_softc *, int); 135 static void my_phy_writereg(struct my_softc *, int, int); 136 static void my_autoneg_xmit(struct my_softc *); 137 static void my_autoneg_mii(struct my_softc *, int, int); 138 static void my_setmode_mii(struct my_softc *, int); 139 static void my_getmode_mii(struct my_softc *); 140 static void my_setcfg(struct my_softc *, int); 141 static u_int8_t my_calchash(caddr_t); 142 static void my_setmulti(struct my_softc *); 143 static void my_reset(struct my_softc *); 144 static int my_list_rx_init(struct my_softc *); 145 static int my_list_tx_init(struct my_softc *); 146 static long my_send_cmd_to_phy(struct my_softc *, int, int); 147 148 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 149 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 150 151 static device_method_t my_methods[] = { 152 /* Device interface */ 153 DEVMETHOD(device_probe, my_probe), 154 DEVMETHOD(device_attach, my_attach), 155 DEVMETHOD(device_detach, my_detach), 156 DEVMETHOD(device_shutdown, my_shutdown), 157 158 {0, 0} 159 }; 160 161 static driver_t my_driver = { 162 "my", 163 my_methods, 164 sizeof(struct my_softc) 165 }; 166 167 static devclass_t my_devclass; 168 169 DECLARE_DUMMY_MODULE(if_my); 170 DRIVER_MODULE(if_my, pci, my_driver, my_devclass, 0, 0); 171 172 static long 173 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad) 174 { 175 long miir; 176 int i; 177 int mask, data; 178 179 MY_LOCK(sc); 180 181 /* enable MII output */ 182 miir = CSR_READ_4(sc, MY_MANAGEMENT); 183 miir &= 0xfffffff0; 184 185 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO; 186 187 /* send 32 1's preamble */ 188 for (i = 0; i < 32; i++) { 189 /* low MDC; MDO is already high (miir) */ 190 miir &= ~MY_MASK_MIIR_MII_MDC; 191 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 192 193 /* high MDC */ 194 miir |= MY_MASK_MIIR_MII_MDC; 195 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 196 } 197 198 /* calculate ST+OP+PHYAD+REGAD+TA */ 199 data = opcode | (sc->my_phy_addr << 7) | (regad << 2); 200 201 /* sent out */ 202 mask = 0x8000; 203 while (mask) { 204 /* low MDC, prepare MDO */ 205 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 206 if (mask & data) 207 miir |= MY_MASK_MIIR_MII_MDO; 208 209 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 210 /* high MDC */ 211 miir |= MY_MASK_MIIR_MII_MDC; 212 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 213 DELAY(30); 214 215 /* next */ 216 mask >>= 1; 217 if (mask == 0x2 && opcode == MY_OP_READ) 218 miir &= ~MY_MASK_MIIR_MII_WRITE; 219 } 220 221 MY_UNLOCK(sc); 222 return miir; 223 } 224 225 226 static u_int16_t 227 my_phy_readreg(struct my_softc * sc, int reg) 228 { 229 long miir; 230 int mask, data; 231 232 MY_LOCK(sc); 233 234 if (sc->my_info->my_did == MTD803ID) 235 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2); 236 else { 237 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg); 238 239 /* read data */ 240 mask = 0x8000; 241 data = 0; 242 while (mask) { 243 /* low MDC */ 244 miir &= ~MY_MASK_MIIR_MII_MDC; 245 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 246 247 /* read MDI */ 248 miir = CSR_READ_4(sc, MY_MANAGEMENT); 249 if (miir & MY_MASK_MIIR_MII_MDI) 250 data |= mask; 251 252 /* high MDC, and wait */ 253 miir |= MY_MASK_MIIR_MII_MDC; 254 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 255 DELAY(30); 256 257 /* next */ 258 mask >>= 1; 259 } 260 261 /* low MDC */ 262 miir &= ~MY_MASK_MIIR_MII_MDC; 263 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 264 } 265 266 MY_UNLOCK(sc); 267 return (u_int16_t) data; 268 } 269 270 271 static void 272 my_phy_writereg(struct my_softc * sc, int reg, int data) 273 { 274 long miir; 275 int mask; 276 277 MY_LOCK(sc); 278 279 if (sc->my_info->my_did == MTD803ID) 280 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data); 281 else { 282 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg); 283 284 /* write data */ 285 mask = 0x8000; 286 while (mask) { 287 /* low MDC, prepare MDO */ 288 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 289 if (mask & data) 290 miir |= MY_MASK_MIIR_MII_MDO; 291 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 292 DELAY(1); 293 294 /* high MDC */ 295 miir |= MY_MASK_MIIR_MII_MDC; 296 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 297 DELAY(1); 298 299 /* next */ 300 mask >>= 1; 301 } 302 303 /* low MDC */ 304 miir &= ~MY_MASK_MIIR_MII_MDC; 305 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 306 } 307 MY_UNLOCK(sc); 308 return; 309 } 310 311 static u_int8_t 312 my_calchash(caddr_t addr) 313 { 314 u_int32_t crc, carry; 315 int i, j; 316 u_int8_t c; 317 318 /* Compute CRC for the address value. */ 319 crc = 0xFFFFFFFF; /* initial value */ 320 321 for (i = 0; i < 6; i++) { 322 c = *(addr + i); 323 for (j = 0; j < 8; j++) { 324 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 325 crc <<= 1; 326 c >>= 1; 327 if (carry) 328 crc = (crc ^ 0x04c11db6) | carry; 329 } 330 } 331 332 /* 333 * return the filter bit position Note: I arrived at the following 334 * nonsense through experimentation. It's not the usual way to 335 * generate the bit position but it's the only thing I could come up 336 * with that works. 337 */ 338 return (~(crc >> 26) & 0x0000003F); 339 } 340 341 342 /* 343 * Program the 64-bit multicast hash filter. 344 */ 345 static void 346 my_setmulti(struct my_softc * sc) 347 { 348 struct ifnet *ifp; 349 int h = 0; 350 u_int32_t hashes[2] = {0, 0}; 351 struct ifmultiaddr *ifma; 352 u_int32_t rxfilt; 353 int mcnt = 0; 354 355 MY_LOCK(sc); 356 357 ifp = &sc->arpcom.ac_if; 358 359 rxfilt = CSR_READ_4(sc, MY_TCRRCR); 360 361 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 362 rxfilt |= MY_AM; 363 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 364 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF); 365 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF); 366 367 MY_UNLOCK(sc); 368 369 return; 370 } 371 /* first, zot all the existing hash bits */ 372 CSR_WRITE_4(sc, MY_MAR0, 0); 373 CSR_WRITE_4(sc, MY_MAR1, 0); 374 375 /* now program new ones */ 376 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 377 if (ifma->ifma_addr->sa_family != AF_LINK) 378 continue; 379 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr)); 380 if (h < 32) 381 hashes[0] |= (1 << h); 382 else 383 hashes[1] |= (1 << (h - 32)); 384 mcnt++; 385 } 386 387 if (mcnt) 388 rxfilt |= MY_AM; 389 else 390 rxfilt &= ~MY_AM; 391 CSR_WRITE_4(sc, MY_MAR0, hashes[0]); 392 CSR_WRITE_4(sc, MY_MAR1, hashes[1]); 393 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 394 MY_UNLOCK(sc); 395 return; 396 } 397 398 /* 399 * Initiate an autonegotiation session. 400 */ 401 static void 402 my_autoneg_xmit(struct my_softc * sc) 403 { 404 u_int16_t phy_sts = 0; 405 406 MY_LOCK(sc); 407 408 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 409 DELAY(500); 410 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 411 412 phy_sts = my_phy_readreg(sc, PHY_BMCR); 413 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR; 414 my_phy_writereg(sc, PHY_BMCR, phy_sts); 415 416 MY_UNLOCK(sc); 417 return; 418 } 419 420 421 /* 422 * Invoke autonegotiation on a PHY. 423 */ 424 static void 425 my_autoneg_mii(struct my_softc * sc, int flag, int verbose) 426 { 427 u_int16_t phy_sts = 0, media, advert, ability; 428 u_int16_t ability2 = 0; 429 struct ifnet *ifp; 430 struct ifmedia *ifm; 431 432 MY_LOCK(sc); 433 434 ifm = &sc->ifmedia; 435 ifp = &sc->arpcom.ac_if; 436 437 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 438 439 #ifndef FORCE_AUTONEG_TFOUR 440 /* 441 * First, see if autoneg is supported. If not, there's no point in 442 * continuing. 443 */ 444 phy_sts = my_phy_readreg(sc, PHY_BMSR); 445 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 446 if (verbose) 447 printf("my%d: autonegotiation not supported\n", 448 sc->my_unit); 449 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 450 MY_UNLOCK(sc); 451 return; 452 } 453 #endif 454 switch (flag) { 455 case MY_FLAG_FORCEDELAY: 456 /* 457 * XXX Never use this option anywhere but in the probe 458 * routine: making the kernel stop dead in its tracks for 459 * three whole seconds after we've gone multi-user is really 460 * bad manners. 461 */ 462 my_autoneg_xmit(sc); 463 DELAY(5000000); 464 break; 465 case MY_FLAG_SCHEDDELAY: 466 /* 467 * Wait for the transmitter to go idle before starting an 468 * autoneg session, otherwise my_start() may clobber our 469 * timeout, and we don't want to allow transmission during an 470 * autoneg session since that can screw it up. 471 */ 472 if (sc->my_cdata.my_tx_head != NULL) { 473 sc->my_want_auto = 1; 474 MY_UNLOCK(sc); 475 return; 476 } 477 my_autoneg_xmit(sc); 478 ifp->if_timer = 5; 479 sc->my_autoneg = 1; 480 sc->my_want_auto = 0; 481 MY_UNLOCK(sc); 482 return; 483 case MY_FLAG_DELAYTIMEO: 484 ifp->if_timer = 0; 485 sc->my_autoneg = 0; 486 break; 487 default: 488 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag); 489 MY_UNLOCK(sc); 490 return; 491 } 492 493 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 494 if (verbose) 495 printf("my%d: autoneg complete, ", sc->my_unit); 496 phy_sts = my_phy_readreg(sc, PHY_BMSR); 497 } else { 498 if (verbose) 499 printf("my%d: autoneg not complete, ", sc->my_unit); 500 } 501 502 media = my_phy_readreg(sc, PHY_BMCR); 503 504 /* Link is good. Report modes and set duplex mode. */ 505 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 506 if (verbose) 507 printf("my%d: link status good. ", sc->my_unit); 508 advert = my_phy_readreg(sc, PHY_ANAR); 509 ability = my_phy_readreg(sc, PHY_LPAR); 510 if ((sc->my_pinfo->my_vid == MarvellPHYID0) || 511 (sc->my_pinfo->my_vid == LevelOnePHYID0)) { 512 ability2 = my_phy_readreg(sc, PHY_1000SR); 513 if (ability2 & PHY_1000SR_1000BTXFULL) { 514 advert = 0; 515 ability = 0; 516 /* 517 * this version did not support 1000M, 518 * ifm->ifm_media = 519 * IFM_ETHER | IFM_1000_T | IFM_FDX; 520 */ 521 ifm->ifm_media = 522 IFM_ETHER | IFM_100_TX | IFM_FDX; 523 media &= ~PHY_BMCR_SPEEDSEL; 524 media |= PHY_BMCR_1000; 525 media |= PHY_BMCR_DUPLEX; 526 printf("(full-duplex, 1000Mbps)\n"); 527 } else if (ability2 & PHY_1000SR_1000BTXHALF) { 528 advert = 0; 529 ability = 0; 530 /* 531 * this version did not support 1000M, 532 * ifm->ifm_media = IFM_ETHER | IFM_1000_T; 533 */ 534 ifm->ifm_media = IFM_ETHER | IFM_100_TX; 535 media &= ~PHY_BMCR_SPEEDSEL; 536 media &= ~PHY_BMCR_DUPLEX; 537 media |= PHY_BMCR_1000; 538 printf("(half-duplex, 1000Mbps)\n"); 539 } 540 } 541 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 542 ifm->ifm_media = IFM_ETHER | IFM_100_T4; 543 media |= PHY_BMCR_SPEEDSEL; 544 media &= ~PHY_BMCR_DUPLEX; 545 printf("(100baseT4)\n"); 546 } else if (advert & PHY_ANAR_100BTXFULL && 547 ability & PHY_ANAR_100BTXFULL) { 548 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 549 media |= PHY_BMCR_SPEEDSEL; 550 media |= PHY_BMCR_DUPLEX; 551 printf("(full-duplex, 100Mbps)\n"); 552 } else if (advert & PHY_ANAR_100BTXHALF && 553 ability & PHY_ANAR_100BTXHALF) { 554 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 555 media |= PHY_BMCR_SPEEDSEL; 556 media &= ~PHY_BMCR_DUPLEX; 557 printf("(half-duplex, 100Mbps)\n"); 558 } else if (advert & PHY_ANAR_10BTFULL && 559 ability & PHY_ANAR_10BTFULL) { 560 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 561 media &= ~PHY_BMCR_SPEEDSEL; 562 media |= PHY_BMCR_DUPLEX; 563 printf("(full-duplex, 10Mbps)\n"); 564 } else if (advert) { 565 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 566 media &= ~PHY_BMCR_SPEEDSEL; 567 media &= ~PHY_BMCR_DUPLEX; 568 printf("(half-duplex, 10Mbps)\n"); 569 } 570 media &= ~PHY_BMCR_AUTONEGENBL; 571 572 /* Set ASIC's duplex mode to match the PHY. */ 573 my_phy_writereg(sc, PHY_BMCR, media); 574 my_setcfg(sc, media); 575 } else { 576 if (verbose) 577 printf("my%d: no carrier\n", sc->my_unit); 578 } 579 580 my_init(sc); 581 if (sc->my_tx_pend) { 582 sc->my_autoneg = 0; 583 sc->my_tx_pend = 0; 584 my_start(ifp); 585 } 586 MY_UNLOCK(sc); 587 return; 588 } 589 590 /* 591 * To get PHY ability. 592 */ 593 static void 594 my_getmode_mii(struct my_softc * sc) 595 { 596 u_int16_t bmsr; 597 struct ifnet *ifp; 598 599 MY_LOCK(sc); 600 ifp = &sc->arpcom.ac_if; 601 bmsr = my_phy_readreg(sc, PHY_BMSR); 602 if (bootverbose) 603 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr); 604 605 /* fallback */ 606 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 607 608 if (bmsr & PHY_BMSR_10BTHALF) { 609 if (bootverbose) 610 printf("my%d: 10Mbps half-duplex mode supported\n", 611 sc->my_unit); 612 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 613 0, NULL); 614 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 615 } 616 if (bmsr & PHY_BMSR_10BTFULL) { 617 if (bootverbose) 618 printf("my%d: 10Mbps full-duplex mode supported\n", 619 sc->my_unit); 620 621 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 622 0, NULL); 623 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 624 } 625 if (bmsr & PHY_BMSR_100BTXHALF) { 626 if (bootverbose) 627 printf("my%d: 100Mbps half-duplex mode supported\n", 628 sc->my_unit); 629 ifp->if_baudrate = 100000000; 630 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 631 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 632 0, NULL); 633 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 634 } 635 if (bmsr & PHY_BMSR_100BTXFULL) { 636 if (bootverbose) 637 printf("my%d: 100Mbps full-duplex mode supported\n", 638 sc->my_unit); 639 ifp->if_baudrate = 100000000; 640 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 641 0, NULL); 642 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 643 } 644 /* Some also support 100BaseT4. */ 645 if (bmsr & PHY_BMSR_100BT4) { 646 if (bootverbose) 647 printf("my%d: 100baseT4 mode supported\n", sc->my_unit); 648 ifp->if_baudrate = 100000000; 649 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL); 650 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4; 651 #ifdef FORCE_AUTONEG_TFOUR 652 if (bootverbose) 653 printf("my%d: forcing on autoneg support for BT4\n", 654 sc->my_unit); 655 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL): 656 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 657 #endif 658 } 659 #if 0 /* this version did not support 1000M, */ 660 if (sc->my_pinfo->my_vid == MarvellPHYID0) { 661 if (bootverbose) 662 printf("my%d: 1000Mbps half-duplex mode supported\n", 663 sc->my_unit); 664 665 ifp->if_baudrate = 1000000000; 666 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 667 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX, 668 0, NULL); 669 if (bootverbose) 670 printf("my%d: 1000Mbps full-duplex mode supported\n", 671 sc->my_unit); 672 ifp->if_baudrate = 1000000000; 673 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 674 0, NULL); 675 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX; 676 } 677 #endif 678 if (bmsr & PHY_BMSR_CANAUTONEG) { 679 if (bootverbose) 680 printf("my%d: autoneg supported\n", sc->my_unit); 681 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 682 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 683 } 684 MY_UNLOCK(sc); 685 return; 686 } 687 688 /* 689 * Set speed and duplex mode. 690 */ 691 static void 692 my_setmode_mii(struct my_softc * sc, int media) 693 { 694 u_int16_t bmcr; 695 struct ifnet *ifp; 696 697 MY_LOCK(sc); 698 ifp = &sc->arpcom.ac_if; 699 /* 700 * If an autoneg session is in progress, stop it. 701 */ 702 if (sc->my_autoneg) { 703 printf("my%d: canceling autoneg session\n", sc->my_unit); 704 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0; 705 bmcr = my_phy_readreg(sc, PHY_BMCR); 706 bmcr &= ~PHY_BMCR_AUTONEGENBL; 707 my_phy_writereg(sc, PHY_BMCR, bmcr); 708 } 709 printf("my%d: selecting MII, ", sc->my_unit); 710 bmcr = my_phy_readreg(sc, PHY_BMCR); 711 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 | 712 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK); 713 714 #if 0 /* this version did not support 1000M, */ 715 if (IFM_SUBTYPE(media) == IFM_1000_T) { 716 printf("1000Mbps/T4, half-duplex\n"); 717 bmcr &= ~PHY_BMCR_SPEEDSEL; 718 bmcr &= ~PHY_BMCR_DUPLEX; 719 bmcr |= PHY_BMCR_1000; 720 } 721 #endif 722 if (IFM_SUBTYPE(media) == IFM_100_T4) { 723 printf("100Mbps/T4, half-duplex\n"); 724 bmcr |= PHY_BMCR_SPEEDSEL; 725 bmcr &= ~PHY_BMCR_DUPLEX; 726 } 727 if (IFM_SUBTYPE(media) == IFM_100_TX) { 728 printf("100Mbps, "); 729 bmcr |= PHY_BMCR_SPEEDSEL; 730 } 731 if (IFM_SUBTYPE(media) == IFM_10_T) { 732 printf("10Mbps, "); 733 bmcr &= ~PHY_BMCR_SPEEDSEL; 734 } 735 if ((media & IFM_GMASK) == IFM_FDX) { 736 printf("full duplex\n"); 737 bmcr |= PHY_BMCR_DUPLEX; 738 } else { 739 printf("half duplex\n"); 740 bmcr &= ~PHY_BMCR_DUPLEX; 741 } 742 my_phy_writereg(sc, PHY_BMCR, bmcr); 743 my_setcfg(sc, bmcr); 744 MY_UNLOCK(sc); 745 return; 746 } 747 748 /* 749 * The Myson manual states that in order to fiddle with the 'full-duplex' and 750 * '100Mbps' bits in the netconfig register, we first have to put the 751 * transmit and/or receive logic in the idle state. 752 */ 753 static void 754 my_setcfg(struct my_softc * sc, int bmcr) 755 { 756 int i, restart = 0; 757 758 MY_LOCK(sc); 759 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { 760 restart = 1; 761 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE)); 762 for (i = 0; i < MY_TIMEOUT; i++) { 763 DELAY(10); 764 if (!(CSR_READ_4(sc, MY_TCRRCR) & 765 (MY_TXRUN | MY_RXRUN))) 766 break; 767 } 768 if (i == MY_TIMEOUT) 769 printf("my%d: failed to force tx and rx to idle \n", 770 sc->my_unit); 771 } 772 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000); 773 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10); 774 if (bmcr & PHY_BMCR_1000) 775 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000); 776 else if (!(bmcr & PHY_BMCR_SPEEDSEL)) 777 MY_SETBIT(sc, MY_TCRRCR, MY_PS10); 778 if (bmcr & PHY_BMCR_DUPLEX) 779 MY_SETBIT(sc, MY_TCRRCR, MY_FD); 780 else 781 MY_CLRBIT(sc, MY_TCRRCR, MY_FD); 782 if (restart) 783 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE); 784 MY_UNLOCK(sc); 785 return; 786 } 787 788 static void 789 my_reset(struct my_softc * sc) 790 { 791 int i; 792 793 MY_LOCK(sc); 794 MY_SETBIT(sc, MY_BCR, MY_SWR); 795 for (i = 0; i < MY_TIMEOUT; i++) { 796 DELAY(10); 797 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) 798 break; 799 } 800 if (i == MY_TIMEOUT) 801 printf("m0x%d: reset never completed!\n", sc->my_unit); 802 803 /* Wait a little while for the chip to get its brains in order. */ 804 DELAY(1000); 805 MY_UNLOCK(sc); 806 return; 807 } 808 809 /* 810 * Probe for a Myson chip. Check the PCI vendor and device IDs against our 811 * list and return a device name if we find a match. 812 */ 813 static int 814 my_probe(device_t dev) 815 { 816 struct my_type *t; 817 818 t = my_devs; 819 while (t->my_name != NULL) { 820 if ((pci_get_vendor(dev) == t->my_vid) && 821 (pci_get_device(dev) == t->my_did)) { 822 device_set_desc(dev, t->my_name); 823 my_info_tmp = t; 824 return (0); 825 } 826 t++; 827 } 828 return (ENXIO); 829 } 830 831 /* 832 * Attach the interface. Allocate softc structures, do ifmedia setup and 833 * ethernet/BPF attach. 834 */ 835 static int 836 my_attach(device_t dev) 837 { 838 int s, i; 839 u_char eaddr[ETHER_ADDR_LEN]; 840 u_int32_t command, iobase; 841 struct my_softc *sc; 842 struct ifnet *ifp; 843 int media = IFM_ETHER | IFM_100_TX | IFM_FDX; 844 unsigned int round; 845 caddr_t roundptr; 846 struct my_type *p; 847 u_int16_t phy_vid, phy_did, phy_sts = 0; 848 int rid, unit, error = 0; 849 850 s = splimp(); 851 sc = device_get_softc(dev); 852 unit = device_get_unit(dev); 853 if (sc == NULL) { 854 printf("my%d: no memory for softc struct!\n", unit); 855 error = ENXIO; 856 goto fail; 857 858 } 859 bzero(sc, sizeof(struct my_softc)); 860 /*mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);*/ 861 MY_LOCK(sc); 862 863 /* 864 * Map control/status registers. 865 */ 866 #if 0 867 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 868 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 869 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command & 0x000000ff, 4); 870 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 871 #endif 872 command = pci_read_config(dev, PCIR_COMMAND, 4); 873 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 874 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4); 875 command = pci_read_config(dev, PCIR_COMMAND, 4); 876 877 if (my_info_tmp->my_did == MTD800ID) { 878 iobase = pci_read_config(dev, MY_PCI_LOIO, 4); 879 if (iobase & 0x300) 880 MY_USEIOSPACE = 0; 881 } 882 if (MY_USEIOSPACE) { 883 if (!(command & PCIM_CMD_PORTEN)) { 884 printf("my%d: failed to enable I/O ports!\n", unit); 885 free(sc, M_DEVBUF); 886 error = ENXIO; 887 goto fail; 888 } 889 #if 0 890 if (!pci_map_port(config_id, MY_PCI_LOIO, (u_int16_t *) & (sc->my_bhandle))) { 891 printf("my%d: couldn't map ports\n", unit); 892 error = ENXIO; 893 goto fail; 894 } 895 896 sc->my_btag = I386_BUS_SPACE_IO; 897 #endif 898 } else { 899 if (!(command & PCIM_CMD_MEMEN)) { 900 printf("my%d: failed to enable memory mapping!\n", 901 unit); 902 error = ENXIO; 903 goto fail; 904 } 905 #if 0 906 if (!pci_map_mem(config_id, MY_PCI_LOMEM, &vbase, &pbase)) { 907 printf ("my%d: couldn't map memory\n", unit); 908 error = ENXIO; 909 goto fail; 910 } 911 sc->my_btag = I386_BUS_SPACE_MEM; 912 sc->my_bhandle = vbase; 913 #endif 914 } 915 916 rid = MY_RID; 917 sc->my_res = bus_alloc_resource(dev, MY_RES, &rid, 918 0, ~0, 1, RF_ACTIVE); 919 920 if (sc->my_res == NULL) { 921 printf("my%d: couldn't map ports/memory\n", unit); 922 error = ENXIO; 923 goto fail; 924 } 925 sc->my_btag = rman_get_bustag(sc->my_res); 926 sc->my_bhandle = rman_get_bushandle(sc->my_res); 927 928 rid = 0; 929 sc->my_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 930 RF_SHAREABLE | RF_ACTIVE); 931 932 if (sc->my_irq == NULL) { 933 printf("my%d: couldn't map interrupt\n", unit); 934 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 935 error = ENXIO; 936 goto fail; 937 } 938 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET, 939 my_intr, sc, &sc->my_intrhand); 940 941 if (error) { 942 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 943 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 944 printf("my%d: couldn't set up irq\n", unit); 945 goto fail; 946 } 947 callout_init(&sc->my_stat_ch); 948 949 sc->my_info = my_info_tmp; 950 951 /* Reset the adapter. */ 952 my_reset(sc); 953 954 /* 955 * Get station address 956 */ 957 for (i = 0; i < ETHER_ADDR_LEN; ++i) 958 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); 959 960 sc->my_unit = unit; 961 962 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8, 963 M_DEVBUF, M_WAITOK); 964 if (sc->my_ldata_ptr == NULL) { 965 free(sc, M_DEVBUF); 966 printf("my%d: no memory for list buffers!\n", unit); 967 error = ENXIO; 968 goto fail; 969 } 970 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr; 971 round = (unsigned int)sc->my_ldata_ptr & 0xF; 972 roundptr = sc->my_ldata_ptr; 973 for (i = 0; i < 8; i++) { 974 if (round % 8) { 975 round++; 976 roundptr++; 977 } else 978 break; 979 } 980 sc->my_ldata = (struct my_list_data *) roundptr; 981 bzero(sc->my_ldata, sizeof(struct my_list_data)); 982 983 ifp = &sc->arpcom.ac_if; 984 ifp->if_softc = sc; 985 if_initname(ifp, "my", unit); 986 ifp->if_mtu = ETHERMTU; 987 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 988 ifp->if_ioctl = my_ioctl; 989 ifp->if_start = my_start; 990 ifp->if_watchdog = my_watchdog; 991 ifp->if_init = my_init; 992 ifp->if_baudrate = 10000000; 993 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 994 ifq_set_ready(&ifp->if_snd); 995 996 if (sc->my_info->my_did == MTD803ID) 997 sc->my_pinfo = my_phys; 998 else { 999 if (bootverbose) 1000 printf("my%d: probing for a PHY\n", sc->my_unit); 1001 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) { 1002 if (bootverbose) 1003 printf("my%d: checking address: %d\n", 1004 sc->my_unit, i); 1005 sc->my_phy_addr = i; 1006 phy_sts = my_phy_readreg(sc, PHY_BMSR); 1007 if ((phy_sts != 0) && (phy_sts != 0xffff)) 1008 break; 1009 else 1010 phy_sts = 0; 1011 } 1012 if (phy_sts) { 1013 phy_vid = my_phy_readreg(sc, PHY_VENID); 1014 phy_did = my_phy_readreg(sc, PHY_DEVID); 1015 if (bootverbose) { 1016 printf("my%d: found PHY at address %d, ", 1017 sc->my_unit, sc->my_phy_addr); 1018 printf("vendor id: %x device id: %x\n", 1019 phy_vid, phy_did); 1020 } 1021 p = my_phys; 1022 while (p->my_vid) { 1023 if (phy_vid == p->my_vid) { 1024 sc->my_pinfo = p; 1025 break; 1026 } 1027 p++; 1028 } 1029 if (sc->my_pinfo == NULL) 1030 sc->my_pinfo = &my_phys[PHY_UNKNOWN]; 1031 if (bootverbose) 1032 printf("my%d: PHY type: %s\n", 1033 sc->my_unit, sc->my_pinfo->my_name); 1034 } else { 1035 printf("my%d: MII without any phy!\n", sc->my_unit); 1036 error = ENXIO; 1037 goto fail; 1038 } 1039 } 1040 1041 /* Do ifmedia setup. */ 1042 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts); 1043 my_getmode_mii(sc); 1044 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1); 1045 media = sc->ifmedia.ifm_media; 1046 my_stop(sc); 1047 ifmedia_set(&sc->ifmedia, media); 1048 1049 ether_ifattach(ifp, eaddr); 1050 1051 #if 0 1052 at_shutdown(my_shutdown, sc, SHUTDOWN_POST_SYNC); 1053 shutdownhook_establish(my_shutdown, sc); 1054 #endif 1055 1056 MY_UNLOCK(sc); 1057 return (0); 1058 1059 fail: 1060 MY_UNLOCK(sc); 1061 /*mtx_destroy(&sc->my_mtx);*/ 1062 splx(s); 1063 return (error); 1064 } 1065 1066 static int 1067 my_detach(device_t dev) 1068 { 1069 struct my_softc *sc; 1070 struct ifnet *ifp; 1071 int s; 1072 1073 s = splimp(); 1074 sc = device_get_softc(dev); 1075 MY_LOCK(sc); 1076 ifp = &sc->arpcom.ac_if; 1077 ether_ifdetach(ifp); 1078 my_stop(sc); 1079 1080 #if 0 1081 bus_generic_detach(dev); 1082 device_delete_child(dev, sc->rl_miibus); 1083 #endif 1084 1085 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand); 1086 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 1087 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 1088 #if 0 1089 contigfree(sc->my_cdata.my_rx_buf, MY_RXBUFLEN + 32, M_DEVBUF); 1090 #endif 1091 free(sc, M_DEVBUF); 1092 MY_UNLOCK(sc); 1093 splx(s); 1094 /*mtx_destroy(&sc->my_mtx);*/ 1095 return (0); 1096 } 1097 1098 1099 /* 1100 * Initialize the transmit descriptors. 1101 */ 1102 static int 1103 my_list_tx_init(struct my_softc * sc) 1104 { 1105 struct my_chain_data *cd; 1106 struct my_list_data *ld; 1107 int i; 1108 1109 MY_LOCK(sc); 1110 cd = &sc->my_cdata; 1111 ld = sc->my_ldata; 1112 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1113 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i]; 1114 if (i == (MY_TX_LIST_CNT - 1)) 1115 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0]; 1116 else 1117 cd->my_tx_chain[i].my_nextdesc = 1118 &cd->my_tx_chain[i + 1]; 1119 } 1120 cd->my_tx_free = &cd->my_tx_chain[0]; 1121 cd->my_tx_tail = cd->my_tx_head = NULL; 1122 MY_UNLOCK(sc); 1123 return (0); 1124 } 1125 1126 /* 1127 * Initialize the RX descriptors and allocate mbufs for them. Note that we 1128 * arrange the descriptors in a closed ring, so that the last descriptor 1129 * points back to the first. 1130 */ 1131 static int 1132 my_list_rx_init(struct my_softc * sc) 1133 { 1134 struct my_chain_data *cd; 1135 struct my_list_data *ld; 1136 int i; 1137 1138 MY_LOCK(sc); 1139 cd = &sc->my_cdata; 1140 ld = sc->my_ldata; 1141 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1142 cd->my_rx_chain[i].my_ptr = 1143 (struct my_desc *) & ld->my_rx_list[i]; 1144 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) 1145 return (ENOBUFS); 1146 if (i == (MY_RX_LIST_CNT - 1)) { 1147 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0]; 1148 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]); 1149 } else { 1150 cd->my_rx_chain[i].my_nextdesc = 1151 &cd->my_rx_chain[i + 1]; 1152 ld->my_rx_list[i].my_next = 1153 vtophys(&ld->my_rx_list[i + 1]); 1154 } 1155 } 1156 cd->my_rx_head = &cd->my_rx_chain[0]; 1157 MY_UNLOCK(sc); 1158 return (0); 1159 } 1160 1161 /* 1162 * Initialize an RX descriptor and attach an MBUF cluster. 1163 */ 1164 static int 1165 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c) 1166 { 1167 struct mbuf *m_new = NULL; 1168 1169 MY_LOCK(sc); 1170 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1171 if (m_new == NULL) { 1172 printf("my%d: no memory for rx list -- packet dropped!\n", 1173 sc->my_unit); 1174 return (ENOBUFS); 1175 } 1176 MCLGET(m_new, MB_DONTWAIT); 1177 if (!(m_new->m_flags & M_EXT)) { 1178 printf("my%d: no memory for rx list -- packet dropped!\n", 1179 sc->my_unit); 1180 m_freem(m_new); 1181 return (ENOBUFS); 1182 } 1183 c->my_mbuf = m_new; 1184 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t)); 1185 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift; 1186 c->my_ptr->my_status = MY_OWNByNIC; 1187 MY_UNLOCK(sc); 1188 return (0); 1189 } 1190 1191 /* 1192 * A frame has been uploaded: pass the resulting mbuf chain up to the higher 1193 * level protocols. 1194 */ 1195 static void 1196 my_rxeof(struct my_softc * sc) 1197 { 1198 struct mbuf *m; 1199 struct ifnet *ifp; 1200 struct my_chain_onefrag *cur_rx; 1201 int total_len = 0; 1202 u_int32_t rxstat; 1203 1204 MY_LOCK(sc); 1205 ifp = &sc->arpcom.ac_if; 1206 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status) 1207 & MY_OWNByNIC)) { 1208 cur_rx = sc->my_cdata.my_rx_head; 1209 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc; 1210 1211 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */ 1212 ifp->if_ierrors++; 1213 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1214 continue; 1215 } 1216 /* No errors; receive the packet. */ 1217 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift; 1218 total_len -= ETHER_CRC_LEN; 1219 1220 if (total_len < MINCLSIZE) { 1221 m = m_devget(mtod(cur_rx->my_mbuf, char *), 1222 total_len, 0, ifp, NULL); 1223 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1224 if (m == NULL) { 1225 ifp->if_ierrors++; 1226 continue; 1227 } 1228 } else { 1229 m = cur_rx->my_mbuf; 1230 /* 1231 * Try to conjure up a new mbuf cluster. If that 1232 * fails, it means we have an out of memory condition 1233 * and should leave the buffer in place and continue. 1234 * This will result in a lost packet, but there's 1235 * little else we can do in this situation. 1236 */ 1237 if (my_newbuf(sc, cur_rx) == ENOBUFS) { 1238 ifp->if_ierrors++; 1239 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1240 continue; 1241 } 1242 m->m_pkthdr.rcvif = ifp; 1243 m->m_pkthdr.len = m->m_len = total_len; 1244 } 1245 ifp->if_ipackets++; 1246 (*ifp->if_input)(ifp, m); 1247 } 1248 MY_UNLOCK(sc); 1249 return; 1250 } 1251 1252 1253 /* 1254 * A frame was downloaded to the chip. It's safe for us to clean up the list 1255 * buffers. 1256 */ 1257 static void 1258 my_txeof(struct my_softc * sc) 1259 { 1260 struct my_chain *cur_tx; 1261 struct ifnet *ifp; 1262 1263 MY_LOCK(sc); 1264 ifp = &sc->arpcom.ac_if; 1265 /* Clear the timeout timer. */ 1266 ifp->if_timer = 0; 1267 if (sc->my_cdata.my_tx_head == NULL) 1268 return; 1269 /* 1270 * Go through our tx list and free mbufs for those frames that have 1271 * been transmitted. 1272 */ 1273 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) { 1274 u_int32_t txstat; 1275 1276 cur_tx = sc->my_cdata.my_tx_head; 1277 txstat = MY_TXSTATUS(cur_tx); 1278 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT) 1279 break; 1280 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { 1281 if (txstat & MY_TXERR) { 1282 ifp->if_oerrors++; 1283 if (txstat & MY_EC) /* excessive collision */ 1284 ifp->if_collisions++; 1285 if (txstat & MY_LC) /* late collision */ 1286 ifp->if_collisions++; 1287 } 1288 ifp->if_collisions += (txstat & MY_NCRMASK) >> 1289 MY_NCRShift; 1290 } 1291 ifp->if_opackets++; 1292 m_freem(cur_tx->my_mbuf); 1293 cur_tx->my_mbuf = NULL; 1294 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) { 1295 sc->my_cdata.my_tx_head = NULL; 1296 sc->my_cdata.my_tx_tail = NULL; 1297 break; 1298 } 1299 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc; 1300 } 1301 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { 1302 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask); 1303 } 1304 MY_UNLOCK(sc); 1305 return; 1306 } 1307 1308 /* 1309 * TX 'end of channel' interrupt handler. 1310 */ 1311 static void 1312 my_txeoc(struct my_softc * sc) 1313 { 1314 struct ifnet *ifp; 1315 1316 MY_LOCK(sc); 1317 ifp = &sc->arpcom.ac_if; 1318 ifp->if_timer = 0; 1319 if (sc->my_cdata.my_tx_head == NULL) { 1320 ifp->if_flags &= ~IFF_OACTIVE; 1321 sc->my_cdata.my_tx_tail = NULL; 1322 if (sc->my_want_auto) 1323 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1324 } else { 1325 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) { 1326 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC; 1327 ifp->if_timer = 5; 1328 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); 1329 } 1330 } 1331 MY_UNLOCK(sc); 1332 return; 1333 } 1334 1335 static void 1336 my_intr(void *arg) 1337 { 1338 struct my_softc *sc; 1339 struct ifnet *ifp; 1340 u_int32_t status; 1341 1342 sc = arg; 1343 MY_LOCK(sc); 1344 ifp = &sc->arpcom.ac_if; 1345 if (!(ifp->if_flags & IFF_UP)) { 1346 MY_UNLOCK(sc); 1347 return; 1348 } 1349 /* Disable interrupts. */ 1350 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1351 1352 for (;;) { 1353 status = CSR_READ_4(sc, MY_ISR); 1354 status &= MY_INTRS; 1355 if (status) 1356 CSR_WRITE_4(sc, MY_ISR, status); 1357 else 1358 break; 1359 1360 if (status & MY_RI) /* receive interrupt */ 1361 my_rxeof(sc); 1362 1363 if ((status & MY_RBU) || (status & MY_RxErr)) { 1364 /* rx buffer unavailable or rx error */ 1365 ifp->if_ierrors++; 1366 #ifdef foo 1367 my_stop(sc); 1368 my_reset(sc); 1369 my_init(sc); 1370 #endif 1371 } 1372 if (status & MY_TI) /* tx interrupt */ 1373 my_txeof(sc); 1374 if (status & MY_ETI) /* tx early interrupt */ 1375 my_txeof(sc); 1376 if (status & MY_TBU) /* tx buffer unavailable */ 1377 my_txeoc(sc); 1378 1379 #if 0 /* 90/1/18 delete */ 1380 if (status & MY_FBE) { 1381 my_reset(sc); 1382 my_init(sc); 1383 } 1384 #endif 1385 1386 } 1387 1388 /* Re-enable interrupts. */ 1389 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1390 if (!ifq_is_empty(&ifp->if_snd)) 1391 my_start(ifp); 1392 MY_UNLOCK(sc); 1393 return; 1394 } 1395 1396 /* 1397 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1398 * pointers to the fragment pointers. 1399 */ 1400 static int 1401 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head) 1402 { 1403 struct my_desc *f = NULL; 1404 int total_len; 1405 struct mbuf *m, *m_new = NULL; 1406 1407 MY_LOCK(sc); 1408 /* calculate the total tx pkt length */ 1409 total_len = 0; 1410 for (m = m_head; m != NULL; m = m->m_next) 1411 total_len += m->m_len; 1412 /* 1413 * Start packing the mbufs in this chain into the fragment pointers. 1414 * Stop when we run out of fragments or hit the end of the mbuf 1415 * chain. 1416 */ 1417 m = m_head; 1418 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1419 if (m_new == NULL) { 1420 printf("my%d: no memory for tx list", sc->my_unit); 1421 return (1); 1422 } 1423 if (m_head->m_pkthdr.len > MHLEN) { 1424 MCLGET(m_new, MB_DONTWAIT); 1425 if (!(m_new->m_flags & M_EXT)) { 1426 m_freem(m_new); 1427 printf("my%d: no memory for tx list", sc->my_unit); 1428 return (1); 1429 } 1430 } 1431 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1432 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1433 m_freem(m_head); 1434 m_head = m_new; 1435 f = &c->my_ptr->my_frag[0]; 1436 f->my_status = 0; 1437 f->my_data = vtophys(mtod(m_new, caddr_t)); 1438 total_len = m_new->m_len; 1439 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable; 1440 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */ 1441 f->my_ctl |= total_len; /* buffer size */ 1442 /* 89/12/29 add, for mtd891 *//* [ 89? ] */ 1443 if (sc->my_info->my_did == MTD891ID) 1444 f->my_ctl |= MY_ETIControl | MY_RetryTxLC; 1445 c->my_mbuf = m_head; 1446 c->my_lastdesc = 0; 1447 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]); 1448 MY_UNLOCK(sc); 1449 return (0); 1450 } 1451 1452 /* 1453 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1454 * to the mbuf data regions directly in the transmit lists. We also save a 1455 * copy of the pointers since the transmit list fragment pointers are 1456 * physical addresses. 1457 */ 1458 static void 1459 my_start(struct ifnet * ifp) 1460 { 1461 struct my_softc *sc; 1462 struct mbuf *m_head = NULL; 1463 struct my_chain *cur_tx = NULL, *start_tx; 1464 1465 sc = ifp->if_softc; 1466 MY_LOCK(sc); 1467 if (sc->my_autoneg) { 1468 sc->my_tx_pend = 1; 1469 MY_UNLOCK(sc); 1470 return; 1471 } 1472 /* 1473 * Check for an available queue slot. If there are none, punt. 1474 */ 1475 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) { 1476 ifp->if_flags |= IFF_OACTIVE; 1477 MY_UNLOCK(sc); 1478 return; 1479 } 1480 start_tx = sc->my_cdata.my_tx_free; 1481 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) { 1482 m_head = ifq_dequeue(&ifp->if_snd); 1483 if (m_head == NULL) 1484 break; 1485 1486 /* Pick a descriptor off the free list. */ 1487 cur_tx = sc->my_cdata.my_tx_free; 1488 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc; 1489 1490 /* Pack the data into the descriptor. */ 1491 my_encap(sc, cur_tx, m_head); 1492 1493 if (cur_tx != start_tx) 1494 MY_TXOWN(cur_tx) = MY_OWNByNIC; 1495 BPF_MTAP(ifp, cur_tx->my_mbuf); 1496 } 1497 /* 1498 * If there are no packets queued, bail. 1499 */ 1500 if (cur_tx == NULL) { 1501 MY_UNLOCK(sc); 1502 return; 1503 } 1504 /* 1505 * Place the request for the upload interrupt in the last descriptor 1506 * in the chain. This way, if we're chaining several packets at once, 1507 * we'll only get an interupt once for the whole chain rather than 1508 * once for each packet. 1509 */ 1510 MY_TXCTL(cur_tx) |= MY_TXIC; 1511 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC; 1512 sc->my_cdata.my_tx_tail = cur_tx; 1513 if (sc->my_cdata.my_tx_head == NULL) 1514 sc->my_cdata.my_tx_head = start_tx; 1515 MY_TXOWN(start_tx) = MY_OWNByNIC; 1516 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */ 1517 1518 /* 1519 * Set a timeout in case the chip goes out to lunch. 1520 */ 1521 ifp->if_timer = 5; 1522 MY_UNLOCK(sc); 1523 return; 1524 } 1525 1526 static void 1527 my_init(void *xsc) 1528 { 1529 struct my_softc *sc = xsc; 1530 struct ifnet *ifp = &sc->arpcom.ac_if; 1531 int s; 1532 u_int16_t phy_bmcr = 0; 1533 1534 MY_LOCK(sc); 1535 if (sc->my_autoneg) { 1536 MY_UNLOCK(sc); 1537 return; 1538 } 1539 s = splimp(); 1540 if (sc->my_pinfo != NULL) 1541 phy_bmcr = my_phy_readreg(sc, PHY_BMCR); 1542 /* 1543 * Cancel pending I/O and free all RX/TX buffers. 1544 */ 1545 my_stop(sc); 1546 my_reset(sc); 1547 1548 /* 1549 * Set cache alignment and burst length. 1550 */ 1551 #if 0 /* 89/9/1 modify, */ 1552 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512); 1553 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF); 1554 #endif 1555 CSR_WRITE_4(sc, MY_BCR, MY_PBL8); 1556 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512); 1557 /* 1558 * 89/12/29 add, for mtd891, 1559 */ 1560 if (sc->my_info->my_did == MTD891ID) { 1561 MY_SETBIT(sc, MY_BCR, MY_PROG); 1562 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced); 1563 } 1564 my_setcfg(sc, phy_bmcr); 1565 /* Init circular RX list. */ 1566 if (my_list_rx_init(sc) == ENOBUFS) { 1567 printf("my%d: init failed: no memory for rx buffers\n", 1568 sc->my_unit); 1569 my_stop(sc); 1570 (void)splx(s); 1571 MY_UNLOCK(sc); 1572 return; 1573 } 1574 /* Init TX descriptors. */ 1575 my_list_tx_init(sc); 1576 1577 /* If we want promiscuous mode, set the allframes bit. */ 1578 if (ifp->if_flags & IFF_PROMISC) 1579 MY_SETBIT(sc, MY_TCRRCR, MY_PROM); 1580 else 1581 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM); 1582 1583 /* 1584 * Set capture broadcast bit to capture broadcast frames. 1585 */ 1586 if (ifp->if_flags & IFF_BROADCAST) 1587 MY_SETBIT(sc, MY_TCRRCR, MY_AB); 1588 else 1589 MY_CLRBIT(sc, MY_TCRRCR, MY_AB); 1590 1591 /* 1592 * Program the multicast filter, if necessary. 1593 */ 1594 my_setmulti(sc); 1595 1596 /* 1597 * Load the address of the RX list. 1598 */ 1599 MY_CLRBIT(sc, MY_TCRRCR, MY_RE); 1600 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0])); 1601 1602 /* 1603 * Enable interrupts. 1604 */ 1605 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1606 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF); 1607 1608 /* Enable receiver and transmitter. */ 1609 MY_SETBIT(sc, MY_TCRRCR, MY_RE); 1610 MY_CLRBIT(sc, MY_TCRRCR, MY_TE); 1611 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0])); 1612 MY_SETBIT(sc, MY_TCRRCR, MY_TE); 1613 1614 /* Restore state of BMCR */ 1615 if (sc->my_pinfo != NULL) 1616 my_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1617 ifp->if_flags |= IFF_RUNNING; 1618 ifp->if_flags &= ~IFF_OACTIVE; 1619 (void)splx(s); 1620 MY_UNLOCK(sc); 1621 return; 1622 } 1623 1624 /* 1625 * Set media options. 1626 */ 1627 1628 static int 1629 my_ifmedia_upd(struct ifnet * ifp) 1630 { 1631 struct my_softc *sc; 1632 struct ifmedia *ifm; 1633 1634 sc = ifp->if_softc; 1635 MY_LOCK(sc); 1636 ifm = &sc->ifmedia; 1637 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) { 1638 MY_UNLOCK(sc); 1639 return (EINVAL); 1640 } 1641 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1642 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1643 else 1644 my_setmode_mii(sc, ifm->ifm_media); 1645 MY_UNLOCK(sc); 1646 return (0); 1647 } 1648 1649 /* 1650 * Report current media status. 1651 */ 1652 1653 static void 1654 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr) 1655 { 1656 struct my_softc *sc; 1657 u_int16_t advert = 0, ability = 0; 1658 1659 sc = ifp->if_softc; 1660 MY_LOCK(sc); 1661 ifmr->ifm_active = IFM_ETHER; 1662 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1663 #if 0 /* this version did not support 1000M, */ 1664 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000) 1665 ifmr->ifm_active = IFM_ETHER | IFM_1000TX; 1666 #endif 1667 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1668 ifmr->ifm_active = IFM_ETHER | IFM_100_TX; 1669 else 1670 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1671 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1672 ifmr->ifm_active |= IFM_FDX; 1673 else 1674 ifmr->ifm_active |= IFM_HDX; 1675 1676 MY_UNLOCK(sc); 1677 return; 1678 } 1679 ability = my_phy_readreg(sc, PHY_LPAR); 1680 advert = my_phy_readreg(sc, PHY_ANAR); 1681 1682 #if 0 /* this version did not support 1000M, */ 1683 if (sc->my_pinfo->my_vid = MarvellPHYID0) { 1684 ability2 = my_phy_readreg(sc, PHY_1000SR); 1685 if (ability2 & PHY_1000SR_1000BTXFULL) { 1686 advert = 0; 1687 ability = 0; 1688 ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_FDX; 1689 } else if (ability & PHY_1000SR_1000BTXHALF) { 1690 advert = 0; 1691 ability = 0; 1692 ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_HDX; 1693 } 1694 } 1695 #endif 1696 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) 1697 ifmr->ifm_active = IFM_ETHER | IFM_100_T4; 1698 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) 1699 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1700 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) 1701 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1702 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) 1703 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1704 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) 1705 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1706 MY_UNLOCK(sc); 1707 return; 1708 } 1709 1710 static int 1711 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data, struct ucred *cr) 1712 { 1713 struct my_softc *sc = ifp->if_softc; 1714 struct ifreq *ifr = (struct ifreq *) data; 1715 int s, error = 0; 1716 1717 s = splimp(); 1718 MY_LOCK(sc); 1719 switch (command) { 1720 case SIOCSIFADDR: 1721 case SIOCGIFADDR: 1722 case SIOCSIFMTU: 1723 error = ether_ioctl(ifp, command, data); 1724 break; 1725 case SIOCSIFFLAGS: 1726 if (ifp->if_flags & IFF_UP) 1727 my_init(sc); 1728 else if (ifp->if_flags & IFF_RUNNING) 1729 my_stop(sc); 1730 error = 0; 1731 break; 1732 case SIOCADDMULTI: 1733 case SIOCDELMULTI: 1734 my_setmulti(sc); 1735 error = 0; 1736 break; 1737 case SIOCGIFMEDIA: 1738 case SIOCSIFMEDIA: 1739 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1740 break; 1741 default: 1742 error = EINVAL; 1743 break; 1744 } 1745 MY_UNLOCK(sc); 1746 (void)splx(s); 1747 return (error); 1748 } 1749 1750 static void 1751 my_watchdog(struct ifnet * ifp) 1752 { 1753 struct my_softc *sc; 1754 1755 sc = ifp->if_softc; 1756 MY_LOCK(sc); 1757 if (sc->my_autoneg) { 1758 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1); 1759 MY_UNLOCK(sc); 1760 return; 1761 } 1762 ifp->if_oerrors++; 1763 printf("my%d: watchdog timeout\n", sc->my_unit); 1764 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1765 printf("my%d: no carrier - transceiver cable problem?\n", 1766 sc->my_unit); 1767 my_stop(sc); 1768 my_reset(sc); 1769 my_init(sc); 1770 if (!ifq_is_empty(&ifp->if_snd)) 1771 my_start(ifp); 1772 MY_LOCK(sc); 1773 return; 1774 } 1775 1776 1777 /* 1778 * Stop the adapter and free any mbufs allocated to the RX and TX lists. 1779 */ 1780 static void 1781 my_stop(struct my_softc * sc) 1782 { 1783 int i; 1784 struct ifnet *ifp; 1785 1786 MY_LOCK(sc); 1787 ifp = &sc->arpcom.ac_if; 1788 ifp->if_timer = 0; 1789 1790 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE)); 1791 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1792 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000); 1793 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000); 1794 1795 /* 1796 * Free data in the RX lists. 1797 */ 1798 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1799 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) { 1800 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf); 1801 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL; 1802 } 1803 } 1804 bzero((char *)&sc->my_ldata->my_rx_list, 1805 sizeof(sc->my_ldata->my_rx_list)); 1806 /* 1807 * Free the TX list buffers. 1808 */ 1809 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1810 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) { 1811 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf); 1812 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL; 1813 } 1814 } 1815 bzero((char *)&sc->my_ldata->my_tx_list, 1816 sizeof(sc->my_ldata->my_tx_list)); 1817 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1818 MY_UNLOCK(sc); 1819 return; 1820 } 1821 1822 /* 1823 * Stop all chip I/O so that the kernel's probe routines don't get confused 1824 * by errant DMAs when rebooting. 1825 */ 1826 static void 1827 my_shutdown(device_t dev) 1828 { 1829 struct my_softc *sc; 1830 1831 sc = device_get_softc(dev); 1832 my_stop(sc); 1833 return; 1834 } 1835