1 /* $OpenBSD: if_nfe.c,v 1.63 2006/06/17 18:00:43 brad Exp $ */ 2 /* $DragonFly: src/sys/dev/netif/nfe/if_nfe.c,v 1.9 2007/05/01 23:48:03 dillon Exp $ */ 3 4 /* 5 * Copyright (c) 2006 The DragonFly Project. All rights reserved. 6 * 7 * This code is derived from software contributed to The DragonFly Project 8 * by Sepherosa Ziehau <sepherosa@gmail.com> and 9 * Matthew Dillon <dillon@apollo.backplane.com> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in 19 * the documentation and/or other materials provided with the 20 * distribution. 21 * 3. Neither the name of The DragonFly Project nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific, prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 28 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 29 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 30 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 31 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 33 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 35 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr> 41 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org> 42 * 43 * Permission to use, copy, modify, and distribute this software for any 44 * purpose with or without fee is hereby granted, provided that the above 45 * copyright notice and this permission notice appear in all copies. 46 * 47 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 48 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 49 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 50 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 51 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 52 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 53 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 54 */ 55 56 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 57 58 #include "opt_polling.h" 59 60 #include <sys/param.h> 61 #include <sys/endian.h> 62 #include <sys/kernel.h> 63 #include <sys/bus.h> 64 #include <sys/proc.h> 65 #include <sys/rman.h> 66 #include <sys/serialize.h> 67 #include <sys/socket.h> 68 #include <sys/sockio.h> 69 #include <sys/sysctl.h> 70 71 #include <net/ethernet.h> 72 #include <net/if.h> 73 #include <net/bpf.h> 74 #include <net/if_arp.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/ifq_var.h> 78 #include <net/if_types.h> 79 #include <net/if_var.h> 80 #include <net/vlan/if_vlan_var.h> 81 82 #include <bus/pci/pcireg.h> 83 #include <bus/pci/pcivar.h> 84 #include <bus/pci/pcidevs.h> 85 86 #include <dev/netif/mii_layer/mii.h> 87 #include <dev/netif/mii_layer/miivar.h> 88 89 #include "miibus_if.h" 90 91 #include "if_nfereg.h" 92 #include "if_nfevar.h" 93 94 static int nfe_probe(device_t); 95 static int nfe_attach(device_t); 96 static int nfe_detach(device_t); 97 static void nfe_shutdown(device_t); 98 static int nfe_resume(device_t); 99 static int nfe_suspend(device_t); 100 101 static int nfe_miibus_readreg(device_t, int, int); 102 static void nfe_miibus_writereg(device_t, int, int, int); 103 static void nfe_miibus_statchg(device_t); 104 105 #ifdef DEVICE_POLLING 106 static void nfe_poll(struct ifnet *, enum poll_cmd, int); 107 #endif 108 static void nfe_intr(void *); 109 static int nfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 110 static void nfe_rxeof(struct nfe_softc *); 111 static void nfe_txeof(struct nfe_softc *); 112 static int nfe_encap(struct nfe_softc *, struct nfe_tx_ring *, 113 struct mbuf *); 114 static void nfe_start(struct ifnet *); 115 static void nfe_watchdog(struct ifnet *); 116 static void nfe_init(void *); 117 static void nfe_stop(struct nfe_softc *); 118 static struct nfe_jbuf *nfe_jalloc(struct nfe_softc *); 119 static void nfe_jfree(void *); 120 static void nfe_jref(void *); 121 static int nfe_jpool_alloc(struct nfe_softc *, struct nfe_rx_ring *); 122 static void nfe_jpool_free(struct nfe_softc *, struct nfe_rx_ring *); 123 static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 124 static void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 125 static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 126 static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 127 static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 128 static void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 129 static int nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 130 static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 131 static int nfe_ifmedia_upd(struct ifnet *); 132 static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 133 static void nfe_setmulti(struct nfe_softc *); 134 static void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 135 static void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 136 static void nfe_tick(void *); 137 static void nfe_ring_dma_addr(void *, bus_dma_segment_t *, int, int); 138 static void nfe_buf_dma_addr(void *, bus_dma_segment_t *, int, bus_size_t, 139 int); 140 static void nfe_set_paddr_rxdesc(struct nfe_softc *, struct nfe_rx_ring *, 141 int, bus_addr_t); 142 static void nfe_set_ready_rxdesc(struct nfe_softc *, struct nfe_rx_ring *, 143 int); 144 static int nfe_newbuf_std(struct nfe_softc *, struct nfe_rx_ring *, int, 145 int); 146 static int nfe_newbuf_jumbo(struct nfe_softc *, struct nfe_rx_ring *, int, 147 int); 148 149 #define NFE_DEBUG 150 #ifdef NFE_DEBUG 151 152 static int nfe_debug = 0; 153 154 SYSCTL_NODE(_hw, OID_AUTO, nfe, CTLFLAG_RD, 0, "nVidia GigE parameters"); 155 SYSCTL_INT(_hw_nfe, OID_AUTO, debug, CTLFLAG_RW, &nfe_debug, 0, 156 "control debugging printfs"); 157 158 #define DPRINTF(sc, fmt, ...) do { \ 159 if (nfe_debug) { \ 160 if_printf(&(sc)->arpcom.ac_if, \ 161 fmt, __VA_ARGS__); \ 162 } \ 163 } while (0) 164 165 #define DPRINTFN(sc, lv, fmt, ...) do { \ 166 if (nfe_debug >= (lv)) { \ 167 if_printf(&(sc)->arpcom.ac_if, \ 168 fmt, __VA_ARGS__); \ 169 } \ 170 } while (0) 171 172 #else /* !NFE_DEBUG */ 173 174 #define DPRINTF(sc, fmt, ...) 175 #define DPRINTFN(sc, lv, fmt, ...) 176 177 #endif /* NFE_DEBUG */ 178 179 struct nfe_dma_ctx { 180 int nsegs; 181 bus_dma_segment_t *segs; 182 }; 183 184 static const struct nfe_dev { 185 uint16_t vid; 186 uint16_t did; 187 const char *desc; 188 } nfe_devices[] = { 189 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN, 190 "NVIDIA nForce Fast Ethernet" }, 191 192 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN, 193 "NVIDIA nForce2 Fast Ethernet" }, 194 195 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1, 196 "NVIDIA nForce3 Gigabit Ethernet" }, 197 198 /* XXX TGEN the next chip can also be found in the nForce2 Ultra 400Gb 199 chipset, and possibly also the 400R; it might be both nForce2- and 200 nForce3-based boards can use the same MCPs (= southbridges) */ 201 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2, 202 "NVIDIA nForce3 Gigabit Ethernet" }, 203 204 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3, 205 "NVIDIA nForce3 Gigabit Ethernet" }, 206 207 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4, 208 "NVIDIA nForce3 Gigabit Ethernet" }, 209 210 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5, 211 "NVIDIA nForce3 Gigabit Ethernet" }, 212 213 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1, 214 "NVIDIA CK804 Gigabit Ethernet" }, 215 216 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2, 217 "NVIDIA CK804 Gigabit Ethernet" }, 218 219 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1, 220 "NVIDIA MCP04 Gigabit Ethernet" }, 221 222 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2, 223 "NVIDIA MCP04 Gigabit Ethernet" }, 224 225 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1, 226 "NVIDIA MCP51 Gigabit Ethernet" }, 227 228 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2, 229 "NVIDIA MCP51 Gigabit Ethernet" }, 230 231 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1, 232 "NVIDIA MCP55 Gigabit Ethernet" }, 233 234 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2, 235 "NVIDIA MCP55 Gigabit Ethernet" }, 236 237 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1, 238 "NVIDIA MCP61 Gigabit Ethernet" }, 239 240 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2, 241 "NVIDIA MCP61 Gigabit Ethernet" }, 242 243 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3, 244 "NVIDIA MCP61 Gigabit Ethernet" }, 245 246 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4, 247 "NVIDIA MCP61 Gigabit Ethernet" }, 248 249 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1, 250 "NVIDIA MCP65 Gigabit Ethernet" }, 251 252 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2, 253 "NVIDIA MCP65 Gigabit Ethernet" }, 254 255 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3, 256 "NVIDIA MCP65 Gigabit Ethernet" }, 257 258 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4, 259 "NVIDIA MCP65 Gigabit Ethernet" }, 260 261 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1, 262 "NVIDIA MCP67 Gigabit Ethernet" }, 263 264 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2, 265 "NVIDIA MCP67 Gigabit Ethernet" }, 266 267 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3, 268 "NVIDIA MCP67 Gigabit Ethernet" }, 269 270 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4, 271 "NVIDIA MCP67 Gigabit Ethernet" } 272 }; 273 274 static device_method_t nfe_methods[] = { 275 /* Device interface */ 276 DEVMETHOD(device_probe, nfe_probe), 277 DEVMETHOD(device_attach, nfe_attach), 278 DEVMETHOD(device_detach, nfe_detach), 279 DEVMETHOD(device_suspend, nfe_suspend), 280 DEVMETHOD(device_resume, nfe_resume), 281 DEVMETHOD(device_shutdown, nfe_shutdown), 282 283 /* Bus interface */ 284 DEVMETHOD(bus_print_child, bus_generic_print_child), 285 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 286 287 /* MII interface */ 288 DEVMETHOD(miibus_readreg, nfe_miibus_readreg), 289 DEVMETHOD(miibus_writereg, nfe_miibus_writereg), 290 DEVMETHOD(miibus_statchg, nfe_miibus_statchg), 291 292 { 0, 0 } 293 }; 294 295 static driver_t nfe_driver = { 296 "nfe", 297 nfe_methods, 298 sizeof(struct nfe_softc) 299 }; 300 301 static devclass_t nfe_devclass; 302 303 DECLARE_DUMMY_MODULE(if_nfe); 304 MODULE_DEPEND(if_nfe, miibus, 1, 1, 1); 305 DRIVER_MODULE(if_nfe, pci, nfe_driver, nfe_devclass, 0, 0); 306 DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0); 307 308 static int 309 nfe_probe(device_t dev) 310 { 311 const struct nfe_dev *n; 312 uint16_t vid, did; 313 314 vid = pci_get_vendor(dev); 315 did = pci_get_device(dev); 316 for (n = nfe_devices; n->desc != NULL; ++n) { 317 if (vid == n->vid && did == n->did) { 318 struct nfe_softc *sc = device_get_softc(dev); 319 320 switch (did) { 321 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 322 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 323 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 324 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 325 sc->sc_flags = NFE_JUMBO_SUP | 326 NFE_HW_CSUM; 327 break; 328 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 329 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 330 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 331 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 332 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 333 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 334 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 335 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 336 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 337 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 338 sc->sc_flags = NFE_40BIT_ADDR; 339 break; 340 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 341 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 342 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 343 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 344 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 345 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 346 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 347 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 348 sc->sc_flags = NFE_JUMBO_SUP | 349 NFE_40BIT_ADDR | 350 NFE_HW_CSUM; 351 break; 352 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 353 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 354 sc->sc_flags = NFE_JUMBO_SUP | 355 NFE_40BIT_ADDR | 356 NFE_HW_CSUM | 357 NFE_HW_VLAN; 358 break; 359 } 360 361 /* Enable jumbo frames for adapters that support it */ 362 if (sc->sc_flags & NFE_JUMBO_SUP) 363 sc->sc_flags |= NFE_USE_JUMBO; 364 365 device_set_desc(dev, n->desc); 366 device_set_async_attach(dev, TRUE); 367 return 0; 368 } 369 } 370 return ENXIO; 371 } 372 373 static int 374 nfe_attach(device_t dev) 375 { 376 struct nfe_softc *sc = device_get_softc(dev); 377 struct ifnet *ifp = &sc->arpcom.ac_if; 378 uint8_t eaddr[ETHER_ADDR_LEN]; 379 int error; 380 381 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 382 lwkt_serialize_init(&sc->sc_jbuf_serializer); 383 384 sc->sc_mem_rid = PCIR_BAR(0); 385 386 #ifndef BURN_BRIDGES 387 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 388 uint32_t mem, irq; 389 390 mem = pci_read_config(dev, sc->sc_mem_rid, 4); 391 irq = pci_read_config(dev, PCIR_INTLINE, 4); 392 393 device_printf(dev, "chip is in D%d power mode " 394 "-- setting to D0\n", pci_get_powerstate(dev)); 395 396 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 397 398 pci_write_config(dev, sc->sc_mem_rid, mem, 4); 399 pci_write_config(dev, PCIR_INTLINE, irq, 4); 400 } 401 #endif /* !BURN_BRIDGE */ 402 403 /* Enable bus mastering */ 404 pci_enable_busmaster(dev); 405 406 /* Allocate IO memory */ 407 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 408 &sc->sc_mem_rid, RF_ACTIVE); 409 if (sc->sc_mem_res == NULL) { 410 device_printf(dev, "cound not allocate io memory\n"); 411 return ENXIO; 412 } 413 sc->sc_memh = rman_get_bushandle(sc->sc_mem_res); 414 sc->sc_memt = rman_get_bustag(sc->sc_mem_res); 415 416 /* Allocate IRQ */ 417 sc->sc_irq_rid = 0; 418 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 419 &sc->sc_irq_rid, 420 RF_SHAREABLE | RF_ACTIVE); 421 if (sc->sc_irq_res == NULL) { 422 device_printf(dev, "could not allocate irq\n"); 423 error = ENXIO; 424 goto fail; 425 } 426 427 nfe_get_macaddr(sc, eaddr); 428 429 /* 430 * Allocate Tx and Rx rings. 431 */ 432 error = nfe_alloc_tx_ring(sc, &sc->txq); 433 if (error) { 434 device_printf(dev, "could not allocate Tx ring\n"); 435 goto fail; 436 } 437 438 error = nfe_alloc_rx_ring(sc, &sc->rxq); 439 if (error) { 440 device_printf(dev, "could not allocate Rx ring\n"); 441 goto fail; 442 } 443 444 error = mii_phy_probe(dev, &sc->sc_miibus, nfe_ifmedia_upd, 445 nfe_ifmedia_sts); 446 if (error) { 447 device_printf(dev, "MII without any phy\n"); 448 goto fail; 449 } 450 451 ifp->if_softc = sc; 452 ifp->if_mtu = ETHERMTU; 453 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 454 ifp->if_ioctl = nfe_ioctl; 455 ifp->if_start = nfe_start; 456 #ifdef DEVICE_POLLING 457 ifp->if_poll = nfe_poll; 458 #endif 459 ifp->if_watchdog = nfe_watchdog; 460 ifp->if_init = nfe_init; 461 ifq_set_maxlen(&ifp->if_snd, NFE_IFQ_MAXLEN); 462 ifq_set_ready(&ifp->if_snd); 463 464 ifp->if_capabilities = IFCAP_VLAN_MTU; 465 466 #if 0 467 if (sc->sc_flags & NFE_USE_JUMBO) 468 ifp->if_hardmtu = NFE_JUMBO_MTU; 469 #endif 470 471 if (sc->sc_flags & NFE_HW_VLAN) 472 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 473 474 #ifdef NFE_CSUM 475 if (sc->sc_flags & NFE_HW_CSUM) { 476 #if 0 477 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 478 IFCAP_CSUM_UDPv4; 479 #else 480 ifp->if_capabilities = IFCAP_HWCSUM; 481 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 482 #endif 483 } 484 #endif 485 ifp->if_capenable = ifp->if_capabilities; 486 487 callout_init(&sc->sc_tick_ch); 488 489 ether_ifattach(ifp, eaddr, NULL); 490 491 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, nfe_intr, sc, 492 &sc->sc_ih, ifp->if_serializer); 493 if (error) { 494 device_printf(dev, "could not setup intr\n"); 495 ether_ifdetach(ifp); 496 goto fail; 497 } 498 499 return 0; 500 fail: 501 nfe_detach(dev); 502 return error; 503 } 504 505 static int 506 nfe_detach(device_t dev) 507 { 508 struct nfe_softc *sc = device_get_softc(dev); 509 510 if (device_is_attached(dev)) { 511 struct ifnet *ifp = &sc->arpcom.ac_if; 512 513 lwkt_serialize_enter(ifp->if_serializer); 514 nfe_stop(sc); 515 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_ih); 516 lwkt_serialize_exit(ifp->if_serializer); 517 518 ether_ifdetach(ifp); 519 } 520 521 if (sc->sc_miibus != NULL) 522 device_delete_child(dev, sc->sc_miibus); 523 bus_generic_detach(dev); 524 525 if (sc->sc_irq_res != NULL) { 526 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, 527 sc->sc_irq_res); 528 } 529 530 if (sc->sc_mem_res != NULL) { 531 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, 532 sc->sc_mem_res); 533 } 534 535 nfe_free_tx_ring(sc, &sc->txq); 536 nfe_free_rx_ring(sc, &sc->rxq); 537 538 return 0; 539 } 540 541 static void 542 nfe_shutdown(device_t dev) 543 { 544 struct nfe_softc *sc = device_get_softc(dev); 545 struct ifnet *ifp = &sc->arpcom.ac_if; 546 547 lwkt_serialize_enter(ifp->if_serializer); 548 nfe_stop(sc); 549 lwkt_serialize_exit(ifp->if_serializer); 550 } 551 552 static int 553 nfe_suspend(device_t dev) 554 { 555 struct nfe_softc *sc = device_get_softc(dev); 556 struct ifnet *ifp = &sc->arpcom.ac_if; 557 558 lwkt_serialize_enter(ifp->if_serializer); 559 nfe_stop(sc); 560 lwkt_serialize_exit(ifp->if_serializer); 561 562 return 0; 563 } 564 565 static int 566 nfe_resume(device_t dev) 567 { 568 struct nfe_softc *sc = device_get_softc(dev); 569 struct ifnet *ifp = &sc->arpcom.ac_if; 570 571 lwkt_serialize_enter(ifp->if_serializer); 572 if (ifp->if_flags & IFF_UP) { 573 nfe_init(sc); 574 if (ifp->if_flags & IFF_RUNNING) 575 ifp->if_start(ifp); 576 } 577 lwkt_serialize_exit(ifp->if_serializer); 578 579 return 0; 580 } 581 582 static void 583 nfe_miibus_statchg(device_t dev) 584 { 585 struct nfe_softc *sc = device_get_softc(dev); 586 struct mii_data *mii = device_get_softc(sc->sc_miibus); 587 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 588 589 phy = NFE_READ(sc, NFE_PHY_IFACE); 590 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 591 592 seed = NFE_READ(sc, NFE_RNDSEED); 593 seed &= ~NFE_SEED_MASK; 594 595 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 596 phy |= NFE_PHY_HDX; /* half-duplex */ 597 misc |= NFE_MISC1_HDX; 598 } 599 600 switch (IFM_SUBTYPE(mii->mii_media_active)) { 601 case IFM_1000_T: /* full-duplex only */ 602 link |= NFE_MEDIA_1000T; 603 seed |= NFE_SEED_1000T; 604 phy |= NFE_PHY_1000T; 605 break; 606 case IFM_100_TX: 607 link |= NFE_MEDIA_100TX; 608 seed |= NFE_SEED_100TX; 609 phy |= NFE_PHY_100TX; 610 break; 611 case IFM_10_T: 612 link |= NFE_MEDIA_10T; 613 seed |= NFE_SEED_10T; 614 break; 615 } 616 617 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 618 619 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 620 NFE_WRITE(sc, NFE_MISC1, misc); 621 NFE_WRITE(sc, NFE_LINKSPEED, link); 622 } 623 624 static int 625 nfe_miibus_readreg(device_t dev, int phy, int reg) 626 { 627 struct nfe_softc *sc = device_get_softc(dev); 628 uint32_t val; 629 int ntries; 630 631 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 632 633 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 634 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 635 DELAY(100); 636 } 637 638 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 639 640 for (ntries = 0; ntries < 1000; ntries++) { 641 DELAY(100); 642 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 643 break; 644 } 645 if (ntries == 1000) { 646 DPRINTFN(sc, 2, "timeout waiting for PHY %s\n", ""); 647 return 0; 648 } 649 650 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 651 DPRINTFN(sc, 2, "could not read PHY %s\n", ""); 652 return 0; 653 } 654 655 val = NFE_READ(sc, NFE_PHY_DATA); 656 if (val != 0xffffffff && val != 0) 657 sc->mii_phyaddr = phy; 658 659 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val); 660 661 return val; 662 } 663 664 static void 665 nfe_miibus_writereg(device_t dev, int phy, int reg, int val) 666 { 667 struct nfe_softc *sc = device_get_softc(dev); 668 uint32_t ctl; 669 int ntries; 670 671 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 672 673 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 674 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 675 DELAY(100); 676 } 677 678 NFE_WRITE(sc, NFE_PHY_DATA, val); 679 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 680 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 681 682 for (ntries = 0; ntries < 1000; ntries++) { 683 DELAY(100); 684 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 685 break; 686 } 687 688 #ifdef NFE_DEBUG 689 if (ntries == 1000) 690 DPRINTFN(sc, 2, "could not write to PHY %s\n", ""); 691 #endif 692 } 693 694 #ifdef DEVICE_POLLING 695 696 static void 697 nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 698 { 699 struct nfe_softc *sc = ifp->if_softc; 700 701 switch(cmd) { 702 case POLL_REGISTER: 703 /* Disable interrupts */ 704 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 705 break; 706 case POLL_DEREGISTER: 707 /* enable interrupts */ 708 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 709 break; 710 case POLL_AND_CHECK_STATUS: 711 /* fall through */ 712 case POLL_ONLY: 713 if (ifp->if_flags & IFF_RUNNING) { 714 nfe_rxeof(sc); 715 nfe_txeof(sc); 716 } 717 break; 718 } 719 } 720 721 #endif 722 723 static void 724 nfe_intr(void *arg) 725 { 726 struct nfe_softc *sc = arg; 727 struct ifnet *ifp = &sc->arpcom.ac_if; 728 uint32_t r; 729 730 r = NFE_READ(sc, NFE_IRQ_STATUS); 731 if (r == 0) 732 return; /* not for us */ 733 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 734 735 DPRINTFN(sc, 5, "%s: interrupt register %x\n", __func__, r); 736 737 if (r & NFE_IRQ_LINK) { 738 NFE_READ(sc, NFE_PHY_STATUS); 739 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 740 DPRINTF(sc, "link state changed %s\n", ""); 741 } 742 743 if (ifp->if_flags & IFF_RUNNING) { 744 /* check Rx ring */ 745 nfe_rxeof(sc); 746 747 /* check Tx ring */ 748 nfe_txeof(sc); 749 } 750 } 751 752 static int 753 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 754 { 755 struct nfe_softc *sc = ifp->if_softc; 756 struct ifreq *ifr = (struct ifreq *)data; 757 struct mii_data *mii; 758 int error = 0, mask; 759 760 switch (cmd) { 761 case SIOCSIFMTU: 762 /* XXX NFE_USE_JUMBO should be set here */ 763 break; 764 case SIOCSIFFLAGS: 765 if (ifp->if_flags & IFF_UP) { 766 /* 767 * If only the PROMISC or ALLMULTI flag changes, then 768 * don't do a full re-init of the chip, just update 769 * the Rx filter. 770 */ 771 if ((ifp->if_flags & IFF_RUNNING) && 772 ((ifp->if_flags ^ sc->sc_if_flags) & 773 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 774 nfe_setmulti(sc); 775 } else { 776 if (!(ifp->if_flags & IFF_RUNNING)) 777 nfe_init(sc); 778 } 779 } else { 780 if (ifp->if_flags & IFF_RUNNING) 781 nfe_stop(sc); 782 } 783 sc->sc_if_flags = ifp->if_flags; 784 break; 785 case SIOCADDMULTI: 786 case SIOCDELMULTI: 787 if (ifp->if_flags & IFF_RUNNING) 788 nfe_setmulti(sc); 789 break; 790 case SIOCSIFMEDIA: 791 case SIOCGIFMEDIA: 792 mii = device_get_softc(sc->sc_miibus); 793 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 794 break; 795 case SIOCSIFCAP: 796 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 797 if (mask & IFCAP_HWCSUM) { 798 if (IFCAP_HWCSUM & ifp->if_capenable) 799 ifp->if_capenable &= ~IFCAP_HWCSUM; 800 else 801 ifp->if_capenable |= IFCAP_HWCSUM; 802 } 803 break; 804 default: 805 error = ether_ioctl(ifp, cmd, data); 806 break; 807 } 808 return error; 809 } 810 811 static void 812 nfe_rxeof(struct nfe_softc *sc) 813 { 814 struct ifnet *ifp = &sc->arpcom.ac_if; 815 struct nfe_rx_ring *ring = &sc->rxq; 816 int reap; 817 818 reap = 0; 819 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD); 820 821 for (;;) { 822 struct nfe_rx_data *data = &ring->data[ring->cur]; 823 struct mbuf *m; 824 uint16_t flags; 825 int len, error; 826 827 if (sc->sc_flags & NFE_40BIT_ADDR) { 828 struct nfe_desc64 *desc64 = &ring->desc64[ring->cur]; 829 830 flags = le16toh(desc64->flags); 831 len = le16toh(desc64->length) & 0x3fff; 832 } else { 833 struct nfe_desc32 *desc32 = &ring->desc32[ring->cur]; 834 835 flags = le16toh(desc32->flags); 836 len = le16toh(desc32->length) & 0x3fff; 837 } 838 839 if (flags & NFE_RX_READY) 840 break; 841 842 reap = 1; 843 844 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 845 if (!(flags & NFE_RX_VALID_V1)) 846 goto skip; 847 848 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 849 flags &= ~NFE_RX_ERROR; 850 len--; /* fix buffer length */ 851 } 852 } else { 853 if (!(flags & NFE_RX_VALID_V2)) 854 goto skip; 855 856 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 857 flags &= ~NFE_RX_ERROR; 858 len--; /* fix buffer length */ 859 } 860 } 861 862 if (flags & NFE_RX_ERROR) { 863 ifp->if_ierrors++; 864 goto skip; 865 } 866 867 m = data->m; 868 869 if (sc->sc_flags & NFE_USE_JUMBO) 870 error = nfe_newbuf_jumbo(sc, ring, ring->cur, 0); 871 else 872 error = nfe_newbuf_std(sc, ring, ring->cur, 0); 873 if (error) { 874 ifp->if_ierrors++; 875 goto skip; 876 } 877 878 /* finalize mbuf */ 879 m->m_pkthdr.len = m->m_len = len; 880 m->m_pkthdr.rcvif = ifp; 881 882 #ifdef notyet 883 if (sc->sc_flags & NFE_HW_CSUM) { 884 if (flags & NFE_RX_IP_CSUMOK) 885 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 886 if (flags & NFE_RX_UDP_CSUMOK) 887 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK; 888 if (flags & NFE_RX_TCP_CSUMOK) 889 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 890 } 891 #elif defined(NFE_CSUM) 892 if ((sc->sc_flags & NFE_HW_CSUM) && (flags & NFE_RX_CSUMOK)) 893 m->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK; 894 #endif 895 896 ifp->if_ipackets++; 897 ifp->if_input(ifp, m); 898 skip: 899 nfe_set_ready_rxdesc(sc, ring, ring->cur); 900 sc->rxq.cur = (sc->rxq.cur + 1) % NFE_RX_RING_COUNT; 901 } 902 903 if (reap) 904 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE); 905 } 906 907 static void 908 nfe_txeof(struct nfe_softc *sc) 909 { 910 struct ifnet *ifp = &sc->arpcom.ac_if; 911 struct nfe_tx_ring *ring = &sc->txq; 912 struct nfe_tx_data *data = NULL; 913 914 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD); 915 while (ring->next != ring->cur) { 916 uint16_t flags; 917 918 if (sc->sc_flags & NFE_40BIT_ADDR) 919 flags = le16toh(ring->desc64[ring->next].flags); 920 else 921 flags = le16toh(ring->desc32[ring->next].flags); 922 923 if (flags & NFE_TX_VALID) 924 break; 925 926 data = &ring->data[ring->next]; 927 928 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 929 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL) 930 goto skip; 931 932 if ((flags & NFE_TX_ERROR_V1) != 0) { 933 if_printf(ifp, "tx v1 error 0x%4b\n", flags, 934 NFE_V1_TXERR); 935 ifp->if_oerrors++; 936 } else { 937 ifp->if_opackets++; 938 } 939 } else { 940 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL) 941 goto skip; 942 943 if ((flags & NFE_TX_ERROR_V2) != 0) { 944 if_printf(ifp, "tx v2 error 0x%4b\n", flags, 945 NFE_V2_TXERR); 946 ifp->if_oerrors++; 947 } else { 948 ifp->if_opackets++; 949 } 950 } 951 952 if (data->m == NULL) { /* should not get there */ 953 if_printf(ifp, 954 "last fragment bit w/o associated mbuf!\n"); 955 goto skip; 956 } 957 958 /* last fragment of the mbuf chain transmitted */ 959 bus_dmamap_sync(ring->data_tag, data->map, 960 BUS_DMASYNC_POSTWRITE); 961 bus_dmamap_unload(ring->data_tag, data->map); 962 m_freem(data->m); 963 data->m = NULL; 964 965 ifp->if_timer = 0; 966 skip: 967 ring->queued--; 968 KKASSERT(ring->queued >= 0); 969 ring->next = (ring->next + 1) % NFE_TX_RING_COUNT; 970 } 971 972 if (data != NULL) { /* at least one slot freed */ 973 ifp->if_flags &= ~IFF_OACTIVE; 974 ifp->if_start(ifp); 975 } 976 } 977 978 static int 979 nfe_encap(struct nfe_softc *sc, struct nfe_tx_ring *ring, struct mbuf *m0) 980 { 981 struct nfe_dma_ctx ctx; 982 bus_dma_segment_t segs[NFE_MAX_SCATTER]; 983 struct nfe_tx_data *data, *data_map; 984 bus_dmamap_t map; 985 struct nfe_desc64 *desc64 = NULL; 986 struct nfe_desc32 *desc32 = NULL; 987 uint16_t flags = 0; 988 uint32_t vtag = 0; 989 int error, i, j; 990 991 data = &ring->data[ring->cur]; 992 map = data->map; 993 data_map = data; /* Remember who owns the DMA map */ 994 995 ctx.nsegs = NFE_MAX_SCATTER; 996 ctx.segs = segs; 997 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0, 998 nfe_buf_dma_addr, &ctx, BUS_DMA_NOWAIT); 999 if (error && error != EFBIG) { 1000 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n"); 1001 goto back; 1002 } 1003 1004 if (error) { /* error == EFBIG */ 1005 struct mbuf *m_new; 1006 1007 m_new = m_defrag(m0, MB_DONTWAIT); 1008 if (m_new == NULL) { 1009 if_printf(&sc->arpcom.ac_if, 1010 "could not defrag TX mbuf\n"); 1011 error = ENOBUFS; 1012 goto back; 1013 } else { 1014 m0 = m_new; 1015 } 1016 1017 ctx.nsegs = NFE_MAX_SCATTER; 1018 ctx.segs = segs; 1019 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0, 1020 nfe_buf_dma_addr, &ctx, 1021 BUS_DMA_NOWAIT); 1022 if (error) { 1023 if_printf(&sc->arpcom.ac_if, 1024 "could not map defraged TX mbuf\n"); 1025 goto back; 1026 } 1027 } 1028 1029 error = 0; 1030 1031 if (ring->queued + ctx.nsegs >= NFE_TX_RING_COUNT - 1) { 1032 bus_dmamap_unload(ring->data_tag, map); 1033 error = ENOBUFS; 1034 goto back; 1035 } 1036 1037 /* setup h/w VLAN tagging */ 1038 if ((m0->m_flags & (M_PROTO1 | M_PKTHDR)) == (M_PROTO1 | M_PKTHDR) && 1039 m0->m_pkthdr.rcvif != NULL && 1040 m0->m_pkthdr.rcvif->if_type == IFT_L2VLAN) { 1041 struct ifvlan *ifv = m0->m_pkthdr.rcvif->if_softc; 1042 1043 if (ifv != NULL) 1044 vtag = NFE_TX_VTAG | htons(ifv->ifv_tag); 1045 } 1046 1047 #ifdef NFE_CSUM 1048 if (m0->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1049 flags |= NFE_TX_IP_CSUM; 1050 if (m0->m_pkthdr.csum_flags & (M_TCPV4_CSUM_OUT | M_UDPV4_CSUM_OUT)) 1051 flags |= NFE_TX_TCP_CSUM; 1052 #endif 1053 1054 /* 1055 * XXX urm. somebody is unaware of how hardware works. You 1056 * absolutely CANNOT set NFE_TX_VALID on the next descriptor in 1057 * the ring until the entire chain is actually *VALID*. Otherwise 1058 * the hardware may encounter a partially initialized chain that 1059 * is marked as being ready to go when it in fact is not ready to 1060 * go. 1061 */ 1062 1063 for (i = 0; i < ctx.nsegs; i++) { 1064 j = (ring->cur + i) % NFE_TX_RING_COUNT; 1065 data = &ring->data[j]; 1066 1067 if (sc->sc_flags & NFE_40BIT_ADDR) { 1068 desc64 = &ring->desc64[j]; 1069 #if defined(__LP64__) 1070 desc64->physaddr[0] = 1071 htole32(segs[i].ds_addr >> 32); 1072 #endif 1073 desc64->physaddr[1] = 1074 htole32(segs[i].ds_addr & 0xffffffff); 1075 desc64->length = htole16(segs[i].ds_len - 1); 1076 desc64->vtag = htole32(vtag); 1077 desc64->flags = htole16(flags); 1078 } else { 1079 desc32 = &ring->desc32[j]; 1080 desc32->physaddr = htole32(segs[i].ds_addr); 1081 desc32->length = htole16(segs[i].ds_len - 1); 1082 desc32->flags = htole16(flags); 1083 } 1084 1085 /* csum flags and vtag belong to the first fragment only */ 1086 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM); 1087 vtag = 0; 1088 1089 ring->queued++; 1090 KKASSERT(ring->queued <= NFE_TX_RING_COUNT); 1091 } 1092 1093 /* the whole mbuf chain has been DMA mapped, fix last descriptor */ 1094 if (sc->sc_flags & NFE_40BIT_ADDR) { 1095 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2); 1096 } else { 1097 if (sc->sc_flags & NFE_JUMBO_SUP) 1098 flags = NFE_TX_LASTFRAG_V2; 1099 else 1100 flags = NFE_TX_LASTFRAG_V1; 1101 desc32->flags |= htole16(flags); 1102 } 1103 1104 /* 1105 * Set NFE_TX_VALID backwards so the hardware doesn't see the 1106 * whole mess until the first descriptor in the map is flagged. 1107 */ 1108 for (i = ctx.nsegs - 1; i >= 0; --i) { 1109 j = (ring->cur + i) % NFE_TX_RING_COUNT; 1110 if (sc->sc_flags & NFE_40BIT_ADDR) { 1111 desc64 = &ring->desc64[j]; 1112 desc64->flags |= htole16(NFE_TX_VALID); 1113 } else { 1114 desc32 = &ring->desc32[j]; 1115 desc32->flags |= htole16(NFE_TX_VALID); 1116 } 1117 } 1118 ring->cur = (ring->cur + ctx.nsegs) % NFE_TX_RING_COUNT; 1119 1120 /* Exchange DMA map */ 1121 data_map->map = data->map; 1122 data->map = map; 1123 data->m = m0; 1124 1125 bus_dmamap_sync(ring->data_tag, map, BUS_DMASYNC_PREWRITE); 1126 back: 1127 if (error) 1128 m_freem(m0); 1129 return error; 1130 } 1131 1132 static void 1133 nfe_start(struct ifnet *ifp) 1134 { 1135 struct nfe_softc *sc = ifp->if_softc; 1136 struct nfe_tx_ring *ring = &sc->txq; 1137 int count = 0; 1138 struct mbuf *m0; 1139 1140 if (ifp->if_flags & IFF_OACTIVE) 1141 return; 1142 1143 if (ifq_is_empty(&ifp->if_snd)) 1144 return; 1145 1146 for (;;) { 1147 m0 = ifq_dequeue(&ifp->if_snd, NULL); 1148 if (m0 == NULL) 1149 break; 1150 1151 BPF_MTAP(ifp, m0); 1152 1153 if (nfe_encap(sc, ring, m0) != 0) { 1154 ifp->if_flags |= IFF_OACTIVE; 1155 break; 1156 } 1157 ++count; 1158 1159 /* 1160 * NOTE: 1161 * `m0' may be freed in nfe_encap(), so 1162 * it should not be touched any more. 1163 */ 1164 } 1165 if (count == 0) /* nothing sent */ 1166 return; 1167 1168 /* Sync TX descriptor ring */ 1169 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE); 1170 1171 /* Kick Tx */ 1172 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1173 1174 /* 1175 * Set a timeout in case the chip goes out to lunch. 1176 */ 1177 ifp->if_timer = 5; 1178 } 1179 1180 static void 1181 nfe_watchdog(struct ifnet *ifp) 1182 { 1183 struct nfe_softc *sc = ifp->if_softc; 1184 1185 if (ifp->if_flags & IFF_RUNNING) { 1186 if_printf(ifp, "watchdog timeout - lost interrupt recovered\n"); 1187 nfe_txeof(sc); 1188 return; 1189 } 1190 1191 if_printf(ifp, "watchdog timeout\n"); 1192 1193 nfe_init(ifp->if_softc); 1194 1195 ifp->if_oerrors++; 1196 1197 if (!ifq_is_empty(&ifp->if_snd)) 1198 ifp->if_start(ifp); 1199 } 1200 1201 static void 1202 nfe_init(void *xsc) 1203 { 1204 struct nfe_softc *sc = xsc; 1205 struct ifnet *ifp = &sc->arpcom.ac_if; 1206 uint32_t tmp; 1207 int error; 1208 1209 nfe_stop(sc); 1210 1211 error = nfe_init_tx_ring(sc, &sc->txq); 1212 if (error) { 1213 nfe_stop(sc); 1214 return; 1215 } 1216 1217 error = nfe_init_rx_ring(sc, &sc->rxq); 1218 if (error) { 1219 nfe_stop(sc); 1220 return; 1221 } 1222 1223 NFE_WRITE(sc, NFE_TX_UNK, 0); 1224 NFE_WRITE(sc, NFE_STATUS, 0); 1225 1226 sc->rxtxctl = NFE_RXTX_BIT2; 1227 if (sc->sc_flags & NFE_40BIT_ADDR) 1228 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1229 else if (sc->sc_flags & NFE_JUMBO_SUP) 1230 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1231 #ifdef NFE_CSUM 1232 if (sc->sc_flags & NFE_HW_CSUM) 1233 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1234 #endif 1235 1236 /* 1237 * Although the adapter is capable of stripping VLAN tags from received 1238 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1239 * purpose. This will be done in software by our network stack. 1240 */ 1241 if (sc->sc_flags & NFE_HW_VLAN) 1242 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1243 1244 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1245 DELAY(10); 1246 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1247 1248 if (sc->sc_flags & NFE_HW_VLAN) 1249 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1250 1251 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1252 1253 /* set MAC address */ 1254 nfe_set_macaddr(sc, sc->arpcom.ac_enaddr); 1255 1256 /* tell MAC where rings are in memory */ 1257 #ifdef __LP64__ 1258 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1259 #endif 1260 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1261 #ifdef __LP64__ 1262 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1263 #endif 1264 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1265 1266 NFE_WRITE(sc, NFE_RING_SIZE, 1267 (NFE_RX_RING_COUNT - 1) << 16 | 1268 (NFE_TX_RING_COUNT - 1)); 1269 1270 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1271 1272 /* force MAC to wakeup */ 1273 tmp = NFE_READ(sc, NFE_PWR_STATE); 1274 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1275 DELAY(10); 1276 tmp = NFE_READ(sc, NFE_PWR_STATE); 1277 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1278 1279 /* 1280 * NFE_IMTIMER generates a periodic interrupt via NFE_IRQ_TIMER. 1281 * It is unclear how wide the timer is. Base programming does 1282 * not seem to effect NFE_IRQ_TX_DONE or NFE_IRQ_RX_DONE so 1283 * we don't get any interrupt moderation. TX moderation is 1284 * possible by using the timer interrupt instead of TX_DONE. 1285 * 1286 * It is unclear whether there are other bits that can be 1287 * set to make the NFE device actually do interrupt moderation 1288 * on the RX side. 1289 * 1290 * For now set a 128uS interval as a placemark, but don't use 1291 * the timer. 1292 */ 1293 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1294 1295 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1296 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1297 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1298 1299 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1300 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1301 1302 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1303 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1304 1305 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1306 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1307 DELAY(10); 1308 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1309 1310 /* set Rx filter */ 1311 nfe_setmulti(sc); 1312 1313 nfe_ifmedia_upd(ifp); 1314 1315 /* enable Rx */ 1316 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1317 1318 /* enable Tx */ 1319 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1320 1321 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1322 1323 #ifdef DEVICE_POLLING 1324 if ((ifp->if_flags & IFF_POLLING) == 0) 1325 #endif 1326 /* enable interrupts */ 1327 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1328 1329 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc); 1330 1331 ifp->if_flags |= IFF_RUNNING; 1332 ifp->if_flags &= ~IFF_OACTIVE; 1333 } 1334 1335 static void 1336 nfe_stop(struct nfe_softc *sc) 1337 { 1338 struct ifnet *ifp = &sc->arpcom.ac_if; 1339 1340 callout_stop(&sc->sc_tick_ch); 1341 1342 ifp->if_timer = 0; 1343 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1344 1345 /* Abort Tx */ 1346 NFE_WRITE(sc, NFE_TX_CTL, 0); 1347 1348 /* Disable Rx */ 1349 NFE_WRITE(sc, NFE_RX_CTL, 0); 1350 1351 /* Disable interrupts */ 1352 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1353 1354 /* Reset Tx and Rx rings */ 1355 nfe_reset_tx_ring(sc, &sc->txq); 1356 nfe_reset_rx_ring(sc, &sc->rxq); 1357 } 1358 1359 static int 1360 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1361 { 1362 int i, j, error, descsize; 1363 void **desc; 1364 1365 if (sc->sc_flags & NFE_40BIT_ADDR) { 1366 desc = (void **)&ring->desc64; 1367 descsize = sizeof(struct nfe_desc64); 1368 } else { 1369 desc = (void **)&ring->desc32; 1370 descsize = sizeof(struct nfe_desc32); 1371 } 1372 1373 ring->bufsz = MCLBYTES; 1374 ring->cur = ring->next = 0; 1375 1376 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, 1377 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1378 NULL, NULL, 1379 NFE_RX_RING_COUNT * descsize, 1, 1380 NFE_RX_RING_COUNT * descsize, 1381 0, &ring->tag); 1382 if (error) { 1383 if_printf(&sc->arpcom.ac_if, 1384 "could not create desc RX DMA tag\n"); 1385 return error; 1386 } 1387 1388 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO, 1389 &ring->map); 1390 if (error) { 1391 if_printf(&sc->arpcom.ac_if, 1392 "could not allocate RX desc DMA memory\n"); 1393 bus_dma_tag_destroy(ring->tag); 1394 ring->tag = NULL; 1395 return error; 1396 } 1397 1398 error = bus_dmamap_load(ring->tag, ring->map, *desc, 1399 NFE_RX_RING_COUNT * descsize, 1400 nfe_ring_dma_addr, &ring->physaddr, 1401 BUS_DMA_WAITOK); 1402 if (error) { 1403 if_printf(&sc->arpcom.ac_if, 1404 "could not load RX desc DMA map\n"); 1405 bus_dmamem_free(ring->tag, *desc, ring->map); 1406 bus_dma_tag_destroy(ring->tag); 1407 ring->tag = NULL; 1408 return error; 1409 } 1410 1411 if (sc->sc_flags & NFE_USE_JUMBO) { 1412 ring->bufsz = NFE_JBYTES; 1413 1414 error = nfe_jpool_alloc(sc, ring); 1415 if (error) { 1416 if_printf(&sc->arpcom.ac_if, 1417 "could not allocate jumbo frames\n"); 1418 return error; 1419 } 1420 } 1421 1422 error = bus_dma_tag_create(NULL, 1, 0, 1423 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1424 NULL, NULL, 1425 MCLBYTES, 1, MCLBYTES, 1426 0, &ring->data_tag); 1427 if (error) { 1428 if_printf(&sc->arpcom.ac_if, 1429 "could not create RX mbuf DMA tag\n"); 1430 return error; 1431 } 1432 1433 /* Create a spare RX mbuf DMA map */ 1434 error = bus_dmamap_create(ring->data_tag, 0, &ring->data_tmpmap); 1435 if (error) { 1436 if_printf(&sc->arpcom.ac_if, 1437 "could not create spare RX mbuf DMA map\n"); 1438 bus_dma_tag_destroy(ring->data_tag); 1439 ring->data_tag = NULL; 1440 return error; 1441 } 1442 1443 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1444 error = bus_dmamap_create(ring->data_tag, 0, 1445 &ring->data[i].map); 1446 if (error) { 1447 if_printf(&sc->arpcom.ac_if, 1448 "could not create %dth RX mbuf DMA mapn", i); 1449 goto fail; 1450 } 1451 } 1452 return 0; 1453 fail: 1454 for (j = 0; j < i; ++j) 1455 bus_dmamap_destroy(ring->data_tag, ring->data[i].map); 1456 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap); 1457 bus_dma_tag_destroy(ring->data_tag); 1458 ring->data_tag = NULL; 1459 return error; 1460 } 1461 1462 static void 1463 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1464 { 1465 int i; 1466 1467 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1468 struct nfe_rx_data *data = &ring->data[i]; 1469 1470 if (data->m != NULL) { 1471 bus_dmamap_unload(ring->data_tag, data->map); 1472 m_freem(data->m); 1473 data->m = NULL; 1474 } 1475 } 1476 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE); 1477 1478 ring->cur = ring->next = 0; 1479 } 1480 1481 static int 1482 nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1483 { 1484 int i; 1485 1486 for (i = 0; i < NFE_RX_RING_COUNT; ++i) { 1487 int error; 1488 1489 /* XXX should use a function pointer */ 1490 if (sc->sc_flags & NFE_USE_JUMBO) 1491 error = nfe_newbuf_jumbo(sc, ring, i, 1); 1492 else 1493 error = nfe_newbuf_std(sc, ring, i, 1); 1494 if (error) { 1495 if_printf(&sc->arpcom.ac_if, 1496 "could not allocate RX buffer\n"); 1497 return error; 1498 } 1499 1500 nfe_set_ready_rxdesc(sc, ring, i); 1501 } 1502 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE); 1503 1504 return 0; 1505 } 1506 1507 static void 1508 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1509 { 1510 if (ring->data_tag != NULL) { 1511 struct nfe_rx_data *data; 1512 int i; 1513 1514 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1515 data = &ring->data[i]; 1516 1517 if (data->m != NULL) { 1518 bus_dmamap_unload(ring->data_tag, data->map); 1519 m_freem(data->m); 1520 } 1521 bus_dmamap_destroy(ring->data_tag, data->map); 1522 } 1523 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap); 1524 bus_dma_tag_destroy(ring->data_tag); 1525 } 1526 1527 nfe_jpool_free(sc, ring); 1528 1529 if (ring->tag != NULL) { 1530 void *desc; 1531 1532 if (sc->sc_flags & NFE_40BIT_ADDR) 1533 desc = ring->desc64; 1534 else 1535 desc = ring->desc32; 1536 1537 bus_dmamap_unload(ring->tag, ring->map); 1538 bus_dmamem_free(ring->tag, desc, ring->map); 1539 bus_dma_tag_destroy(ring->tag); 1540 } 1541 } 1542 1543 static struct nfe_jbuf * 1544 nfe_jalloc(struct nfe_softc *sc) 1545 { 1546 struct ifnet *ifp = &sc->arpcom.ac_if; 1547 struct nfe_jbuf *jbuf; 1548 1549 lwkt_serialize_enter(&sc->sc_jbuf_serializer); 1550 1551 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1552 if (jbuf != NULL) { 1553 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1554 jbuf->inuse = 1; 1555 } else { 1556 if_printf(ifp, "no free jumbo buffer\n"); 1557 } 1558 1559 lwkt_serialize_exit(&sc->sc_jbuf_serializer); 1560 1561 return jbuf; 1562 } 1563 1564 static void 1565 nfe_jfree(void *arg) 1566 { 1567 struct nfe_jbuf *jbuf = arg; 1568 struct nfe_softc *sc = jbuf->sc; 1569 struct nfe_rx_ring *ring = jbuf->ring; 1570 1571 if (&ring->jbuf[jbuf->slot] != jbuf) 1572 panic("%s: free wrong jumbo buffer\n", __func__); 1573 else if (jbuf->inuse == 0) 1574 panic("%s: jumbo buffer already freed\n", __func__); 1575 1576 lwkt_serialize_enter(&sc->sc_jbuf_serializer); 1577 atomic_subtract_int(&jbuf->inuse, 1); 1578 if (jbuf->inuse == 0) 1579 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1580 lwkt_serialize_exit(&sc->sc_jbuf_serializer); 1581 } 1582 1583 static void 1584 nfe_jref(void *arg) 1585 { 1586 struct nfe_jbuf *jbuf = arg; 1587 struct nfe_rx_ring *ring = jbuf->ring; 1588 1589 if (&ring->jbuf[jbuf->slot] != jbuf) 1590 panic("%s: ref wrong jumbo buffer\n", __func__); 1591 else if (jbuf->inuse == 0) 1592 panic("%s: jumbo buffer already freed\n", __func__); 1593 1594 atomic_add_int(&jbuf->inuse, 1); 1595 } 1596 1597 static int 1598 nfe_jpool_alloc(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1599 { 1600 struct nfe_jbuf *jbuf; 1601 bus_addr_t physaddr; 1602 caddr_t buf; 1603 int i, error; 1604 1605 /* 1606 * Allocate a big chunk of DMA'able memory. 1607 */ 1608 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, 1609 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1610 NULL, NULL, 1611 NFE_JPOOL_SIZE, 1, NFE_JPOOL_SIZE, 1612 0, &ring->jtag); 1613 if (error) { 1614 if_printf(&sc->arpcom.ac_if, 1615 "could not create jumbo DMA tag\n"); 1616 return error; 1617 } 1618 1619 error = bus_dmamem_alloc(ring->jtag, (void **)&ring->jpool, 1620 BUS_DMA_WAITOK, &ring->jmap); 1621 if (error) { 1622 if_printf(&sc->arpcom.ac_if, 1623 "could not allocate jumbo DMA memory\n"); 1624 bus_dma_tag_destroy(ring->jtag); 1625 ring->jtag = NULL; 1626 return error; 1627 } 1628 1629 error = bus_dmamap_load(ring->jtag, ring->jmap, ring->jpool, 1630 NFE_JPOOL_SIZE, nfe_ring_dma_addr, &physaddr, 1631 BUS_DMA_WAITOK); 1632 if (error) { 1633 if_printf(&sc->arpcom.ac_if, 1634 "could not load jumbo DMA map\n"); 1635 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap); 1636 bus_dma_tag_destroy(ring->jtag); 1637 ring->jtag = NULL; 1638 return error; 1639 } 1640 1641 /* ..and split it into 9KB chunks */ 1642 SLIST_INIT(&ring->jfreelist); 1643 1644 buf = ring->jpool; 1645 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1646 jbuf = &ring->jbuf[i]; 1647 1648 jbuf->sc = sc; 1649 jbuf->ring = ring; 1650 jbuf->inuse = 0; 1651 jbuf->slot = i; 1652 jbuf->buf = buf; 1653 jbuf->physaddr = physaddr; 1654 1655 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1656 1657 buf += NFE_JBYTES; 1658 physaddr += NFE_JBYTES; 1659 } 1660 1661 return 0; 1662 } 1663 1664 static void 1665 nfe_jpool_free(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1666 { 1667 if (ring->jtag != NULL) { 1668 bus_dmamap_unload(ring->jtag, ring->jmap); 1669 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap); 1670 bus_dma_tag_destroy(ring->jtag); 1671 } 1672 } 1673 1674 static int 1675 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1676 { 1677 int i, j, error, descsize; 1678 void **desc; 1679 1680 if (sc->sc_flags & NFE_40BIT_ADDR) { 1681 desc = (void **)&ring->desc64; 1682 descsize = sizeof(struct nfe_desc64); 1683 } else { 1684 desc = (void **)&ring->desc32; 1685 descsize = sizeof(struct nfe_desc32); 1686 } 1687 1688 ring->queued = 0; 1689 ring->cur = ring->next = 0; 1690 1691 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, 1692 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1693 NULL, NULL, 1694 NFE_TX_RING_COUNT * descsize, 1, 1695 NFE_TX_RING_COUNT * descsize, 1696 0, &ring->tag); 1697 if (error) { 1698 if_printf(&sc->arpcom.ac_if, 1699 "could not create TX desc DMA map\n"); 1700 return error; 1701 } 1702 1703 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO, 1704 &ring->map); 1705 if (error) { 1706 if_printf(&sc->arpcom.ac_if, 1707 "could not allocate TX desc DMA memory\n"); 1708 bus_dma_tag_destroy(ring->tag); 1709 ring->tag = NULL; 1710 return error; 1711 } 1712 1713 error = bus_dmamap_load(ring->tag, ring->map, *desc, 1714 NFE_TX_RING_COUNT * descsize, 1715 nfe_ring_dma_addr, &ring->physaddr, 1716 BUS_DMA_WAITOK); 1717 if (error) { 1718 if_printf(&sc->arpcom.ac_if, 1719 "could not load TX desc DMA map\n"); 1720 bus_dmamem_free(ring->tag, *desc, ring->map); 1721 bus_dma_tag_destroy(ring->tag); 1722 ring->tag = NULL; 1723 return error; 1724 } 1725 1726 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, 1727 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1728 NULL, NULL, 1729 NFE_JBYTES * NFE_MAX_SCATTER, 1730 NFE_MAX_SCATTER, NFE_JBYTES, 1731 0, &ring->data_tag); 1732 if (error) { 1733 if_printf(&sc->arpcom.ac_if, 1734 "could not create TX buf DMA tag\n"); 1735 return error; 1736 } 1737 1738 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1739 error = bus_dmamap_create(ring->data_tag, 0, 1740 &ring->data[i].map); 1741 if (error) { 1742 if_printf(&sc->arpcom.ac_if, 1743 "could not create %dth TX buf DMA map\n", i); 1744 goto fail; 1745 } 1746 } 1747 1748 return 0; 1749 fail: 1750 for (j = 0; j < i; ++j) 1751 bus_dmamap_destroy(ring->data_tag, ring->data[i].map); 1752 bus_dma_tag_destroy(ring->data_tag); 1753 ring->data_tag = NULL; 1754 return error; 1755 } 1756 1757 static void 1758 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1759 { 1760 int i; 1761 1762 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1763 struct nfe_tx_data *data = &ring->data[i]; 1764 1765 if (sc->sc_flags & NFE_40BIT_ADDR) 1766 ring->desc64[i].flags = 0; 1767 else 1768 ring->desc32[i].flags = 0; 1769 1770 if (data->m != NULL) { 1771 bus_dmamap_sync(ring->data_tag, data->map, 1772 BUS_DMASYNC_POSTWRITE); 1773 bus_dmamap_unload(ring->data_tag, data->map); 1774 m_freem(data->m); 1775 data->m = NULL; 1776 } 1777 } 1778 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE); 1779 1780 ring->queued = 0; 1781 ring->cur = ring->next = 0; 1782 } 1783 1784 static int 1785 nfe_init_tx_ring(struct nfe_softc *sc __unused, 1786 struct nfe_tx_ring *ring __unused) 1787 { 1788 return 0; 1789 } 1790 1791 static void 1792 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1793 { 1794 if (ring->data_tag != NULL) { 1795 struct nfe_tx_data *data; 1796 int i; 1797 1798 for (i = 0; i < NFE_TX_RING_COUNT; ++i) { 1799 data = &ring->data[i]; 1800 1801 if (data->m != NULL) { 1802 bus_dmamap_unload(ring->data_tag, data->map); 1803 m_freem(data->m); 1804 } 1805 bus_dmamap_destroy(ring->data_tag, data->map); 1806 } 1807 1808 bus_dma_tag_destroy(ring->data_tag); 1809 } 1810 1811 if (ring->tag != NULL) { 1812 void *desc; 1813 1814 if (sc->sc_flags & NFE_40BIT_ADDR) 1815 desc = ring->desc64; 1816 else 1817 desc = ring->desc32; 1818 1819 bus_dmamap_unload(ring->tag, ring->map); 1820 bus_dmamem_free(ring->tag, desc, ring->map); 1821 bus_dma_tag_destroy(ring->tag); 1822 } 1823 } 1824 1825 static int 1826 nfe_ifmedia_upd(struct ifnet *ifp) 1827 { 1828 struct nfe_softc *sc = ifp->if_softc; 1829 struct mii_data *mii = device_get_softc(sc->sc_miibus); 1830 1831 if (mii->mii_instance != 0) { 1832 struct mii_softc *miisc; 1833 1834 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1835 mii_phy_reset(miisc); 1836 } 1837 mii_mediachg(mii); 1838 1839 return 0; 1840 } 1841 1842 static void 1843 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1844 { 1845 struct nfe_softc *sc = ifp->if_softc; 1846 struct mii_data *mii = device_get_softc(sc->sc_miibus); 1847 1848 mii_pollstat(mii); 1849 ifmr->ifm_status = mii->mii_media_status; 1850 ifmr->ifm_active = mii->mii_media_active; 1851 } 1852 1853 static void 1854 nfe_setmulti(struct nfe_softc *sc) 1855 { 1856 struct ifnet *ifp = &sc->arpcom.ac_if; 1857 struct ifmultiaddr *ifma; 1858 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1859 uint32_t filter = NFE_RXFILTER_MAGIC; 1860 int i; 1861 1862 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1863 bzero(addr, ETHER_ADDR_LEN); 1864 bzero(mask, ETHER_ADDR_LEN); 1865 goto done; 1866 } 1867 1868 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1869 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1870 1871 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1872 caddr_t maddr; 1873 1874 if (ifma->ifma_addr->sa_family != AF_LINK) 1875 continue; 1876 1877 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1878 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1879 addr[i] &= maddr[i]; 1880 mask[i] &= ~maddr[i]; 1881 } 1882 } 1883 1884 for (i = 0; i < ETHER_ADDR_LEN; i++) 1885 mask[i] |= addr[i]; 1886 1887 done: 1888 addr[0] |= 0x01; /* make sure multicast bit is set */ 1889 1890 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1891 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1892 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1893 addr[5] << 8 | addr[4]); 1894 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1895 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1896 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1897 mask[5] << 8 | mask[4]); 1898 1899 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1900 NFE_WRITE(sc, NFE_RXFILTER, filter); 1901 } 1902 1903 static void 1904 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1905 { 1906 uint32_t tmp; 1907 1908 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1909 addr[0] = (tmp >> 8) & 0xff; 1910 addr[1] = (tmp & 0xff); 1911 1912 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1913 addr[2] = (tmp >> 24) & 0xff; 1914 addr[3] = (tmp >> 16) & 0xff; 1915 addr[4] = (tmp >> 8) & 0xff; 1916 addr[5] = (tmp & 0xff); 1917 } 1918 1919 static void 1920 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1921 { 1922 NFE_WRITE(sc, NFE_MACADDR_LO, 1923 addr[5] << 8 | addr[4]); 1924 NFE_WRITE(sc, NFE_MACADDR_HI, 1925 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1926 } 1927 1928 static void 1929 nfe_tick(void *arg) 1930 { 1931 struct nfe_softc *sc = arg; 1932 struct ifnet *ifp = &sc->arpcom.ac_if; 1933 struct mii_data *mii = device_get_softc(sc->sc_miibus); 1934 1935 lwkt_serialize_enter(ifp->if_serializer); 1936 1937 mii_tick(mii); 1938 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc); 1939 1940 lwkt_serialize_exit(ifp->if_serializer); 1941 } 1942 1943 static void 1944 nfe_ring_dma_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 1945 { 1946 if (error) 1947 return; 1948 1949 KASSERT(nseg == 1, ("too many segments, should be 1\n")); 1950 1951 *((uint32_t *)arg) = seg->ds_addr; 1952 } 1953 1954 static void 1955 nfe_buf_dma_addr(void *arg, bus_dma_segment_t *segs, int nsegs, 1956 bus_size_t mapsz __unused, int error) 1957 { 1958 struct nfe_dma_ctx *ctx = arg; 1959 int i; 1960 1961 if (error) 1962 return; 1963 1964 KASSERT(nsegs <= ctx->nsegs, 1965 ("too many segments(%d), should be <= %d\n", 1966 nsegs, ctx->nsegs)); 1967 1968 ctx->nsegs = nsegs; 1969 for (i = 0; i < nsegs; ++i) 1970 ctx->segs[i] = segs[i]; 1971 } 1972 1973 static int 1974 nfe_newbuf_std(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx, 1975 int wait) 1976 { 1977 struct nfe_rx_data *data = &ring->data[idx]; 1978 struct nfe_dma_ctx ctx; 1979 bus_dma_segment_t seg; 1980 bus_dmamap_t map; 1981 struct mbuf *m; 1982 int error; 1983 1984 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 1985 if (m == NULL) 1986 return ENOBUFS; 1987 m->m_len = m->m_pkthdr.len = MCLBYTES; 1988 1989 ctx.nsegs = 1; 1990 ctx.segs = &seg; 1991 error = bus_dmamap_load_mbuf(ring->data_tag, ring->data_tmpmap, 1992 m, nfe_buf_dma_addr, &ctx, 1993 wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT); 1994 if (error) { 1995 m_freem(m); 1996 if_printf(&sc->arpcom.ac_if, "could map RX mbuf %d\n", error); 1997 return error; 1998 } 1999 2000 /* Unload originally mapped mbuf */ 2001 bus_dmamap_unload(ring->data_tag, data->map); 2002 2003 /* Swap this DMA map with tmp DMA map */ 2004 map = data->map; 2005 data->map = ring->data_tmpmap; 2006 ring->data_tmpmap = map; 2007 2008 /* Caller is assumed to have collected the old mbuf */ 2009 data->m = m; 2010 2011 nfe_set_paddr_rxdesc(sc, ring, idx, seg.ds_addr); 2012 2013 bus_dmamap_sync(ring->data_tag, data->map, BUS_DMASYNC_PREREAD); 2014 return 0; 2015 } 2016 2017 static int 2018 nfe_newbuf_jumbo(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx, 2019 int wait) 2020 { 2021 struct nfe_rx_data *data = &ring->data[idx]; 2022 struct nfe_jbuf *jbuf; 2023 struct mbuf *m; 2024 2025 MGETHDR(m, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA); 2026 if (m == NULL) 2027 return ENOBUFS; 2028 2029 jbuf = nfe_jalloc(sc); 2030 if (jbuf == NULL) { 2031 m_freem(m); 2032 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed " 2033 "-- packet dropped!\n"); 2034 return ENOBUFS; 2035 } 2036 2037 m->m_ext.ext_arg = jbuf; 2038 m->m_ext.ext_buf = jbuf->buf; 2039 m->m_ext.ext_free = nfe_jfree; 2040 m->m_ext.ext_ref = nfe_jref; 2041 m->m_ext.ext_size = NFE_JBYTES; 2042 2043 m->m_data = m->m_ext.ext_buf; 2044 m->m_flags |= M_EXT; 2045 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2046 2047 /* Caller is assumed to have collected the old mbuf */ 2048 data->m = m; 2049 2050 nfe_set_paddr_rxdesc(sc, ring, idx, jbuf->physaddr); 2051 2052 bus_dmamap_sync(ring->jtag, ring->jmap, BUS_DMASYNC_PREREAD); 2053 return 0; 2054 } 2055 2056 static void 2057 nfe_set_paddr_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx, 2058 bus_addr_t physaddr) 2059 { 2060 if (sc->sc_flags & NFE_40BIT_ADDR) { 2061 struct nfe_desc64 *desc64 = &ring->desc64[idx]; 2062 2063 #if defined(__LP64__) 2064 desc64->physaddr[0] = htole32(physaddr >> 32); 2065 #endif 2066 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 2067 } else { 2068 struct nfe_desc32 *desc32 = &ring->desc32[idx]; 2069 2070 desc32->physaddr = htole32(physaddr); 2071 } 2072 } 2073 2074 static void 2075 nfe_set_ready_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx) 2076 { 2077 if (sc->sc_flags & NFE_40BIT_ADDR) { 2078 struct nfe_desc64 *desc64 = &ring->desc64[idx]; 2079 2080 desc64->length = htole16(ring->bufsz); 2081 desc64->flags = htole16(NFE_RX_READY); 2082 } else { 2083 struct nfe_desc32 *desc32 = &ring->desc32[idx]; 2084 2085 desc32->length = htole16(ring->bufsz); 2086 desc32->flags = htole16(NFE_RX_READY); 2087 } 2088 } 2089