1 /* $OpenBSD: if_nfereg.h,v 1.19 2006/05/28 00:20:21 brad Exp $ */ 2 /* $DragonFly: src/sys/dev/netif/nfe/if_nfereg.h,v 1.2 2006/10/21 09:25:58 sephe Exp $ */ 3 4 /* 5 * Copyright (c) 2005 Jonathan Gray <jsg@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define NFE_PCI_BA 0x10 21 22 #define NFE_RX_RING_COUNT 128 23 #define NFE_TX_RING_COUNT 256 24 25 #define NFE_JUMBO_FRAMELEN 9018 26 #define NFE_JUMBO_MTU (NFE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 27 28 #define NFE_JBYTES (NFE_JUMBO_FRAMELEN + ETHER_ALIGN) 29 #define NFE_JPOOL_COUNT (NFE_RX_RING_COUNT + 64) 30 #define NFE_JPOOL_SIZE (NFE_JPOOL_COUNT * NFE_JBYTES) 31 32 #define NFE_MAX_SCATTER (NFE_TX_RING_COUNT - 2) 33 34 #define NFE_IRQ_STATUS 0x000 35 #define NFE_IRQ_MASK 0x004 36 #define NFE_SETUP_R6 0x008 37 #define NFE_IMTIMER 0x00c 38 #define NFE_MISC1 0x080 39 #define NFE_TX_CTL 0x084 40 #define NFE_TX_STATUS 0x088 41 #define NFE_RXFILTER 0x08c 42 #define NFE_RXBUFSZ 0x090 43 #define NFE_RX_CTL 0x094 44 #define NFE_RX_STATUS 0x098 45 #define NFE_RNDSEED 0x09c 46 #define NFE_SETUP_R1 0x0a0 47 #define NFE_SETUP_R2 0x0a4 48 #define NFE_MACADDR_HI 0x0a8 49 #define NFE_MACADDR_LO 0x0ac 50 #define NFE_MULTIADDR_HI 0x0b0 51 #define NFE_MULTIADDR_LO 0x0b4 52 #define NFE_MULTIMASK_HI 0x0b8 53 #define NFE_MULTIMASK_LO 0x0bc 54 #define NFE_PHY_IFACE 0x0c0 55 #define NFE_TX_RING_ADDR_LO 0x100 56 #define NFE_RX_RING_ADDR_LO 0x104 57 #define NFE_RING_SIZE 0x108 58 #define NFE_TX_UNK 0x10c 59 #define NFE_LINKSPEED 0x110 60 #define NFE_SETUP_R5 0x130 61 #define NFE_SETUP_R3 0x13C 62 #define NFE_SETUP_R7 0x140 63 #define NFE_RXTX_CTL 0x144 64 #define NFE_TX_RING_ADDR_HI 0x148 65 #define NFE_RX_RING_ADDR_HI 0x14c 66 #define NFE_PHY_STATUS 0x180 67 #define NFE_SETUP_R4 0x184 68 #define NFE_STATUS 0x188 69 #define NFE_PHY_SPEED 0x18c 70 #define NFE_PHY_CTL 0x190 71 #define NFE_PHY_DATA 0x194 72 #define NFE_WOL_CTL 0x200 73 #define NFE_PATTERN_CRC 0x204 74 #define NFE_PATTERN_MASK 0x208 75 #define NFE_PWR_CAP 0x268 76 #define NFE_PWR_STATE 0x26c 77 #define NFE_VTAG_CTL 0x300 78 79 #define NFE_PHY_ERROR 0x00001 80 #define NFE_PHY_WRITE 0x00400 81 #define NFE_PHY_BUSY 0x08000 82 #define NFE_PHYADD_SHIFT 5 83 84 #define NFE_STATUS_MAGIC 0x140000 85 86 #define NFE_R1_MAGIC 0x16070f 87 #define NFE_R2_MAGIC 0x16 88 #define NFE_R4_MAGIC 0x08 89 #define NFE_R6_MAGIC 0x03 90 #define NFE_WOL_MAGIC 0x1111 91 #define NFE_RX_START 0x01 92 #define NFE_TX_START 0x01 93 94 #define NFE_IRQ_RXERR 0x0001 95 #define NFE_IRQ_RX 0x0002 96 #define NFE_IRQ_RX_NOBUF 0x0004 97 #define NFE_IRQ_TXERR 0x0008 98 #define NFE_IRQ_TX_DONE 0x0010 99 #define NFE_IRQ_TIMER 0x0020 100 #define NFE_IRQ_LINK 0x0040 101 #define NFE_IRQ_TXERR2 0x0080 102 #define NFE_IRQ_TX1 0x0100 103 104 #define NFE_IRQ_WANTED \ 105 (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX | \ 106 NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE | \ 107 NFE_IRQ_LINK) 108 109 #define NFE_RXTX_KICKTX 0x0001 110 #define NFE_RXTX_BIT1 0x0002 111 #define NFE_RXTX_BIT2 0x0004 112 #define NFE_RXTX_RESET 0x0010 113 #define NFE_RXTX_VTAG_STRIP 0x0040 114 #define NFE_RXTX_VTAG_INSERT 0x0080 115 #define NFE_RXTX_RXCSUM 0x0400 116 #define NFE_RXTX_V2MAGIC 0x2100 117 #define NFE_RXTX_V3MAGIC 0x2200 118 #define NFE_RXFILTER_MAGIC 0x007f0008 119 #define NFE_U2M (1 << 5) 120 #define NFE_PROMISC (1 << 7) 121 122 /* default interrupt moderation timer of 128us */ 123 #define NFE_IM_DEFAULT ((128 * 100) / 1024) 124 125 #define NFE_VTAG_ENABLE (1 << 13) 126 127 #define NFE_PWR_VALID (1 << 8) 128 #define NFE_PWR_WAKEUP (1 << 15) 129 130 #define NFE_MEDIA_SET 0x10000 131 #define NFE_MEDIA_1000T 0x00032 132 #define NFE_MEDIA_100TX 0x00064 133 #define NFE_MEDIA_10T 0x003e8 134 135 #define NFE_PHY_100TX (1 << 0) 136 #define NFE_PHY_1000T (1 << 1) 137 #define NFE_PHY_HDX (1 << 8) 138 139 #define NFE_MISC1_MAGIC 0x003b0f3c 140 #define NFE_MISC1_HDX (1 << 1) 141 142 #define NFE_SEED_MASK 0x0003ff00 143 #define NFE_SEED_10T 0x00007f00 144 #define NFE_SEED_100TX 0x00002d00 145 #define NFE_SEED_1000T 0x00007400 146 147 /* Rx/Tx descriptor */ 148 struct nfe_desc32 { 149 uint32_t physaddr; 150 uint16_t length; 151 uint16_t flags; 152 #define NFE_RX_FIXME_V1 0x6004 153 #define NFE_RX_VALID_V1 (1 << 0) 154 #define NFE_TX_ERROR_V1 0x7808 155 #define NFE_TX_LASTFRAG_V1 (1 << 0) 156 } __packed; 157 158 #define NFE_V1_TXERR "\020" \ 159 "\14TXERROR\13UNDERFLOW\12LATECOLLISION\11LOSTCARRIER\10DEFERRED" \ 160 "\08FORCEDINT\03RETRY\00LASTPACKET" 161 162 /* V2 Rx/Tx descriptor */ 163 struct nfe_desc64 { 164 uint32_t physaddr[2]; 165 uint32_t vtag; 166 #define NFE_RX_VTAG (1 << 16) 167 #define NFE_TX_VTAG (1 << 18) 168 uint16_t length; 169 uint16_t flags; 170 #define NFE_RX_FIXME_V2 0x4300 171 #define NFE_RX_VALID_V2 (1 << 13) 172 #define NFE_TX_ERROR_V2 0x5c04 173 #define NFE_TX_LASTFRAG_V2 (1 << 13) 174 } __packed; 175 176 #define NFE_V2_TXERR "\020" \ 177 "\14FORCEDINT\13LASTPACKET\12UNDERFLOW\10LOSTCARRIER\09DEFERRED\02RETRY" 178 179 /* flags common to V1/V2 descriptors */ 180 #define NFE_RX_CSUMOK 0x1c00 181 #define NFE_RX_ERROR (1 << 14) 182 #define NFE_RX_READY (1 << 15) 183 #define NFE_TX_TCP_CSUM (1 << 10) 184 #define NFE_TX_IP_CSUM (1 << 11) 185 #define NFE_TX_VALID (1 << 15) 186 187 #define NFE_READ(sc, reg) \ 188 bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (reg)) 189 190 #define NFE_WRITE(sc, reg, val) \ 191 bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (val)) 192