1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $ 34 * $DragonFly: src/sys/dev/netif/nge/if_nge.c,v 1.33 2005/11/22 00:24:33 dillon Exp $ 35 */ 36 37 /* 38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 39 * for FreeBSD. Datasheets are available from: 40 * 41 * http://www.national.com/ds/DP/DP83820.pdf 42 * http://www.national.com/ds/DP/DP83821.pdf 43 * 44 * These chips are used on several low cost gigabit ethernet NICs 45 * sold by D-Link, Addtron, SMC and Asante. Both parts are 46 * virtually the same, except the 83820 is a 64-bit/32-bit part, 47 * while the 83821 is 32-bit only. 48 * 49 * Many cards also use National gigE transceivers, such as the 50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 51 * contains a full register description that applies to all of these 52 * components: 53 * 54 * http://www.national.com/ds/DP/DP83861.pdf 55 * 56 * Written by Bill Paul <wpaul@bsdi.com> 57 * BSDi Open Source Solutions 58 */ 59 60 /* 61 * The NatSemi DP83820 and 83821 controllers are enhanced versions 62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 67 * matching buffers, one perfect address filter buffer and interrupt 68 * moderation. The 83820 supports both 64-bit and 32-bit addressing 69 * and data transfers: the 64-bit support can be toggled on or off 70 * via software. This affects the size of certain fields in the DMA 71 * descriptors. 72 * 73 * There are two bugs/misfeatures in the 83820/83821 that I have 74 * discovered so far: 75 * 76 * - Receive buffers must be aligned on 64-bit boundaries, which means 77 * you must resort to copying data in order to fix up the payload 78 * alignment. 79 * 80 * - In order to transmit jumbo frames larger than 8170 bytes, you have 81 * to turn off transmit checksum offloading, because the chip can't 82 * compute the checksum on an outgoing frame unless it fits entirely 83 * within the TX FIFO, which is only 8192 bytes in size. If you have 84 * TX checksum offload enabled and you transmit attempt to transmit a 85 * frame larger than 8170 bytes, the transmitter will wedge. 86 * 87 * To work around the latter problem, TX checksum offload is disabled 88 * if the user selects an MTU larger than 8152 (8170 - 18). 89 */ 90 91 #include "opt_polling.h" 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/sockio.h> 96 #include <sys/mbuf.h> 97 #include <sys/malloc.h> 98 #include <sys/kernel.h> 99 #include <sys/socket.h> 100 #include <sys/thread2.h> 101 102 #include <net/if.h> 103 #include <net/ifq_var.h> 104 #include <net/if_arp.h> 105 #include <net/ethernet.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 #include <net/if_types.h> 109 #include <net/vlan/if_vlan_var.h> 110 111 #include <net/bpf.h> 112 113 #include <vm/vm.h> /* for vtophys */ 114 #include <vm/pmap.h> /* for vtophys */ 115 #include <machine/bus.h> 116 #include <machine/resource.h> 117 #include <sys/bus.h> 118 #include <sys/rman.h> 119 120 #include <dev/netif/mii_layer/mii.h> 121 #include <dev/netif/mii_layer/miivar.h> 122 123 #include <bus/pci/pcireg.h> 124 #include <bus/pci/pcivar.h> 125 126 #define NGE_USEIOSPACE 127 128 #include "if_ngereg.h" 129 130 131 /* "controller miibus0" required. See GENERIC if you get errors here. */ 132 #include "miibus_if.h" 133 134 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 135 136 /* 137 * Various supported device vendors/types and their names. 138 */ 139 static struct nge_type nge_devs[] = { 140 { NGE_VENDORID, NGE_DEVICEID, 141 "National Semiconductor Gigabit Ethernet" }, 142 { 0, 0, NULL } 143 }; 144 145 static int nge_probe(device_t); 146 static int nge_attach(device_t); 147 static int nge_detach(device_t); 148 149 static int nge_alloc_jumbo_mem(struct nge_softc *); 150 static struct nge_jslot 151 *nge_jalloc(struct nge_softc *); 152 static void nge_jfree(void *); 153 static void nge_jref(void *); 154 155 static int nge_newbuf(struct nge_softc *, struct nge_desc *, 156 struct mbuf *); 157 static int nge_encap(struct nge_softc *, struct mbuf *, uint32_t *); 158 static void nge_rxeof(struct nge_softc *); 159 static void nge_txeof(struct nge_softc *); 160 static void nge_intr(void *); 161 static void nge_tick(void *); 162 static void nge_start(struct ifnet *); 163 static int nge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 164 static void nge_init(void *); 165 static void nge_stop(struct nge_softc *); 166 static void nge_watchdog(struct ifnet *); 167 static void nge_shutdown(device_t); 168 static int nge_ifmedia_upd(struct ifnet *); 169 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 170 171 static void nge_delay(struct nge_softc *); 172 static void nge_eeprom_idle(struct nge_softc *); 173 static void nge_eeprom_putbyte(struct nge_softc *, int); 174 static void nge_eeprom_getword(struct nge_softc *, int, uint16_t *); 175 static void nge_read_eeprom(struct nge_softc *, void *, int, int); 176 177 static void nge_mii_sync(struct nge_softc *); 178 static void nge_mii_send(struct nge_softc *, uint32_t, int); 179 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *); 180 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *); 181 182 static int nge_miibus_readreg(device_t, int, int); 183 static int nge_miibus_writereg(device_t, int, int, int); 184 static void nge_miibus_statchg(device_t); 185 186 static void nge_setmulti(struct nge_softc *); 187 static void nge_reset(struct nge_softc *); 188 static int nge_list_rx_init(struct nge_softc *); 189 static int nge_list_tx_init(struct nge_softc *); 190 #ifdef DEVICE_POLLING 191 static void nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 192 #endif 193 194 #ifdef NGE_USEIOSPACE 195 #define NGE_RES SYS_RES_IOPORT 196 #define NGE_RID NGE_PCI_LOIO 197 #else 198 #define NGE_RES SYS_RES_MEMORY 199 #define NGE_RID NGE_PCI_LOMEM 200 #endif 201 202 static device_method_t nge_methods[] = { 203 /* Device interface */ 204 DEVMETHOD(device_probe, nge_probe), 205 DEVMETHOD(device_attach, nge_attach), 206 DEVMETHOD(device_detach, nge_detach), 207 DEVMETHOD(device_shutdown, nge_shutdown), 208 209 /* bus interface */ 210 DEVMETHOD(bus_print_child, bus_generic_print_child), 211 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 212 213 /* MII interface */ 214 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 215 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 216 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 217 218 { 0, 0 } 219 }; 220 221 static DEFINE_CLASS_0(nge, nge_driver, nge_methods, sizeof(struct nge_softc)); 222 static devclass_t nge_devclass; 223 224 DECLARE_DUMMY_MODULE(if_nge); 225 MODULE_DEPEND(if_nge, miibus, 1, 1, 1); 226 DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0); 227 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 228 229 #define NGE_SETBIT(sc, reg, x) \ 230 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 231 232 #define NGE_CLRBIT(sc, reg, x) \ 233 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 234 235 #define SIO_SET(x) \ 236 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) 237 238 #define SIO_CLR(x) \ 239 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) 240 241 static void 242 nge_delay(struct nge_softc *sc) 243 { 244 int idx; 245 246 for (idx = (300 / 33) + 1; idx > 0; idx--) 247 CSR_READ_4(sc, NGE_CSR); 248 } 249 250 static void 251 nge_eeprom_idle(struct nge_softc *sc) 252 { 253 int i; 254 255 SIO_SET(NGE_MEAR_EE_CSEL); 256 nge_delay(sc); 257 SIO_SET(NGE_MEAR_EE_CLK); 258 nge_delay(sc); 259 260 for (i = 0; i < 25; i++) { 261 SIO_CLR(NGE_MEAR_EE_CLK); 262 nge_delay(sc); 263 SIO_SET(NGE_MEAR_EE_CLK); 264 nge_delay(sc); 265 } 266 267 SIO_CLR(NGE_MEAR_EE_CLK); 268 nge_delay(sc); 269 SIO_CLR(NGE_MEAR_EE_CSEL); 270 nge_delay(sc); 271 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 272 } 273 274 /* 275 * Send a read command and address to the EEPROM, check for ACK. 276 */ 277 static void 278 nge_eeprom_putbyte(struct nge_softc *sc, int addr) 279 { 280 int d, i; 281 282 d = addr | NGE_EECMD_READ; 283 284 /* 285 * Feed in each bit and stobe the clock. 286 */ 287 for (i = 0x400; i; i >>= 1) { 288 if (d & i) 289 SIO_SET(NGE_MEAR_EE_DIN); 290 else 291 SIO_CLR(NGE_MEAR_EE_DIN); 292 nge_delay(sc); 293 SIO_SET(NGE_MEAR_EE_CLK); 294 nge_delay(sc); 295 SIO_CLR(NGE_MEAR_EE_CLK); 296 nge_delay(sc); 297 } 298 } 299 300 /* 301 * Read a word of data stored in the EEPROM at address 'addr.' 302 */ 303 static void 304 nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest) 305 { 306 int i; 307 uint16_t word = 0; 308 309 /* Force EEPROM to idle state. */ 310 nge_eeprom_idle(sc); 311 312 /* Enter EEPROM access mode. */ 313 nge_delay(sc); 314 SIO_CLR(NGE_MEAR_EE_CLK); 315 nge_delay(sc); 316 SIO_SET(NGE_MEAR_EE_CSEL); 317 nge_delay(sc); 318 319 /* 320 * Send address of word we want to read. 321 */ 322 nge_eeprom_putbyte(sc, addr); 323 324 /* 325 * Start reading bits from EEPROM. 326 */ 327 for (i = 0x8000; i; i >>= 1) { 328 SIO_SET(NGE_MEAR_EE_CLK); 329 nge_delay(sc); 330 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 331 word |= i; 332 nge_delay(sc); 333 SIO_CLR(NGE_MEAR_EE_CLK); 334 nge_delay(sc); 335 } 336 337 /* Turn off EEPROM access mode. */ 338 nge_eeprom_idle(sc); 339 340 *dest = word; 341 } 342 343 /* 344 * Read a sequence of words from the EEPROM. 345 */ 346 static void 347 nge_read_eeprom(struct nge_softc *sc, void *dest, int off, int cnt) 348 { 349 int i; 350 uint16_t word = 0, *ptr; 351 352 for (i = 0; i < cnt; i++) { 353 nge_eeprom_getword(sc, off + i, &word); 354 ptr = (uint16_t *)((uint8_t *)dest + (i * 2)); 355 *ptr = word; 356 } 357 } 358 359 /* 360 * Sync the PHYs by setting data bit and strobing the clock 32 times. 361 */ 362 static void 363 nge_mii_sync(struct nge_softc *sc) 364 { 365 int i; 366 367 SIO_SET(NGE_MEAR_MII_DIR | NGE_MEAR_MII_DATA); 368 369 for (i = 0; i < 32; i++) { 370 SIO_SET(NGE_MEAR_MII_CLK); 371 DELAY(1); 372 SIO_CLR(NGE_MEAR_MII_CLK); 373 DELAY(1); 374 } 375 } 376 377 /* 378 * Clock a series of bits through the MII. 379 */ 380 static void 381 nge_mii_send(struct nge_softc *sc, uint32_t bits, int cnt) 382 { 383 int i; 384 385 SIO_CLR(NGE_MEAR_MII_CLK); 386 387 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 388 if (bits & i) 389 SIO_SET(NGE_MEAR_MII_DATA); 390 else 391 SIO_CLR(NGE_MEAR_MII_DATA); 392 DELAY(1); 393 SIO_CLR(NGE_MEAR_MII_CLK); 394 DELAY(1); 395 SIO_SET(NGE_MEAR_MII_CLK); 396 } 397 } 398 399 /* 400 * Read an PHY register through the MII. 401 */ 402 static int 403 nge_mii_readreg(struct nge_softc *sc, struct nge_mii_frame *frame) 404 { 405 int ack, i; 406 407 crit_enter(); 408 409 /* 410 * Set up frame for RX. 411 */ 412 frame->mii_stdelim = NGE_MII_STARTDELIM; 413 frame->mii_opcode = NGE_MII_READOP; 414 frame->mii_turnaround = 0; 415 frame->mii_data = 0; 416 417 CSR_WRITE_4(sc, NGE_MEAR, 0); 418 419 /* 420 * Turn on data xmit. 421 */ 422 SIO_SET(NGE_MEAR_MII_DIR); 423 424 nge_mii_sync(sc); 425 426 /* 427 * Send command/address info. 428 */ 429 nge_mii_send(sc, frame->mii_stdelim, 2); 430 nge_mii_send(sc, frame->mii_opcode, 2); 431 nge_mii_send(sc, frame->mii_phyaddr, 5); 432 nge_mii_send(sc, frame->mii_regaddr, 5); 433 434 /* Idle bit */ 435 SIO_CLR((NGE_MEAR_MII_CLK | NGE_MEAR_MII_DATA)); 436 DELAY(1); 437 SIO_SET(NGE_MEAR_MII_CLK); 438 DELAY(1); 439 440 /* Turn off xmit. */ 441 SIO_CLR(NGE_MEAR_MII_DIR); 442 /* Check for ack */ 443 SIO_CLR(NGE_MEAR_MII_CLK); 444 DELAY(1); 445 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 446 SIO_SET(NGE_MEAR_MII_CLK); 447 DELAY(1); 448 449 /* 450 * Now try reading data bits. If the ack failed, we still 451 * need to clock through 16 cycles to keep the PHY(s) in sync. 452 */ 453 if (ack) { 454 for(i = 0; i < 16; i++) { 455 SIO_CLR(NGE_MEAR_MII_CLK); 456 DELAY(1); 457 SIO_SET(NGE_MEAR_MII_CLK); 458 DELAY(1); 459 } 460 goto fail; 461 } 462 463 for (i = 0x8000; i; i >>= 1) { 464 SIO_CLR(NGE_MEAR_MII_CLK); 465 DELAY(1); 466 if (!ack) { 467 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 468 frame->mii_data |= i; 469 DELAY(1); 470 } 471 SIO_SET(NGE_MEAR_MII_CLK); 472 DELAY(1); 473 } 474 475 fail: 476 SIO_CLR(NGE_MEAR_MII_CLK); 477 DELAY(1); 478 SIO_SET(NGE_MEAR_MII_CLK); 479 DELAY(1); 480 481 crit_exit(); 482 483 if (ack) 484 return(1); 485 return(0); 486 } 487 488 /* 489 * Write to a PHY register through the MII. 490 */ 491 static int 492 nge_mii_writereg(struct nge_softc *sc, struct nge_mii_frame *frame) 493 { 494 crit_enter(); 495 496 /* 497 * Set up frame for TX. 498 */ 499 500 frame->mii_stdelim = NGE_MII_STARTDELIM; 501 frame->mii_opcode = NGE_MII_WRITEOP; 502 frame->mii_turnaround = NGE_MII_TURNAROUND; 503 504 /* 505 * Turn on data output. 506 */ 507 SIO_SET(NGE_MEAR_MII_DIR); 508 509 nge_mii_sync(sc); 510 511 nge_mii_send(sc, frame->mii_stdelim, 2); 512 nge_mii_send(sc, frame->mii_opcode, 2); 513 nge_mii_send(sc, frame->mii_phyaddr, 5); 514 nge_mii_send(sc, frame->mii_regaddr, 5); 515 nge_mii_send(sc, frame->mii_turnaround, 2); 516 nge_mii_send(sc, frame->mii_data, 16); 517 518 /* Idle bit. */ 519 SIO_SET(NGE_MEAR_MII_CLK); 520 DELAY(1); 521 SIO_CLR(NGE_MEAR_MII_CLK); 522 DELAY(1); 523 524 /* 525 * Turn off xmit. 526 */ 527 SIO_CLR(NGE_MEAR_MII_DIR); 528 529 crit_exit(); 530 531 return(0); 532 } 533 534 static int 535 nge_miibus_readreg(device_t dev, int phy, int reg) 536 { 537 struct nge_softc *sc = device_get_softc(dev); 538 struct nge_mii_frame frame; 539 540 bzero((char *)&frame, sizeof(frame)); 541 542 frame.mii_phyaddr = phy; 543 frame.mii_regaddr = reg; 544 nge_mii_readreg(sc, &frame); 545 546 return(frame.mii_data); 547 } 548 549 static int 550 nge_miibus_writereg(device_t dev, int phy, int reg, int data) 551 { 552 struct nge_softc *sc = device_get_softc(dev); 553 struct nge_mii_frame frame; 554 555 bzero((char *)&frame, sizeof(frame)); 556 557 frame.mii_phyaddr = phy; 558 frame.mii_regaddr = reg; 559 frame.mii_data = data; 560 nge_mii_writereg(sc, &frame); 561 562 return(0); 563 } 564 565 static void 566 nge_miibus_statchg(device_t dev) 567 { 568 struct nge_softc *sc = device_get_softc(dev); 569 struct mii_data *mii; 570 int status; 571 572 if (sc->nge_tbi) { 573 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 574 == IFM_AUTO) { 575 status = CSR_READ_4(sc, NGE_TBI_ANLPAR); 576 if (status == 0 || status & NGE_TBIANAR_FDX) { 577 NGE_SETBIT(sc, NGE_TX_CFG, 578 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 579 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 580 } else { 581 NGE_CLRBIT(sc, NGE_TX_CFG, 582 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 583 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 584 } 585 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 586 != IFM_FDX) { 587 NGE_CLRBIT(sc, NGE_TX_CFG, 588 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 589 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 590 } else { 591 NGE_SETBIT(sc, NGE_TX_CFG, 592 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 593 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 594 } 595 } else { 596 mii = device_get_softc(sc->nge_miibus); 597 598 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 599 NGE_SETBIT(sc, NGE_TX_CFG, 600 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 601 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 602 } else { 603 NGE_CLRBIT(sc, NGE_TX_CFG, 604 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 605 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 606 } 607 608 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 609 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 610 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 611 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 612 } else { 613 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 614 } 615 } 616 } 617 618 static void 619 nge_setmulti(struct nge_softc *sc) 620 { 621 struct ifnet *ifp = &sc->arpcom.ac_if; 622 struct ifmultiaddr *ifma; 623 uint32_t filtsave, h = 0, i; 624 int bit, index; 625 626 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 627 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 628 NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH); 629 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 630 return; 631 } 632 633 /* 634 * We have to explicitly enable the multicast hash table 635 * on the NatSemi chip if we want to use it, which we do. 636 * We also have to tell it that we don't want to use the 637 * hash table for matching unicast addresses. 638 */ 639 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 640 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 641 NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_UCHASH); 642 643 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 644 645 /* first, zot all the existing hash bits */ 646 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 647 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 648 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 649 } 650 651 /* 652 * From the 11 bits returned by the crc routine, the top 7 653 * bits represent the 16-bit word in the mcast hash table 654 * that needs to be updated, and the lower 4 bits represent 655 * which bit within that byte needs to be set. 656 */ 657 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 658 if (ifma->ifma_addr->sa_family != AF_LINK) 659 continue; 660 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 661 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21; 662 index = (h >> 4) & 0x7F; 663 bit = h & 0xF; 664 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 665 NGE_FILTADDR_MCAST_LO + (index * 2)); 666 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 667 } 668 669 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 670 } 671 672 static void 673 nge_reset(struct nge_softc *sc) 674 { 675 int i; 676 677 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 678 679 for (i = 0; i < NGE_TIMEOUT; i++) { 680 if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET) == 0) 681 break; 682 } 683 684 if (i == NGE_TIMEOUT) 685 printf("nge%d: reset never completed\n", sc->nge_unit); 686 687 /* Wait a little while for the chip to get its brains in order. */ 688 DELAY(1000); 689 690 /* 691 * If this is a NetSemi chip, make sure to clear 692 * PME mode. 693 */ 694 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 695 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 696 } 697 698 /* 699 * Probe for an NatSemi chip. Check the PCI vendor and device 700 * IDs against our list and return a device name if we find a match. 701 */ 702 static int 703 nge_probe(device_t dev) 704 { 705 struct nge_type *t; 706 uint16_t vendor, product; 707 708 vendor = pci_get_vendor(dev); 709 product = pci_get_device(dev); 710 711 for (t = nge_devs; t->nge_name != NULL; t++) { 712 if (vendor == t->nge_vid && product == t->nge_did) { 713 device_set_desc(dev, t->nge_name); 714 return(0); 715 } 716 } 717 718 return(ENXIO); 719 } 720 721 /* 722 * Attach the interface. Allocate softc structures, do ifmedia 723 * setup and ethernet/BPF attach. 724 */ 725 static int 726 nge_attach(device_t dev) 727 { 728 struct nge_softc *sc; 729 struct ifnet *ifp; 730 uint8_t eaddr[ETHER_ADDR_LEN]; 731 uint32_t command; 732 int error = 0, rid, unit; 733 const char *sep = ""; 734 735 sc = device_get_softc(dev); 736 unit = device_get_unit(dev); 737 callout_init(&sc->nge_stat_timer); 738 739 /* 740 * Handle power management nonsense. 741 */ 742 command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF; 743 if (command == 0x01) { 744 command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4); 745 if (command & NGE_PSTATE_MASK) { 746 uint32_t iobase, membase, irq; 747 748 /* Save important PCI config data. */ 749 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4); 750 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4); 751 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4); 752 753 /* Reset the power state. */ 754 printf("nge%d: chip is in D%d power mode " 755 "-- setting to D0\n", unit, command & NGE_PSTATE_MASK); 756 command &= 0xFFFFFFFC; 757 pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4); 758 759 /* Restore PCI config data. */ 760 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4); 761 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4); 762 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4); 763 } 764 } 765 766 /* 767 * Map control/status registers. 768 */ 769 command = pci_read_config(dev, PCIR_COMMAND, 4); 770 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 771 pci_write_config(dev, PCIR_COMMAND, command, 4); 772 command = pci_read_config(dev, PCIR_COMMAND, 4); 773 774 #ifdef NGE_USEIOSPACE 775 if (!(command & PCIM_CMD_PORTEN)) { 776 printf("nge%d: failed to enable I/O ports!\n", unit); 777 error = ENXIO; 778 return(error); 779 } 780 #else 781 if (!(command & PCIM_CMD_MEMEN)) { 782 printf("nge%d: failed to enable memory mapping!\n", unit); 783 error = ENXIO; 784 return(error); 785 } 786 #endif 787 788 rid = NGE_RID; 789 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE); 790 791 if (sc->nge_res == NULL) { 792 printf("nge%d: couldn't map ports/memory\n", unit); 793 error = ENXIO; 794 return(error); 795 } 796 797 sc->nge_btag = rman_get_bustag(sc->nge_res); 798 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 799 800 /* Allocate interrupt */ 801 rid = 0; 802 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 803 RF_SHAREABLE | RF_ACTIVE); 804 805 if (sc->nge_irq == NULL) { 806 printf("nge%d: couldn't map interrupt\n", unit); 807 error = ENXIO; 808 goto fail; 809 } 810 811 /* Reset the adapter. */ 812 nge_reset(sc); 813 814 /* 815 * Get station address from the EEPROM. 816 */ 817 nge_read_eeprom(sc, &eaddr[4], NGE_EE_NODEADDR, 1); 818 nge_read_eeprom(sc, &eaddr[2], NGE_EE_NODEADDR + 1, 1); 819 nge_read_eeprom(sc, &eaddr[0], NGE_EE_NODEADDR + 2, 1); 820 821 sc->nge_unit = unit; 822 823 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 824 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 825 826 if (sc->nge_ldata == NULL) { 827 printf("nge%d: no memory for list buffers!\n", unit); 828 error = ENXIO; 829 goto fail; 830 } 831 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 832 833 /* Try to allocate memory for jumbo buffers. */ 834 if (nge_alloc_jumbo_mem(sc)) { 835 printf("nge%d: jumbo buffer allocation failed\n", 836 sc->nge_unit); 837 error = ENXIO; 838 goto fail; 839 } 840 841 ifp = &sc->arpcom.ac_if; 842 ifp->if_softc = sc; 843 if_initname(ifp, "nge", unit); 844 ifp->if_mtu = ETHERMTU; 845 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 846 ifp->if_ioctl = nge_ioctl; 847 ifp->if_start = nge_start; 848 #ifdef DEVICE_POLLING 849 ifp->if_poll = nge_poll; 850 #endif 851 ifp->if_watchdog = nge_watchdog; 852 ifp->if_init = nge_init; 853 ifp->if_baudrate = 1000000000; 854 ifq_set_maxlen(&ifp->if_snd, NGE_TX_LIST_CNT - 1); 855 ifq_set_ready(&ifp->if_snd); 856 ifp->if_hwassist = NGE_CSUM_FEATURES; 857 ifp->if_capabilities = IFCAP_HWCSUM; 858 ifp->if_capenable = ifp->if_capabilities; 859 860 /* 861 * Do MII setup. 862 */ 863 if (mii_phy_probe(dev, &sc->nge_miibus, 864 nge_ifmedia_upd, nge_ifmedia_sts)) { 865 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) { 866 sc->nge_tbi = 1; 867 device_printf(dev, "Using TBI\n"); 868 869 sc->nge_miibus = dev; 870 871 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd, 872 nge_ifmedia_sts); 873 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL) 874 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 875 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0); 876 device_printf(dev, " "); 877 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0); 878 PRINT("1000baseSX"); 879 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0); 880 PRINT("1000baseSX-FDX"); 881 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0); 882 PRINT("auto"); 883 884 printf("\n"); 885 #undef ADD 886 #undef PRINT 887 ifmedia_set(&sc->nge_ifmedia, 888 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0)); 889 890 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 891 | NGE_GPIO_GP4_OUT 892 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 893 | NGE_GPIO_GP3_OUTENB 894 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 895 896 } else { 897 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 898 error = ENXIO; 899 goto fail; 900 } 901 } 902 903 /* 904 * Call MI attach routine. 905 */ 906 ether_ifattach(ifp, eaddr); 907 908 error = bus_setup_intr(dev, sc->nge_irq, 0, 909 nge_intr, sc, &sc->nge_intrhand, NULL); 910 if (error) { 911 ether_ifdetach(ifp); 912 device_printf(dev, "couldn't set up irq\n"); 913 goto fail; 914 } 915 916 return(0); 917 fail: 918 nge_detach(dev); 919 return(error); 920 } 921 922 static int 923 nge_detach(device_t dev) 924 { 925 struct nge_softc *sc = device_get_softc(dev); 926 struct ifnet *ifp = &sc->arpcom.ac_if; 927 928 crit_enter(); 929 930 if (device_is_attached(dev)) { 931 nge_reset(sc); 932 nge_stop(sc); 933 ether_ifdetach(ifp); 934 } 935 936 if (sc->nge_miibus) 937 device_delete_child(dev, sc->nge_miibus); 938 bus_generic_detach(dev); 939 940 if (sc->nge_intrhand) 941 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 942 943 crit_exit(); 944 945 if (sc->nge_irq) 946 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 947 if (sc->nge_res) 948 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 949 if (sc->nge_ldata) { 950 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), 951 M_DEVBUF); 952 } 953 if (sc->nge_cdata.nge_jumbo_buf) 954 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF); 955 956 return(0); 957 } 958 959 /* 960 * Initialize the transmit descriptors. 961 */ 962 static int 963 nge_list_tx_init(struct nge_softc *sc) 964 { 965 struct nge_list_data *ld; 966 struct nge_ring_data *cd; 967 int i; 968 969 cd = &sc->nge_cdata; 970 ld = sc->nge_ldata; 971 972 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 973 if (i == (NGE_TX_LIST_CNT - 1)) { 974 ld->nge_tx_list[i].nge_nextdesc = 975 &ld->nge_tx_list[0]; 976 ld->nge_tx_list[i].nge_next = 977 vtophys(&ld->nge_tx_list[0]); 978 } else { 979 ld->nge_tx_list[i].nge_nextdesc = 980 &ld->nge_tx_list[i + 1]; 981 ld->nge_tx_list[i].nge_next = 982 vtophys(&ld->nge_tx_list[i + 1]); 983 } 984 ld->nge_tx_list[i].nge_mbuf = NULL; 985 ld->nge_tx_list[i].nge_ptr = 0; 986 ld->nge_tx_list[i].nge_ctl = 0; 987 } 988 989 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 990 991 return(0); 992 } 993 994 995 /* 996 * Initialize the RX descriptors and allocate mbufs for them. Note that 997 * we arrange the descriptors in a closed ring, so that the last descriptor 998 * points back to the first. 999 */ 1000 static int 1001 nge_list_rx_init(struct nge_softc *sc) 1002 { 1003 struct nge_list_data *ld; 1004 struct nge_ring_data *cd; 1005 int i; 1006 1007 ld = sc->nge_ldata; 1008 cd = &sc->nge_cdata; 1009 1010 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1011 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1012 return(ENOBUFS); 1013 if (i == (NGE_RX_LIST_CNT - 1)) { 1014 ld->nge_rx_list[i].nge_nextdesc = 1015 &ld->nge_rx_list[0]; 1016 ld->nge_rx_list[i].nge_next = 1017 vtophys(&ld->nge_rx_list[0]); 1018 } else { 1019 ld->nge_rx_list[i].nge_nextdesc = 1020 &ld->nge_rx_list[i + 1]; 1021 ld->nge_rx_list[i].nge_next = 1022 vtophys(&ld->nge_rx_list[i + 1]); 1023 } 1024 } 1025 1026 cd->nge_rx_prod = 0; 1027 1028 return(0); 1029 } 1030 1031 /* 1032 * Initialize an RX descriptor and attach an MBUF cluster. 1033 */ 1034 static int 1035 nge_newbuf(struct nge_softc *sc, struct nge_desc *c, struct mbuf *m) 1036 { 1037 struct mbuf *m_new = NULL; 1038 struct nge_jslot *buf; 1039 1040 if (m == NULL) { 1041 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1042 if (m_new == NULL) { 1043 printf("nge%d: no memory for rx list " 1044 "-- packet dropped!\n", sc->nge_unit); 1045 return(ENOBUFS); 1046 } 1047 1048 /* Allocate the jumbo buffer */ 1049 buf = nge_jalloc(sc); 1050 if (buf == NULL) { 1051 #ifdef NGE_VERBOSE 1052 printf("nge%d: jumbo allocation failed " 1053 "-- packet dropped!\n", sc->nge_unit); 1054 #endif 1055 m_freem(m_new); 1056 return(ENOBUFS); 1057 } 1058 /* Attach the buffer to the mbuf */ 1059 m_new->m_ext.ext_arg = buf; 1060 m_new->m_ext.ext_buf = buf->nge_buf; 1061 m_new->m_ext.ext_free = nge_jfree; 1062 m_new->m_ext.ext_ref = nge_jref; 1063 m_new->m_ext.ext_size = NGE_JUMBO_FRAMELEN; 1064 1065 m_new->m_data = m_new->m_ext.ext_buf; 1066 m_new->m_flags |= M_EXT; 1067 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 1068 } else { 1069 m_new = m; 1070 m_new->m_len = m_new->m_pkthdr.len = NGE_JLEN; 1071 m_new->m_data = m_new->m_ext.ext_buf; 1072 } 1073 1074 m_adj(m_new, sizeof(uint64_t)); 1075 1076 c->nge_mbuf = m_new; 1077 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1078 c->nge_ctl = m_new->m_len; 1079 c->nge_extsts = 0; 1080 1081 return(0); 1082 } 1083 1084 static int 1085 nge_alloc_jumbo_mem(struct nge_softc *sc) 1086 { 1087 caddr_t ptr; 1088 int i; 1089 struct nge_jslot *entry; 1090 1091 /* Grab a big chunk o' storage. */ 1092 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF, 1093 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 1094 1095 if (sc->nge_cdata.nge_jumbo_buf == NULL) { 1096 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit); 1097 return(ENOBUFS); 1098 } 1099 1100 SLIST_INIT(&sc->nge_jfree_listhead); 1101 1102 /* 1103 * Now divide it up into 9K pieces and save the addresses 1104 * in an array. 1105 */ 1106 ptr = sc->nge_cdata.nge_jumbo_buf; 1107 for (i = 0; i < NGE_JSLOTS; i++) { 1108 entry = &sc->nge_cdata.nge_jslots[i]; 1109 entry->nge_sc = sc; 1110 entry->nge_buf = ptr; 1111 entry->nge_inuse = 0; 1112 entry->nge_slot = i; 1113 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jslot_link); 1114 ptr += NGE_JLEN; 1115 } 1116 1117 return(0); 1118 } 1119 1120 1121 /* 1122 * Allocate a jumbo buffer. 1123 */ 1124 static struct nge_jslot * 1125 nge_jalloc(struct nge_softc *sc) 1126 { 1127 struct nge_jslot *entry; 1128 1129 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1130 1131 if (entry == NULL) { 1132 #ifdef NGE_VERBOSE 1133 printf("nge%d: no free jumbo buffers\n", sc->nge_unit); 1134 #endif 1135 return(NULL); 1136 } 1137 1138 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jslot_link); 1139 entry->nge_inuse = 1; 1140 1141 return(entry); 1142 } 1143 1144 /* 1145 * Adjust usage count on a jumbo buffer. In general this doesn't 1146 * get used much because our jumbo buffers don't get passed around 1147 * a lot, but it's implemented for correctness. 1148 */ 1149 static void 1150 nge_jref(void *arg) 1151 { 1152 struct nge_jslot *entry = (struct nge_jslot *)arg; 1153 struct nge_softc *sc = entry->nge_sc; 1154 1155 if (sc == NULL) 1156 panic("nge_jref: can't find softc pointer!"); 1157 1158 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry) 1159 panic("nge_jref: asked to reference buffer " 1160 "that we don't manage!"); 1161 else if (entry->nge_inuse == 0) 1162 panic("nge_jref: buffer already free!"); 1163 else 1164 entry->nge_inuse++; 1165 } 1166 1167 /* 1168 * Release a jumbo buffer. 1169 */ 1170 static void 1171 nge_jfree(void *arg) 1172 { 1173 struct nge_jslot *entry = (struct nge_jslot *)arg; 1174 struct nge_softc *sc = entry->nge_sc; 1175 1176 if (sc == NULL) 1177 panic("nge_jref: can't find softc pointer!"); 1178 1179 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry) 1180 panic("nge_jref: asked to reference buffer " 1181 "that we don't manage!"); 1182 else if (entry->nge_inuse == 0) 1183 panic("nge_jref: buffer already free!"); 1184 else if (--entry->nge_inuse == 0) 1185 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jslot_link); 1186 } 1187 /* 1188 * A frame has been uploaded: pass the resulting mbuf chain up to 1189 * the higher level protocols. 1190 */ 1191 static void 1192 nge_rxeof(struct nge_softc *sc) 1193 { 1194 struct mbuf *m; 1195 struct ifnet *ifp = &sc->arpcom.ac_if; 1196 struct nge_desc *cur_rx; 1197 int i, total_len = 0; 1198 uint32_t rxstat; 1199 1200 i = sc->nge_cdata.nge_rx_prod; 1201 1202 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1203 struct mbuf *m0 = NULL; 1204 uint32_t extsts; 1205 1206 #ifdef DEVICE_POLLING 1207 if (ifp->if_flags & IFF_POLLING) { 1208 if (sc->rxcycles <= 0) 1209 break; 1210 sc->rxcycles--; 1211 } 1212 #endif /* DEVICE_POLLING */ 1213 1214 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1215 rxstat = cur_rx->nge_rxstat; 1216 extsts = cur_rx->nge_extsts; 1217 m = cur_rx->nge_mbuf; 1218 cur_rx->nge_mbuf = NULL; 1219 total_len = NGE_RXBYTES(cur_rx); 1220 NGE_INC(i, NGE_RX_LIST_CNT); 1221 /* 1222 * If an error occurs, update stats, clear the 1223 * status word and leave the mbuf cluster in place: 1224 * it should simply get re-used next time this descriptor 1225 * comes up in the ring. 1226 */ 1227 if ((rxstat & NGE_CMDSTS_PKT_OK) == 0) { 1228 ifp->if_ierrors++; 1229 nge_newbuf(sc, cur_rx, m); 1230 continue; 1231 } 1232 1233 /* 1234 * Ok. NatSemi really screwed up here. This is the 1235 * only gigE chip I know of with alignment constraints 1236 * on receive buffers. RX buffers must be 64-bit aligned. 1237 */ 1238 #ifdef __i386__ 1239 /* 1240 * By popular demand, ignore the alignment problems 1241 * on the Intel x86 platform. The performance hit 1242 * incurred due to unaligned accesses is much smaller 1243 * than the hit produced by forcing buffer copies all 1244 * the time, especially with jumbo frames. We still 1245 * need to fix up the alignment everywhere else though. 1246 */ 1247 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 1248 #endif 1249 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1250 total_len + ETHER_ALIGN, 0, ifp, NULL); 1251 nge_newbuf(sc, cur_rx, m); 1252 if (m0 == NULL) { 1253 printf("nge%d: no receive buffers " 1254 "available -- packet dropped!\n", 1255 sc->nge_unit); 1256 ifp->if_ierrors++; 1257 continue; 1258 } 1259 m_adj(m0, ETHER_ALIGN); 1260 m = m0; 1261 #ifdef __i386__ 1262 } else { 1263 m->m_pkthdr.rcvif = ifp; 1264 m->m_pkthdr.len = m->m_len = total_len; 1265 } 1266 #endif 1267 1268 ifp->if_ipackets++; 1269 1270 /* Do IP checksum checking. */ 1271 if (extsts & NGE_RXEXTSTS_IPPKT) 1272 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1273 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1274 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1275 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1276 (extsts & NGE_RXEXTSTS_TCPCSUMERR) == 0) || 1277 (extsts & NGE_RXEXTSTS_UDPPKT && 1278 (extsts & NGE_RXEXTSTS_UDPCSUMERR) == 0)) { 1279 m->m_pkthdr.csum_flags |= 1280 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1281 m->m_pkthdr.csum_data = 0xffff; 1282 } 1283 1284 /* 1285 * If we received a packet with a vlan tag, pass it 1286 * to vlan_input() instead of ether_input(). 1287 */ 1288 if (extsts & NGE_RXEXTSTS_VLANPKT) 1289 VLAN_INPUT_TAG(m, extsts & NGE_RXEXTSTS_VTCI); 1290 else 1291 (*ifp->if_input)(ifp, m); 1292 } 1293 1294 sc->nge_cdata.nge_rx_prod = i; 1295 } 1296 1297 /* 1298 * A frame was downloaded to the chip. It's safe for us to clean up 1299 * the list buffers. 1300 */ 1301 static void 1302 nge_txeof(struct nge_softc *sc) 1303 { 1304 struct ifnet *ifp = &sc->arpcom.ac_if; 1305 struct nge_desc *cur_tx = NULL; 1306 uint32_t idx; 1307 1308 /* Clear the timeout timer. */ 1309 ifp->if_timer = 0; 1310 1311 /* 1312 * Go through our tx list and free mbufs for those 1313 * frames that have been transmitted. 1314 */ 1315 idx = sc->nge_cdata.nge_tx_cons; 1316 while (idx != sc->nge_cdata.nge_tx_prod) { 1317 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1318 1319 if (NGE_OWNDESC(cur_tx)) 1320 break; 1321 1322 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1323 sc->nge_cdata.nge_tx_cnt--; 1324 NGE_INC(idx, NGE_TX_LIST_CNT); 1325 continue; 1326 } 1327 1328 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1329 ifp->if_oerrors++; 1330 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1331 ifp->if_collisions++; 1332 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1333 ifp->if_collisions++; 1334 } 1335 1336 ifp->if_collisions += 1337 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1338 1339 ifp->if_opackets++; 1340 if (cur_tx->nge_mbuf != NULL) { 1341 m_freem(cur_tx->nge_mbuf); 1342 cur_tx->nge_mbuf = NULL; 1343 } 1344 1345 sc->nge_cdata.nge_tx_cnt--; 1346 NGE_INC(idx, NGE_TX_LIST_CNT); 1347 ifp->if_timer = 0; 1348 } 1349 1350 sc->nge_cdata.nge_tx_cons = idx; 1351 1352 if (cur_tx != NULL) 1353 ifp->if_flags &= ~IFF_OACTIVE; 1354 } 1355 1356 static void 1357 nge_tick(void *xsc) 1358 { 1359 struct nge_softc *sc = xsc; 1360 struct ifnet *ifp = &sc->arpcom.ac_if; 1361 struct mii_data *mii; 1362 1363 crit_enter(); 1364 1365 if (sc->nge_tbi) { 1366 if (sc->nge_link == 0) { 1367 if (CSR_READ_4(sc, NGE_TBI_BMSR) 1368 & NGE_TBIBMSR_ANEG_DONE) { 1369 printf("nge%d: gigabit link up\n", 1370 sc->nge_unit); 1371 nge_miibus_statchg(sc->nge_miibus); 1372 sc->nge_link++; 1373 if (!ifq_is_empty(&ifp->if_snd)) 1374 nge_start(ifp); 1375 } 1376 } 1377 } else { 1378 mii = device_get_softc(sc->nge_miibus); 1379 mii_tick(mii); 1380 1381 if (sc->nge_link == 0) { 1382 if (mii->mii_media_status & IFM_ACTIVE && 1383 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1384 sc->nge_link++; 1385 if (IFM_SUBTYPE(mii->mii_media_active) 1386 == IFM_1000_T) 1387 printf("nge%d: gigabit link up\n", 1388 sc->nge_unit); 1389 if (!ifq_is_empty(&ifp->if_snd)) 1390 nge_start(ifp); 1391 } 1392 } 1393 } 1394 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc); 1395 1396 crit_exit(); 1397 } 1398 1399 #ifdef DEVICE_POLLING 1400 1401 static void 1402 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1403 { 1404 struct nge_softc *sc = ifp->if_softc; 1405 1406 switch(cmd) { 1407 case POLL_REGISTER: 1408 /* disable interrupts */ 1409 CSR_WRITE_4(sc, NGE_IER, 0); 1410 break; 1411 case POLL_DEREGISTER: 1412 /* enable interrupts */ 1413 CSR_WRITE_4(sc, NGE_IER, 1); 1414 break; 1415 default: 1416 /* 1417 * On the nge, reading the status register also clears it. 1418 * So before returning to intr mode we must make sure that all 1419 * possible pending sources of interrupts have been served. 1420 * In practice this means run to completion the *eof routines, 1421 * and then call the interrupt routine 1422 */ 1423 sc->rxcycles = count; 1424 nge_rxeof(sc); 1425 nge_txeof(sc); 1426 if (!ifq_is_empty(&ifp->if_snd)) 1427 nge_start(ifp); 1428 1429 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1430 uint32_t status; 1431 1432 /* Reading the ISR register clears all interrupts. */ 1433 status = CSR_READ_4(sc, NGE_ISR); 1434 1435 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) 1436 nge_rxeof(sc); 1437 1438 if (status & (NGE_ISR_RX_IDLE)) 1439 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1440 1441 if (status & NGE_ISR_SYSERR) { 1442 nge_reset(sc); 1443 nge_init(sc); 1444 } 1445 } 1446 break; 1447 } 1448 } 1449 1450 #endif /* DEVICE_POLLING */ 1451 1452 static void 1453 nge_intr(void *arg) 1454 { 1455 struct nge_softc *sc = arg; 1456 struct ifnet *ifp = &sc->arpcom.ac_if; 1457 uint32_t status; 1458 1459 /* Supress unwanted interrupts */ 1460 if (!(ifp->if_flags & IFF_UP)) { 1461 nge_stop(sc); 1462 return; 1463 } 1464 1465 /* Disable interrupts. */ 1466 CSR_WRITE_4(sc, NGE_IER, 0); 1467 1468 /* Data LED on for TBI mode */ 1469 if(sc->nge_tbi) 1470 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1471 | NGE_GPIO_GP3_OUT); 1472 1473 for (;;) { 1474 /* Reading the ISR register clears all interrupts. */ 1475 status = CSR_READ_4(sc, NGE_ISR); 1476 1477 if ((status & NGE_INTRS) == 0) 1478 break; 1479 1480 if ((status & NGE_ISR_TX_DESC_OK) || 1481 (status & NGE_ISR_TX_ERR) || 1482 (status & NGE_ISR_TX_OK) || 1483 (status & NGE_ISR_TX_IDLE)) 1484 nge_txeof(sc); 1485 1486 if ((status & NGE_ISR_RX_DESC_OK) || 1487 (status & NGE_ISR_RX_ERR) || 1488 (status & NGE_ISR_RX_OFLOW) || 1489 (status & NGE_ISR_RX_FIFO_OFLOW) || 1490 (status & NGE_ISR_RX_IDLE) || 1491 (status & NGE_ISR_RX_OK)) 1492 nge_rxeof(sc); 1493 1494 if ((status & NGE_ISR_RX_IDLE)) 1495 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1496 1497 if (status & NGE_ISR_SYSERR) { 1498 nge_reset(sc); 1499 ifp->if_flags &= ~IFF_RUNNING; 1500 nge_init(sc); 1501 } 1502 1503 #ifdef notyet 1504 /* mii_tick should only be called once per second */ 1505 if (status & NGE_ISR_PHY_INTR) { 1506 sc->nge_link = 0; 1507 nge_tick(sc); 1508 } 1509 #endif 1510 } 1511 1512 /* Re-enable interrupts. */ 1513 CSR_WRITE_4(sc, NGE_IER, 1); 1514 1515 if (!ifq_is_empty(&ifp->if_snd)) 1516 nge_start(ifp); 1517 1518 /* Data LED off for TBI mode */ 1519 1520 if(sc->nge_tbi) 1521 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1522 & ~NGE_GPIO_GP3_OUT); 1523 } 1524 1525 /* 1526 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1527 * pointers to the fragment pointers. 1528 */ 1529 static int 1530 nge_encap(struct nge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1531 { 1532 struct nge_desc *f = NULL; 1533 struct mbuf *m; 1534 int frag, cur, cnt = 0; 1535 struct ifvlan *ifv = NULL; 1536 1537 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1538 m_head->m_pkthdr.rcvif != NULL && 1539 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 1540 ifv = m_head->m_pkthdr.rcvif->if_softc; 1541 1542 /* 1543 * Start packing the mbufs in this chain into 1544 * the fragment pointers. Stop when we run out 1545 * of fragments or hit the end of the mbuf chain. 1546 */ 1547 m = m_head; 1548 cur = frag = *txidx; 1549 1550 for (m = m_head; m != NULL; m = m->m_next) { 1551 if (m->m_len != 0) { 1552 if ((NGE_TX_LIST_CNT - 1553 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1554 return(ENOBUFS); 1555 f = &sc->nge_ldata->nge_tx_list[frag]; 1556 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1557 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1558 if (cnt != 0) 1559 f->nge_ctl |= NGE_CMDSTS_OWN; 1560 cur = frag; 1561 NGE_INC(frag, NGE_TX_LIST_CNT); 1562 cnt++; 1563 } 1564 } 1565 1566 if (m != NULL) 1567 return(ENOBUFS); 1568 1569 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1570 if (m_head->m_pkthdr.csum_flags) { 1571 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1572 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1573 NGE_TXEXTSTS_IPCSUM; 1574 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1575 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1576 NGE_TXEXTSTS_TCPCSUM; 1577 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1578 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1579 NGE_TXEXTSTS_UDPCSUM; 1580 } 1581 1582 if (ifv != NULL) { 1583 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1584 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag); 1585 } 1586 1587 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1588 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1589 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1590 sc->nge_cdata.nge_tx_cnt += cnt; 1591 *txidx = frag; 1592 1593 return(0); 1594 } 1595 1596 /* 1597 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1598 * to the mbuf data regions directly in the transmit lists. We also save a 1599 * copy of the pointers since the transmit list fragment pointers are 1600 * physical addresses. 1601 */ 1602 1603 static void 1604 nge_start(struct ifnet *ifp) 1605 { 1606 struct nge_softc *sc = ifp->if_softc; 1607 struct mbuf *m_head = NULL; 1608 uint32_t idx; 1609 int need_trans; 1610 1611 if (!sc->nge_link) 1612 return; 1613 1614 idx = sc->nge_cdata.nge_tx_prod; 1615 1616 if (ifp->if_flags & IFF_OACTIVE) 1617 return; 1618 1619 need_trans = 0; 1620 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1621 m_head = ifq_poll(&ifp->if_snd); 1622 if (m_head == NULL) 1623 break; 1624 1625 if (nge_encap(sc, m_head, &idx)) { 1626 ifp->if_flags |= IFF_OACTIVE; 1627 break; 1628 } 1629 ifq_dequeue(&ifp->if_snd, m_head); 1630 need_trans = 1; 1631 1632 BPF_MTAP(ifp, m_head); 1633 } 1634 1635 if (!need_trans) 1636 return; 1637 1638 /* Transmit */ 1639 sc->nge_cdata.nge_tx_prod = idx; 1640 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1641 1642 /* 1643 * Set a timeout in case the chip goes out to lunch. 1644 */ 1645 ifp->if_timer = 5; 1646 } 1647 1648 static void 1649 nge_init(void *xsc) 1650 { 1651 struct nge_softc *sc = xsc; 1652 struct ifnet *ifp = &sc->arpcom.ac_if; 1653 struct mii_data *mii; 1654 1655 crit_enter(); 1656 1657 if (ifp->if_flags & IFF_RUNNING) { 1658 crit_exit(); 1659 return; 1660 } 1661 1662 /* 1663 * Cancel pending I/O and free all RX/TX buffers. 1664 */ 1665 nge_stop(sc); 1666 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc); 1667 1668 if (sc->nge_tbi) 1669 mii = NULL; 1670 else 1671 mii = device_get_softc(sc->nge_miibus); 1672 1673 /* Set MAC address */ 1674 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1675 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1676 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1677 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1678 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1679 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1680 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1681 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1682 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1683 1684 /* Init circular RX list. */ 1685 if (nge_list_rx_init(sc) == ENOBUFS) { 1686 printf("nge%d: initialization failed: no " 1687 "memory for rx buffers\n", sc->nge_unit); 1688 nge_stop(sc); 1689 crit_exit(); 1690 return; 1691 } 1692 1693 /* 1694 * Init tx descriptors. 1695 */ 1696 nge_list_tx_init(sc); 1697 1698 /* 1699 * For the NatSemi chip, we have to explicitly enable the 1700 * reception of ARP frames, as well as turn on the 'perfect 1701 * match' filter where we store the station address, otherwise 1702 * we won't receive unicasts meant for this host. 1703 */ 1704 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1705 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1706 1707 /* If we want promiscuous mode, set the allframes bit. */ 1708 if (ifp->if_flags & IFF_PROMISC) 1709 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1710 else 1711 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1712 1713 /* 1714 * Set the capture broadcast bit to capture broadcast frames. 1715 */ 1716 if (ifp->if_flags & IFF_BROADCAST) 1717 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1718 else 1719 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1720 1721 /* 1722 * Load the multicast filter. 1723 */ 1724 nge_setmulti(sc); 1725 1726 /* Turn the receive filter on */ 1727 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1728 1729 /* 1730 * Load the address of the RX and TX lists. 1731 */ 1732 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1733 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1734 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1735 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1736 1737 /* Set RX configuration */ 1738 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1739 /* 1740 * Enable hardware checksum validation for all IPv4 1741 * packets, do not reject packets with bad checksums. 1742 */ 1743 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1744 1745 /* 1746 * Tell the chip to detect and strip VLAN tag info from 1747 * received frames. The tag will be provided in the extsts 1748 * field in the RX descriptors. 1749 */ 1750 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1751 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1752 1753 /* Set TX configuration */ 1754 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1755 1756 /* 1757 * Enable TX IPv4 checksumming on a per-packet basis. 1758 */ 1759 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1760 1761 /* 1762 * Tell the chip to insert VLAN tags on a per-packet basis as 1763 * dictated by the code in the frame encapsulation routine. 1764 */ 1765 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1766 1767 /* Set full/half duplex mode. */ 1768 if (sc->nge_tbi) { 1769 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1770 == IFM_FDX) { 1771 NGE_SETBIT(sc, NGE_TX_CFG, 1772 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 1773 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1774 } else { 1775 NGE_CLRBIT(sc, NGE_TX_CFG, 1776 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 1777 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1778 } 1779 } else { 1780 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1781 NGE_SETBIT(sc, NGE_TX_CFG, 1782 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 1783 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1784 } else { 1785 NGE_CLRBIT(sc, NGE_TX_CFG, 1786 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 1787 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1788 } 1789 } 1790 1791 /* 1792 * Enable the delivery of PHY interrupts based on 1793 * link/speed/duplex status changes. Also enable the 1794 * extsts field in the DMA descriptors (needed for 1795 * TCP/IP checksum offload on transmit). 1796 */ 1797 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD | 1798 NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB); 1799 1800 /* 1801 * Configure interrupt holdoff (moderation). We can 1802 * have the chip delay interrupt delivery for a certain 1803 * period. Units are in 100us, and the max setting 1804 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 1805 */ 1806 CSR_WRITE_4(sc, NGE_IHR, 0x01); 1807 1808 /* 1809 * Enable interrupts. 1810 */ 1811 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1812 #ifdef DEVICE_POLLING 1813 /* 1814 * ... only enable interrupts if we are not polling, make sure 1815 * they are off otherwise. 1816 */ 1817 if (ifp->if_flags & IFF_POLLING) 1818 CSR_WRITE_4(sc, NGE_IER, 0); 1819 else 1820 #endif /* DEVICE_POLLING */ 1821 CSR_WRITE_4(sc, NGE_IER, 1); 1822 1823 /* Enable receiver and transmitter. */ 1824 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE); 1825 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1826 1827 nge_ifmedia_upd(ifp); 1828 1829 ifp->if_flags |= IFF_RUNNING; 1830 ifp->if_flags &= ~IFF_OACTIVE; 1831 1832 crit_exit(); 1833 } 1834 1835 /* 1836 * Set media options. 1837 */ 1838 static int 1839 nge_ifmedia_upd(struct ifnet *ifp) 1840 { 1841 struct nge_softc *sc = ifp->if_softc; 1842 struct mii_data *mii; 1843 1844 if (sc->nge_tbi) { 1845 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1846 == IFM_AUTO) { 1847 CSR_WRITE_4(sc, NGE_TBI_ANAR, 1848 CSR_READ_4(sc, NGE_TBI_ANAR) 1849 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX 1850 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2); 1851 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG 1852 | NGE_TBIBMCR_RESTART_ANEG); 1853 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG); 1854 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media 1855 & IFM_GMASK) == IFM_FDX) { 1856 NGE_SETBIT(sc, NGE_TX_CFG, 1857 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1858 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1859 1860 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 1861 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 1862 } else { 1863 NGE_CLRBIT(sc, NGE_TX_CFG, 1864 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1865 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1866 1867 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 1868 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 1869 } 1870 1871 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1872 & ~NGE_GPIO_GP3_OUT); 1873 } else { 1874 mii = device_get_softc(sc->nge_miibus); 1875 sc->nge_link = 0; 1876 if (mii->mii_instance) { 1877 struct mii_softc *miisc; 1878 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1879 miisc = LIST_NEXT(miisc, mii_list)) 1880 mii_phy_reset(miisc); 1881 } 1882 mii_mediachg(mii); 1883 } 1884 1885 return(0); 1886 } 1887 1888 /* 1889 * Report current media status. 1890 */ 1891 static void 1892 nge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1893 { 1894 struct nge_softc *sc = ifp->if_softc; 1895 struct mii_data *mii; 1896 1897 if (sc->nge_tbi) { 1898 ifmr->ifm_status = IFM_AVALID; 1899 ifmr->ifm_active = IFM_ETHER; 1900 1901 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) 1902 ifmr->ifm_status |= IFM_ACTIVE; 1903 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK) 1904 ifmr->ifm_active |= IFM_LOOP; 1905 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 1906 ifmr->ifm_active |= IFM_NONE; 1907 ifmr->ifm_status = 0; 1908 return; 1909 } 1910 ifmr->ifm_active |= IFM_1000_SX; 1911 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1912 == IFM_AUTO) { 1913 ifmr->ifm_active |= IFM_AUTO; 1914 if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 1915 & NGE_TBIANAR_FDX) { 1916 ifmr->ifm_active |= IFM_FDX; 1917 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 1918 & NGE_TBIANAR_HDX) { 1919 ifmr->ifm_active |= IFM_HDX; 1920 } 1921 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1922 == IFM_FDX) 1923 ifmr->ifm_active |= IFM_FDX; 1924 else 1925 ifmr->ifm_active |= IFM_HDX; 1926 1927 } else { 1928 mii = device_get_softc(sc->nge_miibus); 1929 mii_pollstat(mii); 1930 ifmr->ifm_active = mii->mii_media_active; 1931 ifmr->ifm_status = mii->mii_media_status; 1932 } 1933 } 1934 1935 static int 1936 nge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1937 { 1938 struct nge_softc *sc = ifp->if_softc; 1939 struct ifreq *ifr = (struct ifreq *) data; 1940 struct mii_data *mii; 1941 int error = 0; 1942 1943 crit_enter(); 1944 1945 switch(command) { 1946 case SIOCSIFMTU: 1947 if (ifr->ifr_mtu > NGE_JUMBO_MTU) { 1948 error = EINVAL; 1949 } else { 1950 ifp->if_mtu = ifr->ifr_mtu; 1951 /* 1952 * Workaround: if the MTU is larger than 1953 * 8152 (TX FIFO size minus 64 minus 18), turn off 1954 * TX checksum offloading. 1955 */ 1956 if (ifr->ifr_mtu >= 8152) 1957 ifp->if_hwassist = 0; 1958 else 1959 ifp->if_hwassist = NGE_CSUM_FEATURES; 1960 } 1961 break; 1962 case SIOCSIFFLAGS: 1963 if (ifp->if_flags & IFF_UP) { 1964 if (ifp->if_flags & IFF_RUNNING && 1965 ifp->if_flags & IFF_PROMISC && 1966 !(sc->nge_if_flags & IFF_PROMISC)) { 1967 NGE_SETBIT(sc, NGE_RXFILT_CTL, 1968 NGE_RXFILTCTL_ALLPHYS| 1969 NGE_RXFILTCTL_ALLMULTI); 1970 } else if (ifp->if_flags & IFF_RUNNING && 1971 !(ifp->if_flags & IFF_PROMISC) && 1972 sc->nge_if_flags & IFF_PROMISC) { 1973 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1974 NGE_RXFILTCTL_ALLPHYS); 1975 if (!(ifp->if_flags & IFF_ALLMULTI)) 1976 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1977 NGE_RXFILTCTL_ALLMULTI); 1978 } else { 1979 ifp->if_flags &= ~IFF_RUNNING; 1980 nge_init(sc); 1981 } 1982 } else { 1983 if (ifp->if_flags & IFF_RUNNING) 1984 nge_stop(sc); 1985 } 1986 sc->nge_if_flags = ifp->if_flags; 1987 error = 0; 1988 break; 1989 case SIOCADDMULTI: 1990 case SIOCDELMULTI: 1991 nge_setmulti(sc); 1992 error = 0; 1993 break; 1994 case SIOCGIFMEDIA: 1995 case SIOCSIFMEDIA: 1996 if (sc->nge_tbi) { 1997 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, 1998 command); 1999 } else { 2000 mii = device_get_softc(sc->nge_miibus); 2001 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2002 command); 2003 } 2004 break; 2005 default: 2006 error = ether_ioctl(ifp, command, data); 2007 break; 2008 } 2009 2010 crit_exit(); 2011 2012 return(error); 2013 } 2014 2015 static void 2016 nge_watchdog(struct ifnet *ifp) 2017 { 2018 struct nge_softc *sc = ifp->if_softc; 2019 2020 ifp->if_oerrors++; 2021 printf("nge%d: watchdog timeout\n", sc->nge_unit); 2022 2023 nge_stop(sc); 2024 nge_reset(sc); 2025 ifp->if_flags &= ~IFF_RUNNING; 2026 nge_init(sc); 2027 2028 if (!ifq_is_empty(&ifp->if_snd)) 2029 nge_start(ifp); 2030 } 2031 2032 /* 2033 * Stop the adapter and free any mbufs allocated to the 2034 * RX and TX lists. 2035 */ 2036 static void 2037 nge_stop(struct nge_softc *sc) 2038 { 2039 struct ifnet *ifp = &sc->arpcom.ac_if; 2040 struct ifmedia_entry *ifm; 2041 struct mii_data *mii; 2042 int i, itmp, mtmp; 2043 2044 ifp->if_timer = 0; 2045 if (sc->nge_tbi) 2046 mii = NULL; 2047 else 2048 mii = device_get_softc(sc->nge_miibus); 2049 2050 callout_stop(&sc->nge_stat_timer); 2051 CSR_WRITE_4(sc, NGE_IER, 0); 2052 CSR_WRITE_4(sc, NGE_IMR, 0); 2053 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2054 DELAY(1000); 2055 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 2056 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 2057 2058 /* 2059 * Isolate/power down the PHY, but leave the media selection 2060 * unchanged so that things will be put back to normal when 2061 * we bring the interface back up. 2062 */ 2063 itmp = ifp->if_flags; 2064 ifp->if_flags |= IFF_UP; 2065 2066 if (sc->nge_tbi) 2067 ifm = sc->nge_ifmedia.ifm_cur; 2068 else 2069 ifm = mii->mii_media.ifm_cur; 2070 2071 mtmp = ifm->ifm_media; 2072 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2073 2074 if (!sc->nge_tbi) 2075 mii_mediachg(mii); 2076 ifm->ifm_media = mtmp; 2077 ifp->if_flags = itmp; 2078 2079 sc->nge_link = 0; 2080 2081 /* 2082 * Free data in the RX lists. 2083 */ 2084 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2085 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2086 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2087 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2088 } 2089 } 2090 bzero(&sc->nge_ldata->nge_rx_list, 2091 sizeof(sc->nge_ldata->nge_rx_list)); 2092 2093 /* 2094 * Free the TX list buffers. 2095 */ 2096 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2097 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2098 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2099 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2100 } 2101 } 2102 2103 bzero(&sc->nge_ldata->nge_tx_list, 2104 sizeof(sc->nge_ldata->nge_tx_list)); 2105 2106 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2107 } 2108 2109 /* 2110 * Stop all chip I/O so that the kernel's probe routines don't 2111 * get confused by errant DMAs when rebooting. 2112 */ 2113 static void 2114 nge_shutdown(device_t dev) 2115 { 2116 struct nge_softc *sc = device_get_softc(dev); 2117 2118 nge_reset(sc); 2119 nge_stop(sc); 2120 } 2121