1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $ 34 * $DragonFly: src/sys/dev/netif/nge/if_nge.c,v 1.38 2006/08/01 18:05:43 swildner Exp $ 35 */ 36 37 /* 38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 39 * for FreeBSD. Datasheets are available from: 40 * 41 * http://www.national.com/ds/DP/DP83820.pdf 42 * http://www.national.com/ds/DP/DP83821.pdf 43 * 44 * These chips are used on several low cost gigabit ethernet NICs 45 * sold by D-Link, Addtron, SMC and Asante. Both parts are 46 * virtually the same, except the 83820 is a 64-bit/32-bit part, 47 * while the 83821 is 32-bit only. 48 * 49 * Many cards also use National gigE transceivers, such as the 50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 51 * contains a full register description that applies to all of these 52 * components: 53 * 54 * http://www.national.com/ds/DP/DP83861.pdf 55 * 56 * Written by Bill Paul <wpaul@bsdi.com> 57 * BSDi Open Source Solutions 58 */ 59 60 /* 61 * The NatSemi DP83820 and 83821 controllers are enhanced versions 62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 67 * matching buffers, one perfect address filter buffer and interrupt 68 * moderation. The 83820 supports both 64-bit and 32-bit addressing 69 * and data transfers: the 64-bit support can be toggled on or off 70 * via software. This affects the size of certain fields in the DMA 71 * descriptors. 72 * 73 * There are two bugs/misfeatures in the 83820/83821 that I have 74 * discovered so far: 75 * 76 * - Receive buffers must be aligned on 64-bit boundaries, which means 77 * you must resort to copying data in order to fix up the payload 78 * alignment. 79 * 80 * - In order to transmit jumbo frames larger than 8170 bytes, you have 81 * to turn off transmit checksum offloading, because the chip can't 82 * compute the checksum on an outgoing frame unless it fits entirely 83 * within the TX FIFO, which is only 8192 bytes in size. If you have 84 * TX checksum offload enabled and you transmit attempt to transmit a 85 * frame larger than 8170 bytes, the transmitter will wedge. 86 * 87 * To work around the latter problem, TX checksum offload is disabled 88 * if the user selects an MTU larger than 8152 (8170 - 18). 89 */ 90 91 #include "opt_polling.h" 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/sockio.h> 96 #include <sys/mbuf.h> 97 #include <sys/malloc.h> 98 #include <sys/kernel.h> 99 #include <sys/socket.h> 100 #include <sys/serialize.h> 101 102 #include <sys/thread2.h> 103 104 #include <net/if.h> 105 #include <net/ifq_var.h> 106 #include <net/if_arp.h> 107 #include <net/ethernet.h> 108 #include <net/if_dl.h> 109 #include <net/if_media.h> 110 #include <net/if_types.h> 111 #include <net/vlan/if_vlan_var.h> 112 113 #include <net/bpf.h> 114 115 #include <vm/vm.h> /* for vtophys */ 116 #include <vm/pmap.h> /* for vtophys */ 117 #include <machine/bus.h> 118 #include <machine/resource.h> 119 #include <sys/bus.h> 120 #include <sys/rman.h> 121 122 #include <dev/netif/mii_layer/mii.h> 123 #include <dev/netif/mii_layer/miivar.h> 124 125 #include <bus/pci/pcidevs.h> 126 #include <bus/pci/pcireg.h> 127 #include <bus/pci/pcivar.h> 128 129 #define NGE_USEIOSPACE 130 131 #include "if_ngereg.h" 132 133 134 /* "controller miibus0" required. See GENERIC if you get errors here. */ 135 #include "miibus_if.h" 136 137 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 138 139 /* 140 * Various supported device vendors/types and their names. 141 */ 142 static struct nge_type nge_devs[] = { 143 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 144 "National Semiconductor Gigabit Ethernet" }, 145 { 0, 0, NULL } 146 }; 147 148 static int nge_probe(device_t); 149 static int nge_attach(device_t); 150 static int nge_detach(device_t); 151 152 static int nge_alloc_jumbo_mem(struct nge_softc *); 153 static struct nge_jslot 154 *nge_jalloc(struct nge_softc *); 155 static void nge_jfree(void *); 156 static void nge_jref(void *); 157 158 static int nge_newbuf(struct nge_softc *, struct nge_desc *, 159 struct mbuf *); 160 static int nge_encap(struct nge_softc *, struct mbuf *, uint32_t *); 161 static void nge_rxeof(struct nge_softc *); 162 static void nge_txeof(struct nge_softc *); 163 static void nge_intr(void *); 164 static void nge_tick(void *); 165 static void nge_start(struct ifnet *); 166 static int nge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 167 static void nge_init(void *); 168 static void nge_stop(struct nge_softc *); 169 static void nge_watchdog(struct ifnet *); 170 static void nge_shutdown(device_t); 171 static int nge_ifmedia_upd(struct ifnet *); 172 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 173 174 static void nge_delay(struct nge_softc *); 175 static void nge_eeprom_idle(struct nge_softc *); 176 static void nge_eeprom_putbyte(struct nge_softc *, int); 177 static void nge_eeprom_getword(struct nge_softc *, int, uint16_t *); 178 static void nge_read_eeprom(struct nge_softc *, void *, int, int); 179 180 static void nge_mii_sync(struct nge_softc *); 181 static void nge_mii_send(struct nge_softc *, uint32_t, int); 182 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *); 183 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *); 184 185 static int nge_miibus_readreg(device_t, int, int); 186 static int nge_miibus_writereg(device_t, int, int, int); 187 static void nge_miibus_statchg(device_t); 188 189 static void nge_setmulti(struct nge_softc *); 190 static void nge_reset(struct nge_softc *); 191 static int nge_list_rx_init(struct nge_softc *); 192 static int nge_list_tx_init(struct nge_softc *); 193 #ifdef DEVICE_POLLING 194 static void nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 195 #endif 196 197 #ifdef NGE_USEIOSPACE 198 #define NGE_RES SYS_RES_IOPORT 199 #define NGE_RID NGE_PCI_LOIO 200 #else 201 #define NGE_RES SYS_RES_MEMORY 202 #define NGE_RID NGE_PCI_LOMEM 203 #endif 204 205 static device_method_t nge_methods[] = { 206 /* Device interface */ 207 DEVMETHOD(device_probe, nge_probe), 208 DEVMETHOD(device_attach, nge_attach), 209 DEVMETHOD(device_detach, nge_detach), 210 DEVMETHOD(device_shutdown, nge_shutdown), 211 212 /* bus interface */ 213 DEVMETHOD(bus_print_child, bus_generic_print_child), 214 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 215 216 /* MII interface */ 217 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 218 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 219 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 220 221 { 0, 0 } 222 }; 223 224 static DEFINE_CLASS_0(nge, nge_driver, nge_methods, sizeof(struct nge_softc)); 225 static devclass_t nge_devclass; 226 227 DECLARE_DUMMY_MODULE(if_nge); 228 MODULE_DEPEND(if_nge, miibus, 1, 1, 1); 229 DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0); 230 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 231 232 #define NGE_SETBIT(sc, reg, x) \ 233 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 234 235 #define NGE_CLRBIT(sc, reg, x) \ 236 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 237 238 #define SIO_SET(x) \ 239 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) 240 241 #define SIO_CLR(x) \ 242 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) 243 244 static void 245 nge_delay(struct nge_softc *sc) 246 { 247 int idx; 248 249 for (idx = (300 / 33) + 1; idx > 0; idx--) 250 CSR_READ_4(sc, NGE_CSR); 251 } 252 253 static void 254 nge_eeprom_idle(struct nge_softc *sc) 255 { 256 int i; 257 258 SIO_SET(NGE_MEAR_EE_CSEL); 259 nge_delay(sc); 260 SIO_SET(NGE_MEAR_EE_CLK); 261 nge_delay(sc); 262 263 for (i = 0; i < 25; i++) { 264 SIO_CLR(NGE_MEAR_EE_CLK); 265 nge_delay(sc); 266 SIO_SET(NGE_MEAR_EE_CLK); 267 nge_delay(sc); 268 } 269 270 SIO_CLR(NGE_MEAR_EE_CLK); 271 nge_delay(sc); 272 SIO_CLR(NGE_MEAR_EE_CSEL); 273 nge_delay(sc); 274 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 275 } 276 277 /* 278 * Send a read command and address to the EEPROM, check for ACK. 279 */ 280 static void 281 nge_eeprom_putbyte(struct nge_softc *sc, int addr) 282 { 283 int d, i; 284 285 d = addr | NGE_EECMD_READ; 286 287 /* 288 * Feed in each bit and stobe the clock. 289 */ 290 for (i = 0x400; i; i >>= 1) { 291 if (d & i) 292 SIO_SET(NGE_MEAR_EE_DIN); 293 else 294 SIO_CLR(NGE_MEAR_EE_DIN); 295 nge_delay(sc); 296 SIO_SET(NGE_MEAR_EE_CLK); 297 nge_delay(sc); 298 SIO_CLR(NGE_MEAR_EE_CLK); 299 nge_delay(sc); 300 } 301 } 302 303 /* 304 * Read a word of data stored in the EEPROM at address 'addr.' 305 */ 306 static void 307 nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest) 308 { 309 int i; 310 uint16_t word = 0; 311 312 /* Force EEPROM to idle state. */ 313 nge_eeprom_idle(sc); 314 315 /* Enter EEPROM access mode. */ 316 nge_delay(sc); 317 SIO_CLR(NGE_MEAR_EE_CLK); 318 nge_delay(sc); 319 SIO_SET(NGE_MEAR_EE_CSEL); 320 nge_delay(sc); 321 322 /* 323 * Send address of word we want to read. 324 */ 325 nge_eeprom_putbyte(sc, addr); 326 327 /* 328 * Start reading bits from EEPROM. 329 */ 330 for (i = 0x8000; i; i >>= 1) { 331 SIO_SET(NGE_MEAR_EE_CLK); 332 nge_delay(sc); 333 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 334 word |= i; 335 nge_delay(sc); 336 SIO_CLR(NGE_MEAR_EE_CLK); 337 nge_delay(sc); 338 } 339 340 /* Turn off EEPROM access mode. */ 341 nge_eeprom_idle(sc); 342 343 *dest = word; 344 } 345 346 /* 347 * Read a sequence of words from the EEPROM. 348 */ 349 static void 350 nge_read_eeprom(struct nge_softc *sc, void *dest, int off, int cnt) 351 { 352 int i; 353 uint16_t word = 0, *ptr; 354 355 for (i = 0; i < cnt; i++) { 356 nge_eeprom_getword(sc, off + i, &word); 357 ptr = (uint16_t *)((uint8_t *)dest + (i * 2)); 358 *ptr = word; 359 } 360 } 361 362 /* 363 * Sync the PHYs by setting data bit and strobing the clock 32 times. 364 */ 365 static void 366 nge_mii_sync(struct nge_softc *sc) 367 { 368 int i; 369 370 SIO_SET(NGE_MEAR_MII_DIR | NGE_MEAR_MII_DATA); 371 372 for (i = 0; i < 32; i++) { 373 SIO_SET(NGE_MEAR_MII_CLK); 374 DELAY(1); 375 SIO_CLR(NGE_MEAR_MII_CLK); 376 DELAY(1); 377 } 378 } 379 380 /* 381 * Clock a series of bits through the MII. 382 */ 383 static void 384 nge_mii_send(struct nge_softc *sc, uint32_t bits, int cnt) 385 { 386 int i; 387 388 SIO_CLR(NGE_MEAR_MII_CLK); 389 390 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 391 if (bits & i) 392 SIO_SET(NGE_MEAR_MII_DATA); 393 else 394 SIO_CLR(NGE_MEAR_MII_DATA); 395 DELAY(1); 396 SIO_CLR(NGE_MEAR_MII_CLK); 397 DELAY(1); 398 SIO_SET(NGE_MEAR_MII_CLK); 399 } 400 } 401 402 /* 403 * Read an PHY register through the MII. 404 */ 405 static int 406 nge_mii_readreg(struct nge_softc *sc, struct nge_mii_frame *frame) 407 { 408 int ack, i; 409 410 /* 411 * Set up frame for RX. 412 */ 413 frame->mii_stdelim = NGE_MII_STARTDELIM; 414 frame->mii_opcode = NGE_MII_READOP; 415 frame->mii_turnaround = 0; 416 frame->mii_data = 0; 417 418 CSR_WRITE_4(sc, NGE_MEAR, 0); 419 420 /* 421 * Turn on data xmit. 422 */ 423 SIO_SET(NGE_MEAR_MII_DIR); 424 425 nge_mii_sync(sc); 426 427 /* 428 * Send command/address info. 429 */ 430 nge_mii_send(sc, frame->mii_stdelim, 2); 431 nge_mii_send(sc, frame->mii_opcode, 2); 432 nge_mii_send(sc, frame->mii_phyaddr, 5); 433 nge_mii_send(sc, frame->mii_regaddr, 5); 434 435 /* Idle bit */ 436 SIO_CLR((NGE_MEAR_MII_CLK | NGE_MEAR_MII_DATA)); 437 DELAY(1); 438 SIO_SET(NGE_MEAR_MII_CLK); 439 DELAY(1); 440 441 /* Turn off xmit. */ 442 SIO_CLR(NGE_MEAR_MII_DIR); 443 /* Check for ack */ 444 SIO_CLR(NGE_MEAR_MII_CLK); 445 DELAY(1); 446 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 447 SIO_SET(NGE_MEAR_MII_CLK); 448 DELAY(1); 449 450 /* 451 * Now try reading data bits. If the ack failed, we still 452 * need to clock through 16 cycles to keep the PHY(s) in sync. 453 */ 454 if (ack) { 455 for(i = 0; i < 16; i++) { 456 SIO_CLR(NGE_MEAR_MII_CLK); 457 DELAY(1); 458 SIO_SET(NGE_MEAR_MII_CLK); 459 DELAY(1); 460 } 461 goto fail; 462 } 463 464 for (i = 0x8000; i; i >>= 1) { 465 SIO_CLR(NGE_MEAR_MII_CLK); 466 DELAY(1); 467 if (!ack) { 468 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 469 frame->mii_data |= i; 470 DELAY(1); 471 } 472 SIO_SET(NGE_MEAR_MII_CLK); 473 DELAY(1); 474 } 475 476 fail: 477 SIO_CLR(NGE_MEAR_MII_CLK); 478 DELAY(1); 479 SIO_SET(NGE_MEAR_MII_CLK); 480 DELAY(1); 481 482 if (ack) 483 return(1); 484 return(0); 485 } 486 487 /* 488 * Write to a PHY register through the MII. 489 */ 490 static int 491 nge_mii_writereg(struct nge_softc *sc, struct nge_mii_frame *frame) 492 { 493 /* 494 * Set up frame for TX. 495 */ 496 497 frame->mii_stdelim = NGE_MII_STARTDELIM; 498 frame->mii_opcode = NGE_MII_WRITEOP; 499 frame->mii_turnaround = NGE_MII_TURNAROUND; 500 501 /* 502 * Turn on data output. 503 */ 504 SIO_SET(NGE_MEAR_MII_DIR); 505 506 nge_mii_sync(sc); 507 508 nge_mii_send(sc, frame->mii_stdelim, 2); 509 nge_mii_send(sc, frame->mii_opcode, 2); 510 nge_mii_send(sc, frame->mii_phyaddr, 5); 511 nge_mii_send(sc, frame->mii_regaddr, 5); 512 nge_mii_send(sc, frame->mii_turnaround, 2); 513 nge_mii_send(sc, frame->mii_data, 16); 514 515 /* Idle bit. */ 516 SIO_SET(NGE_MEAR_MII_CLK); 517 DELAY(1); 518 SIO_CLR(NGE_MEAR_MII_CLK); 519 DELAY(1); 520 521 /* 522 * Turn off xmit. 523 */ 524 SIO_CLR(NGE_MEAR_MII_DIR); 525 526 return(0); 527 } 528 529 static int 530 nge_miibus_readreg(device_t dev, int phy, int reg) 531 { 532 struct nge_softc *sc = device_get_softc(dev); 533 struct nge_mii_frame frame; 534 535 bzero((char *)&frame, sizeof(frame)); 536 537 frame.mii_phyaddr = phy; 538 frame.mii_regaddr = reg; 539 nge_mii_readreg(sc, &frame); 540 541 return(frame.mii_data); 542 } 543 544 static int 545 nge_miibus_writereg(device_t dev, int phy, int reg, int data) 546 { 547 struct nge_softc *sc = device_get_softc(dev); 548 struct nge_mii_frame frame; 549 550 bzero((char *)&frame, sizeof(frame)); 551 552 frame.mii_phyaddr = phy; 553 frame.mii_regaddr = reg; 554 frame.mii_data = data; 555 nge_mii_writereg(sc, &frame); 556 557 return(0); 558 } 559 560 static void 561 nge_miibus_statchg(device_t dev) 562 { 563 struct nge_softc *sc = device_get_softc(dev); 564 struct mii_data *mii; 565 int status; 566 567 if (sc->nge_tbi) { 568 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 569 == IFM_AUTO) { 570 status = CSR_READ_4(sc, NGE_TBI_ANLPAR); 571 if (status == 0 || status & NGE_TBIANAR_FDX) { 572 NGE_SETBIT(sc, NGE_TX_CFG, 573 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 574 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 575 } else { 576 NGE_CLRBIT(sc, NGE_TX_CFG, 577 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 578 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 579 } 580 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 581 != IFM_FDX) { 582 NGE_CLRBIT(sc, NGE_TX_CFG, 583 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 584 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 585 } else { 586 NGE_SETBIT(sc, NGE_TX_CFG, 587 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 588 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 589 } 590 } else { 591 mii = device_get_softc(sc->nge_miibus); 592 593 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 594 NGE_SETBIT(sc, NGE_TX_CFG, 595 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 596 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 597 } else { 598 NGE_CLRBIT(sc, NGE_TX_CFG, 599 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 600 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 601 } 602 603 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 604 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 605 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 606 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 607 } else { 608 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 609 } 610 } 611 } 612 613 static void 614 nge_setmulti(struct nge_softc *sc) 615 { 616 struct ifnet *ifp = &sc->arpcom.ac_if; 617 struct ifmultiaddr *ifma; 618 uint32_t filtsave, h = 0, i; 619 int bit, index; 620 621 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 622 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 623 NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH); 624 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 625 return; 626 } 627 628 /* 629 * We have to explicitly enable the multicast hash table 630 * on the NatSemi chip if we want to use it, which we do. 631 * We also have to tell it that we don't want to use the 632 * hash table for matching unicast addresses. 633 */ 634 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 635 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 636 NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_UCHASH); 637 638 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 639 640 /* first, zot all the existing hash bits */ 641 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 642 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 643 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 644 } 645 646 /* 647 * From the 11 bits returned by the crc routine, the top 7 648 * bits represent the 16-bit word in the mcast hash table 649 * that needs to be updated, and the lower 4 bits represent 650 * which bit within that byte needs to be set. 651 */ 652 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 653 if (ifma->ifma_addr->sa_family != AF_LINK) 654 continue; 655 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 656 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21; 657 index = (h >> 4) & 0x7F; 658 bit = h & 0xF; 659 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 660 NGE_FILTADDR_MCAST_LO + (index * 2)); 661 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 662 } 663 664 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 665 } 666 667 static void 668 nge_reset(struct nge_softc *sc) 669 { 670 int i; 671 672 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 673 674 for (i = 0; i < NGE_TIMEOUT; i++) { 675 if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET) == 0) 676 break; 677 } 678 679 if (i == NGE_TIMEOUT) 680 printf("nge%d: reset never completed\n", sc->nge_unit); 681 682 /* Wait a little while for the chip to get its brains in order. */ 683 DELAY(1000); 684 685 /* 686 * If this is a NetSemi chip, make sure to clear 687 * PME mode. 688 */ 689 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 690 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 691 } 692 693 /* 694 * Probe for an NatSemi chip. Check the PCI vendor and device 695 * IDs against our list and return a device name if we find a match. 696 */ 697 static int 698 nge_probe(device_t dev) 699 { 700 struct nge_type *t; 701 uint16_t vendor, product; 702 703 vendor = pci_get_vendor(dev); 704 product = pci_get_device(dev); 705 706 for (t = nge_devs; t->nge_name != NULL; t++) { 707 if (vendor == t->nge_vid && product == t->nge_did) { 708 device_set_desc(dev, t->nge_name); 709 return(0); 710 } 711 } 712 713 return(ENXIO); 714 } 715 716 /* 717 * Attach the interface. Allocate softc structures, do ifmedia 718 * setup and ethernet/BPF attach. 719 */ 720 static int 721 nge_attach(device_t dev) 722 { 723 struct nge_softc *sc; 724 struct ifnet *ifp; 725 uint8_t eaddr[ETHER_ADDR_LEN]; 726 uint32_t command; 727 int error = 0, rid, unit; 728 const char *sep = ""; 729 730 sc = device_get_softc(dev); 731 unit = device_get_unit(dev); 732 callout_init(&sc->nge_stat_timer); 733 lwkt_serialize_init(&sc->nge_jslot_serializer); 734 735 /* 736 * Handle power management nonsense. 737 */ 738 command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF; 739 if (command == 0x01) { 740 command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4); 741 if (command & NGE_PSTATE_MASK) { 742 uint32_t iobase, membase, irq; 743 744 /* Save important PCI config data. */ 745 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4); 746 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4); 747 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4); 748 749 /* Reset the power state. */ 750 printf("nge%d: chip is in D%d power mode " 751 "-- setting to D0\n", unit, command & NGE_PSTATE_MASK); 752 command &= 0xFFFFFFFC; 753 pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4); 754 755 /* Restore PCI config data. */ 756 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4); 757 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4); 758 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4); 759 } 760 } 761 762 /* 763 * Map control/status registers. 764 */ 765 command = pci_read_config(dev, PCIR_COMMAND, 4); 766 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 767 pci_write_config(dev, PCIR_COMMAND, command, 4); 768 command = pci_read_config(dev, PCIR_COMMAND, 4); 769 770 #ifdef NGE_USEIOSPACE 771 if (!(command & PCIM_CMD_PORTEN)) { 772 printf("nge%d: failed to enable I/O ports!\n", unit); 773 error = ENXIO; 774 return(error); 775 } 776 #else 777 if (!(command & PCIM_CMD_MEMEN)) { 778 printf("nge%d: failed to enable memory mapping!\n", unit); 779 error = ENXIO; 780 return(error); 781 } 782 #endif 783 784 rid = NGE_RID; 785 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE); 786 787 if (sc->nge_res == NULL) { 788 printf("nge%d: couldn't map ports/memory\n", unit); 789 error = ENXIO; 790 return(error); 791 } 792 793 sc->nge_btag = rman_get_bustag(sc->nge_res); 794 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 795 796 /* Allocate interrupt */ 797 rid = 0; 798 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 799 RF_SHAREABLE | RF_ACTIVE); 800 801 if (sc->nge_irq == NULL) { 802 printf("nge%d: couldn't map interrupt\n", unit); 803 error = ENXIO; 804 goto fail; 805 } 806 807 /* Reset the adapter. */ 808 nge_reset(sc); 809 810 /* 811 * Get station address from the EEPROM. 812 */ 813 nge_read_eeprom(sc, &eaddr[4], NGE_EE_NODEADDR, 1); 814 nge_read_eeprom(sc, &eaddr[2], NGE_EE_NODEADDR + 1, 1); 815 nge_read_eeprom(sc, &eaddr[0], NGE_EE_NODEADDR + 2, 1); 816 817 sc->nge_unit = unit; 818 819 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 820 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 821 822 if (sc->nge_ldata == NULL) { 823 printf("nge%d: no memory for list buffers!\n", unit); 824 error = ENXIO; 825 goto fail; 826 } 827 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 828 829 /* Try to allocate memory for jumbo buffers. */ 830 if (nge_alloc_jumbo_mem(sc)) { 831 printf("nge%d: jumbo buffer allocation failed\n", 832 sc->nge_unit); 833 error = ENXIO; 834 goto fail; 835 } 836 837 ifp = &sc->arpcom.ac_if; 838 ifp->if_softc = sc; 839 if_initname(ifp, "nge", unit); 840 ifp->if_mtu = ETHERMTU; 841 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 842 ifp->if_ioctl = nge_ioctl; 843 ifp->if_start = nge_start; 844 #ifdef DEVICE_POLLING 845 ifp->if_poll = nge_poll; 846 #endif 847 ifp->if_watchdog = nge_watchdog; 848 ifp->if_init = nge_init; 849 ifp->if_baudrate = 1000000000; 850 ifq_set_maxlen(&ifp->if_snd, NGE_TX_LIST_CNT - 1); 851 ifq_set_ready(&ifp->if_snd); 852 ifp->if_hwassist = NGE_CSUM_FEATURES; 853 ifp->if_capabilities = IFCAP_HWCSUM; 854 ifp->if_capenable = ifp->if_capabilities; 855 856 /* 857 * Do MII setup. 858 */ 859 if (mii_phy_probe(dev, &sc->nge_miibus, 860 nge_ifmedia_upd, nge_ifmedia_sts)) { 861 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) { 862 sc->nge_tbi = 1; 863 device_printf(dev, "Using TBI\n"); 864 865 sc->nge_miibus = dev; 866 867 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd, 868 nge_ifmedia_sts); 869 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL) 870 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 871 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0); 872 device_printf(dev, " "); 873 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0); 874 PRINT("1000baseSX"); 875 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0); 876 PRINT("1000baseSX-FDX"); 877 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0); 878 PRINT("auto"); 879 880 printf("\n"); 881 #undef ADD 882 #undef PRINT 883 ifmedia_set(&sc->nge_ifmedia, 884 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0)); 885 886 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 887 | NGE_GPIO_GP4_OUT 888 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 889 | NGE_GPIO_GP3_OUTENB 890 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 891 892 } else { 893 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 894 error = ENXIO; 895 goto fail; 896 } 897 } 898 899 /* 900 * Call MI attach routine. 901 */ 902 ether_ifattach(ifp, eaddr, NULL); 903 904 error = bus_setup_intr(dev, sc->nge_irq, INTR_NETSAFE, 905 nge_intr, sc, &sc->nge_intrhand, 906 ifp->if_serializer); 907 if (error) { 908 ether_ifdetach(ifp); 909 device_printf(dev, "couldn't set up irq\n"); 910 goto fail; 911 } 912 913 return(0); 914 fail: 915 nge_detach(dev); 916 return(error); 917 } 918 919 static int 920 nge_detach(device_t dev) 921 { 922 struct nge_softc *sc = device_get_softc(dev); 923 struct ifnet *ifp = &sc->arpcom.ac_if; 924 925 if (device_is_attached(dev)) { 926 lwkt_serialize_enter(ifp->if_serializer); 927 nge_reset(sc); 928 nge_stop(sc); 929 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 930 lwkt_serialize_exit(ifp->if_serializer); 931 932 ether_ifdetach(ifp); 933 } 934 935 if (sc->nge_miibus) 936 device_delete_child(dev, sc->nge_miibus); 937 bus_generic_detach(dev); 938 939 if (sc->nge_irq) 940 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 941 if (sc->nge_res) 942 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 943 if (sc->nge_ldata) { 944 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), 945 M_DEVBUF); 946 } 947 if (sc->nge_cdata.nge_jumbo_buf) 948 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF); 949 950 return(0); 951 } 952 953 /* 954 * Initialize the transmit descriptors. 955 */ 956 static int 957 nge_list_tx_init(struct nge_softc *sc) 958 { 959 struct nge_list_data *ld; 960 struct nge_ring_data *cd; 961 int i; 962 963 cd = &sc->nge_cdata; 964 ld = sc->nge_ldata; 965 966 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 967 if (i == (NGE_TX_LIST_CNT - 1)) { 968 ld->nge_tx_list[i].nge_nextdesc = 969 &ld->nge_tx_list[0]; 970 ld->nge_tx_list[i].nge_next = 971 vtophys(&ld->nge_tx_list[0]); 972 } else { 973 ld->nge_tx_list[i].nge_nextdesc = 974 &ld->nge_tx_list[i + 1]; 975 ld->nge_tx_list[i].nge_next = 976 vtophys(&ld->nge_tx_list[i + 1]); 977 } 978 ld->nge_tx_list[i].nge_mbuf = NULL; 979 ld->nge_tx_list[i].nge_ptr = 0; 980 ld->nge_tx_list[i].nge_ctl = 0; 981 } 982 983 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 984 985 return(0); 986 } 987 988 989 /* 990 * Initialize the RX descriptors and allocate mbufs for them. Note that 991 * we arrange the descriptors in a closed ring, so that the last descriptor 992 * points back to the first. 993 */ 994 static int 995 nge_list_rx_init(struct nge_softc *sc) 996 { 997 struct nge_list_data *ld; 998 struct nge_ring_data *cd; 999 int i; 1000 1001 ld = sc->nge_ldata; 1002 cd = &sc->nge_cdata; 1003 1004 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1005 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1006 return(ENOBUFS); 1007 if (i == (NGE_RX_LIST_CNT - 1)) { 1008 ld->nge_rx_list[i].nge_nextdesc = 1009 &ld->nge_rx_list[0]; 1010 ld->nge_rx_list[i].nge_next = 1011 vtophys(&ld->nge_rx_list[0]); 1012 } else { 1013 ld->nge_rx_list[i].nge_nextdesc = 1014 &ld->nge_rx_list[i + 1]; 1015 ld->nge_rx_list[i].nge_next = 1016 vtophys(&ld->nge_rx_list[i + 1]); 1017 } 1018 } 1019 1020 cd->nge_rx_prod = 0; 1021 1022 return(0); 1023 } 1024 1025 /* 1026 * Initialize an RX descriptor and attach an MBUF cluster. 1027 */ 1028 static int 1029 nge_newbuf(struct nge_softc *sc, struct nge_desc *c, struct mbuf *m) 1030 { 1031 struct mbuf *m_new = NULL; 1032 struct nge_jslot *buf; 1033 1034 if (m == NULL) { 1035 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1036 if (m_new == NULL) { 1037 printf("nge%d: no memory for rx list " 1038 "-- packet dropped!\n", sc->nge_unit); 1039 return(ENOBUFS); 1040 } 1041 1042 /* Allocate the jumbo buffer */ 1043 buf = nge_jalloc(sc); 1044 if (buf == NULL) { 1045 #ifdef NGE_VERBOSE 1046 printf("nge%d: jumbo allocation failed " 1047 "-- packet dropped!\n", sc->nge_unit); 1048 #endif 1049 m_freem(m_new); 1050 return(ENOBUFS); 1051 } 1052 /* Attach the buffer to the mbuf */ 1053 m_new->m_ext.ext_arg = buf; 1054 m_new->m_ext.ext_buf = buf->nge_buf; 1055 m_new->m_ext.ext_free = nge_jfree; 1056 m_new->m_ext.ext_ref = nge_jref; 1057 m_new->m_ext.ext_size = NGE_JUMBO_FRAMELEN; 1058 1059 m_new->m_data = m_new->m_ext.ext_buf; 1060 m_new->m_flags |= M_EXT; 1061 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 1062 } else { 1063 m_new = m; 1064 m_new->m_len = m_new->m_pkthdr.len = NGE_JLEN; 1065 m_new->m_data = m_new->m_ext.ext_buf; 1066 } 1067 1068 m_adj(m_new, sizeof(uint64_t)); 1069 1070 c->nge_mbuf = m_new; 1071 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1072 c->nge_ctl = m_new->m_len; 1073 c->nge_extsts = 0; 1074 1075 return(0); 1076 } 1077 1078 static int 1079 nge_alloc_jumbo_mem(struct nge_softc *sc) 1080 { 1081 caddr_t ptr; 1082 int i; 1083 struct nge_jslot *entry; 1084 1085 /* Grab a big chunk o' storage. */ 1086 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF, 1087 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 1088 1089 if (sc->nge_cdata.nge_jumbo_buf == NULL) { 1090 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit); 1091 return(ENOBUFS); 1092 } 1093 1094 SLIST_INIT(&sc->nge_jfree_listhead); 1095 1096 /* 1097 * Now divide it up into 9K pieces and save the addresses 1098 * in an array. 1099 */ 1100 ptr = sc->nge_cdata.nge_jumbo_buf; 1101 for (i = 0; i < NGE_JSLOTS; i++) { 1102 entry = &sc->nge_cdata.nge_jslots[i]; 1103 entry->nge_sc = sc; 1104 entry->nge_buf = ptr; 1105 entry->nge_inuse = 0; 1106 entry->nge_slot = i; 1107 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jslot_link); 1108 ptr += NGE_JLEN; 1109 } 1110 1111 return(0); 1112 } 1113 1114 1115 /* 1116 * Allocate a jumbo buffer. 1117 */ 1118 static struct nge_jslot * 1119 nge_jalloc(struct nge_softc *sc) 1120 { 1121 struct nge_jslot *entry; 1122 1123 lwkt_serialize_enter(&sc->nge_jslot_serializer); 1124 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1125 if (entry) { 1126 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jslot_link); 1127 entry->nge_inuse = 1; 1128 } else { 1129 #ifdef NGE_VERBOSE 1130 printf("nge%d: no free jumbo buffers\n", sc->nge_unit); 1131 #endif 1132 } 1133 lwkt_serialize_exit(&sc->nge_jslot_serializer); 1134 return(entry); 1135 } 1136 1137 /* 1138 * Adjust usage count on a jumbo buffer. In general this doesn't 1139 * get used much because our jumbo buffers don't get passed around 1140 * a lot, but it's implemented for correctness. 1141 */ 1142 static void 1143 nge_jref(void *arg) 1144 { 1145 struct nge_jslot *entry = (struct nge_jslot *)arg; 1146 struct nge_softc *sc = entry->nge_sc; 1147 1148 if (sc == NULL) 1149 panic("nge_jref: can't find softc pointer!"); 1150 1151 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry) 1152 panic("nge_jref: asked to reference buffer " 1153 "that we don't manage!"); 1154 else if (entry->nge_inuse == 0) 1155 panic("nge_jref: buffer already free!"); 1156 else 1157 atomic_add_int(&entry->nge_inuse, 1); 1158 } 1159 1160 /* 1161 * Release a jumbo buffer. 1162 */ 1163 static void 1164 nge_jfree(void *arg) 1165 { 1166 struct nge_jslot *entry = (struct nge_jslot *)arg; 1167 struct nge_softc *sc = entry->nge_sc; 1168 1169 if (sc == NULL) 1170 panic("nge_jref: can't find softc pointer!"); 1171 1172 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry) { 1173 panic("nge_jref: asked to reference buffer " 1174 "that we don't manage!"); 1175 } else if (entry->nge_inuse == 0) { 1176 panic("nge_jref: buffer already free!"); 1177 } else { 1178 lwkt_serialize_enter(&sc->nge_jslot_serializer); 1179 atomic_subtract_int(&entry->nge_inuse, 1); 1180 if (entry->nge_inuse == 0) { 1181 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1182 entry, jslot_link); 1183 } 1184 lwkt_serialize_exit(&sc->nge_jslot_serializer); 1185 } 1186 } 1187 /* 1188 * A frame has been uploaded: pass the resulting mbuf chain up to 1189 * the higher level protocols. 1190 */ 1191 static void 1192 nge_rxeof(struct nge_softc *sc) 1193 { 1194 struct mbuf *m; 1195 struct ifnet *ifp = &sc->arpcom.ac_if; 1196 struct nge_desc *cur_rx; 1197 int i, total_len = 0; 1198 uint32_t rxstat; 1199 1200 i = sc->nge_cdata.nge_rx_prod; 1201 1202 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1203 struct mbuf *m0 = NULL; 1204 uint32_t extsts; 1205 1206 #ifdef DEVICE_POLLING 1207 if (ifp->if_flags & IFF_POLLING) { 1208 if (sc->rxcycles <= 0) 1209 break; 1210 sc->rxcycles--; 1211 } 1212 #endif /* DEVICE_POLLING */ 1213 1214 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1215 rxstat = cur_rx->nge_rxstat; 1216 extsts = cur_rx->nge_extsts; 1217 m = cur_rx->nge_mbuf; 1218 cur_rx->nge_mbuf = NULL; 1219 total_len = NGE_RXBYTES(cur_rx); 1220 NGE_INC(i, NGE_RX_LIST_CNT); 1221 /* 1222 * If an error occurs, update stats, clear the 1223 * status word and leave the mbuf cluster in place: 1224 * it should simply get re-used next time this descriptor 1225 * comes up in the ring. 1226 */ 1227 if ((rxstat & NGE_CMDSTS_PKT_OK) == 0) { 1228 ifp->if_ierrors++; 1229 nge_newbuf(sc, cur_rx, m); 1230 continue; 1231 } 1232 1233 /* 1234 * Ok. NatSemi really screwed up here. This is the 1235 * only gigE chip I know of with alignment constraints 1236 * on receive buffers. RX buffers must be 64-bit aligned. 1237 */ 1238 #ifdef __i386__ 1239 /* 1240 * By popular demand, ignore the alignment problems 1241 * on the Intel x86 platform. The performance hit 1242 * incurred due to unaligned accesses is much smaller 1243 * than the hit produced by forcing buffer copies all 1244 * the time, especially with jumbo frames. We still 1245 * need to fix up the alignment everywhere else though. 1246 */ 1247 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 1248 #endif 1249 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1250 total_len + ETHER_ALIGN, 0, ifp, NULL); 1251 nge_newbuf(sc, cur_rx, m); 1252 if (m0 == NULL) { 1253 printf("nge%d: no receive buffers " 1254 "available -- packet dropped!\n", 1255 sc->nge_unit); 1256 ifp->if_ierrors++; 1257 continue; 1258 } 1259 m_adj(m0, ETHER_ALIGN); 1260 m = m0; 1261 #ifdef __i386__ 1262 } else { 1263 m->m_pkthdr.rcvif = ifp; 1264 m->m_pkthdr.len = m->m_len = total_len; 1265 } 1266 #endif 1267 1268 ifp->if_ipackets++; 1269 1270 /* Do IP checksum checking. */ 1271 if (extsts & NGE_RXEXTSTS_IPPKT) 1272 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1273 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1274 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1275 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1276 (extsts & NGE_RXEXTSTS_TCPCSUMERR) == 0) || 1277 (extsts & NGE_RXEXTSTS_UDPPKT && 1278 (extsts & NGE_RXEXTSTS_UDPCSUMERR) == 0)) { 1279 m->m_pkthdr.csum_flags |= 1280 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1281 m->m_pkthdr.csum_data = 0xffff; 1282 } 1283 1284 /* 1285 * If we received a packet with a vlan tag, pass it 1286 * to vlan_input() instead of ether_input(). 1287 */ 1288 if (extsts & NGE_RXEXTSTS_VLANPKT) 1289 VLAN_INPUT_TAG(m, extsts & NGE_RXEXTSTS_VTCI); 1290 else 1291 ifp->if_input(ifp, m); 1292 } 1293 1294 sc->nge_cdata.nge_rx_prod = i; 1295 } 1296 1297 /* 1298 * A frame was downloaded to the chip. It's safe for us to clean up 1299 * the list buffers. 1300 */ 1301 static void 1302 nge_txeof(struct nge_softc *sc) 1303 { 1304 struct ifnet *ifp = &sc->arpcom.ac_if; 1305 struct nge_desc *cur_tx = NULL; 1306 uint32_t idx; 1307 1308 /* Clear the timeout timer. */ 1309 ifp->if_timer = 0; 1310 1311 /* 1312 * Go through our tx list and free mbufs for those 1313 * frames that have been transmitted. 1314 */ 1315 idx = sc->nge_cdata.nge_tx_cons; 1316 while (idx != sc->nge_cdata.nge_tx_prod) { 1317 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1318 1319 if (NGE_OWNDESC(cur_tx)) 1320 break; 1321 1322 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1323 sc->nge_cdata.nge_tx_cnt--; 1324 NGE_INC(idx, NGE_TX_LIST_CNT); 1325 continue; 1326 } 1327 1328 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1329 ifp->if_oerrors++; 1330 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1331 ifp->if_collisions++; 1332 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1333 ifp->if_collisions++; 1334 } 1335 1336 ifp->if_collisions += 1337 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1338 1339 ifp->if_opackets++; 1340 if (cur_tx->nge_mbuf != NULL) { 1341 m_freem(cur_tx->nge_mbuf); 1342 cur_tx->nge_mbuf = NULL; 1343 } 1344 1345 sc->nge_cdata.nge_tx_cnt--; 1346 NGE_INC(idx, NGE_TX_LIST_CNT); 1347 ifp->if_timer = 0; 1348 } 1349 1350 sc->nge_cdata.nge_tx_cons = idx; 1351 1352 if (cur_tx != NULL) 1353 ifp->if_flags &= ~IFF_OACTIVE; 1354 } 1355 1356 static void 1357 nge_tick(void *xsc) 1358 { 1359 struct nge_softc *sc = xsc; 1360 struct ifnet *ifp = &sc->arpcom.ac_if; 1361 struct mii_data *mii; 1362 1363 lwkt_serialize_enter(ifp->if_serializer); 1364 1365 if (sc->nge_tbi) { 1366 if (sc->nge_link == 0) { 1367 if (CSR_READ_4(sc, NGE_TBI_BMSR) 1368 & NGE_TBIBMSR_ANEG_DONE) { 1369 printf("nge%d: gigabit link up\n", 1370 sc->nge_unit); 1371 nge_miibus_statchg(sc->nge_miibus); 1372 sc->nge_link++; 1373 if (!ifq_is_empty(&ifp->if_snd)) 1374 nge_start(ifp); 1375 } 1376 } 1377 } else { 1378 mii = device_get_softc(sc->nge_miibus); 1379 mii_tick(mii); 1380 1381 if (sc->nge_link == 0) { 1382 if (mii->mii_media_status & IFM_ACTIVE && 1383 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1384 sc->nge_link++; 1385 if (IFM_SUBTYPE(mii->mii_media_active) 1386 == IFM_1000_T) 1387 printf("nge%d: gigabit link up\n", 1388 sc->nge_unit); 1389 if (!ifq_is_empty(&ifp->if_snd)) 1390 nge_start(ifp); 1391 } 1392 } 1393 } 1394 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc); 1395 1396 lwkt_serialize_exit(ifp->if_serializer); 1397 } 1398 1399 #ifdef DEVICE_POLLING 1400 1401 static void 1402 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1403 { 1404 struct nge_softc *sc = ifp->if_softc; 1405 1406 switch(cmd) { 1407 case POLL_REGISTER: 1408 /* disable interrupts */ 1409 CSR_WRITE_4(sc, NGE_IER, 0); 1410 break; 1411 case POLL_DEREGISTER: 1412 /* enable interrupts */ 1413 CSR_WRITE_4(sc, NGE_IER, 1); 1414 break; 1415 default: 1416 /* 1417 * On the nge, reading the status register also clears it. 1418 * So before returning to intr mode we must make sure that all 1419 * possible pending sources of interrupts have been served. 1420 * In practice this means run to completion the *eof routines, 1421 * and then call the interrupt routine 1422 */ 1423 sc->rxcycles = count; 1424 nge_rxeof(sc); 1425 nge_txeof(sc); 1426 if (!ifq_is_empty(&ifp->if_snd)) 1427 nge_start(ifp); 1428 1429 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1430 uint32_t status; 1431 1432 /* Reading the ISR register clears all interrupts. */ 1433 status = CSR_READ_4(sc, NGE_ISR); 1434 1435 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) 1436 nge_rxeof(sc); 1437 1438 if (status & (NGE_ISR_RX_IDLE)) 1439 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1440 1441 if (status & NGE_ISR_SYSERR) { 1442 nge_reset(sc); 1443 nge_init(sc); 1444 } 1445 } 1446 break; 1447 } 1448 } 1449 1450 #endif /* DEVICE_POLLING */ 1451 1452 static void 1453 nge_intr(void *arg) 1454 { 1455 struct nge_softc *sc = arg; 1456 struct ifnet *ifp = &sc->arpcom.ac_if; 1457 uint32_t status; 1458 1459 /* Supress unwanted interrupts */ 1460 if (!(ifp->if_flags & IFF_UP)) { 1461 nge_stop(sc); 1462 return; 1463 } 1464 1465 /* Disable interrupts. */ 1466 CSR_WRITE_4(sc, NGE_IER, 0); 1467 1468 /* Data LED on for TBI mode */ 1469 if(sc->nge_tbi) 1470 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1471 | NGE_GPIO_GP3_OUT); 1472 1473 for (;;) { 1474 /* Reading the ISR register clears all interrupts. */ 1475 status = CSR_READ_4(sc, NGE_ISR); 1476 1477 if ((status & NGE_INTRS) == 0) 1478 break; 1479 1480 if ((status & NGE_ISR_TX_DESC_OK) || 1481 (status & NGE_ISR_TX_ERR) || 1482 (status & NGE_ISR_TX_OK) || 1483 (status & NGE_ISR_TX_IDLE)) 1484 nge_txeof(sc); 1485 1486 if ((status & NGE_ISR_RX_DESC_OK) || 1487 (status & NGE_ISR_RX_ERR) || 1488 (status & NGE_ISR_RX_OFLOW) || 1489 (status & NGE_ISR_RX_FIFO_OFLOW) || 1490 (status & NGE_ISR_RX_IDLE) || 1491 (status & NGE_ISR_RX_OK)) 1492 nge_rxeof(sc); 1493 1494 if ((status & NGE_ISR_RX_IDLE)) 1495 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1496 1497 if (status & NGE_ISR_SYSERR) { 1498 nge_reset(sc); 1499 ifp->if_flags &= ~IFF_RUNNING; 1500 nge_init(sc); 1501 } 1502 1503 #ifdef notyet 1504 /* mii_tick should only be called once per second */ 1505 if (status & NGE_ISR_PHY_INTR) { 1506 sc->nge_link = 0; 1507 nge_tick_serialized(sc); 1508 } 1509 #endif 1510 } 1511 1512 /* Re-enable interrupts. */ 1513 CSR_WRITE_4(sc, NGE_IER, 1); 1514 1515 if (!ifq_is_empty(&ifp->if_snd)) 1516 nge_start(ifp); 1517 1518 /* Data LED off for TBI mode */ 1519 1520 if(sc->nge_tbi) 1521 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1522 & ~NGE_GPIO_GP3_OUT); 1523 } 1524 1525 /* 1526 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1527 * pointers to the fragment pointers. 1528 */ 1529 static int 1530 nge_encap(struct nge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1531 { 1532 struct nge_desc *f = NULL; 1533 struct mbuf *m; 1534 int frag, cur, cnt = 0; 1535 struct ifvlan *ifv = NULL; 1536 1537 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1538 m_head->m_pkthdr.rcvif != NULL && 1539 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 1540 ifv = m_head->m_pkthdr.rcvif->if_softc; 1541 1542 /* 1543 * Start packing the mbufs in this chain into 1544 * the fragment pointers. Stop when we run out 1545 * of fragments or hit the end of the mbuf chain. 1546 */ 1547 m = m_head; 1548 cur = frag = *txidx; 1549 1550 for (m = m_head; m != NULL; m = m->m_next) { 1551 if (m->m_len != 0) { 1552 if ((NGE_TX_LIST_CNT - 1553 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1554 return(ENOBUFS); 1555 f = &sc->nge_ldata->nge_tx_list[frag]; 1556 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1557 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1558 if (cnt != 0) 1559 f->nge_ctl |= NGE_CMDSTS_OWN; 1560 cur = frag; 1561 NGE_INC(frag, NGE_TX_LIST_CNT); 1562 cnt++; 1563 } 1564 } 1565 1566 if (m != NULL) 1567 return(ENOBUFS); 1568 1569 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1570 if (m_head->m_pkthdr.csum_flags) { 1571 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1572 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1573 NGE_TXEXTSTS_IPCSUM; 1574 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1575 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1576 NGE_TXEXTSTS_TCPCSUM; 1577 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1578 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1579 NGE_TXEXTSTS_UDPCSUM; 1580 } 1581 1582 if (ifv != NULL) { 1583 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1584 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag); 1585 } 1586 1587 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1588 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1589 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1590 sc->nge_cdata.nge_tx_cnt += cnt; 1591 *txidx = frag; 1592 1593 return(0); 1594 } 1595 1596 /* 1597 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1598 * to the mbuf data regions directly in the transmit lists. We also save a 1599 * copy of the pointers since the transmit list fragment pointers are 1600 * physical addresses. 1601 */ 1602 1603 static void 1604 nge_start(struct ifnet *ifp) 1605 { 1606 struct nge_softc *sc = ifp->if_softc; 1607 struct mbuf *m_head = NULL; 1608 uint32_t idx; 1609 int need_trans; 1610 1611 if (!sc->nge_link) 1612 return; 1613 1614 idx = sc->nge_cdata.nge_tx_prod; 1615 1616 if (ifp->if_flags & IFF_OACTIVE) 1617 return; 1618 1619 need_trans = 0; 1620 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1621 m_head = ifq_poll(&ifp->if_snd); 1622 if (m_head == NULL) 1623 break; 1624 1625 if (nge_encap(sc, m_head, &idx)) { 1626 ifp->if_flags |= IFF_OACTIVE; 1627 break; 1628 } 1629 ifq_dequeue(&ifp->if_snd, m_head); 1630 need_trans = 1; 1631 1632 BPF_MTAP(ifp, m_head); 1633 } 1634 1635 if (!need_trans) 1636 return; 1637 1638 /* Transmit */ 1639 sc->nge_cdata.nge_tx_prod = idx; 1640 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1641 1642 /* 1643 * Set a timeout in case the chip goes out to lunch. 1644 */ 1645 ifp->if_timer = 5; 1646 } 1647 1648 static void 1649 nge_init(void *xsc) 1650 { 1651 struct nge_softc *sc = xsc; 1652 struct ifnet *ifp = &sc->arpcom.ac_if; 1653 struct mii_data *mii; 1654 1655 if (ifp->if_flags & IFF_RUNNING) { 1656 return; 1657 } 1658 1659 /* 1660 * Cancel pending I/O and free all RX/TX buffers. 1661 */ 1662 nge_stop(sc); 1663 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc); 1664 1665 if (sc->nge_tbi) 1666 mii = NULL; 1667 else 1668 mii = device_get_softc(sc->nge_miibus); 1669 1670 /* Set MAC address */ 1671 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1672 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1673 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1674 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1675 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1676 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1677 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1678 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1679 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1680 1681 /* Init circular RX list. */ 1682 if (nge_list_rx_init(sc) == ENOBUFS) { 1683 printf("nge%d: initialization failed: no " 1684 "memory for rx buffers\n", sc->nge_unit); 1685 nge_stop(sc); 1686 return; 1687 } 1688 1689 /* 1690 * Init tx descriptors. 1691 */ 1692 nge_list_tx_init(sc); 1693 1694 /* 1695 * For the NatSemi chip, we have to explicitly enable the 1696 * reception of ARP frames, as well as turn on the 'perfect 1697 * match' filter where we store the station address, otherwise 1698 * we won't receive unicasts meant for this host. 1699 */ 1700 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1701 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1702 1703 /* If we want promiscuous mode, set the allframes bit. */ 1704 if (ifp->if_flags & IFF_PROMISC) 1705 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1706 else 1707 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1708 1709 /* 1710 * Set the capture broadcast bit to capture broadcast frames. 1711 */ 1712 if (ifp->if_flags & IFF_BROADCAST) 1713 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1714 else 1715 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1716 1717 /* 1718 * Load the multicast filter. 1719 */ 1720 nge_setmulti(sc); 1721 1722 /* Turn the receive filter on */ 1723 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1724 1725 /* 1726 * Load the address of the RX and TX lists. 1727 */ 1728 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1729 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1730 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1731 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1732 1733 /* Set RX configuration */ 1734 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1735 /* 1736 * Enable hardware checksum validation for all IPv4 1737 * packets, do not reject packets with bad checksums. 1738 */ 1739 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1740 1741 /* 1742 * Tell the chip to detect and strip VLAN tag info from 1743 * received frames. The tag will be provided in the extsts 1744 * field in the RX descriptors. 1745 */ 1746 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1747 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1748 1749 /* Set TX configuration */ 1750 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1751 1752 /* 1753 * Enable TX IPv4 checksumming on a per-packet basis. 1754 */ 1755 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1756 1757 /* 1758 * Tell the chip to insert VLAN tags on a per-packet basis as 1759 * dictated by the code in the frame encapsulation routine. 1760 */ 1761 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1762 1763 /* Set full/half duplex mode. */ 1764 if (sc->nge_tbi) { 1765 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1766 == IFM_FDX) { 1767 NGE_SETBIT(sc, NGE_TX_CFG, 1768 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 1769 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1770 } else { 1771 NGE_CLRBIT(sc, NGE_TX_CFG, 1772 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 1773 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1774 } 1775 } else { 1776 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1777 NGE_SETBIT(sc, NGE_TX_CFG, 1778 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 1779 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1780 } else { 1781 NGE_CLRBIT(sc, NGE_TX_CFG, 1782 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 1783 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1784 } 1785 } 1786 1787 /* 1788 * Enable the delivery of PHY interrupts based on 1789 * link/speed/duplex status changes. Also enable the 1790 * extsts field in the DMA descriptors (needed for 1791 * TCP/IP checksum offload on transmit). 1792 */ 1793 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD | 1794 NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB); 1795 1796 /* 1797 * Configure interrupt holdoff (moderation). We can 1798 * have the chip delay interrupt delivery for a certain 1799 * period. Units are in 100us, and the max setting 1800 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 1801 */ 1802 CSR_WRITE_4(sc, NGE_IHR, 0x01); 1803 1804 /* 1805 * Enable interrupts. 1806 */ 1807 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1808 #ifdef DEVICE_POLLING 1809 /* 1810 * ... only enable interrupts if we are not polling, make sure 1811 * they are off otherwise. 1812 */ 1813 if (ifp->if_flags & IFF_POLLING) 1814 CSR_WRITE_4(sc, NGE_IER, 0); 1815 else 1816 #endif /* DEVICE_POLLING */ 1817 CSR_WRITE_4(sc, NGE_IER, 1); 1818 1819 /* Enable receiver and transmitter. */ 1820 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE); 1821 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1822 1823 nge_ifmedia_upd(ifp); 1824 1825 ifp->if_flags |= IFF_RUNNING; 1826 ifp->if_flags &= ~IFF_OACTIVE; 1827 } 1828 1829 /* 1830 * Set media options. 1831 */ 1832 static int 1833 nge_ifmedia_upd(struct ifnet *ifp) 1834 { 1835 struct nge_softc *sc = ifp->if_softc; 1836 struct mii_data *mii; 1837 1838 if (sc->nge_tbi) { 1839 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1840 == IFM_AUTO) { 1841 CSR_WRITE_4(sc, NGE_TBI_ANAR, 1842 CSR_READ_4(sc, NGE_TBI_ANAR) 1843 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX 1844 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2); 1845 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG 1846 | NGE_TBIBMCR_RESTART_ANEG); 1847 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG); 1848 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media 1849 & IFM_GMASK) == IFM_FDX) { 1850 NGE_SETBIT(sc, NGE_TX_CFG, 1851 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1852 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1853 1854 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 1855 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 1856 } else { 1857 NGE_CLRBIT(sc, NGE_TX_CFG, 1858 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1859 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1860 1861 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 1862 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 1863 } 1864 1865 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1866 & ~NGE_GPIO_GP3_OUT); 1867 } else { 1868 mii = device_get_softc(sc->nge_miibus); 1869 sc->nge_link = 0; 1870 if (mii->mii_instance) { 1871 struct mii_softc *miisc; 1872 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1873 miisc = LIST_NEXT(miisc, mii_list)) 1874 mii_phy_reset(miisc); 1875 } 1876 mii_mediachg(mii); 1877 } 1878 1879 return(0); 1880 } 1881 1882 /* 1883 * Report current media status. 1884 */ 1885 static void 1886 nge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1887 { 1888 struct nge_softc *sc = ifp->if_softc; 1889 struct mii_data *mii; 1890 1891 if (sc->nge_tbi) { 1892 ifmr->ifm_status = IFM_AVALID; 1893 ifmr->ifm_active = IFM_ETHER; 1894 1895 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) 1896 ifmr->ifm_status |= IFM_ACTIVE; 1897 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK) 1898 ifmr->ifm_active |= IFM_LOOP; 1899 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 1900 ifmr->ifm_active |= IFM_NONE; 1901 ifmr->ifm_status = 0; 1902 return; 1903 } 1904 ifmr->ifm_active |= IFM_1000_SX; 1905 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1906 == IFM_AUTO) { 1907 ifmr->ifm_active |= IFM_AUTO; 1908 if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 1909 & NGE_TBIANAR_FDX) { 1910 ifmr->ifm_active |= IFM_FDX; 1911 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 1912 & NGE_TBIANAR_HDX) { 1913 ifmr->ifm_active |= IFM_HDX; 1914 } 1915 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1916 == IFM_FDX) 1917 ifmr->ifm_active |= IFM_FDX; 1918 else 1919 ifmr->ifm_active |= IFM_HDX; 1920 1921 } else { 1922 mii = device_get_softc(sc->nge_miibus); 1923 mii_pollstat(mii); 1924 ifmr->ifm_active = mii->mii_media_active; 1925 ifmr->ifm_status = mii->mii_media_status; 1926 } 1927 } 1928 1929 static int 1930 nge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1931 { 1932 struct nge_softc *sc = ifp->if_softc; 1933 struct ifreq *ifr = (struct ifreq *) data; 1934 struct mii_data *mii; 1935 int error = 0; 1936 1937 switch(command) { 1938 case SIOCSIFMTU: 1939 if (ifr->ifr_mtu > NGE_JUMBO_MTU) { 1940 error = EINVAL; 1941 } else { 1942 ifp->if_mtu = ifr->ifr_mtu; 1943 /* 1944 * Workaround: if the MTU is larger than 1945 * 8152 (TX FIFO size minus 64 minus 18), turn off 1946 * TX checksum offloading. 1947 */ 1948 if (ifr->ifr_mtu >= 8152) 1949 ifp->if_hwassist = 0; 1950 else 1951 ifp->if_hwassist = NGE_CSUM_FEATURES; 1952 } 1953 break; 1954 case SIOCSIFFLAGS: 1955 if (ifp->if_flags & IFF_UP) { 1956 if (ifp->if_flags & IFF_RUNNING && 1957 ifp->if_flags & IFF_PROMISC && 1958 !(sc->nge_if_flags & IFF_PROMISC)) { 1959 NGE_SETBIT(sc, NGE_RXFILT_CTL, 1960 NGE_RXFILTCTL_ALLPHYS| 1961 NGE_RXFILTCTL_ALLMULTI); 1962 } else if (ifp->if_flags & IFF_RUNNING && 1963 !(ifp->if_flags & IFF_PROMISC) && 1964 sc->nge_if_flags & IFF_PROMISC) { 1965 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1966 NGE_RXFILTCTL_ALLPHYS); 1967 if (!(ifp->if_flags & IFF_ALLMULTI)) 1968 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1969 NGE_RXFILTCTL_ALLMULTI); 1970 } else { 1971 ifp->if_flags &= ~IFF_RUNNING; 1972 nge_init(sc); 1973 } 1974 } else { 1975 if (ifp->if_flags & IFF_RUNNING) 1976 nge_stop(sc); 1977 } 1978 sc->nge_if_flags = ifp->if_flags; 1979 error = 0; 1980 break; 1981 case SIOCADDMULTI: 1982 case SIOCDELMULTI: 1983 nge_setmulti(sc); 1984 error = 0; 1985 break; 1986 case SIOCGIFMEDIA: 1987 case SIOCSIFMEDIA: 1988 if (sc->nge_tbi) { 1989 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, 1990 command); 1991 } else { 1992 mii = device_get_softc(sc->nge_miibus); 1993 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1994 command); 1995 } 1996 break; 1997 default: 1998 error = ether_ioctl(ifp, command, data); 1999 break; 2000 } 2001 return(error); 2002 } 2003 2004 static void 2005 nge_watchdog(struct ifnet *ifp) 2006 { 2007 struct nge_softc *sc = ifp->if_softc; 2008 2009 ifp->if_oerrors++; 2010 printf("nge%d: watchdog timeout\n", sc->nge_unit); 2011 2012 nge_stop(sc); 2013 nge_reset(sc); 2014 ifp->if_flags &= ~IFF_RUNNING; 2015 nge_init(sc); 2016 2017 if (!ifq_is_empty(&ifp->if_snd)) 2018 nge_start(ifp); 2019 } 2020 2021 /* 2022 * Stop the adapter and free any mbufs allocated to the 2023 * RX and TX lists. 2024 */ 2025 static void 2026 nge_stop(struct nge_softc *sc) 2027 { 2028 struct ifnet *ifp = &sc->arpcom.ac_if; 2029 struct ifmedia_entry *ifm; 2030 struct mii_data *mii; 2031 int i, itmp, mtmp; 2032 2033 ifp->if_timer = 0; 2034 if (sc->nge_tbi) 2035 mii = NULL; 2036 else 2037 mii = device_get_softc(sc->nge_miibus); 2038 2039 callout_stop(&sc->nge_stat_timer); 2040 CSR_WRITE_4(sc, NGE_IER, 0); 2041 CSR_WRITE_4(sc, NGE_IMR, 0); 2042 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2043 DELAY(1000); 2044 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 2045 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 2046 2047 /* 2048 * Isolate/power down the PHY, but leave the media selection 2049 * unchanged so that things will be put back to normal when 2050 * we bring the interface back up. 2051 */ 2052 itmp = ifp->if_flags; 2053 ifp->if_flags |= IFF_UP; 2054 2055 if (sc->nge_tbi) 2056 ifm = sc->nge_ifmedia.ifm_cur; 2057 else 2058 ifm = mii->mii_media.ifm_cur; 2059 2060 mtmp = ifm->ifm_media; 2061 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2062 2063 if (!sc->nge_tbi) 2064 mii_mediachg(mii); 2065 ifm->ifm_media = mtmp; 2066 ifp->if_flags = itmp; 2067 2068 sc->nge_link = 0; 2069 2070 /* 2071 * Free data in the RX lists. 2072 */ 2073 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2074 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2075 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2076 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2077 } 2078 } 2079 bzero(&sc->nge_ldata->nge_rx_list, 2080 sizeof(sc->nge_ldata->nge_rx_list)); 2081 2082 /* 2083 * Free the TX list buffers. 2084 */ 2085 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2086 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2087 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2088 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2089 } 2090 } 2091 2092 bzero(&sc->nge_ldata->nge_tx_list, 2093 sizeof(sc->nge_ldata->nge_tx_list)); 2094 2095 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2096 } 2097 2098 /* 2099 * Stop all chip I/O so that the kernel's probe routines don't 2100 * get confused by errant DMAs when rebooting. 2101 */ 2102 static void 2103 nge_shutdown(device_t dev) 2104 { 2105 struct nge_softc *sc = device_get_softc(dev); 2106 struct ifnet *ifp = &sc->arpcom.ac_if; 2107 2108 lwkt_serialize_enter(ifp->if_serializer); 2109 nge_reset(sc); 2110 nge_stop(sc); 2111 lwkt_serialize_exit(ifp->if_serializer); 2112 } 2113 2114