1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $ 34 * $DragonFly: src/sys/dev/netif/nge/if_nge.c,v 1.37 2006/01/10 14:14:00 sephe Exp $ 35 */ 36 37 /* 38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 39 * for FreeBSD. Datasheets are available from: 40 * 41 * http://www.national.com/ds/DP/DP83820.pdf 42 * http://www.national.com/ds/DP/DP83821.pdf 43 * 44 * These chips are used on several low cost gigabit ethernet NICs 45 * sold by D-Link, Addtron, SMC and Asante. Both parts are 46 * virtually the same, except the 83820 is a 64-bit/32-bit part, 47 * while the 83821 is 32-bit only. 48 * 49 * Many cards also use National gigE transceivers, such as the 50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 51 * contains a full register description that applies to all of these 52 * components: 53 * 54 * http://www.national.com/ds/DP/DP83861.pdf 55 * 56 * Written by Bill Paul <wpaul@bsdi.com> 57 * BSDi Open Source Solutions 58 */ 59 60 /* 61 * The NatSemi DP83820 and 83821 controllers are enhanced versions 62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 67 * matching buffers, one perfect address filter buffer and interrupt 68 * moderation. The 83820 supports both 64-bit and 32-bit addressing 69 * and data transfers: the 64-bit support can be toggled on or off 70 * via software. This affects the size of certain fields in the DMA 71 * descriptors. 72 * 73 * There are two bugs/misfeatures in the 83820/83821 that I have 74 * discovered so far: 75 * 76 * - Receive buffers must be aligned on 64-bit boundaries, which means 77 * you must resort to copying data in order to fix up the payload 78 * alignment. 79 * 80 * - In order to transmit jumbo frames larger than 8170 bytes, you have 81 * to turn off transmit checksum offloading, because the chip can't 82 * compute the checksum on an outgoing frame unless it fits entirely 83 * within the TX FIFO, which is only 8192 bytes in size. If you have 84 * TX checksum offload enabled and you transmit attempt to transmit a 85 * frame larger than 8170 bytes, the transmitter will wedge. 86 * 87 * To work around the latter problem, TX checksum offload is disabled 88 * if the user selects an MTU larger than 8152 (8170 - 18). 89 */ 90 91 #include "opt_polling.h" 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/sockio.h> 96 #include <sys/mbuf.h> 97 #include <sys/malloc.h> 98 #include <sys/kernel.h> 99 #include <sys/socket.h> 100 #include <sys/serialize.h> 101 102 #include <sys/thread2.h> 103 104 #include <net/if.h> 105 #include <net/ifq_var.h> 106 #include <net/if_arp.h> 107 #include <net/ethernet.h> 108 #include <net/if_dl.h> 109 #include <net/if_media.h> 110 #include <net/if_types.h> 111 #include <net/vlan/if_vlan_var.h> 112 113 #include <net/bpf.h> 114 115 #include <vm/vm.h> /* for vtophys */ 116 #include <vm/pmap.h> /* for vtophys */ 117 #include <machine/bus.h> 118 #include <machine/resource.h> 119 #include <sys/bus.h> 120 #include <sys/rman.h> 121 122 #include <dev/netif/mii_layer/mii.h> 123 #include <dev/netif/mii_layer/miivar.h> 124 125 #include <bus/pci/pcireg.h> 126 #include <bus/pci/pcivar.h> 127 128 #define NGE_USEIOSPACE 129 130 #include "if_ngereg.h" 131 132 133 /* "controller miibus0" required. See GENERIC if you get errors here. */ 134 #include "miibus_if.h" 135 136 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 137 138 /* 139 * Various supported device vendors/types and their names. 140 */ 141 static struct nge_type nge_devs[] = { 142 { NGE_VENDORID, NGE_DEVICEID, 143 "National Semiconductor Gigabit Ethernet" }, 144 { 0, 0, NULL } 145 }; 146 147 static int nge_probe(device_t); 148 static int nge_attach(device_t); 149 static int nge_detach(device_t); 150 151 static int nge_alloc_jumbo_mem(struct nge_softc *); 152 static struct nge_jslot 153 *nge_jalloc(struct nge_softc *); 154 static void nge_jfree(void *); 155 static void nge_jref(void *); 156 157 static int nge_newbuf(struct nge_softc *, struct nge_desc *, 158 struct mbuf *); 159 static int nge_encap(struct nge_softc *, struct mbuf *, uint32_t *); 160 static void nge_rxeof(struct nge_softc *); 161 static void nge_txeof(struct nge_softc *); 162 static void nge_intr(void *); 163 static void nge_tick(void *); 164 static void nge_start(struct ifnet *); 165 static int nge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 166 static void nge_init(void *); 167 static void nge_stop(struct nge_softc *); 168 static void nge_watchdog(struct ifnet *); 169 static void nge_shutdown(device_t); 170 static int nge_ifmedia_upd(struct ifnet *); 171 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 172 173 static void nge_delay(struct nge_softc *); 174 static void nge_eeprom_idle(struct nge_softc *); 175 static void nge_eeprom_putbyte(struct nge_softc *, int); 176 static void nge_eeprom_getword(struct nge_softc *, int, uint16_t *); 177 static void nge_read_eeprom(struct nge_softc *, void *, int, int); 178 179 static void nge_mii_sync(struct nge_softc *); 180 static void nge_mii_send(struct nge_softc *, uint32_t, int); 181 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *); 182 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *); 183 184 static int nge_miibus_readreg(device_t, int, int); 185 static int nge_miibus_writereg(device_t, int, int, int); 186 static void nge_miibus_statchg(device_t); 187 188 static void nge_setmulti(struct nge_softc *); 189 static void nge_reset(struct nge_softc *); 190 static int nge_list_rx_init(struct nge_softc *); 191 static int nge_list_tx_init(struct nge_softc *); 192 #ifdef DEVICE_POLLING 193 static void nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 194 #endif 195 196 #ifdef NGE_USEIOSPACE 197 #define NGE_RES SYS_RES_IOPORT 198 #define NGE_RID NGE_PCI_LOIO 199 #else 200 #define NGE_RES SYS_RES_MEMORY 201 #define NGE_RID NGE_PCI_LOMEM 202 #endif 203 204 static device_method_t nge_methods[] = { 205 /* Device interface */ 206 DEVMETHOD(device_probe, nge_probe), 207 DEVMETHOD(device_attach, nge_attach), 208 DEVMETHOD(device_detach, nge_detach), 209 DEVMETHOD(device_shutdown, nge_shutdown), 210 211 /* bus interface */ 212 DEVMETHOD(bus_print_child, bus_generic_print_child), 213 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 214 215 /* MII interface */ 216 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 217 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 218 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 219 220 { 0, 0 } 221 }; 222 223 static DEFINE_CLASS_0(nge, nge_driver, nge_methods, sizeof(struct nge_softc)); 224 static devclass_t nge_devclass; 225 226 DECLARE_DUMMY_MODULE(if_nge); 227 MODULE_DEPEND(if_nge, miibus, 1, 1, 1); 228 DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0); 229 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 230 231 #define NGE_SETBIT(sc, reg, x) \ 232 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 233 234 #define NGE_CLRBIT(sc, reg, x) \ 235 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 236 237 #define SIO_SET(x) \ 238 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) 239 240 #define SIO_CLR(x) \ 241 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) 242 243 static void 244 nge_delay(struct nge_softc *sc) 245 { 246 int idx; 247 248 for (idx = (300 / 33) + 1; idx > 0; idx--) 249 CSR_READ_4(sc, NGE_CSR); 250 } 251 252 static void 253 nge_eeprom_idle(struct nge_softc *sc) 254 { 255 int i; 256 257 SIO_SET(NGE_MEAR_EE_CSEL); 258 nge_delay(sc); 259 SIO_SET(NGE_MEAR_EE_CLK); 260 nge_delay(sc); 261 262 for (i = 0; i < 25; i++) { 263 SIO_CLR(NGE_MEAR_EE_CLK); 264 nge_delay(sc); 265 SIO_SET(NGE_MEAR_EE_CLK); 266 nge_delay(sc); 267 } 268 269 SIO_CLR(NGE_MEAR_EE_CLK); 270 nge_delay(sc); 271 SIO_CLR(NGE_MEAR_EE_CSEL); 272 nge_delay(sc); 273 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 274 } 275 276 /* 277 * Send a read command and address to the EEPROM, check for ACK. 278 */ 279 static void 280 nge_eeprom_putbyte(struct nge_softc *sc, int addr) 281 { 282 int d, i; 283 284 d = addr | NGE_EECMD_READ; 285 286 /* 287 * Feed in each bit and stobe the clock. 288 */ 289 for (i = 0x400; i; i >>= 1) { 290 if (d & i) 291 SIO_SET(NGE_MEAR_EE_DIN); 292 else 293 SIO_CLR(NGE_MEAR_EE_DIN); 294 nge_delay(sc); 295 SIO_SET(NGE_MEAR_EE_CLK); 296 nge_delay(sc); 297 SIO_CLR(NGE_MEAR_EE_CLK); 298 nge_delay(sc); 299 } 300 } 301 302 /* 303 * Read a word of data stored in the EEPROM at address 'addr.' 304 */ 305 static void 306 nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest) 307 { 308 int i; 309 uint16_t word = 0; 310 311 /* Force EEPROM to idle state. */ 312 nge_eeprom_idle(sc); 313 314 /* Enter EEPROM access mode. */ 315 nge_delay(sc); 316 SIO_CLR(NGE_MEAR_EE_CLK); 317 nge_delay(sc); 318 SIO_SET(NGE_MEAR_EE_CSEL); 319 nge_delay(sc); 320 321 /* 322 * Send address of word we want to read. 323 */ 324 nge_eeprom_putbyte(sc, addr); 325 326 /* 327 * Start reading bits from EEPROM. 328 */ 329 for (i = 0x8000; i; i >>= 1) { 330 SIO_SET(NGE_MEAR_EE_CLK); 331 nge_delay(sc); 332 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 333 word |= i; 334 nge_delay(sc); 335 SIO_CLR(NGE_MEAR_EE_CLK); 336 nge_delay(sc); 337 } 338 339 /* Turn off EEPROM access mode. */ 340 nge_eeprom_idle(sc); 341 342 *dest = word; 343 } 344 345 /* 346 * Read a sequence of words from the EEPROM. 347 */ 348 static void 349 nge_read_eeprom(struct nge_softc *sc, void *dest, int off, int cnt) 350 { 351 int i; 352 uint16_t word = 0, *ptr; 353 354 for (i = 0; i < cnt; i++) { 355 nge_eeprom_getword(sc, off + i, &word); 356 ptr = (uint16_t *)((uint8_t *)dest + (i * 2)); 357 *ptr = word; 358 } 359 } 360 361 /* 362 * Sync the PHYs by setting data bit and strobing the clock 32 times. 363 */ 364 static void 365 nge_mii_sync(struct nge_softc *sc) 366 { 367 int i; 368 369 SIO_SET(NGE_MEAR_MII_DIR | NGE_MEAR_MII_DATA); 370 371 for (i = 0; i < 32; i++) { 372 SIO_SET(NGE_MEAR_MII_CLK); 373 DELAY(1); 374 SIO_CLR(NGE_MEAR_MII_CLK); 375 DELAY(1); 376 } 377 } 378 379 /* 380 * Clock a series of bits through the MII. 381 */ 382 static void 383 nge_mii_send(struct nge_softc *sc, uint32_t bits, int cnt) 384 { 385 int i; 386 387 SIO_CLR(NGE_MEAR_MII_CLK); 388 389 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 390 if (bits & i) 391 SIO_SET(NGE_MEAR_MII_DATA); 392 else 393 SIO_CLR(NGE_MEAR_MII_DATA); 394 DELAY(1); 395 SIO_CLR(NGE_MEAR_MII_CLK); 396 DELAY(1); 397 SIO_SET(NGE_MEAR_MII_CLK); 398 } 399 } 400 401 /* 402 * Read an PHY register through the MII. 403 */ 404 static int 405 nge_mii_readreg(struct nge_softc *sc, struct nge_mii_frame *frame) 406 { 407 int ack, i; 408 409 /* 410 * Set up frame for RX. 411 */ 412 frame->mii_stdelim = NGE_MII_STARTDELIM; 413 frame->mii_opcode = NGE_MII_READOP; 414 frame->mii_turnaround = 0; 415 frame->mii_data = 0; 416 417 CSR_WRITE_4(sc, NGE_MEAR, 0); 418 419 /* 420 * Turn on data xmit. 421 */ 422 SIO_SET(NGE_MEAR_MII_DIR); 423 424 nge_mii_sync(sc); 425 426 /* 427 * Send command/address info. 428 */ 429 nge_mii_send(sc, frame->mii_stdelim, 2); 430 nge_mii_send(sc, frame->mii_opcode, 2); 431 nge_mii_send(sc, frame->mii_phyaddr, 5); 432 nge_mii_send(sc, frame->mii_regaddr, 5); 433 434 /* Idle bit */ 435 SIO_CLR((NGE_MEAR_MII_CLK | NGE_MEAR_MII_DATA)); 436 DELAY(1); 437 SIO_SET(NGE_MEAR_MII_CLK); 438 DELAY(1); 439 440 /* Turn off xmit. */ 441 SIO_CLR(NGE_MEAR_MII_DIR); 442 /* Check for ack */ 443 SIO_CLR(NGE_MEAR_MII_CLK); 444 DELAY(1); 445 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 446 SIO_SET(NGE_MEAR_MII_CLK); 447 DELAY(1); 448 449 /* 450 * Now try reading data bits. If the ack failed, we still 451 * need to clock through 16 cycles to keep the PHY(s) in sync. 452 */ 453 if (ack) { 454 for(i = 0; i < 16; i++) { 455 SIO_CLR(NGE_MEAR_MII_CLK); 456 DELAY(1); 457 SIO_SET(NGE_MEAR_MII_CLK); 458 DELAY(1); 459 } 460 goto fail; 461 } 462 463 for (i = 0x8000; i; i >>= 1) { 464 SIO_CLR(NGE_MEAR_MII_CLK); 465 DELAY(1); 466 if (!ack) { 467 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 468 frame->mii_data |= i; 469 DELAY(1); 470 } 471 SIO_SET(NGE_MEAR_MII_CLK); 472 DELAY(1); 473 } 474 475 fail: 476 SIO_CLR(NGE_MEAR_MII_CLK); 477 DELAY(1); 478 SIO_SET(NGE_MEAR_MII_CLK); 479 DELAY(1); 480 481 if (ack) 482 return(1); 483 return(0); 484 } 485 486 /* 487 * Write to a PHY register through the MII. 488 */ 489 static int 490 nge_mii_writereg(struct nge_softc *sc, struct nge_mii_frame *frame) 491 { 492 /* 493 * Set up frame for TX. 494 */ 495 496 frame->mii_stdelim = NGE_MII_STARTDELIM; 497 frame->mii_opcode = NGE_MII_WRITEOP; 498 frame->mii_turnaround = NGE_MII_TURNAROUND; 499 500 /* 501 * Turn on data output. 502 */ 503 SIO_SET(NGE_MEAR_MII_DIR); 504 505 nge_mii_sync(sc); 506 507 nge_mii_send(sc, frame->mii_stdelim, 2); 508 nge_mii_send(sc, frame->mii_opcode, 2); 509 nge_mii_send(sc, frame->mii_phyaddr, 5); 510 nge_mii_send(sc, frame->mii_regaddr, 5); 511 nge_mii_send(sc, frame->mii_turnaround, 2); 512 nge_mii_send(sc, frame->mii_data, 16); 513 514 /* Idle bit. */ 515 SIO_SET(NGE_MEAR_MII_CLK); 516 DELAY(1); 517 SIO_CLR(NGE_MEAR_MII_CLK); 518 DELAY(1); 519 520 /* 521 * Turn off xmit. 522 */ 523 SIO_CLR(NGE_MEAR_MII_DIR); 524 525 return(0); 526 } 527 528 static int 529 nge_miibus_readreg(device_t dev, int phy, int reg) 530 { 531 struct nge_softc *sc = device_get_softc(dev); 532 struct nge_mii_frame frame; 533 534 bzero((char *)&frame, sizeof(frame)); 535 536 frame.mii_phyaddr = phy; 537 frame.mii_regaddr = reg; 538 nge_mii_readreg(sc, &frame); 539 540 return(frame.mii_data); 541 } 542 543 static int 544 nge_miibus_writereg(device_t dev, int phy, int reg, int data) 545 { 546 struct nge_softc *sc = device_get_softc(dev); 547 struct nge_mii_frame frame; 548 549 bzero((char *)&frame, sizeof(frame)); 550 551 frame.mii_phyaddr = phy; 552 frame.mii_regaddr = reg; 553 frame.mii_data = data; 554 nge_mii_writereg(sc, &frame); 555 556 return(0); 557 } 558 559 static void 560 nge_miibus_statchg(device_t dev) 561 { 562 struct nge_softc *sc = device_get_softc(dev); 563 struct mii_data *mii; 564 int status; 565 566 if (sc->nge_tbi) { 567 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 568 == IFM_AUTO) { 569 status = CSR_READ_4(sc, NGE_TBI_ANLPAR); 570 if (status == 0 || status & NGE_TBIANAR_FDX) { 571 NGE_SETBIT(sc, NGE_TX_CFG, 572 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 573 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 574 } else { 575 NGE_CLRBIT(sc, NGE_TX_CFG, 576 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 577 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 578 } 579 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 580 != IFM_FDX) { 581 NGE_CLRBIT(sc, NGE_TX_CFG, 582 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 583 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 584 } else { 585 NGE_SETBIT(sc, NGE_TX_CFG, 586 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 587 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 588 } 589 } else { 590 mii = device_get_softc(sc->nge_miibus); 591 592 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 593 NGE_SETBIT(sc, NGE_TX_CFG, 594 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 595 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 596 } else { 597 NGE_CLRBIT(sc, NGE_TX_CFG, 598 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 599 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 600 } 601 602 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 603 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 604 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 605 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 606 } else { 607 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 608 } 609 } 610 } 611 612 static void 613 nge_setmulti(struct nge_softc *sc) 614 { 615 struct ifnet *ifp = &sc->arpcom.ac_if; 616 struct ifmultiaddr *ifma; 617 uint32_t filtsave, h = 0, i; 618 int bit, index; 619 620 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 621 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 622 NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH); 623 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 624 return; 625 } 626 627 /* 628 * We have to explicitly enable the multicast hash table 629 * on the NatSemi chip if we want to use it, which we do. 630 * We also have to tell it that we don't want to use the 631 * hash table for matching unicast addresses. 632 */ 633 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 634 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 635 NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_UCHASH); 636 637 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 638 639 /* first, zot all the existing hash bits */ 640 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 641 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 642 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 643 } 644 645 /* 646 * From the 11 bits returned by the crc routine, the top 7 647 * bits represent the 16-bit word in the mcast hash table 648 * that needs to be updated, and the lower 4 bits represent 649 * which bit within that byte needs to be set. 650 */ 651 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 652 if (ifma->ifma_addr->sa_family != AF_LINK) 653 continue; 654 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 655 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21; 656 index = (h >> 4) & 0x7F; 657 bit = h & 0xF; 658 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 659 NGE_FILTADDR_MCAST_LO + (index * 2)); 660 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 661 } 662 663 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 664 } 665 666 static void 667 nge_reset(struct nge_softc *sc) 668 { 669 int i; 670 671 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 672 673 for (i = 0; i < NGE_TIMEOUT; i++) { 674 if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET) == 0) 675 break; 676 } 677 678 if (i == NGE_TIMEOUT) 679 printf("nge%d: reset never completed\n", sc->nge_unit); 680 681 /* Wait a little while for the chip to get its brains in order. */ 682 DELAY(1000); 683 684 /* 685 * If this is a NetSemi chip, make sure to clear 686 * PME mode. 687 */ 688 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 689 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 690 } 691 692 /* 693 * Probe for an NatSemi chip. Check the PCI vendor and device 694 * IDs against our list and return a device name if we find a match. 695 */ 696 static int 697 nge_probe(device_t dev) 698 { 699 struct nge_type *t; 700 uint16_t vendor, product; 701 702 vendor = pci_get_vendor(dev); 703 product = pci_get_device(dev); 704 705 for (t = nge_devs; t->nge_name != NULL; t++) { 706 if (vendor == t->nge_vid && product == t->nge_did) { 707 device_set_desc(dev, t->nge_name); 708 return(0); 709 } 710 } 711 712 return(ENXIO); 713 } 714 715 /* 716 * Attach the interface. Allocate softc structures, do ifmedia 717 * setup and ethernet/BPF attach. 718 */ 719 static int 720 nge_attach(device_t dev) 721 { 722 struct nge_softc *sc; 723 struct ifnet *ifp; 724 uint8_t eaddr[ETHER_ADDR_LEN]; 725 uint32_t command; 726 int error = 0, rid, unit; 727 const char *sep = ""; 728 729 sc = device_get_softc(dev); 730 unit = device_get_unit(dev); 731 callout_init(&sc->nge_stat_timer); 732 lwkt_serialize_init(&sc->nge_jslot_serializer); 733 734 /* 735 * Handle power management nonsense. 736 */ 737 command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF; 738 if (command == 0x01) { 739 command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4); 740 if (command & NGE_PSTATE_MASK) { 741 uint32_t iobase, membase, irq; 742 743 /* Save important PCI config data. */ 744 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4); 745 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4); 746 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4); 747 748 /* Reset the power state. */ 749 printf("nge%d: chip is in D%d power mode " 750 "-- setting to D0\n", unit, command & NGE_PSTATE_MASK); 751 command &= 0xFFFFFFFC; 752 pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4); 753 754 /* Restore PCI config data. */ 755 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4); 756 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4); 757 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4); 758 } 759 } 760 761 /* 762 * Map control/status registers. 763 */ 764 command = pci_read_config(dev, PCIR_COMMAND, 4); 765 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 766 pci_write_config(dev, PCIR_COMMAND, command, 4); 767 command = pci_read_config(dev, PCIR_COMMAND, 4); 768 769 #ifdef NGE_USEIOSPACE 770 if (!(command & PCIM_CMD_PORTEN)) { 771 printf("nge%d: failed to enable I/O ports!\n", unit); 772 error = ENXIO; 773 return(error); 774 } 775 #else 776 if (!(command & PCIM_CMD_MEMEN)) { 777 printf("nge%d: failed to enable memory mapping!\n", unit); 778 error = ENXIO; 779 return(error); 780 } 781 #endif 782 783 rid = NGE_RID; 784 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE); 785 786 if (sc->nge_res == NULL) { 787 printf("nge%d: couldn't map ports/memory\n", unit); 788 error = ENXIO; 789 return(error); 790 } 791 792 sc->nge_btag = rman_get_bustag(sc->nge_res); 793 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 794 795 /* Allocate interrupt */ 796 rid = 0; 797 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 798 RF_SHAREABLE | RF_ACTIVE); 799 800 if (sc->nge_irq == NULL) { 801 printf("nge%d: couldn't map interrupt\n", unit); 802 error = ENXIO; 803 goto fail; 804 } 805 806 /* Reset the adapter. */ 807 nge_reset(sc); 808 809 /* 810 * Get station address from the EEPROM. 811 */ 812 nge_read_eeprom(sc, &eaddr[4], NGE_EE_NODEADDR, 1); 813 nge_read_eeprom(sc, &eaddr[2], NGE_EE_NODEADDR + 1, 1); 814 nge_read_eeprom(sc, &eaddr[0], NGE_EE_NODEADDR + 2, 1); 815 816 sc->nge_unit = unit; 817 818 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 819 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 820 821 if (sc->nge_ldata == NULL) { 822 printf("nge%d: no memory for list buffers!\n", unit); 823 error = ENXIO; 824 goto fail; 825 } 826 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 827 828 /* Try to allocate memory for jumbo buffers. */ 829 if (nge_alloc_jumbo_mem(sc)) { 830 printf("nge%d: jumbo buffer allocation failed\n", 831 sc->nge_unit); 832 error = ENXIO; 833 goto fail; 834 } 835 836 ifp = &sc->arpcom.ac_if; 837 ifp->if_softc = sc; 838 if_initname(ifp, "nge", unit); 839 ifp->if_mtu = ETHERMTU; 840 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 841 ifp->if_ioctl = nge_ioctl; 842 ifp->if_start = nge_start; 843 #ifdef DEVICE_POLLING 844 ifp->if_poll = nge_poll; 845 #endif 846 ifp->if_watchdog = nge_watchdog; 847 ifp->if_init = nge_init; 848 ifp->if_baudrate = 1000000000; 849 ifq_set_maxlen(&ifp->if_snd, NGE_TX_LIST_CNT - 1); 850 ifq_set_ready(&ifp->if_snd); 851 ifp->if_hwassist = NGE_CSUM_FEATURES; 852 ifp->if_capabilities = IFCAP_HWCSUM; 853 ifp->if_capenable = ifp->if_capabilities; 854 855 /* 856 * Do MII setup. 857 */ 858 if (mii_phy_probe(dev, &sc->nge_miibus, 859 nge_ifmedia_upd, nge_ifmedia_sts)) { 860 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) { 861 sc->nge_tbi = 1; 862 device_printf(dev, "Using TBI\n"); 863 864 sc->nge_miibus = dev; 865 866 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd, 867 nge_ifmedia_sts); 868 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL) 869 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 870 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0); 871 device_printf(dev, " "); 872 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0); 873 PRINT("1000baseSX"); 874 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0); 875 PRINT("1000baseSX-FDX"); 876 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0); 877 PRINT("auto"); 878 879 printf("\n"); 880 #undef ADD 881 #undef PRINT 882 ifmedia_set(&sc->nge_ifmedia, 883 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0)); 884 885 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 886 | NGE_GPIO_GP4_OUT 887 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 888 | NGE_GPIO_GP3_OUTENB 889 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 890 891 } else { 892 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 893 error = ENXIO; 894 goto fail; 895 } 896 } 897 898 /* 899 * Call MI attach routine. 900 */ 901 ether_ifattach(ifp, eaddr, NULL); 902 903 error = bus_setup_intr(dev, sc->nge_irq, INTR_NETSAFE, 904 nge_intr, sc, &sc->nge_intrhand, 905 ifp->if_serializer); 906 if (error) { 907 ether_ifdetach(ifp); 908 device_printf(dev, "couldn't set up irq\n"); 909 goto fail; 910 } 911 912 return(0); 913 fail: 914 nge_detach(dev); 915 return(error); 916 } 917 918 static int 919 nge_detach(device_t dev) 920 { 921 struct nge_softc *sc = device_get_softc(dev); 922 struct ifnet *ifp = &sc->arpcom.ac_if; 923 924 if (device_is_attached(dev)) { 925 lwkt_serialize_enter(ifp->if_serializer); 926 nge_reset(sc); 927 nge_stop(sc); 928 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 929 lwkt_serialize_exit(ifp->if_serializer); 930 931 ether_ifdetach(ifp); 932 } 933 934 if (sc->nge_miibus) 935 device_delete_child(dev, sc->nge_miibus); 936 bus_generic_detach(dev); 937 938 if (sc->nge_irq) 939 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 940 if (sc->nge_res) 941 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 942 if (sc->nge_ldata) { 943 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), 944 M_DEVBUF); 945 } 946 if (sc->nge_cdata.nge_jumbo_buf) 947 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF); 948 949 return(0); 950 } 951 952 /* 953 * Initialize the transmit descriptors. 954 */ 955 static int 956 nge_list_tx_init(struct nge_softc *sc) 957 { 958 struct nge_list_data *ld; 959 struct nge_ring_data *cd; 960 int i; 961 962 cd = &sc->nge_cdata; 963 ld = sc->nge_ldata; 964 965 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 966 if (i == (NGE_TX_LIST_CNT - 1)) { 967 ld->nge_tx_list[i].nge_nextdesc = 968 &ld->nge_tx_list[0]; 969 ld->nge_tx_list[i].nge_next = 970 vtophys(&ld->nge_tx_list[0]); 971 } else { 972 ld->nge_tx_list[i].nge_nextdesc = 973 &ld->nge_tx_list[i + 1]; 974 ld->nge_tx_list[i].nge_next = 975 vtophys(&ld->nge_tx_list[i + 1]); 976 } 977 ld->nge_tx_list[i].nge_mbuf = NULL; 978 ld->nge_tx_list[i].nge_ptr = 0; 979 ld->nge_tx_list[i].nge_ctl = 0; 980 } 981 982 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 983 984 return(0); 985 } 986 987 988 /* 989 * Initialize the RX descriptors and allocate mbufs for them. Note that 990 * we arrange the descriptors in a closed ring, so that the last descriptor 991 * points back to the first. 992 */ 993 static int 994 nge_list_rx_init(struct nge_softc *sc) 995 { 996 struct nge_list_data *ld; 997 struct nge_ring_data *cd; 998 int i; 999 1000 ld = sc->nge_ldata; 1001 cd = &sc->nge_cdata; 1002 1003 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1004 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1005 return(ENOBUFS); 1006 if (i == (NGE_RX_LIST_CNT - 1)) { 1007 ld->nge_rx_list[i].nge_nextdesc = 1008 &ld->nge_rx_list[0]; 1009 ld->nge_rx_list[i].nge_next = 1010 vtophys(&ld->nge_rx_list[0]); 1011 } else { 1012 ld->nge_rx_list[i].nge_nextdesc = 1013 &ld->nge_rx_list[i + 1]; 1014 ld->nge_rx_list[i].nge_next = 1015 vtophys(&ld->nge_rx_list[i + 1]); 1016 } 1017 } 1018 1019 cd->nge_rx_prod = 0; 1020 1021 return(0); 1022 } 1023 1024 /* 1025 * Initialize an RX descriptor and attach an MBUF cluster. 1026 */ 1027 static int 1028 nge_newbuf(struct nge_softc *sc, struct nge_desc *c, struct mbuf *m) 1029 { 1030 struct mbuf *m_new = NULL; 1031 struct nge_jslot *buf; 1032 1033 if (m == NULL) { 1034 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1035 if (m_new == NULL) { 1036 printf("nge%d: no memory for rx list " 1037 "-- packet dropped!\n", sc->nge_unit); 1038 return(ENOBUFS); 1039 } 1040 1041 /* Allocate the jumbo buffer */ 1042 buf = nge_jalloc(sc); 1043 if (buf == NULL) { 1044 #ifdef NGE_VERBOSE 1045 printf("nge%d: jumbo allocation failed " 1046 "-- packet dropped!\n", sc->nge_unit); 1047 #endif 1048 m_freem(m_new); 1049 return(ENOBUFS); 1050 } 1051 /* Attach the buffer to the mbuf */ 1052 m_new->m_ext.ext_arg = buf; 1053 m_new->m_ext.ext_buf = buf->nge_buf; 1054 m_new->m_ext.ext_free = nge_jfree; 1055 m_new->m_ext.ext_ref = nge_jref; 1056 m_new->m_ext.ext_size = NGE_JUMBO_FRAMELEN; 1057 1058 m_new->m_data = m_new->m_ext.ext_buf; 1059 m_new->m_flags |= M_EXT; 1060 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 1061 } else { 1062 m_new = m; 1063 m_new->m_len = m_new->m_pkthdr.len = NGE_JLEN; 1064 m_new->m_data = m_new->m_ext.ext_buf; 1065 } 1066 1067 m_adj(m_new, sizeof(uint64_t)); 1068 1069 c->nge_mbuf = m_new; 1070 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1071 c->nge_ctl = m_new->m_len; 1072 c->nge_extsts = 0; 1073 1074 return(0); 1075 } 1076 1077 static int 1078 nge_alloc_jumbo_mem(struct nge_softc *sc) 1079 { 1080 caddr_t ptr; 1081 int i; 1082 struct nge_jslot *entry; 1083 1084 /* Grab a big chunk o' storage. */ 1085 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF, 1086 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 1087 1088 if (sc->nge_cdata.nge_jumbo_buf == NULL) { 1089 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit); 1090 return(ENOBUFS); 1091 } 1092 1093 SLIST_INIT(&sc->nge_jfree_listhead); 1094 1095 /* 1096 * Now divide it up into 9K pieces and save the addresses 1097 * in an array. 1098 */ 1099 ptr = sc->nge_cdata.nge_jumbo_buf; 1100 for (i = 0; i < NGE_JSLOTS; i++) { 1101 entry = &sc->nge_cdata.nge_jslots[i]; 1102 entry->nge_sc = sc; 1103 entry->nge_buf = ptr; 1104 entry->nge_inuse = 0; 1105 entry->nge_slot = i; 1106 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jslot_link); 1107 ptr += NGE_JLEN; 1108 } 1109 1110 return(0); 1111 } 1112 1113 1114 /* 1115 * Allocate a jumbo buffer. 1116 */ 1117 static struct nge_jslot * 1118 nge_jalloc(struct nge_softc *sc) 1119 { 1120 struct nge_jslot *entry; 1121 1122 lwkt_serialize_enter(&sc->nge_jslot_serializer); 1123 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1124 if (entry) { 1125 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jslot_link); 1126 entry->nge_inuse = 1; 1127 } else { 1128 #ifdef NGE_VERBOSE 1129 printf("nge%d: no free jumbo buffers\n", sc->nge_unit); 1130 #endif 1131 } 1132 lwkt_serialize_exit(&sc->nge_jslot_serializer); 1133 return(entry); 1134 } 1135 1136 /* 1137 * Adjust usage count on a jumbo buffer. In general this doesn't 1138 * get used much because our jumbo buffers don't get passed around 1139 * a lot, but it's implemented for correctness. 1140 */ 1141 static void 1142 nge_jref(void *arg) 1143 { 1144 struct nge_jslot *entry = (struct nge_jslot *)arg; 1145 struct nge_softc *sc = entry->nge_sc; 1146 1147 if (sc == NULL) 1148 panic("nge_jref: can't find softc pointer!"); 1149 1150 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry) 1151 panic("nge_jref: asked to reference buffer " 1152 "that we don't manage!"); 1153 else if (entry->nge_inuse == 0) 1154 panic("nge_jref: buffer already free!"); 1155 else 1156 atomic_add_int(&entry->nge_inuse, 1); 1157 } 1158 1159 /* 1160 * Release a jumbo buffer. 1161 */ 1162 static void 1163 nge_jfree(void *arg) 1164 { 1165 struct nge_jslot *entry = (struct nge_jslot *)arg; 1166 struct nge_softc *sc = entry->nge_sc; 1167 1168 if (sc == NULL) 1169 panic("nge_jref: can't find softc pointer!"); 1170 1171 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry) { 1172 panic("nge_jref: asked to reference buffer " 1173 "that we don't manage!"); 1174 } else if (entry->nge_inuse == 0) { 1175 panic("nge_jref: buffer already free!"); 1176 } else { 1177 lwkt_serialize_enter(&sc->nge_jslot_serializer); 1178 atomic_subtract_int(&entry->nge_inuse, 1); 1179 if (entry->nge_inuse == 0) { 1180 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1181 entry, jslot_link); 1182 } 1183 lwkt_serialize_exit(&sc->nge_jslot_serializer); 1184 } 1185 } 1186 /* 1187 * A frame has been uploaded: pass the resulting mbuf chain up to 1188 * the higher level protocols. 1189 */ 1190 static void 1191 nge_rxeof(struct nge_softc *sc) 1192 { 1193 struct mbuf *m; 1194 struct ifnet *ifp = &sc->arpcom.ac_if; 1195 struct nge_desc *cur_rx; 1196 int i, total_len = 0; 1197 uint32_t rxstat; 1198 1199 i = sc->nge_cdata.nge_rx_prod; 1200 1201 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1202 struct mbuf *m0 = NULL; 1203 uint32_t extsts; 1204 1205 #ifdef DEVICE_POLLING 1206 if (ifp->if_flags & IFF_POLLING) { 1207 if (sc->rxcycles <= 0) 1208 break; 1209 sc->rxcycles--; 1210 } 1211 #endif /* DEVICE_POLLING */ 1212 1213 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1214 rxstat = cur_rx->nge_rxstat; 1215 extsts = cur_rx->nge_extsts; 1216 m = cur_rx->nge_mbuf; 1217 cur_rx->nge_mbuf = NULL; 1218 total_len = NGE_RXBYTES(cur_rx); 1219 NGE_INC(i, NGE_RX_LIST_CNT); 1220 /* 1221 * If an error occurs, update stats, clear the 1222 * status word and leave the mbuf cluster in place: 1223 * it should simply get re-used next time this descriptor 1224 * comes up in the ring. 1225 */ 1226 if ((rxstat & NGE_CMDSTS_PKT_OK) == 0) { 1227 ifp->if_ierrors++; 1228 nge_newbuf(sc, cur_rx, m); 1229 continue; 1230 } 1231 1232 /* 1233 * Ok. NatSemi really screwed up here. This is the 1234 * only gigE chip I know of with alignment constraints 1235 * on receive buffers. RX buffers must be 64-bit aligned. 1236 */ 1237 #ifdef __i386__ 1238 /* 1239 * By popular demand, ignore the alignment problems 1240 * on the Intel x86 platform. The performance hit 1241 * incurred due to unaligned accesses is much smaller 1242 * than the hit produced by forcing buffer copies all 1243 * the time, especially with jumbo frames. We still 1244 * need to fix up the alignment everywhere else though. 1245 */ 1246 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 1247 #endif 1248 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1249 total_len + ETHER_ALIGN, 0, ifp, NULL); 1250 nge_newbuf(sc, cur_rx, m); 1251 if (m0 == NULL) { 1252 printf("nge%d: no receive buffers " 1253 "available -- packet dropped!\n", 1254 sc->nge_unit); 1255 ifp->if_ierrors++; 1256 continue; 1257 } 1258 m_adj(m0, ETHER_ALIGN); 1259 m = m0; 1260 #ifdef __i386__ 1261 } else { 1262 m->m_pkthdr.rcvif = ifp; 1263 m->m_pkthdr.len = m->m_len = total_len; 1264 } 1265 #endif 1266 1267 ifp->if_ipackets++; 1268 1269 /* Do IP checksum checking. */ 1270 if (extsts & NGE_RXEXTSTS_IPPKT) 1271 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1272 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1273 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1274 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1275 (extsts & NGE_RXEXTSTS_TCPCSUMERR) == 0) || 1276 (extsts & NGE_RXEXTSTS_UDPPKT && 1277 (extsts & NGE_RXEXTSTS_UDPCSUMERR) == 0)) { 1278 m->m_pkthdr.csum_flags |= 1279 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1280 m->m_pkthdr.csum_data = 0xffff; 1281 } 1282 1283 /* 1284 * If we received a packet with a vlan tag, pass it 1285 * to vlan_input() instead of ether_input(). 1286 */ 1287 if (extsts & NGE_RXEXTSTS_VLANPKT) 1288 VLAN_INPUT_TAG(m, extsts & NGE_RXEXTSTS_VTCI); 1289 else 1290 ifp->if_input(ifp, m); 1291 } 1292 1293 sc->nge_cdata.nge_rx_prod = i; 1294 } 1295 1296 /* 1297 * A frame was downloaded to the chip. It's safe for us to clean up 1298 * the list buffers. 1299 */ 1300 static void 1301 nge_txeof(struct nge_softc *sc) 1302 { 1303 struct ifnet *ifp = &sc->arpcom.ac_if; 1304 struct nge_desc *cur_tx = NULL; 1305 uint32_t idx; 1306 1307 /* Clear the timeout timer. */ 1308 ifp->if_timer = 0; 1309 1310 /* 1311 * Go through our tx list and free mbufs for those 1312 * frames that have been transmitted. 1313 */ 1314 idx = sc->nge_cdata.nge_tx_cons; 1315 while (idx != sc->nge_cdata.nge_tx_prod) { 1316 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1317 1318 if (NGE_OWNDESC(cur_tx)) 1319 break; 1320 1321 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1322 sc->nge_cdata.nge_tx_cnt--; 1323 NGE_INC(idx, NGE_TX_LIST_CNT); 1324 continue; 1325 } 1326 1327 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1328 ifp->if_oerrors++; 1329 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1330 ifp->if_collisions++; 1331 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1332 ifp->if_collisions++; 1333 } 1334 1335 ifp->if_collisions += 1336 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1337 1338 ifp->if_opackets++; 1339 if (cur_tx->nge_mbuf != NULL) { 1340 m_freem(cur_tx->nge_mbuf); 1341 cur_tx->nge_mbuf = NULL; 1342 } 1343 1344 sc->nge_cdata.nge_tx_cnt--; 1345 NGE_INC(idx, NGE_TX_LIST_CNT); 1346 ifp->if_timer = 0; 1347 } 1348 1349 sc->nge_cdata.nge_tx_cons = idx; 1350 1351 if (cur_tx != NULL) 1352 ifp->if_flags &= ~IFF_OACTIVE; 1353 } 1354 1355 static void 1356 nge_tick(void *xsc) 1357 { 1358 struct nge_softc *sc = xsc; 1359 struct ifnet *ifp = &sc->arpcom.ac_if; 1360 struct mii_data *mii; 1361 1362 lwkt_serialize_enter(ifp->if_serializer); 1363 1364 if (sc->nge_tbi) { 1365 if (sc->nge_link == 0) { 1366 if (CSR_READ_4(sc, NGE_TBI_BMSR) 1367 & NGE_TBIBMSR_ANEG_DONE) { 1368 printf("nge%d: gigabit link up\n", 1369 sc->nge_unit); 1370 nge_miibus_statchg(sc->nge_miibus); 1371 sc->nge_link++; 1372 if (!ifq_is_empty(&ifp->if_snd)) 1373 nge_start(ifp); 1374 } 1375 } 1376 } else { 1377 mii = device_get_softc(sc->nge_miibus); 1378 mii_tick(mii); 1379 1380 if (sc->nge_link == 0) { 1381 if (mii->mii_media_status & IFM_ACTIVE && 1382 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1383 sc->nge_link++; 1384 if (IFM_SUBTYPE(mii->mii_media_active) 1385 == IFM_1000_T) 1386 printf("nge%d: gigabit link up\n", 1387 sc->nge_unit); 1388 if (!ifq_is_empty(&ifp->if_snd)) 1389 nge_start(ifp); 1390 } 1391 } 1392 } 1393 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc); 1394 1395 lwkt_serialize_exit(ifp->if_serializer); 1396 } 1397 1398 #ifdef DEVICE_POLLING 1399 1400 static void 1401 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1402 { 1403 struct nge_softc *sc = ifp->if_softc; 1404 1405 switch(cmd) { 1406 case POLL_REGISTER: 1407 /* disable interrupts */ 1408 CSR_WRITE_4(sc, NGE_IER, 0); 1409 break; 1410 case POLL_DEREGISTER: 1411 /* enable interrupts */ 1412 CSR_WRITE_4(sc, NGE_IER, 1); 1413 break; 1414 default: 1415 /* 1416 * On the nge, reading the status register also clears it. 1417 * So before returning to intr mode we must make sure that all 1418 * possible pending sources of interrupts have been served. 1419 * In practice this means run to completion the *eof routines, 1420 * and then call the interrupt routine 1421 */ 1422 sc->rxcycles = count; 1423 nge_rxeof(sc); 1424 nge_txeof(sc); 1425 if (!ifq_is_empty(&ifp->if_snd)) 1426 nge_start(ifp); 1427 1428 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1429 uint32_t status; 1430 1431 /* Reading the ISR register clears all interrupts. */ 1432 status = CSR_READ_4(sc, NGE_ISR); 1433 1434 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) 1435 nge_rxeof(sc); 1436 1437 if (status & (NGE_ISR_RX_IDLE)) 1438 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1439 1440 if (status & NGE_ISR_SYSERR) { 1441 nge_reset(sc); 1442 nge_init(sc); 1443 } 1444 } 1445 break; 1446 } 1447 } 1448 1449 #endif /* DEVICE_POLLING */ 1450 1451 static void 1452 nge_intr(void *arg) 1453 { 1454 struct nge_softc *sc = arg; 1455 struct ifnet *ifp = &sc->arpcom.ac_if; 1456 uint32_t status; 1457 1458 /* Supress unwanted interrupts */ 1459 if (!(ifp->if_flags & IFF_UP)) { 1460 nge_stop(sc); 1461 return; 1462 } 1463 1464 /* Disable interrupts. */ 1465 CSR_WRITE_4(sc, NGE_IER, 0); 1466 1467 /* Data LED on for TBI mode */ 1468 if(sc->nge_tbi) 1469 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1470 | NGE_GPIO_GP3_OUT); 1471 1472 for (;;) { 1473 /* Reading the ISR register clears all interrupts. */ 1474 status = CSR_READ_4(sc, NGE_ISR); 1475 1476 if ((status & NGE_INTRS) == 0) 1477 break; 1478 1479 if ((status & NGE_ISR_TX_DESC_OK) || 1480 (status & NGE_ISR_TX_ERR) || 1481 (status & NGE_ISR_TX_OK) || 1482 (status & NGE_ISR_TX_IDLE)) 1483 nge_txeof(sc); 1484 1485 if ((status & NGE_ISR_RX_DESC_OK) || 1486 (status & NGE_ISR_RX_ERR) || 1487 (status & NGE_ISR_RX_OFLOW) || 1488 (status & NGE_ISR_RX_FIFO_OFLOW) || 1489 (status & NGE_ISR_RX_IDLE) || 1490 (status & NGE_ISR_RX_OK)) 1491 nge_rxeof(sc); 1492 1493 if ((status & NGE_ISR_RX_IDLE)) 1494 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1495 1496 if (status & NGE_ISR_SYSERR) { 1497 nge_reset(sc); 1498 ifp->if_flags &= ~IFF_RUNNING; 1499 nge_init(sc); 1500 } 1501 1502 #ifdef notyet 1503 /* mii_tick should only be called once per second */ 1504 if (status & NGE_ISR_PHY_INTR) { 1505 sc->nge_link = 0; 1506 nge_tick_serialized(sc); 1507 } 1508 #endif 1509 } 1510 1511 /* Re-enable interrupts. */ 1512 CSR_WRITE_4(sc, NGE_IER, 1); 1513 1514 if (!ifq_is_empty(&ifp->if_snd)) 1515 nge_start(ifp); 1516 1517 /* Data LED off for TBI mode */ 1518 1519 if(sc->nge_tbi) 1520 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1521 & ~NGE_GPIO_GP3_OUT); 1522 } 1523 1524 /* 1525 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1526 * pointers to the fragment pointers. 1527 */ 1528 static int 1529 nge_encap(struct nge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1530 { 1531 struct nge_desc *f = NULL; 1532 struct mbuf *m; 1533 int frag, cur, cnt = 0; 1534 struct ifvlan *ifv = NULL; 1535 1536 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1537 m_head->m_pkthdr.rcvif != NULL && 1538 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 1539 ifv = m_head->m_pkthdr.rcvif->if_softc; 1540 1541 /* 1542 * Start packing the mbufs in this chain into 1543 * the fragment pointers. Stop when we run out 1544 * of fragments or hit the end of the mbuf chain. 1545 */ 1546 m = m_head; 1547 cur = frag = *txidx; 1548 1549 for (m = m_head; m != NULL; m = m->m_next) { 1550 if (m->m_len != 0) { 1551 if ((NGE_TX_LIST_CNT - 1552 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1553 return(ENOBUFS); 1554 f = &sc->nge_ldata->nge_tx_list[frag]; 1555 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1556 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1557 if (cnt != 0) 1558 f->nge_ctl |= NGE_CMDSTS_OWN; 1559 cur = frag; 1560 NGE_INC(frag, NGE_TX_LIST_CNT); 1561 cnt++; 1562 } 1563 } 1564 1565 if (m != NULL) 1566 return(ENOBUFS); 1567 1568 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1569 if (m_head->m_pkthdr.csum_flags) { 1570 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1571 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1572 NGE_TXEXTSTS_IPCSUM; 1573 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1574 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1575 NGE_TXEXTSTS_TCPCSUM; 1576 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1577 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1578 NGE_TXEXTSTS_UDPCSUM; 1579 } 1580 1581 if (ifv != NULL) { 1582 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1583 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag); 1584 } 1585 1586 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1587 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1588 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1589 sc->nge_cdata.nge_tx_cnt += cnt; 1590 *txidx = frag; 1591 1592 return(0); 1593 } 1594 1595 /* 1596 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1597 * to the mbuf data regions directly in the transmit lists. We also save a 1598 * copy of the pointers since the transmit list fragment pointers are 1599 * physical addresses. 1600 */ 1601 1602 static void 1603 nge_start(struct ifnet *ifp) 1604 { 1605 struct nge_softc *sc = ifp->if_softc; 1606 struct mbuf *m_head = NULL; 1607 uint32_t idx; 1608 int need_trans; 1609 1610 if (!sc->nge_link) 1611 return; 1612 1613 idx = sc->nge_cdata.nge_tx_prod; 1614 1615 if (ifp->if_flags & IFF_OACTIVE) 1616 return; 1617 1618 need_trans = 0; 1619 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1620 m_head = ifq_poll(&ifp->if_snd); 1621 if (m_head == NULL) 1622 break; 1623 1624 if (nge_encap(sc, m_head, &idx)) { 1625 ifp->if_flags |= IFF_OACTIVE; 1626 break; 1627 } 1628 ifq_dequeue(&ifp->if_snd, m_head); 1629 need_trans = 1; 1630 1631 BPF_MTAP(ifp, m_head); 1632 } 1633 1634 if (!need_trans) 1635 return; 1636 1637 /* Transmit */ 1638 sc->nge_cdata.nge_tx_prod = idx; 1639 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1640 1641 /* 1642 * Set a timeout in case the chip goes out to lunch. 1643 */ 1644 ifp->if_timer = 5; 1645 } 1646 1647 static void 1648 nge_init(void *xsc) 1649 { 1650 struct nge_softc *sc = xsc; 1651 struct ifnet *ifp = &sc->arpcom.ac_if; 1652 struct mii_data *mii; 1653 1654 if (ifp->if_flags & IFF_RUNNING) { 1655 return; 1656 } 1657 1658 /* 1659 * Cancel pending I/O and free all RX/TX buffers. 1660 */ 1661 nge_stop(sc); 1662 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc); 1663 1664 if (sc->nge_tbi) 1665 mii = NULL; 1666 else 1667 mii = device_get_softc(sc->nge_miibus); 1668 1669 /* Set MAC address */ 1670 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1671 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1672 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1673 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1674 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1675 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1676 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1677 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1678 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1679 1680 /* Init circular RX list. */ 1681 if (nge_list_rx_init(sc) == ENOBUFS) { 1682 printf("nge%d: initialization failed: no " 1683 "memory for rx buffers\n", sc->nge_unit); 1684 nge_stop(sc); 1685 return; 1686 } 1687 1688 /* 1689 * Init tx descriptors. 1690 */ 1691 nge_list_tx_init(sc); 1692 1693 /* 1694 * For the NatSemi chip, we have to explicitly enable the 1695 * reception of ARP frames, as well as turn on the 'perfect 1696 * match' filter where we store the station address, otherwise 1697 * we won't receive unicasts meant for this host. 1698 */ 1699 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1700 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1701 1702 /* If we want promiscuous mode, set the allframes bit. */ 1703 if (ifp->if_flags & IFF_PROMISC) 1704 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1705 else 1706 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1707 1708 /* 1709 * Set the capture broadcast bit to capture broadcast frames. 1710 */ 1711 if (ifp->if_flags & IFF_BROADCAST) 1712 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1713 else 1714 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1715 1716 /* 1717 * Load the multicast filter. 1718 */ 1719 nge_setmulti(sc); 1720 1721 /* Turn the receive filter on */ 1722 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1723 1724 /* 1725 * Load the address of the RX and TX lists. 1726 */ 1727 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1728 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1729 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1730 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1731 1732 /* Set RX configuration */ 1733 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1734 /* 1735 * Enable hardware checksum validation for all IPv4 1736 * packets, do not reject packets with bad checksums. 1737 */ 1738 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1739 1740 /* 1741 * Tell the chip to detect and strip VLAN tag info from 1742 * received frames. The tag will be provided in the extsts 1743 * field in the RX descriptors. 1744 */ 1745 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1746 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1747 1748 /* Set TX configuration */ 1749 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1750 1751 /* 1752 * Enable TX IPv4 checksumming on a per-packet basis. 1753 */ 1754 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1755 1756 /* 1757 * Tell the chip to insert VLAN tags on a per-packet basis as 1758 * dictated by the code in the frame encapsulation routine. 1759 */ 1760 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1761 1762 /* Set full/half duplex mode. */ 1763 if (sc->nge_tbi) { 1764 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1765 == IFM_FDX) { 1766 NGE_SETBIT(sc, NGE_TX_CFG, 1767 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 1768 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1769 } else { 1770 NGE_CLRBIT(sc, NGE_TX_CFG, 1771 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 1772 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1773 } 1774 } else { 1775 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1776 NGE_SETBIT(sc, NGE_TX_CFG, 1777 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 1778 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1779 } else { 1780 NGE_CLRBIT(sc, NGE_TX_CFG, 1781 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 1782 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1783 } 1784 } 1785 1786 /* 1787 * Enable the delivery of PHY interrupts based on 1788 * link/speed/duplex status changes. Also enable the 1789 * extsts field in the DMA descriptors (needed for 1790 * TCP/IP checksum offload on transmit). 1791 */ 1792 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD | 1793 NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB); 1794 1795 /* 1796 * Configure interrupt holdoff (moderation). We can 1797 * have the chip delay interrupt delivery for a certain 1798 * period. Units are in 100us, and the max setting 1799 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 1800 */ 1801 CSR_WRITE_4(sc, NGE_IHR, 0x01); 1802 1803 /* 1804 * Enable interrupts. 1805 */ 1806 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1807 #ifdef DEVICE_POLLING 1808 /* 1809 * ... only enable interrupts if we are not polling, make sure 1810 * they are off otherwise. 1811 */ 1812 if (ifp->if_flags & IFF_POLLING) 1813 CSR_WRITE_4(sc, NGE_IER, 0); 1814 else 1815 #endif /* DEVICE_POLLING */ 1816 CSR_WRITE_4(sc, NGE_IER, 1); 1817 1818 /* Enable receiver and transmitter. */ 1819 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE); 1820 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1821 1822 nge_ifmedia_upd(ifp); 1823 1824 ifp->if_flags |= IFF_RUNNING; 1825 ifp->if_flags &= ~IFF_OACTIVE; 1826 } 1827 1828 /* 1829 * Set media options. 1830 */ 1831 static int 1832 nge_ifmedia_upd(struct ifnet *ifp) 1833 { 1834 struct nge_softc *sc = ifp->if_softc; 1835 struct mii_data *mii; 1836 1837 if (sc->nge_tbi) { 1838 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1839 == IFM_AUTO) { 1840 CSR_WRITE_4(sc, NGE_TBI_ANAR, 1841 CSR_READ_4(sc, NGE_TBI_ANAR) 1842 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX 1843 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2); 1844 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG 1845 | NGE_TBIBMCR_RESTART_ANEG); 1846 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG); 1847 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media 1848 & IFM_GMASK) == IFM_FDX) { 1849 NGE_SETBIT(sc, NGE_TX_CFG, 1850 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1851 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1852 1853 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 1854 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 1855 } else { 1856 NGE_CLRBIT(sc, NGE_TX_CFG, 1857 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1858 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1859 1860 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 1861 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 1862 } 1863 1864 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1865 & ~NGE_GPIO_GP3_OUT); 1866 } else { 1867 mii = device_get_softc(sc->nge_miibus); 1868 sc->nge_link = 0; 1869 if (mii->mii_instance) { 1870 struct mii_softc *miisc; 1871 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1872 miisc = LIST_NEXT(miisc, mii_list)) 1873 mii_phy_reset(miisc); 1874 } 1875 mii_mediachg(mii); 1876 } 1877 1878 return(0); 1879 } 1880 1881 /* 1882 * Report current media status. 1883 */ 1884 static void 1885 nge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1886 { 1887 struct nge_softc *sc = ifp->if_softc; 1888 struct mii_data *mii; 1889 1890 if (sc->nge_tbi) { 1891 ifmr->ifm_status = IFM_AVALID; 1892 ifmr->ifm_active = IFM_ETHER; 1893 1894 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) 1895 ifmr->ifm_status |= IFM_ACTIVE; 1896 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK) 1897 ifmr->ifm_active |= IFM_LOOP; 1898 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 1899 ifmr->ifm_active |= IFM_NONE; 1900 ifmr->ifm_status = 0; 1901 return; 1902 } 1903 ifmr->ifm_active |= IFM_1000_SX; 1904 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1905 == IFM_AUTO) { 1906 ifmr->ifm_active |= IFM_AUTO; 1907 if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 1908 & NGE_TBIANAR_FDX) { 1909 ifmr->ifm_active |= IFM_FDX; 1910 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 1911 & NGE_TBIANAR_HDX) { 1912 ifmr->ifm_active |= IFM_HDX; 1913 } 1914 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1915 == IFM_FDX) 1916 ifmr->ifm_active |= IFM_FDX; 1917 else 1918 ifmr->ifm_active |= IFM_HDX; 1919 1920 } else { 1921 mii = device_get_softc(sc->nge_miibus); 1922 mii_pollstat(mii); 1923 ifmr->ifm_active = mii->mii_media_active; 1924 ifmr->ifm_status = mii->mii_media_status; 1925 } 1926 } 1927 1928 static int 1929 nge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1930 { 1931 struct nge_softc *sc = ifp->if_softc; 1932 struct ifreq *ifr = (struct ifreq *) data; 1933 struct mii_data *mii; 1934 int error = 0; 1935 1936 switch(command) { 1937 case SIOCSIFMTU: 1938 if (ifr->ifr_mtu > NGE_JUMBO_MTU) { 1939 error = EINVAL; 1940 } else { 1941 ifp->if_mtu = ifr->ifr_mtu; 1942 /* 1943 * Workaround: if the MTU is larger than 1944 * 8152 (TX FIFO size minus 64 minus 18), turn off 1945 * TX checksum offloading. 1946 */ 1947 if (ifr->ifr_mtu >= 8152) 1948 ifp->if_hwassist = 0; 1949 else 1950 ifp->if_hwassist = NGE_CSUM_FEATURES; 1951 } 1952 break; 1953 case SIOCSIFFLAGS: 1954 if (ifp->if_flags & IFF_UP) { 1955 if (ifp->if_flags & IFF_RUNNING && 1956 ifp->if_flags & IFF_PROMISC && 1957 !(sc->nge_if_flags & IFF_PROMISC)) { 1958 NGE_SETBIT(sc, NGE_RXFILT_CTL, 1959 NGE_RXFILTCTL_ALLPHYS| 1960 NGE_RXFILTCTL_ALLMULTI); 1961 } else if (ifp->if_flags & IFF_RUNNING && 1962 !(ifp->if_flags & IFF_PROMISC) && 1963 sc->nge_if_flags & IFF_PROMISC) { 1964 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1965 NGE_RXFILTCTL_ALLPHYS); 1966 if (!(ifp->if_flags & IFF_ALLMULTI)) 1967 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1968 NGE_RXFILTCTL_ALLMULTI); 1969 } else { 1970 ifp->if_flags &= ~IFF_RUNNING; 1971 nge_init(sc); 1972 } 1973 } else { 1974 if (ifp->if_flags & IFF_RUNNING) 1975 nge_stop(sc); 1976 } 1977 sc->nge_if_flags = ifp->if_flags; 1978 error = 0; 1979 break; 1980 case SIOCADDMULTI: 1981 case SIOCDELMULTI: 1982 nge_setmulti(sc); 1983 error = 0; 1984 break; 1985 case SIOCGIFMEDIA: 1986 case SIOCSIFMEDIA: 1987 if (sc->nge_tbi) { 1988 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, 1989 command); 1990 } else { 1991 mii = device_get_softc(sc->nge_miibus); 1992 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1993 command); 1994 } 1995 break; 1996 default: 1997 error = ether_ioctl(ifp, command, data); 1998 break; 1999 } 2000 return(error); 2001 } 2002 2003 static void 2004 nge_watchdog(struct ifnet *ifp) 2005 { 2006 struct nge_softc *sc = ifp->if_softc; 2007 2008 ifp->if_oerrors++; 2009 printf("nge%d: watchdog timeout\n", sc->nge_unit); 2010 2011 nge_stop(sc); 2012 nge_reset(sc); 2013 ifp->if_flags &= ~IFF_RUNNING; 2014 nge_init(sc); 2015 2016 if (!ifq_is_empty(&ifp->if_snd)) 2017 nge_start(ifp); 2018 } 2019 2020 /* 2021 * Stop the adapter and free any mbufs allocated to the 2022 * RX and TX lists. 2023 */ 2024 static void 2025 nge_stop(struct nge_softc *sc) 2026 { 2027 struct ifnet *ifp = &sc->arpcom.ac_if; 2028 struct ifmedia_entry *ifm; 2029 struct mii_data *mii; 2030 int i, itmp, mtmp; 2031 2032 ifp->if_timer = 0; 2033 if (sc->nge_tbi) 2034 mii = NULL; 2035 else 2036 mii = device_get_softc(sc->nge_miibus); 2037 2038 callout_stop(&sc->nge_stat_timer); 2039 CSR_WRITE_4(sc, NGE_IER, 0); 2040 CSR_WRITE_4(sc, NGE_IMR, 0); 2041 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2042 DELAY(1000); 2043 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 2044 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 2045 2046 /* 2047 * Isolate/power down the PHY, but leave the media selection 2048 * unchanged so that things will be put back to normal when 2049 * we bring the interface back up. 2050 */ 2051 itmp = ifp->if_flags; 2052 ifp->if_flags |= IFF_UP; 2053 2054 if (sc->nge_tbi) 2055 ifm = sc->nge_ifmedia.ifm_cur; 2056 else 2057 ifm = mii->mii_media.ifm_cur; 2058 2059 mtmp = ifm->ifm_media; 2060 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2061 2062 if (!sc->nge_tbi) 2063 mii_mediachg(mii); 2064 ifm->ifm_media = mtmp; 2065 ifp->if_flags = itmp; 2066 2067 sc->nge_link = 0; 2068 2069 /* 2070 * Free data in the RX lists. 2071 */ 2072 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2073 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2074 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2075 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2076 } 2077 } 2078 bzero(&sc->nge_ldata->nge_rx_list, 2079 sizeof(sc->nge_ldata->nge_rx_list)); 2080 2081 /* 2082 * Free the TX list buffers. 2083 */ 2084 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2085 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2086 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2087 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2088 } 2089 } 2090 2091 bzero(&sc->nge_ldata->nge_tx_list, 2092 sizeof(sc->nge_ldata->nge_tx_list)); 2093 2094 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2095 } 2096 2097 /* 2098 * Stop all chip I/O so that the kernel's probe routines don't 2099 * get confused by errant DMAs when rebooting. 2100 */ 2101 static void 2102 nge_shutdown(device_t dev) 2103 { 2104 struct nge_softc *sc = device_get_softc(dev); 2105 struct ifnet *ifp = &sc->arpcom.ac_if; 2106 2107 lwkt_serialize_enter(ifp->if_serializer); 2108 nge_reset(sc); 2109 nge_stop(sc); 2110 lwkt_serialize_exit(ifp->if_serializer); 2111 } 2112 2113