1 /*- 2 * Copyright (C) 2012 Emulex 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Emulex Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Contact Information: 32 * freebsd-drivers@emulex.com 33 * 34 * Emulex 35 * 3333 Susan Street 36 * Costa Mesa, CA 92626 37 */ 38 39 40 /* $FreeBSD: src/sys/dev/oce/oce_if.c,v 1.13 2013/03/07 00:29:47 svnexp Exp $ */ 41 42 #include "opt_inet6.h" 43 #include "opt_inet.h" 44 45 #include "oce_if.h" 46 47 48 /* Driver entry points prototypes */ 49 static int oce_probe(device_t dev); 50 static int oce_attach(device_t dev); 51 static int oce_detach(device_t dev); 52 static int oce_shutdown(device_t dev); 53 static int oce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr); 54 static void oce_init(void *xsc); 55 #if 0 /* XXX swildner: MULTIQUEUE */ 56 static int oce_multiq_start(struct ifnet *ifp, struct mbuf *m); 57 static void oce_multiq_flush(struct ifnet *ifp); 58 #endif 59 60 /* Driver interrupt routines protypes */ 61 static void oce_intr(void *arg, int pending); 62 static int oce_setup_intr(POCE_SOFTC sc); 63 static void oce_fast_isr(void *arg); 64 static int oce_alloc_intr(POCE_SOFTC sc, int vector, 65 void (*isr) (void *arg, int pending)); 66 67 /* Media callbacks prototypes */ 68 static void oce_media_status(struct ifnet *ifp, struct ifmediareq *req); 69 static int oce_media_change(struct ifnet *ifp); 70 71 /* Transmit routines prototypes */ 72 static int oce_tx(POCE_SOFTC sc, struct mbuf **mpp, int wq_index); 73 static void oce_tx_restart(POCE_SOFTC sc, struct oce_wq *wq); 74 static void oce_tx_complete(struct oce_wq *wq, uint32_t wqe_idx, 75 uint32_t status); 76 #if 0 /* XXX swildner: MULTIQUEUE */ 77 static int oce_multiq_transmit(struct ifnet *ifp, struct mbuf *m, 78 struct oce_wq *wq); 79 #endif 80 81 /* Receive routines prototypes */ 82 static void oce_discard_rx_comp(struct oce_rq *rq, struct oce_nic_rx_cqe *cqe); 83 #if 0 /* XXX swildner: ETHER_VTAG */ 84 static int oce_cqe_vtp_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe); 85 #endif 86 static int oce_cqe_portid_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe); 87 static void oce_rx(struct oce_rq *rq, uint32_t rqe_idx, 88 struct oce_nic_rx_cqe *cqe); 89 90 /* Helper function prototypes in this file */ 91 static int oce_attach_ifp(POCE_SOFTC sc); 92 static void oce_add_vlan(void *arg, struct ifnet *ifp, uint16_t vtag); 93 static void oce_del_vlan(void *arg, struct ifnet *ifp, uint16_t vtag); 94 static int oce_vid_config(POCE_SOFTC sc); 95 static void oce_mac_addr_set(POCE_SOFTC sc); 96 static int oce_handle_passthrough(struct ifnet *ifp, caddr_t data); 97 static void oce_local_timer(void *arg); 98 static void oce_if_deactivate(POCE_SOFTC sc); 99 static void oce_if_activate(POCE_SOFTC sc); 100 static void setup_max_queues_want(POCE_SOFTC sc); 101 static void update_queues_got(POCE_SOFTC sc); 102 static void process_link_state(POCE_SOFTC sc, 103 struct oce_async_cqe_link_state *acqe); 104 static int oce_tx_asic_stall_verify(POCE_SOFTC sc, struct mbuf *m); 105 static struct mbuf *oce_insert_vlan_tag(POCE_SOFTC sc, struct mbuf *m, boolean_t *complete); 106 107 /* IP specific */ 108 #if defined(INET6) || defined(INET) 109 #if 0 /* XXX swildner: LRO */ 110 static int oce_init_lro(POCE_SOFTC sc); 111 static void oce_rx_flush_lro(struct oce_rq *rq); 112 #endif 113 static struct mbuf * oce_tso_setup(POCE_SOFTC sc, struct mbuf **mpp); 114 #endif 115 116 static device_method_t oce_dispatch[] = { 117 DEVMETHOD(device_probe, oce_probe), 118 DEVMETHOD(device_attach, oce_attach), 119 DEVMETHOD(device_detach, oce_detach), 120 DEVMETHOD(device_shutdown, oce_shutdown), 121 122 DEVMETHOD_END 123 }; 124 125 static driver_t oce_driver = { 126 "oce", 127 oce_dispatch, 128 sizeof(OCE_SOFTC) 129 }; 130 static devclass_t oce_devclass; 131 132 133 DRIVER_MODULE(oce, pci, oce_driver, oce_devclass, 0, 0); 134 MODULE_DEPEND(oce, pci, 1, 1, 1); 135 MODULE_DEPEND(oce, ether, 1, 1, 1); 136 MODULE_VERSION(oce, 1); 137 138 139 /* global vars */ 140 const char component_revision[32] = {"///" COMPONENT_REVISION "///"}; 141 142 /* Module capabilites and parameters */ 143 uint32_t oce_max_rsp_handled = OCE_MAX_RSP_HANDLED; 144 #if 0 /* XXX swildner: RSS */ 145 uint32_t oce_enable_rss = OCE_MODCAP_RSS; 146 #else 147 uint32_t oce_enable_rss = 0; 148 #endif 149 150 151 TUNABLE_INT("hw.oce.max_rsp_handled", &oce_max_rsp_handled); 152 TUNABLE_INT("hw.oce.enable_rss", &oce_enable_rss); 153 154 155 /* Supported devices table */ 156 static uint32_t supportedDevices[] = { 157 (PCI_VENDOR_SERVERENGINES << 16) | PCI_PRODUCT_BE2, 158 (PCI_VENDOR_SERVERENGINES << 16) | PCI_PRODUCT_BE3, 159 (PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_BE3, 160 (PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_XE201, 161 (PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_XE201_VF, 162 }; 163 164 165 166 167 /***************************************************************************** 168 * Driver entry points functions * 169 *****************************************************************************/ 170 171 static int 172 oce_probe(device_t dev) 173 { 174 uint16_t vendor = 0; 175 uint16_t device = 0; 176 int i = 0; 177 char str[256] = {0}; 178 POCE_SOFTC sc; 179 180 sc = device_get_softc(dev); 181 bzero(sc, sizeof(OCE_SOFTC)); 182 sc->dev = dev; 183 184 vendor = pci_get_vendor(dev); 185 device = pci_get_device(dev); 186 187 for (i = 0; i < (sizeof(supportedDevices) / sizeof(uint32_t)); i++) { 188 if (vendor == ((supportedDevices[i] >> 16) & 0xffff)) { 189 if (device == (supportedDevices[i] & 0xffff)) { 190 ksprintf(str, "%s:%s", "Emulex CNA NIC function", 191 component_revision); 192 device_set_desc_copy(dev, str); 193 194 switch (device) { 195 case PCI_PRODUCT_BE2: 196 sc->flags |= OCE_FLAGS_BE2; 197 break; 198 case PCI_PRODUCT_BE3: 199 sc->flags |= OCE_FLAGS_BE3; 200 break; 201 case PCI_PRODUCT_XE201: 202 case PCI_PRODUCT_XE201_VF: 203 sc->flags |= OCE_FLAGS_XE201; 204 break; 205 default: 206 return ENXIO; 207 } 208 return BUS_PROBE_DEFAULT; 209 } 210 } 211 } 212 213 return ENXIO; 214 } 215 216 217 static int 218 oce_attach(device_t dev) 219 { 220 POCE_SOFTC sc; 221 int rc = 0; 222 223 sc = device_get_softc(dev); 224 225 rc = oce_hw_pci_alloc(sc); 226 if (rc) 227 return rc; 228 229 sc->rss_enable = oce_enable_rss; 230 sc->tx_ring_size = OCE_TX_RING_SIZE; 231 sc->rx_ring_size = OCE_RX_RING_SIZE; 232 sc->rq_frag_size = OCE_RQ_BUF_SIZE; 233 sc->flow_control = OCE_DEFAULT_FLOW_CONTROL; 234 sc->promisc = OCE_DEFAULT_PROMISCUOUS; 235 236 LOCK_CREATE(&sc->bmbx_lock, "Mailbox_lock"); 237 LOCK_CREATE(&sc->dev_lock, "Device_lock"); 238 239 /* initialise the hardware */ 240 rc = oce_hw_init(sc); 241 if (rc) 242 goto pci_res_free; 243 244 setup_max_queues_want(sc); 245 246 rc = oce_setup_intr(sc); 247 if (rc) 248 goto mbox_free; 249 250 rc = oce_queue_init_all(sc); 251 if (rc) 252 goto intr_free; 253 254 rc = oce_attach_ifp(sc); 255 if (rc) 256 goto queues_free; 257 258 #if defined(INET6) || defined(INET) 259 #if 0 /* XXX swildner: LRO */ 260 rc = oce_init_lro(sc); 261 if (rc) 262 goto ifp_free; 263 #endif 264 #endif 265 266 rc = oce_hw_start(sc); 267 if (rc) 268 goto lro_free; 269 270 sc->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 271 oce_add_vlan, sc, EVENTHANDLER_PRI_FIRST); 272 sc->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 273 oce_del_vlan, sc, EVENTHANDLER_PRI_FIRST); 274 275 rc = oce_stats_init(sc); 276 if (rc) 277 goto vlan_free; 278 279 sysctl_ctx_init(&sc->sysctl_ctx); 280 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 281 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 282 device_get_nameunit(sc->dev), CTLFLAG_RD, 0, ""); 283 if (sc->sysctl_tree == NULL) { 284 device_printf(sc->dev, "cannot add sysctl tree node\n"); 285 rc = ENXIO; 286 goto vlan_free; 287 } 288 oce_add_sysctls(sc); 289 290 callout_init_mp(&sc->timer); 291 callout_reset(&sc->timer, 2 * hz, oce_local_timer, sc); 292 293 return 0; 294 295 vlan_free: 296 if (sc->vlan_attach) 297 EVENTHANDLER_DEREGISTER(vlan_config, sc->vlan_attach); 298 if (sc->vlan_detach) 299 EVENTHANDLER_DEREGISTER(vlan_unconfig, sc->vlan_detach); 300 oce_hw_intr_disable(sc); 301 lro_free: 302 #if defined(INET6) || defined(INET) 303 #if 0 /* XXX swildner: LRO */ 304 oce_free_lro(sc); 305 ifp_free: 306 #endif 307 #endif 308 ether_ifdetach(sc->ifp); 309 if_free(sc->ifp); 310 queues_free: 311 oce_queue_release_all(sc); 312 intr_free: 313 oce_intr_free(sc); 314 mbox_free: 315 oce_dma_free(sc, &sc->bsmbx); 316 pci_res_free: 317 oce_hw_pci_free(sc); 318 LOCK_DESTROY(&sc->dev_lock); 319 LOCK_DESTROY(&sc->bmbx_lock); 320 return rc; 321 322 } 323 324 325 static int 326 oce_detach(device_t dev) 327 { 328 POCE_SOFTC sc = device_get_softc(dev); 329 330 LOCK(&sc->dev_lock); 331 oce_if_deactivate(sc); 332 UNLOCK(&sc->dev_lock); 333 334 callout_stop_sync(&sc->timer); 335 336 if (sc->vlan_attach != NULL) 337 EVENTHANDLER_DEREGISTER(vlan_config, sc->vlan_attach); 338 if (sc->vlan_detach != NULL) 339 EVENTHANDLER_DEREGISTER(vlan_unconfig, sc->vlan_detach); 340 341 ether_ifdetach(sc->ifp); 342 343 if_free(sc->ifp); 344 345 oce_hw_shutdown(sc); 346 347 bus_generic_detach(dev); 348 349 sysctl_ctx_free(&sc->sysctl_ctx); 350 return 0; 351 } 352 353 354 static int 355 oce_shutdown(device_t dev) 356 { 357 int rc; 358 359 rc = oce_detach(dev); 360 361 return rc; 362 } 363 364 365 static int 366 oce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 367 { 368 struct ifreq *ifr = (struct ifreq *)data; 369 POCE_SOFTC sc = ifp->if_softc; 370 int rc = 0; 371 uint32_t u; 372 373 switch (command) { 374 375 case SIOCGIFMEDIA: 376 rc = ifmedia_ioctl(ifp, ifr, &sc->media, command); 377 break; 378 379 case SIOCSIFMTU: 380 if (ifr->ifr_mtu > OCE_MAX_MTU) 381 rc = EINVAL; 382 else 383 ifp->if_mtu = ifr->ifr_mtu; 384 break; 385 386 case SIOCSIFFLAGS: 387 if (ifp->if_flags & IFF_UP) { 388 if (!(ifp->if_flags & IFF_RUNNING)) { 389 sc->ifp->if_flags |= IFF_RUNNING; 390 oce_init(sc); 391 } 392 device_printf(sc->dev, "Interface Up\n"); 393 } else { 394 LOCK(&sc->dev_lock); 395 396 sc->ifp->if_flags &= ~IFF_RUNNING; 397 ifq_clr_oactive(&ifp->if_snd); 398 oce_if_deactivate(sc); 399 400 UNLOCK(&sc->dev_lock); 401 402 device_printf(sc->dev, "Interface Down\n"); 403 } 404 405 if ((ifp->if_flags & IFF_PROMISC) && !sc->promisc) { 406 sc->promisc = TRUE; 407 oce_rxf_set_promiscuous(sc, sc->promisc); 408 } else if (!(ifp->if_flags & IFF_PROMISC) && sc->promisc) { 409 sc->promisc = FALSE; 410 oce_rxf_set_promiscuous(sc, sc->promisc); 411 } 412 413 break; 414 415 case SIOCADDMULTI: 416 case SIOCDELMULTI: 417 rc = oce_hw_update_multicast(sc); 418 if (rc) 419 device_printf(sc->dev, 420 "Update multicast address failed\n"); 421 break; 422 423 case SIOCSIFCAP: 424 u = ifr->ifr_reqcap ^ ifp->if_capenable; 425 426 if (u & IFCAP_TXCSUM) { 427 ifp->if_capenable ^= IFCAP_TXCSUM; 428 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 429 430 if (IFCAP_TSO & ifp->if_capenable && 431 !(IFCAP_TXCSUM & ifp->if_capenable)) { 432 ifp->if_capenable &= ~IFCAP_TSO; 433 ifp->if_hwassist &= ~CSUM_TSO; 434 if_printf(ifp, 435 "TSO disabled due to -txcsum.\n"); 436 } 437 } 438 439 if (u & IFCAP_RXCSUM) 440 ifp->if_capenable ^= IFCAP_RXCSUM; 441 442 if (u & IFCAP_TSO4) { 443 ifp->if_capenable ^= IFCAP_TSO4; 444 445 if (IFCAP_TSO & ifp->if_capenable) { 446 if (IFCAP_TXCSUM & ifp->if_capenable) 447 ifp->if_hwassist |= CSUM_TSO; 448 else { 449 ifp->if_capenable &= ~IFCAP_TSO; 450 ifp->if_hwassist &= ~CSUM_TSO; 451 if_printf(ifp, 452 "Enable txcsum first.\n"); 453 rc = EAGAIN; 454 } 455 } else 456 ifp->if_hwassist &= ~CSUM_TSO; 457 } 458 459 if (u & IFCAP_VLAN_HWTAGGING) 460 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 461 462 #if 0 /* XXX swildner: VLAN_HWFILTER */ 463 if (u & IFCAP_VLAN_HWFILTER) { 464 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER; 465 oce_vid_config(sc); 466 } 467 #endif 468 #if defined(INET6) || defined(INET) 469 #if 0 /* XXX swildner: LRO */ 470 if (u & IFCAP_LRO) 471 ifp->if_capenable ^= IFCAP_LRO; 472 #endif 473 #endif 474 475 break; 476 477 case SIOCGPRIVATE_0: 478 rc = oce_handle_passthrough(ifp, data); 479 break; 480 default: 481 rc = ether_ioctl(ifp, command, data); 482 break; 483 } 484 485 return rc; 486 } 487 488 489 static void 490 oce_init(void *arg) 491 { 492 POCE_SOFTC sc = arg; 493 494 LOCK(&sc->dev_lock); 495 496 if (sc->ifp->if_flags & IFF_UP) { 497 oce_if_deactivate(sc); 498 oce_if_activate(sc); 499 } 500 501 UNLOCK(&sc->dev_lock); 502 503 } 504 505 506 #if 0 /* XXX swildner: MULTIQUEUE */ 507 static int 508 oce_multiq_start(struct ifnet *ifp, struct mbuf *m) 509 { 510 POCE_SOFTC sc = ifp->if_softc; 511 struct oce_wq *wq = NULL; 512 int queue_index = 0; 513 int status = 0; 514 515 if ((m->m_flags & M_FLOWID) != 0) 516 queue_index = m->m_pkthdr.flowid % sc->nwqs; 517 518 wq = sc->wq[queue_index]; 519 520 if (TRY_LOCK(&wq->tx_lock)) { 521 status = oce_multiq_transmit(ifp, m, wq); 522 UNLOCK(&wq->tx_lock); 523 } else { 524 status = drbr_enqueue(ifp, wq->br, m); 525 } 526 return status; 527 528 } 529 530 531 static void 532 oce_multiq_flush(struct ifnet *ifp) 533 { 534 POCE_SOFTC sc = ifp->if_softc; 535 struct mbuf *m; 536 int i = 0; 537 538 for (i = 0; i < sc->nwqs; i++) { 539 while ((m = buf_ring_dequeue_sc(sc->wq[i]->br)) != NULL) 540 m_freem(m); 541 } 542 if_qflush(ifp); 543 } 544 #endif 545 546 547 548 /***************************************************************************** 549 * Driver interrupt routines functions * 550 *****************************************************************************/ 551 552 static void 553 oce_intr(void *arg, int pending) 554 { 555 556 POCE_INTR_INFO ii = (POCE_INTR_INFO) arg; 557 POCE_SOFTC sc = ii->sc; 558 struct oce_eq *eq = ii->eq; 559 struct oce_eqe *eqe; 560 struct oce_cq *cq = NULL; 561 int i, num_eqes = 0; 562 563 564 bus_dmamap_sync(eq->ring->dma.tag, eq->ring->dma.map, 565 BUS_DMASYNC_POSTWRITE); 566 do { 567 eqe = RING_GET_CONSUMER_ITEM_VA(eq->ring, struct oce_eqe); 568 if (eqe->evnt == 0) 569 break; 570 eqe->evnt = 0; 571 bus_dmamap_sync(eq->ring->dma.tag, eq->ring->dma.map, 572 BUS_DMASYNC_POSTWRITE); 573 RING_GET(eq->ring, 1); 574 num_eqes++; 575 576 } while (TRUE); 577 578 if (!num_eqes) 579 goto eq_arm; /* Spurious */ 580 581 /* Clear EQ entries, but dont arm */ 582 oce_arm_eq(sc, eq->eq_id, num_eqes, FALSE, FALSE); 583 584 /* Process TX, RX and MCC. But dont arm CQ*/ 585 for (i = 0; i < eq->cq_valid; i++) { 586 cq = eq->cq[i]; 587 (*cq->cq_handler)(cq->cb_arg); 588 } 589 590 /* Arm all cqs connected to this EQ */ 591 for (i = 0; i < eq->cq_valid; i++) { 592 cq = eq->cq[i]; 593 oce_arm_cq(sc, cq->cq_id, 0, TRUE); 594 } 595 596 eq_arm: 597 oce_arm_eq(sc, eq->eq_id, 0, TRUE, FALSE); 598 599 return; 600 } 601 602 603 static int 604 oce_setup_intr(POCE_SOFTC sc) 605 { 606 int rc = 0, use_intx = 0; 607 int vector = 0; 608 #if 0 /* XXX swildner: MSI-X */ 609 int req_vectors = 0; 610 611 if (sc->rss_enable) 612 req_vectors = MAX((sc->nrqs - 1), sc->nwqs); 613 else 614 req_vectors = 1; 615 616 if (sc->flags & OCE_FLAGS_MSIX_CAPABLE) { 617 sc->intr_count = req_vectors; 618 rc = pci_alloc_msix(sc->dev, &sc->intr_count); 619 if (rc != 0) { 620 use_intx = 1; 621 pci_release_msi(sc->dev); 622 } else 623 sc->flags |= OCE_FLAGS_USING_MSIX; 624 } else 625 #endif 626 use_intx = 1; 627 628 if (use_intx) 629 sc->intr_count = 1; 630 631 /* Scale number of queues based on intr we got */ 632 update_queues_got(sc); 633 634 if (use_intx) { 635 device_printf(sc->dev, "Using legacy interrupt\n"); 636 rc = oce_alloc_intr(sc, vector, oce_intr); 637 if (rc) 638 goto error; 639 #if 0 /* XXX swildner: MSI-X */ 640 } else { 641 for (; vector < sc->intr_count; vector++) { 642 rc = oce_alloc_intr(sc, vector, oce_intr); 643 if (rc) 644 goto error; 645 } 646 #endif 647 } 648 649 return 0; 650 error: 651 oce_intr_free(sc); 652 return rc; 653 } 654 655 656 void 657 oce_fast_isr(void *arg) 658 { 659 POCE_INTR_INFO ii = (POCE_INTR_INFO) arg; 660 POCE_SOFTC sc = ii->sc; 661 662 if (ii->eq == NULL) 663 return; 664 665 oce_arm_eq(sc, ii->eq->eq_id, 0, FALSE, TRUE); 666 667 taskqueue_enqueue(ii->tq, &ii->task); 668 669 ii->eq->intr++; 670 } 671 672 673 static int 674 oce_alloc_intr(POCE_SOFTC sc, int vector, void (*isr) (void *arg, int pending)) 675 { 676 POCE_INTR_INFO ii = &sc->intrs[vector]; 677 int rc = 0, rr; 678 u_int irq_flags; 679 680 if (vector >= OCE_MAX_EQ) 681 return (EINVAL); 682 683 #if 0 /* XXX swildner: MSI-X */ 684 /* Set the resource id for the interrupt. 685 * MSIx is vector + 1 for the resource id, 686 * INTx is 0 for the resource id. 687 */ 688 if (sc->flags & OCE_FLAGS_USING_MSIX) 689 rr = vector + 1; 690 else 691 #endif 692 rr = 0; 693 ii->irq_type = pci_alloc_1intr(sc->dev, 694 sc->flags & OCE_FLAGS_USING_MSI, &rr, &irq_flags); 695 ii->intr_res = bus_alloc_resource_any(sc->dev, 696 SYS_RES_IRQ, 697 &rr, irq_flags); 698 ii->irq_rr = rr; 699 if (ii->intr_res == NULL) { 700 device_printf(sc->dev, 701 "Could not allocate interrupt\n"); 702 rc = ENXIO; 703 return rc; 704 } 705 706 TASK_INIT(&ii->task, 0, isr, ii); 707 ii->vector = vector; 708 ksprintf(ii->task_name, "oce_task[%d]", ii->vector); 709 ii->tq = taskqueue_create(ii->task_name, 710 M_NOWAIT, 711 taskqueue_thread_enqueue, 712 &ii->tq); 713 taskqueue_start_threads(&ii->tq, 1, TDPRI_KERN_DAEMON, -1, "%s taskq", 714 device_get_nameunit(sc->dev)); 715 716 ii->sc = sc; 717 rc = bus_setup_intr(sc->dev, 718 ii->intr_res, 719 0, 720 oce_fast_isr, ii, &ii->tag, NULL); 721 return rc; 722 723 } 724 725 726 void 727 oce_intr_free(POCE_SOFTC sc) 728 { 729 int i = 0; 730 731 for (i = 0; i < sc->intr_count; i++) { 732 733 if (sc->intrs[i].tag != NULL) 734 bus_teardown_intr(sc->dev, sc->intrs[i].intr_res, 735 sc->intrs[i].tag); 736 if (sc->intrs[i].tq != NULL) 737 taskqueue_free(sc->intrs[i].tq); 738 739 if (sc->intrs[i].intr_res != NULL) 740 bus_release_resource(sc->dev, SYS_RES_IRQ, 741 sc->intrs[i].irq_rr, 742 sc->intrs[i].intr_res); 743 sc->intrs[i].tag = NULL; 744 sc->intrs[i].intr_res = NULL; 745 } 746 747 if (sc->flags & OCE_FLAGS_USING_MSIX || 748 sc->flags & OCE_FLAGS_USING_MSI) 749 pci_release_msi(sc->dev); 750 751 } 752 753 754 755 /****************************************************************************** 756 * Media callbacks functions * 757 ******************************************************************************/ 758 759 static void 760 oce_media_status(struct ifnet *ifp, struct ifmediareq *req) 761 { 762 POCE_SOFTC sc = (POCE_SOFTC) ifp->if_softc; 763 764 765 req->ifm_status = IFM_AVALID; 766 req->ifm_active = IFM_ETHER; 767 768 if (sc->link_status == 1) 769 req->ifm_status |= IFM_ACTIVE; 770 else 771 return; 772 773 switch (sc->link_speed) { 774 case 1: /* 10 Mbps */ 775 req->ifm_active |= IFM_10_T | IFM_FDX; 776 sc->speed = 10; 777 break; 778 case 2: /* 100 Mbps */ 779 req->ifm_active |= IFM_100_TX | IFM_FDX; 780 sc->speed = 100; 781 break; 782 case 3: /* 1 Gbps */ 783 req->ifm_active |= IFM_1000_T | IFM_FDX; 784 sc->speed = 1000; 785 break; 786 case 4: /* 10 Gbps */ 787 req->ifm_active |= IFM_10G_SR | IFM_FDX; 788 sc->speed = 10000; 789 break; 790 } 791 792 return; 793 } 794 795 796 int 797 oce_media_change(struct ifnet *ifp) 798 { 799 return 0; 800 } 801 802 803 804 805 /***************************************************************************** 806 * Transmit routines functions * 807 *****************************************************************************/ 808 809 static int 810 oce_tx(POCE_SOFTC sc, struct mbuf **mpp, int wq_index) 811 { 812 int rc = 0, i, retry_cnt = 0; 813 bus_dma_segment_t segs[OCE_MAX_TX_ELEMENTS]; 814 struct mbuf *m, *m_temp; 815 struct oce_wq *wq = sc->wq[wq_index]; 816 struct oce_packet_desc *pd; 817 uint32_t out; 818 struct oce_nic_hdr_wqe *nichdr; 819 struct oce_nic_frag_wqe *nicfrag; 820 int num_wqes; 821 uint32_t reg_value; 822 boolean_t complete = TRUE; 823 824 m = *mpp; 825 if (!m) 826 return EINVAL; 827 828 if (!(m->m_flags & M_PKTHDR)) { 829 rc = ENXIO; 830 goto free_ret; 831 } 832 833 if(oce_tx_asic_stall_verify(sc, m)) { 834 m = oce_insert_vlan_tag(sc, m, &complete); 835 if(!m) { 836 device_printf(sc->dev, "Insertion unsuccessful\n"); 837 return 0; 838 } 839 840 } 841 842 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 843 /* consolidate packet buffers for TSO/LSO segment offload */ 844 #if defined(INET6) || defined(INET) 845 m = oce_tso_setup(sc, mpp); 846 #else 847 m = NULL; 848 #endif 849 if (m == NULL) { 850 rc = ENXIO; 851 goto free_ret; 852 } 853 } 854 855 out = wq->packets_out + 1; 856 if (out == OCE_WQ_PACKET_ARRAY_SIZE) 857 out = 0; 858 if (out == wq->packets_in) 859 return EBUSY; 860 861 pd = &wq->pckts[wq->packets_out]; 862 retry: 863 rc = bus_dmamap_load_mbuf_defrag(wq->tag, 864 pd->map, 865 mpp, segs, OCE_MAX_TX_ELEMENTS, 866 &pd->nsegs, BUS_DMA_NOWAIT); 867 if (rc == 0) { 868 num_wqes = pd->nsegs + 1; 869 if (IS_BE(sc)) { 870 /*Dummy required only for BE3.*/ 871 if (num_wqes & 1) 872 num_wqes++; 873 } 874 if (num_wqes >= RING_NUM_FREE(wq->ring)) { 875 bus_dmamap_unload(wq->tag, pd->map); 876 return EBUSY; 877 } 878 879 bus_dmamap_sync(wq->tag, pd->map, BUS_DMASYNC_PREWRITE); 880 pd->mbuf = m; 881 wq->packets_out = out; 882 883 nichdr = 884 RING_GET_PRODUCER_ITEM_VA(wq->ring, struct oce_nic_hdr_wqe); 885 nichdr->u0.dw[0] = 0; 886 nichdr->u0.dw[1] = 0; 887 nichdr->u0.dw[2] = 0; 888 nichdr->u0.dw[3] = 0; 889 890 nichdr->u0.s.complete = complete; 891 nichdr->u0.s.event = 1; 892 nichdr->u0.s.crc = 1; 893 nichdr->u0.s.forward = 0; 894 nichdr->u0.s.ipcs = (m->m_pkthdr.csum_flags & CSUM_IP) ? 1 : 0; 895 nichdr->u0.s.udpcs = 896 (m->m_pkthdr.csum_flags & CSUM_UDP) ? 1 : 0; 897 nichdr->u0.s.tcpcs = 898 (m->m_pkthdr.csum_flags & CSUM_TCP) ? 1 : 0; 899 nichdr->u0.s.num_wqe = num_wqes; 900 nichdr->u0.s.total_length = m->m_pkthdr.len; 901 #if 0 /* XXX swildner: ETHER_VTAG */ 902 if (m->m_flags & M_VLANTAG) { 903 nichdr->u0.s.vlan = 1; /*Vlan present*/ 904 nichdr->u0.s.vlan_tag = m->m_pkthdr.ether_vtag; 905 } 906 #endif 907 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 908 if (m->m_pkthdr.tso_segsz) { 909 nichdr->u0.s.lso = 1; 910 nichdr->u0.s.lso_mss = m->m_pkthdr.tso_segsz; 911 } 912 if (!IS_BE(sc)) 913 nichdr->u0.s.ipcs = 1; 914 } 915 916 RING_PUT(wq->ring, 1); 917 wq->ring->num_used++; 918 919 for (i = 0; i < pd->nsegs; i++) { 920 nicfrag = 921 RING_GET_PRODUCER_ITEM_VA(wq->ring, 922 struct oce_nic_frag_wqe); 923 nicfrag->u0.s.rsvd0 = 0; 924 nicfrag->u0.s.frag_pa_hi = ADDR_HI(segs[i].ds_addr); 925 nicfrag->u0.s.frag_pa_lo = ADDR_LO(segs[i].ds_addr); 926 nicfrag->u0.s.frag_len = segs[i].ds_len; 927 pd->wqe_idx = wq->ring->pidx; 928 RING_PUT(wq->ring, 1); 929 wq->ring->num_used++; 930 } 931 if (num_wqes > (pd->nsegs + 1)) { 932 nicfrag = 933 RING_GET_PRODUCER_ITEM_VA(wq->ring, 934 struct oce_nic_frag_wqe); 935 nicfrag->u0.dw[0] = 0; 936 nicfrag->u0.dw[1] = 0; 937 nicfrag->u0.dw[2] = 0; 938 nicfrag->u0.dw[3] = 0; 939 pd->wqe_idx = wq->ring->pidx; 940 RING_PUT(wq->ring, 1); 941 wq->ring->num_used++; 942 pd->nsegs++; 943 } 944 945 sc->ifp->if_opackets++; 946 wq->tx_stats.tx_reqs++; 947 wq->tx_stats.tx_wrbs += num_wqes; 948 wq->tx_stats.tx_bytes += m->m_pkthdr.len; 949 wq->tx_stats.tx_pkts++; 950 951 bus_dmamap_sync(wq->ring->dma.tag, wq->ring->dma.map, 952 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 953 reg_value = (num_wqes << 16) | wq->wq_id; 954 OCE_WRITE_REG32(sc, db, PD_TXULP_DB, reg_value); 955 956 } else if (rc == EFBIG) { 957 if (retry_cnt == 0) { 958 m_temp = m_defrag(m, M_NOWAIT); 959 if (m_temp == NULL) 960 goto free_ret; 961 m = m_temp; 962 *mpp = m_temp; 963 retry_cnt = retry_cnt + 1; 964 goto retry; 965 } else 966 goto free_ret; 967 } else if (rc == ENOMEM) 968 return rc; 969 else 970 goto free_ret; 971 972 return 0; 973 974 free_ret: 975 m_freem(*mpp); 976 *mpp = NULL; 977 return rc; 978 } 979 980 981 static void 982 oce_tx_complete(struct oce_wq *wq, uint32_t wqe_idx, uint32_t status) 983 { 984 uint32_t in; 985 struct oce_packet_desc *pd; 986 POCE_SOFTC sc = (POCE_SOFTC) wq->parent; 987 struct mbuf *m; 988 989 if (wq->packets_out == wq->packets_in) 990 device_printf(sc->dev, "WQ transmit descriptor missing\n"); 991 992 in = wq->packets_in + 1; 993 if (in == OCE_WQ_PACKET_ARRAY_SIZE) 994 in = 0; 995 996 pd = &wq->pckts[wq->packets_in]; 997 wq->packets_in = in; 998 wq->ring->num_used -= (pd->nsegs + 1); 999 bus_dmamap_sync(wq->tag, pd->map, BUS_DMASYNC_POSTWRITE); 1000 bus_dmamap_unload(wq->tag, pd->map); 1001 1002 m = pd->mbuf; 1003 m_freem(m); 1004 pd->mbuf = NULL; 1005 1006 if (ifq_is_oactive(&sc->ifp->if_snd)) { 1007 if (wq->ring->num_used < (wq->ring->num_items / 2)) { 1008 ifq_clr_oactive(&sc->ifp->if_snd); 1009 oce_tx_restart(sc, wq); 1010 } 1011 } 1012 } 1013 1014 1015 static void 1016 oce_tx_restart(POCE_SOFTC sc, struct oce_wq *wq) 1017 { 1018 1019 if ((sc->ifp->if_flags & IFF_RUNNING) != IFF_RUNNING) 1020 return; 1021 1022 #if __FreeBSD_version >= 800000 1023 if (!drbr_empty(sc->ifp, wq->br)) 1024 #else 1025 if (!ifq_is_empty(&sc->ifp->if_snd)) 1026 #endif 1027 taskqueue_enqueue(taskqueue_swi, &wq->txtask); 1028 1029 } 1030 1031 1032 #if defined(INET6) || defined(INET) 1033 static struct mbuf * 1034 oce_tso_setup(POCE_SOFTC sc, struct mbuf **mpp) 1035 { 1036 struct mbuf *m; 1037 #ifdef INET 1038 struct ip *ip; 1039 #endif 1040 #ifdef INET6 1041 struct ip6_hdr *ip6; 1042 #endif 1043 struct ether_vlan_header *eh; 1044 struct tcphdr *th; 1045 uint16_t etype; 1046 int total_len = 0, ehdrlen = 0; 1047 1048 m = *mpp; 1049 1050 if (M_WRITABLE(m) == 0) { 1051 m = m_dup(*mpp, M_NOWAIT); 1052 if (!m) 1053 return NULL; 1054 m_freem(*mpp); 1055 *mpp = m; 1056 } 1057 1058 eh = mtod(m, struct ether_vlan_header *); 1059 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 1060 etype = ntohs(eh->evl_proto); 1061 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1062 } else { 1063 etype = ntohs(eh->evl_encap_proto); 1064 ehdrlen = ETHER_HDR_LEN; 1065 } 1066 1067 switch (etype) { 1068 #ifdef INET 1069 case ETHERTYPE_IP: 1070 ip = (struct ip *)(m->m_data + ehdrlen); 1071 if (ip->ip_p != IPPROTO_TCP) 1072 return NULL; 1073 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 1074 1075 total_len = ehdrlen + (ip->ip_hl << 2) + (th->th_off << 2); 1076 break; 1077 #endif 1078 #ifdef INET6 1079 case ETHERTYPE_IPV6: 1080 ip6 = (struct ip6_hdr *)(m->m_data + ehdrlen); 1081 if (ip6->ip6_nxt != IPPROTO_TCP) 1082 return NULL; 1083 th = (struct tcphdr *)((caddr_t)ip6 + sizeof(struct ip6_hdr)); 1084 1085 total_len = ehdrlen + sizeof(struct ip6_hdr) + (th->th_off << 2); 1086 break; 1087 #endif 1088 default: 1089 return NULL; 1090 } 1091 1092 m = m_pullup(m, total_len); 1093 if (!m) 1094 return NULL; 1095 *mpp = m; 1096 return m; 1097 1098 } 1099 #endif /* INET6 || INET */ 1100 1101 void 1102 oce_tx_task(void *arg, int npending) 1103 { 1104 struct oce_wq *wq = arg; 1105 POCE_SOFTC sc = wq->parent; 1106 struct ifnet *ifp = sc->ifp; 1107 #if 0 /* XXX swildner: MULTIQUEUE */ 1108 int rc = 0; 1109 1110 if (TRY_LOCK(&wq->tx_lock)) { 1111 rc = oce_multiq_transmit(ifp, NULL, wq); 1112 if (rc) { 1113 device_printf(sc->dev, 1114 "TX[%d] restart failed\n", wq->queue_index); 1115 } 1116 UNLOCK(&wq->tx_lock); 1117 } 1118 #else 1119 lwkt_serialize_enter(ifp->if_serializer); 1120 oce_start_locked(ifp); 1121 lwkt_serialize_exit(ifp->if_serializer); 1122 #endif 1123 } 1124 1125 1126 void 1127 oce_start_locked(struct ifnet *ifp) 1128 { 1129 POCE_SOFTC sc = ifp->if_softc; 1130 struct mbuf *m; 1131 int rc = 0; 1132 int def_q = 0; /* Default tx queue is 0 */ 1133 1134 if (!((ifp->if_flags & IFF_RUNNING) && !ifq_is_oactive(&ifp->if_snd))) 1135 return; 1136 1137 if (!sc->link_status) { 1138 ifq_purge(&ifp->if_snd); 1139 return; 1140 } 1141 1142 do { 1143 m = ifq_dequeue(&sc->ifp->if_snd); 1144 if (m == NULL) 1145 break; 1146 1147 rc = oce_tx(sc, &m, def_q); 1148 if (rc) { 1149 if (m != NULL) { 1150 sc->wq[def_q]->tx_stats.tx_stops ++; 1151 ifq_set_oactive(&ifp->if_snd); 1152 ifq_prepend(&ifp->if_snd, m); 1153 m = NULL; 1154 } 1155 break; 1156 } 1157 if (m != NULL) 1158 ETHER_BPF_MTAP(ifp, m); 1159 1160 } while (TRUE); 1161 1162 return; 1163 } 1164 1165 void 1166 oce_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1167 { 1168 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1169 oce_start_locked(ifp); 1170 } 1171 1172 1173 /* Handle the Completion Queue for transmit */ 1174 uint16_t 1175 oce_wq_handler(void *arg) 1176 { 1177 struct oce_wq *wq = (struct oce_wq *)arg; 1178 POCE_SOFTC sc = wq->parent; 1179 struct oce_cq *cq = wq->cq; 1180 struct oce_nic_tx_cqe *cqe; 1181 int num_cqes = 0; 1182 1183 LOCK(&wq->tx_lock); 1184 bus_dmamap_sync(cq->ring->dma.tag, 1185 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE); 1186 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_tx_cqe); 1187 while (cqe->u0.dw[3]) { 1188 DW_SWAP((uint32_t *) cqe, sizeof(oce_wq_cqe)); 1189 1190 wq->ring->cidx = cqe->u0.s.wqe_index + 1; 1191 if (wq->ring->cidx >= wq->ring->num_items) 1192 wq->ring->cidx -= wq->ring->num_items; 1193 1194 oce_tx_complete(wq, cqe->u0.s.wqe_index, cqe->u0.s.status); 1195 wq->tx_stats.tx_compl++; 1196 cqe->u0.dw[3] = 0; 1197 RING_GET(cq->ring, 1); 1198 bus_dmamap_sync(cq->ring->dma.tag, 1199 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE); 1200 cqe = 1201 RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_tx_cqe); 1202 num_cqes++; 1203 } 1204 1205 if (num_cqes) 1206 oce_arm_cq(sc, cq->cq_id, num_cqes, FALSE); 1207 UNLOCK(&wq->tx_lock); 1208 1209 return 0; 1210 } 1211 1212 1213 #if 0 /* XXX swildner: MULTIQUEUE */ 1214 static int 1215 oce_multiq_transmit(struct ifnet *ifp, struct mbuf *m, struct oce_wq *wq) 1216 { 1217 POCE_SOFTC sc = ifp->if_softc; 1218 int status = 0, queue_index = 0; 1219 struct mbuf *next = NULL; 1220 struct buf_ring *br = NULL; 1221 1222 br = wq->br; 1223 queue_index = wq->queue_index; 1224 1225 if (!((ifp->if_flags & IFF_RUNNING) && !ifq_is_oactive(&ifp->if_snd))) { 1226 if (m != NULL) 1227 status = drbr_enqueue(ifp, br, m); 1228 return status; 1229 } 1230 1231 if (m != NULL) { 1232 if ((status = drbr_enqueue(ifp, br, m)) != 0) 1233 return status; 1234 } 1235 while ((next = drbr_peek(ifp, br)) != NULL) { 1236 if (oce_tx(sc, &next, queue_index)) { 1237 if (next == NULL) { 1238 drbr_advance(ifp, br); 1239 } else { 1240 drbr_putback(ifp, br, next); 1241 wq->tx_stats.tx_stops ++; 1242 ifp_set_oactive(&ifp->if_snd); 1243 status = drbr_enqueue(ifp, br, next); 1244 } 1245 break; 1246 } 1247 drbr_advance(ifp, br); 1248 ifp->if_obytes += next->m_pkthdr.len; 1249 if (next->m_flags & M_MCAST) 1250 ifp->if_omcasts++; 1251 ETHER_BPF_MTAP(ifp, next); 1252 } 1253 1254 return status; 1255 } 1256 #endif 1257 1258 1259 1260 1261 /***************************************************************************** 1262 * Receive routines functions * 1263 *****************************************************************************/ 1264 1265 static void 1266 oce_rx(struct oce_rq *rq, uint32_t rqe_idx, struct oce_nic_rx_cqe *cqe) 1267 { 1268 uint32_t out; 1269 struct oce_packet_desc *pd; 1270 POCE_SOFTC sc = (POCE_SOFTC) rq->parent; 1271 int i, len, frag_len; 1272 struct mbuf *m = NULL, *tail = NULL; 1273 uint16_t vtag; 1274 1275 len = cqe->u0.s.pkt_size; 1276 if (!len) { 1277 /*partial DMA workaround for Lancer*/ 1278 oce_discard_rx_comp(rq, cqe); 1279 goto exit; 1280 } 1281 1282 /* Get vlan_tag value */ 1283 if(IS_BE(sc)) 1284 vtag = BSWAP_16(cqe->u0.s.vlan_tag); 1285 else 1286 vtag = cqe->u0.s.vlan_tag; 1287 1288 1289 for (i = 0; i < cqe->u0.s.num_fragments; i++) { 1290 1291 if (rq->packets_out == rq->packets_in) { 1292 device_printf(sc->dev, 1293 "RQ transmit descriptor missing\n"); 1294 } 1295 out = rq->packets_out + 1; 1296 if (out == OCE_RQ_PACKET_ARRAY_SIZE) 1297 out = 0; 1298 pd = &rq->pckts[rq->packets_out]; 1299 rq->packets_out = out; 1300 1301 bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_POSTWRITE); 1302 bus_dmamap_unload(rq->tag, pd->map); 1303 rq->pending--; 1304 1305 frag_len = (len > rq->cfg.frag_size) ? rq->cfg.frag_size : len; 1306 pd->mbuf->m_len = frag_len; 1307 1308 if (tail != NULL) { 1309 /* additional fragments */ 1310 pd->mbuf->m_flags &= ~M_PKTHDR; 1311 tail->m_next = pd->mbuf; 1312 tail = pd->mbuf; 1313 } else { 1314 /* first fragment, fill out much of the packet header */ 1315 pd->mbuf->m_pkthdr.len = len; 1316 pd->mbuf->m_pkthdr.csum_flags = 0; 1317 if (IF_CSUM_ENABLED(sc)) { 1318 if (cqe->u0.s.l4_cksum_pass) { 1319 pd->mbuf->m_pkthdr.csum_flags |= 1320 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1321 pd->mbuf->m_pkthdr.csum_data = 0xffff; 1322 } 1323 if (cqe->u0.s.ip_cksum_pass) { 1324 if (!cqe->u0.s.ip_ver) { /* IPV4 */ 1325 pd->mbuf->m_pkthdr.csum_flags |= 1326 (CSUM_IP_CHECKED|CSUM_IP_VALID); 1327 } 1328 } 1329 } 1330 m = tail = pd->mbuf; 1331 } 1332 pd->mbuf = NULL; 1333 len -= frag_len; 1334 } 1335 1336 if (m) { 1337 if (!oce_cqe_portid_valid(sc, cqe)) { 1338 m_freem(m); 1339 goto exit; 1340 } 1341 1342 m->m_pkthdr.rcvif = sc->ifp; 1343 #if __FreeBSD_version >= 800000 1344 m->m_pkthdr.flowid = rq->queue_index; 1345 m->m_flags |= M_FLOWID; 1346 #endif 1347 #if 0 /* XXX swildner: ETHER_VTAG */ 1348 /* This deternies if vlan tag is Valid */ 1349 if (oce_cqe_vtp_valid(sc, cqe)) { 1350 if (sc->function_mode & FNM_FLEX10_MODE) { 1351 /* FLEX10. If QnQ is not set, neglect VLAN */ 1352 if (cqe->u0.s.qnq) { 1353 m->m_pkthdr.ether_vtag = vtag; 1354 m->m_flags |= M_VLANTAG; 1355 } 1356 } else if (sc->pvid != (vtag & VLAN_VID_MASK)) { 1357 /* In UMC mode generally pvid will be striped by 1358 hw. But in some cases we have seen it comes 1359 with pvid. So if pvid == vlan, neglect vlan. 1360 */ 1361 m->m_pkthdr.ether_vtag = vtag; 1362 m->m_flags |= M_VLANTAG; 1363 } 1364 } 1365 #endif 1366 1367 sc->ifp->if_ipackets++; 1368 #if defined(INET6) || defined(INET) 1369 #if 0 /* XXX swildner: LRO */ 1370 /* Try to queue to LRO */ 1371 if (IF_LRO_ENABLED(sc) && 1372 (cqe->u0.s.ip_cksum_pass) && 1373 (cqe->u0.s.l4_cksum_pass) && 1374 (!cqe->u0.s.ip_ver) && 1375 (rq->lro.lro_cnt != 0)) { 1376 1377 if (tcp_lro_rx(&rq->lro, m, 0) == 0) { 1378 rq->lro_pkts_queued ++; 1379 goto post_done; 1380 } 1381 /* If LRO posting fails then try to post to STACK */ 1382 } 1383 #endif 1384 #endif 1385 1386 (*sc->ifp->if_input) (sc->ifp, m); 1387 #if defined(INET6) || defined(INET) 1388 #if 0 /* XXX swildner: LRO */ 1389 post_done: 1390 #endif 1391 #endif 1392 /* Update rx stats per queue */ 1393 rq->rx_stats.rx_pkts++; 1394 rq->rx_stats.rx_bytes += cqe->u0.s.pkt_size; 1395 rq->rx_stats.rx_frags += cqe->u0.s.num_fragments; 1396 if (cqe->u0.s.pkt_type == OCE_MULTICAST_PACKET) 1397 rq->rx_stats.rx_mcast_pkts++; 1398 if (cqe->u0.s.pkt_type == OCE_UNICAST_PACKET) 1399 rq->rx_stats.rx_ucast_pkts++; 1400 } 1401 exit: 1402 return; 1403 } 1404 1405 1406 static void 1407 oce_discard_rx_comp(struct oce_rq *rq, struct oce_nic_rx_cqe *cqe) 1408 { 1409 uint32_t out, i = 0; 1410 struct oce_packet_desc *pd; 1411 POCE_SOFTC sc = (POCE_SOFTC) rq->parent; 1412 int num_frags = cqe->u0.s.num_fragments; 1413 1414 for (i = 0; i < num_frags; i++) { 1415 if (rq->packets_out == rq->packets_in) { 1416 device_printf(sc->dev, 1417 "RQ transmit descriptor missing\n"); 1418 } 1419 out = rq->packets_out + 1; 1420 if (out == OCE_RQ_PACKET_ARRAY_SIZE) 1421 out = 0; 1422 pd = &rq->pckts[rq->packets_out]; 1423 rq->packets_out = out; 1424 1425 bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_POSTWRITE); 1426 bus_dmamap_unload(rq->tag, pd->map); 1427 rq->pending--; 1428 m_freem(pd->mbuf); 1429 } 1430 1431 } 1432 1433 1434 #if 0 /* XXX swildner: ETHER_VTAG */ 1435 static int 1436 oce_cqe_vtp_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe) 1437 { 1438 struct oce_nic_rx_cqe_v1 *cqe_v1; 1439 int vtp = 0; 1440 1441 if (sc->be3_native) { 1442 cqe_v1 = (struct oce_nic_rx_cqe_v1 *)cqe; 1443 vtp = cqe_v1->u0.s.vlan_tag_present; 1444 } else 1445 vtp = cqe->u0.s.vlan_tag_present; 1446 1447 return vtp; 1448 1449 } 1450 #endif 1451 1452 1453 static int 1454 oce_cqe_portid_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe) 1455 { 1456 struct oce_nic_rx_cqe_v1 *cqe_v1; 1457 int port_id = 0; 1458 1459 if (sc->be3_native && IS_BE(sc)) { 1460 cqe_v1 = (struct oce_nic_rx_cqe_v1 *)cqe; 1461 port_id = cqe_v1->u0.s.port; 1462 if (sc->port_id != port_id) 1463 return 0; 1464 } else 1465 ;/* For BE3 legacy and Lancer this is dummy */ 1466 1467 return 1; 1468 1469 } 1470 1471 #if defined(INET6) || defined(INET) 1472 #if 0 /* XXX swildner: LRO */ 1473 static void 1474 oce_rx_flush_lro(struct oce_rq *rq) 1475 { 1476 struct lro_ctrl *lro = &rq->lro; 1477 struct lro_entry *queued; 1478 POCE_SOFTC sc = (POCE_SOFTC) rq->parent; 1479 1480 if (!IF_LRO_ENABLED(sc)) 1481 return; 1482 1483 while ((queued = SLIST_FIRST(&lro->lro_active)) != NULL) { 1484 SLIST_REMOVE_HEAD(&lro->lro_active, next); 1485 tcp_lro_flush(lro, queued); 1486 } 1487 rq->lro_pkts_queued = 0; 1488 1489 return; 1490 } 1491 1492 1493 static int 1494 oce_init_lro(POCE_SOFTC sc) 1495 { 1496 struct lro_ctrl *lro = NULL; 1497 int i = 0, rc = 0; 1498 1499 for (i = 0; i < sc->nrqs; i++) { 1500 lro = &sc->rq[i]->lro; 1501 rc = tcp_lro_init(lro); 1502 if (rc != 0) { 1503 device_printf(sc->dev, "LRO init failed\n"); 1504 return rc; 1505 } 1506 lro->ifp = sc->ifp; 1507 } 1508 1509 return rc; 1510 } 1511 1512 1513 void 1514 oce_free_lro(POCE_SOFTC sc) 1515 { 1516 struct lro_ctrl *lro = NULL; 1517 int i = 0; 1518 1519 for (i = 0; i < sc->nrqs; i++) { 1520 lro = &sc->rq[i]->lro; 1521 if (lro) 1522 tcp_lro_free(lro); 1523 } 1524 } 1525 #endif 1526 #endif 1527 1528 int 1529 oce_alloc_rx_bufs(struct oce_rq *rq, int count) 1530 { 1531 POCE_SOFTC sc = (POCE_SOFTC) rq->parent; 1532 int i, in, rc; 1533 struct oce_packet_desc *pd; 1534 bus_dma_segment_t segs[6]; 1535 int nsegs, added = 0; 1536 struct oce_nic_rqe *rqe; 1537 pd_rxulp_db_t rxdb_reg; 1538 1539 bzero(&rxdb_reg, sizeof(pd_rxulp_db_t)); 1540 for (i = 0; i < count; i++) { 1541 in = rq->packets_in + 1; 1542 if (in == OCE_RQ_PACKET_ARRAY_SIZE) 1543 in = 0; 1544 if (in == rq->packets_out) 1545 break; /* no more room */ 1546 1547 pd = &rq->pckts[rq->packets_in]; 1548 pd->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1549 if (pd->mbuf == NULL) 1550 break; 1551 1552 pd->mbuf->m_len = pd->mbuf->m_pkthdr.len = MCLBYTES; 1553 rc = bus_dmamap_load_mbuf_segment(rq->tag, 1554 pd->map, 1555 pd->mbuf, 1556 segs, OCE_MAX_TX_ELEMENTS, 1557 &nsegs, BUS_DMA_NOWAIT); 1558 if (rc) { 1559 m_free(pd->mbuf); 1560 break; 1561 } 1562 1563 if (nsegs != 1) { 1564 i--; 1565 continue; 1566 } 1567 1568 rq->packets_in = in; 1569 bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_PREREAD); 1570 1571 rqe = RING_GET_PRODUCER_ITEM_VA(rq->ring, struct oce_nic_rqe); 1572 rqe->u0.s.frag_pa_hi = ADDR_HI(segs[0].ds_addr); 1573 rqe->u0.s.frag_pa_lo = ADDR_LO(segs[0].ds_addr); 1574 DW_SWAP(u32ptr(rqe), sizeof(struct oce_nic_rqe)); 1575 RING_PUT(rq->ring, 1); 1576 added++; 1577 rq->pending++; 1578 } 1579 if (added != 0) { 1580 for (i = added / OCE_MAX_RQ_POSTS; i > 0; i--) { 1581 rxdb_reg.bits.num_posted = OCE_MAX_RQ_POSTS; 1582 rxdb_reg.bits.qid = rq->rq_id; 1583 OCE_WRITE_REG32(sc, db, PD_RXULP_DB, rxdb_reg.dw0); 1584 added -= OCE_MAX_RQ_POSTS; 1585 } 1586 if (added > 0) { 1587 rxdb_reg.bits.qid = rq->rq_id; 1588 rxdb_reg.bits.num_posted = added; 1589 OCE_WRITE_REG32(sc, db, PD_RXULP_DB, rxdb_reg.dw0); 1590 } 1591 } 1592 1593 return 0; 1594 } 1595 1596 1597 /* Handle the Completion Queue for receive */ 1598 uint16_t 1599 oce_rq_handler(void *arg) 1600 { 1601 struct oce_rq *rq = (struct oce_rq *)arg; 1602 struct oce_cq *cq = rq->cq; 1603 POCE_SOFTC sc = rq->parent; 1604 struct oce_nic_rx_cqe *cqe; 1605 int num_cqes = 0, rq_buffers_used = 0; 1606 1607 1608 LOCK(&rq->rx_lock); 1609 bus_dmamap_sync(cq->ring->dma.tag, 1610 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE); 1611 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_rx_cqe); 1612 while (cqe->u0.dw[2]) { 1613 DW_SWAP((uint32_t *) cqe, sizeof(oce_rq_cqe)); 1614 1615 RING_GET(rq->ring, 1); 1616 if (cqe->u0.s.error == 0) { 1617 oce_rx(rq, cqe->u0.s.frag_index, cqe); 1618 } else { 1619 rq->rx_stats.rxcp_err++; 1620 sc->ifp->if_ierrors++; 1621 /* Post L3/L4 errors to stack.*/ 1622 oce_rx(rq, cqe->u0.s.frag_index, cqe); 1623 } 1624 rq->rx_stats.rx_compl++; 1625 cqe->u0.dw[2] = 0; 1626 1627 #if defined(INET6) || defined(INET) 1628 #if 0 /* XXX swildner: LRO */ 1629 if (IF_LRO_ENABLED(sc) && rq->lro_pkts_queued >= 16) { 1630 oce_rx_flush_lro(rq); 1631 } 1632 #endif 1633 #endif 1634 1635 RING_GET(cq->ring, 1); 1636 bus_dmamap_sync(cq->ring->dma.tag, 1637 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE); 1638 cqe = 1639 RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_rx_cqe); 1640 num_cqes++; 1641 if (num_cqes >= (IS_XE201(sc) ? 8 : oce_max_rsp_handled)) 1642 break; 1643 } 1644 1645 #if defined(INET6) || defined(INET) 1646 #if 0 /* XXX swildner: LRO */ 1647 if (IF_LRO_ENABLED(sc)) 1648 oce_rx_flush_lro(rq); 1649 #endif 1650 #endif 1651 1652 if (num_cqes) { 1653 oce_arm_cq(sc, cq->cq_id, num_cqes, FALSE); 1654 rq_buffers_used = OCE_RQ_PACKET_ARRAY_SIZE - rq->pending; 1655 if (rq_buffers_used > 1) 1656 oce_alloc_rx_bufs(rq, (rq_buffers_used - 1)); 1657 } 1658 1659 UNLOCK(&rq->rx_lock); 1660 1661 return 0; 1662 1663 } 1664 1665 1666 1667 1668 /***************************************************************************** 1669 * Helper function prototypes in this file * 1670 *****************************************************************************/ 1671 1672 static int 1673 oce_attach_ifp(POCE_SOFTC sc) 1674 { 1675 1676 sc->ifp = if_alloc(IFT_ETHER); 1677 if (!sc->ifp) 1678 return ENOMEM; 1679 1680 ifmedia_init(&sc->media, IFM_IMASK, oce_media_change, oce_media_status); 1681 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1682 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 1683 1684 sc->ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST; 1685 sc->ifp->if_ioctl = oce_ioctl; 1686 sc->ifp->if_start = oce_start; 1687 sc->ifp->if_init = oce_init; 1688 sc->ifp->if_mtu = ETHERMTU; 1689 sc->ifp->if_softc = sc; 1690 #if 0 /* XXX swildner: MULTIQUEUE */ 1691 sc->ifp->if_transmit = oce_multiq_start; 1692 sc->ifp->if_qflush = oce_multiq_flush; 1693 #endif 1694 1695 if_initname(sc->ifp, 1696 device_get_name(sc->dev), device_get_unit(sc->dev)); 1697 1698 ifq_set_maxlen(&sc->ifp->if_snd, OCE_MAX_TX_DESC - 1); 1699 ifq_set_ready(&sc->ifp->if_snd); 1700 1701 sc->ifp->if_hwassist = OCE_IF_HWASSIST; 1702 sc->ifp->if_hwassist |= CSUM_TSO; 1703 sc->ifp->if_hwassist |= (CSUM_IP | CSUM_TCP | CSUM_UDP); 1704 1705 sc->ifp->if_capabilities = OCE_IF_CAPABILITIES; 1706 sc->ifp->if_capabilities |= IFCAP_HWCSUM; 1707 #if 0 /* XXX swildner: VLAN_HWFILTER */ 1708 sc->ifp->if_capabilities |= IFCAP_VLAN_HWFILTER; 1709 #endif 1710 1711 #if defined(INET6) || defined(INET) 1712 sc->ifp->if_capabilities |= IFCAP_TSO; 1713 #if 0 /* XXX swildner: LRO */ 1714 sc->ifp->if_capabilities |= IFCAP_LRO; 1715 #endif 1716 #if 0 /* XXX swildner: VLAN_HWTSO */ 1717 sc->ifp->if_capabilities |= IFCAP_VLAN_HWTSO; 1718 #endif 1719 #endif 1720 1721 sc->ifp->if_capenable = sc->ifp->if_capabilities; 1722 sc->ifp->if_baudrate = IF_Gbps(10UL); 1723 1724 ether_ifattach(sc->ifp, sc->macaddr.mac_addr, NULL); 1725 1726 return 0; 1727 } 1728 1729 1730 static void 1731 oce_add_vlan(void *arg, struct ifnet *ifp, uint16_t vtag) 1732 { 1733 POCE_SOFTC sc = ifp->if_softc; 1734 1735 if (ifp->if_softc != arg) 1736 return; 1737 if ((vtag == 0) || (vtag > 4095)) 1738 return; 1739 1740 sc->vlan_tag[vtag] = 1; 1741 sc->vlans_added++; 1742 oce_vid_config(sc); 1743 } 1744 1745 1746 static void 1747 oce_del_vlan(void *arg, struct ifnet *ifp, uint16_t vtag) 1748 { 1749 POCE_SOFTC sc = ifp->if_softc; 1750 1751 if (ifp->if_softc != arg) 1752 return; 1753 if ((vtag == 0) || (vtag > 4095)) 1754 return; 1755 1756 sc->vlan_tag[vtag] = 0; 1757 sc->vlans_added--; 1758 oce_vid_config(sc); 1759 } 1760 1761 1762 /* 1763 * A max of 64 vlans can be configured in BE. If the user configures 1764 * more, place the card in vlan promiscuous mode. 1765 */ 1766 static int 1767 oce_vid_config(POCE_SOFTC sc) 1768 { 1769 #if 0 /* XXX swildner: VLAN_HWFILTER */ 1770 struct normal_vlan vtags[MAX_VLANFILTER_SIZE]; 1771 uint16_t ntags = 0, i; 1772 #endif 1773 int status = 0; 1774 1775 #if 0 /* XXX swildner: VLAN_HWFILTER */ 1776 if ((sc->vlans_added <= MAX_VLANFILTER_SIZE) && 1777 (sc->ifp->if_capenable & IFCAP_VLAN_HWFILTER)) { 1778 for (i = 0; i < MAX_VLANS; i++) { 1779 if (sc->vlan_tag[i]) { 1780 vtags[ntags].vtag = i; 1781 ntags++; 1782 } 1783 } 1784 if (ntags) 1785 status = oce_config_vlan(sc, (uint8_t) sc->if_id, 1786 vtags, ntags, 1, 0); 1787 } else 1788 #endif 1789 status = oce_config_vlan(sc, (uint8_t) sc->if_id, 1790 NULL, 0, 1, 1); 1791 return status; 1792 } 1793 1794 1795 static void 1796 oce_mac_addr_set(POCE_SOFTC sc) 1797 { 1798 uint32_t old_pmac_id = sc->pmac_id; 1799 int status = 0; 1800 1801 1802 status = bcmp((IF_LLADDR(sc->ifp)), sc->macaddr.mac_addr, 1803 sc->macaddr.size_of_struct); 1804 if (!status) 1805 return; 1806 1807 status = oce_mbox_macaddr_add(sc, (uint8_t *)(IF_LLADDR(sc->ifp)), 1808 sc->if_id, &sc->pmac_id); 1809 if (!status) { 1810 status = oce_mbox_macaddr_del(sc, sc->if_id, old_pmac_id); 1811 bcopy((IF_LLADDR(sc->ifp)), sc->macaddr.mac_addr, 1812 sc->macaddr.size_of_struct); 1813 } 1814 if (status) 1815 device_printf(sc->dev, "Failed update macaddress\n"); 1816 1817 } 1818 1819 1820 static int 1821 oce_handle_passthrough(struct ifnet *ifp, caddr_t data) 1822 { 1823 POCE_SOFTC sc = ifp->if_softc; 1824 struct ifreq *ifr = (struct ifreq *)data; 1825 int rc = ENXIO; 1826 char cookie[32] = {0}; 1827 void *priv_data = (void *)ifr->ifr_data; 1828 void *ioctl_ptr; 1829 uint32_t req_size; 1830 struct mbx_hdr req; 1831 OCE_DMA_MEM dma_mem; 1832 struct mbx_common_get_cntl_attr *fw_cmd; 1833 1834 if (copyin(priv_data, cookie, strlen(IOCTL_COOKIE))) 1835 return EFAULT; 1836 1837 if (memcmp(cookie, IOCTL_COOKIE, strlen(IOCTL_COOKIE))) 1838 return EINVAL; 1839 1840 ioctl_ptr = (char *)priv_data + strlen(IOCTL_COOKIE); 1841 if (copyin(ioctl_ptr, &req, sizeof(struct mbx_hdr))) 1842 return EFAULT; 1843 1844 req_size = le32toh(req.u0.req.request_length); 1845 if (req_size > 65536) 1846 return EINVAL; 1847 1848 req_size += sizeof(struct mbx_hdr); 1849 rc = oce_dma_alloc(sc, req_size, &dma_mem, 0); 1850 if (rc) 1851 return ENOMEM; 1852 1853 if (copyin(ioctl_ptr, OCE_DMAPTR(&dma_mem,char), req_size)) { 1854 rc = EFAULT; 1855 goto dma_free; 1856 } 1857 1858 rc = oce_pass_through_mbox(sc, &dma_mem, req_size); 1859 if (rc) { 1860 rc = EIO; 1861 goto dma_free; 1862 } 1863 1864 if (copyout(OCE_DMAPTR(&dma_mem,char), ioctl_ptr, req_size)) 1865 rc = EFAULT; 1866 1867 /* 1868 firmware is filling all the attributes for this ioctl except 1869 the driver version..so fill it 1870 */ 1871 if(req.u0.rsp.opcode == OPCODE_COMMON_GET_CNTL_ATTRIBUTES) { 1872 fw_cmd = (struct mbx_common_get_cntl_attr *) ioctl_ptr; 1873 strncpy(fw_cmd->params.rsp.cntl_attr_info.hba_attr.drv_ver_str, 1874 COMPONENT_REVISION, strlen(COMPONENT_REVISION)); 1875 } 1876 1877 dma_free: 1878 oce_dma_free(sc, &dma_mem); 1879 return rc; 1880 1881 } 1882 1883 static void 1884 oce_eqd_set_periodic(POCE_SOFTC sc) 1885 { 1886 struct oce_set_eqd set_eqd[OCE_MAX_EQ]; 1887 struct oce_aic_obj *aic; 1888 struct oce_eq *eqo; 1889 uint64_t now = 0, delta; 1890 int eqd, i, num = 0; 1891 uint32_t ips = 0; 1892 int tps; 1893 1894 for (i = 0 ; i < sc->neqs; i++) { 1895 eqo = sc->eq[i]; 1896 aic = &sc->aic_obj[i]; 1897 /* When setting the static eq delay from the user space */ 1898 if (!aic->enable) { 1899 eqd = aic->et_eqd; 1900 goto modify_eqd; 1901 } 1902 1903 now = ticks; 1904 1905 /* Over flow check */ 1906 if ((now < aic->ticks) || (eqo->intr < aic->intr_prev)) 1907 goto done; 1908 1909 delta = now - aic->ticks; 1910 tps = delta/hz; 1911 1912 /* Interrupt rate based on elapsed ticks */ 1913 if(tps) 1914 ips = (uint32_t)(eqo->intr - aic->intr_prev) / tps; 1915 1916 if (ips > INTR_RATE_HWM) 1917 eqd = aic->cur_eqd + 20; 1918 else if (ips < INTR_RATE_LWM) 1919 eqd = aic->cur_eqd / 2; 1920 else 1921 goto done; 1922 1923 if (eqd < 10) 1924 eqd = 0; 1925 1926 /* Make sure that the eq delay is in the known range */ 1927 eqd = min(eqd, aic->max_eqd); 1928 eqd = max(eqd, aic->min_eqd); 1929 1930 modify_eqd: 1931 if (eqd != aic->cur_eqd) { 1932 set_eqd[num].delay_multiplier = (eqd * 65)/100; 1933 set_eqd[num].eq_id = eqo->eq_id; 1934 aic->cur_eqd = eqd; 1935 num++; 1936 } 1937 done: 1938 aic->intr_prev = eqo->intr; 1939 aic->ticks = now; 1940 } 1941 1942 /* Is there atleast one eq that needs to be modified? */ 1943 if(num) 1944 oce_mbox_eqd_modify_periodic(sc, set_eqd, num); 1945 1946 } 1947 1948 static void 1949 oce_local_timer(void *arg) 1950 { 1951 POCE_SOFTC sc = arg; 1952 int i = 0; 1953 1954 lwkt_serialize_enter(sc->ifp->if_serializer); 1955 oce_refresh_nic_stats(sc); 1956 oce_refresh_queue_stats(sc); 1957 oce_mac_addr_set(sc); 1958 1959 /* TX Watch Dog*/ 1960 for (i = 0; i < sc->nwqs; i++) 1961 oce_tx_restart(sc, sc->wq[i]); 1962 1963 /* calculate and set the eq delay for optimal interrupt rate */ 1964 if (IS_BE(sc)) 1965 oce_eqd_set_periodic(sc); 1966 1967 callout_reset(&sc->timer, hz, oce_local_timer, sc); 1968 lwkt_serialize_exit(sc->ifp->if_serializer); 1969 } 1970 1971 1972 /* NOTE : This should only be called holding 1973 * DEVICE_LOCK. 1974 */ 1975 static void 1976 oce_if_deactivate(POCE_SOFTC sc) 1977 { 1978 int i, mtime = 0; 1979 int wait_req = 0; 1980 struct oce_rq *rq; 1981 struct oce_wq *wq; 1982 struct oce_eq *eq; 1983 1984 sc->ifp->if_flags &= ~IFF_RUNNING; 1985 ifq_clr_oactive(&sc->ifp->if_snd); 1986 1987 /*Wait for max of 400ms for TX completions to be done */ 1988 while (mtime < 400) { 1989 wait_req = 0; 1990 for_all_wq_queues(sc, wq, i) { 1991 if (wq->ring->num_used) { 1992 wait_req = 1; 1993 DELAY(1); 1994 break; 1995 } 1996 } 1997 mtime += 1; 1998 if (!wait_req) 1999 break; 2000 } 2001 2002 /* Stop intrs and finish any bottom halves pending */ 2003 oce_hw_intr_disable(sc); 2004 2005 /* Since taskqueue_drain takes a Gaint Lock, We should not acquire 2006 any other lock. So unlock device lock and require after 2007 completing taskqueue_drain. 2008 */ 2009 UNLOCK(&sc->dev_lock); 2010 for (i = 0; i < sc->intr_count; i++) { 2011 if (sc->intrs[i].tq != NULL) { 2012 taskqueue_drain(sc->intrs[i].tq, &sc->intrs[i].task); 2013 } 2014 } 2015 LOCK(&sc->dev_lock); 2016 2017 /* Delete RX queue in card with flush param */ 2018 oce_stop_rx(sc); 2019 2020 /* Invalidate any pending cq and eq entries*/ 2021 for_all_evnt_queues(sc, eq, i) 2022 oce_drain_eq(eq); 2023 for_all_rq_queues(sc, rq, i) 2024 oce_drain_rq_cq(rq); 2025 for_all_wq_queues(sc, wq, i) 2026 oce_drain_wq_cq(wq); 2027 2028 /* But still we need to get MCC aync events. 2029 So enable intrs and also arm first EQ 2030 */ 2031 oce_hw_intr_enable(sc); 2032 oce_arm_eq(sc, sc->eq[0]->eq_id, 0, TRUE, FALSE); 2033 2034 DELAY(10); 2035 } 2036 2037 2038 static void 2039 oce_if_activate(POCE_SOFTC sc) 2040 { 2041 struct oce_eq *eq; 2042 struct oce_rq *rq; 2043 struct oce_wq *wq; 2044 int i, rc = 0; 2045 2046 sc->ifp->if_flags |= IFF_RUNNING; 2047 2048 oce_hw_intr_disable(sc); 2049 2050 oce_start_rx(sc); 2051 2052 for_all_rq_queues(sc, rq, i) { 2053 rc = oce_start_rq(rq); 2054 if (rc) 2055 device_printf(sc->dev, "Unable to start RX\n"); 2056 } 2057 2058 for_all_wq_queues(sc, wq, i) { 2059 rc = oce_start_wq(wq); 2060 if (rc) 2061 device_printf(sc->dev, "Unable to start TX\n"); 2062 } 2063 2064 2065 for_all_evnt_queues(sc, eq, i) 2066 oce_arm_eq(sc, eq->eq_id, 0, TRUE, FALSE); 2067 2068 oce_hw_intr_enable(sc); 2069 2070 } 2071 2072 static void 2073 process_link_state(POCE_SOFTC sc, struct oce_async_cqe_link_state *acqe) 2074 { 2075 /* Update Link status */ 2076 if ((acqe->u0.s.link_status & ~ASYNC_EVENT_LOGICAL) == 2077 ASYNC_EVENT_LINK_UP) { 2078 sc->link_status = ASYNC_EVENT_LINK_UP; 2079 if_link_state_change(sc->ifp); 2080 } else { 2081 sc->link_status = ASYNC_EVENT_LINK_DOWN; 2082 if_link_state_change(sc->ifp); 2083 } 2084 2085 /* Update speed */ 2086 sc->link_speed = acqe->u0.s.speed; 2087 sc->qos_link_speed = (uint32_t) acqe->u0.s.qos_link_speed * 10; 2088 2089 } 2090 2091 2092 /* Handle the Completion Queue for the Mailbox/Async notifications */ 2093 uint16_t 2094 oce_mq_handler(void *arg) 2095 { 2096 struct oce_mq *mq = (struct oce_mq *)arg; 2097 POCE_SOFTC sc = mq->parent; 2098 struct oce_cq *cq = mq->cq; 2099 int num_cqes = 0, evt_type = 0, optype = 0; 2100 struct oce_mq_cqe *cqe; 2101 struct oce_async_cqe_link_state *acqe; 2102 struct oce_async_event_grp5_pvid_state *gcqe; 2103 struct oce_async_event_qnq *dbgcqe; 2104 2105 2106 bus_dmamap_sync(cq->ring->dma.tag, 2107 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE); 2108 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_mq_cqe); 2109 2110 while (cqe->u0.dw[3]) { 2111 DW_SWAP((uint32_t *) cqe, sizeof(oce_mq_cqe)); 2112 if (cqe->u0.s.async_event) { 2113 evt_type = cqe->u0.s.event_type; 2114 optype = cqe->u0.s.async_type; 2115 if (evt_type == ASYNC_EVENT_CODE_LINK_STATE) { 2116 /* Link status evt */ 2117 acqe = (struct oce_async_cqe_link_state *)cqe; 2118 process_link_state(sc, acqe); 2119 } else if ((evt_type == ASYNC_EVENT_GRP5) && 2120 (optype == ASYNC_EVENT_PVID_STATE)) { 2121 /* GRP5 PVID */ 2122 gcqe = 2123 (struct oce_async_event_grp5_pvid_state *)cqe; 2124 if (gcqe->enabled) 2125 sc->pvid = gcqe->tag & VLAN_VID_MASK; 2126 else 2127 sc->pvid = 0; 2128 2129 } 2130 else if(evt_type == ASYNC_EVENT_CODE_DEBUG && 2131 optype == ASYNC_EVENT_DEBUG_QNQ) { 2132 dbgcqe = 2133 (struct oce_async_event_qnq *)cqe; 2134 if(dbgcqe->valid) 2135 sc->qnqid = dbgcqe->vlan_tag; 2136 sc->qnq_debug_event = TRUE; 2137 } 2138 } 2139 cqe->u0.dw[3] = 0; 2140 RING_GET(cq->ring, 1); 2141 bus_dmamap_sync(cq->ring->dma.tag, 2142 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE); 2143 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_mq_cqe); 2144 num_cqes++; 2145 } 2146 2147 if (num_cqes) 2148 oce_arm_cq(sc, cq->cq_id, num_cqes, FALSE); 2149 2150 return 0; 2151 } 2152 2153 2154 static void 2155 setup_max_queues_want(POCE_SOFTC sc) 2156 { 2157 int max_rss = 0; 2158 2159 /* Check if it is FLEX machine. Is so dont use RSS */ 2160 if ((sc->function_mode & FNM_FLEX10_MODE) || 2161 (sc->function_mode & FNM_UMC_MODE) || 2162 (sc->function_mode & FNM_VNIC_MODE) || 2163 (!sc->rss_enable) || 2164 (sc->flags & OCE_FLAGS_BE2)) { 2165 sc->nrqs = 1; 2166 sc->nwqs = 1; 2167 sc->rss_enable = 0; 2168 } else { 2169 /* For multiq, our deisgn is to have TX rings equal to 2170 RSS rings. So that we can pair up one RSS ring and TX 2171 to a single intr, which improves CPU cache efficiency. 2172 */ 2173 if (IS_BE(sc) && (!sc->be3_native)) 2174 max_rss = OCE_LEGACY_MODE_RSS; 2175 else 2176 max_rss = OCE_MAX_RSS; 2177 2178 sc->nrqs = MIN(OCE_NCPUS, max_rss) + 1; /* 1 for def RX */ 2179 sc->nwqs = MIN(OCE_NCPUS, max_rss); 2180 } 2181 2182 } 2183 2184 2185 static void 2186 update_queues_got(POCE_SOFTC sc) 2187 { 2188 if (sc->rss_enable) { 2189 sc->nrqs = sc->intr_count + 1; 2190 sc->nwqs = sc->intr_count; 2191 } else { 2192 sc->nrqs = 1; 2193 sc->nwqs = 1; 2194 } 2195 } 2196 2197 static int 2198 oce_check_ipv6_ext_hdr(struct mbuf *m) 2199 { 2200 struct ether_header *eh = mtod(m, struct ether_header *); 2201 caddr_t m_datatemp = m->m_data; 2202 2203 if (eh->ether_type == htons(ETHERTYPE_IPV6)) { 2204 m->m_data += sizeof(struct ether_header); 2205 struct ip6_hdr *ip6 = mtod(m, struct ip6_hdr *); 2206 2207 if((ip6->ip6_nxt != IPPROTO_TCP) && \ 2208 (ip6->ip6_nxt != IPPROTO_UDP)){ 2209 struct ip6_ext *ip6e = NULL; 2210 m->m_data += sizeof(struct ip6_hdr); 2211 2212 ip6e = (struct ip6_ext *) mtod(m, struct ip6_ext *); 2213 if(ip6e->ip6e_len == 0xff) { 2214 m->m_data = m_datatemp; 2215 return TRUE; 2216 } 2217 } 2218 m->m_data = m_datatemp; 2219 } 2220 return FALSE; 2221 } 2222 2223 static int 2224 is_be3_a1(POCE_SOFTC sc) 2225 { 2226 if((sc->flags & OCE_FLAGS_BE3) && ((sc->asic_revision & 0xFF) < 2)) { 2227 return TRUE; 2228 } 2229 return FALSE; 2230 } 2231 2232 static struct mbuf * 2233 oce_insert_vlan_tag(POCE_SOFTC sc, struct mbuf *m, boolean_t *complete) 2234 { 2235 uint16_t vlan_tag = 0; 2236 2237 if(!M_WRITABLE(m)) 2238 return NULL; 2239 2240 #if 0 /* XXX swildner: ETHER_VTAG */ 2241 /* Embed vlan tag in the packet if it is not part of it */ 2242 if(m->m_flags & M_VLANTAG) { 2243 vlan_tag = EVL_VLANOFTAG(m->m_pkthdr.ether_vtag); 2244 m->m_flags &= ~M_VLANTAG; 2245 } 2246 #endif 2247 2248 /* if UMC, ignore vlan tag insertion and instead insert pvid */ 2249 if(sc->pvid) { 2250 if(!vlan_tag) 2251 vlan_tag = sc->pvid; 2252 *complete = FALSE; 2253 } 2254 2255 #if 0 /* XXX swildner: ETHER_VTAG */ 2256 if(vlan_tag) { 2257 m = ether_vlanencap(m, vlan_tag); 2258 } 2259 2260 if(sc->qnqid) { 2261 m = ether_vlanencap(m, sc->qnqid); 2262 *complete = FALSE; 2263 } 2264 #endif 2265 return m; 2266 } 2267 2268 static int 2269 oce_tx_asic_stall_verify(POCE_SOFTC sc, struct mbuf *m) 2270 { 2271 if(is_be3_a1(sc) && IS_QNQ_OR_UMC(sc) && \ 2272 oce_check_ipv6_ext_hdr(m)) { 2273 return TRUE; 2274 } 2275 return FALSE; 2276 } 2277