1 /* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/pci/if_pcn.c,v 1.5.2.10 2003/03/05 18:42:33 njl Exp $ 34 * $DragonFly: src/sys/dev/netif/pcn/if_pcn.c,v 1.30 2006/08/01 18:06:14 swildner Exp $ 35 */ 36 37 /* 38 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 39 * from http://www.amd.com. 40 * 41 * Written by Bill Paul <wpaul@osd.bsdi.com> 42 */ 43 44 /* 45 * The AMD PCnet/PCI controllers are more advanced and functional 46 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 47 * backwards compatibility with the LANCE and thus can be made 48 * to work with older LANCE drivers. This is in fact how the 49 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 50 * is that the PCnet/PCI devices offer several performance enhancements 51 * which can't be exploited in LANCE compatibility mode. Chief among 52 * these enhancements is the ability to perform PCI DMA operations 53 * using 32-bit addressing (which eliminates the need for ISA 54 * bounce-buffering), and special receive buffer alignment (which 55 * allows the receive handler to pass packets to the upper protocol 56 * layers without copying on both the x86 and alpha platforms). 57 */ 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/sockio.h> 62 #include <sys/mbuf.h> 63 #include <sys/malloc.h> 64 #include <sys/kernel.h> 65 #include <sys/socket.h> 66 #include <sys/serialize.h> 67 #include <sys/thread2.h> 68 69 #include <net/if.h> 70 #include <net/ifq_var.h> 71 #include <net/if_arp.h> 72 #include <net/ethernet.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 76 #include <net/bpf.h> 77 78 #include <vm/vm.h> /* for vtophys */ 79 #include <vm/pmap.h> /* for vtophys */ 80 #include <machine/clock.h> /* for DELAY */ 81 #include <machine/bus_pio.h> 82 #include <machine/bus_memio.h> 83 #include <machine/bus.h> 84 #include <machine/resource.h> 85 #include <sys/bus.h> 86 #include <sys/rman.h> 87 88 #include "../mii_layer/mii.h" 89 #include "../mii_layer/miivar.h" 90 91 #include <bus/pci/pcidevs.h> 92 #include <bus/pci/pcireg.h> 93 #include <bus/pci/pcivar.h> 94 95 #define PCN_USEIOSPACE 96 97 #include "if_pcnreg.h" 98 99 /* "controller miibus0" required. See GENERIC if you get errors here. */ 100 #include "miibus_if.h" 101 102 /* 103 * Various supported device vendors/types and their names. 104 */ 105 static struct pcn_type pcn_devs[] = { 106 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PCNET_PCI, 107 "AMD PCnet/PCI 10/100BaseTX" }, 108 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PCNET_HOME, 109 "AMD PCnet/Home HomePNA" }, 110 { 0, 0, NULL } 111 }; 112 113 static u_int32_t pcn_csr_read (struct pcn_softc *, int); 114 static u_int16_t pcn_csr_read16 (struct pcn_softc *, int); 115 static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int); 116 static void pcn_csr_write (struct pcn_softc *, int, int); 117 static u_int32_t pcn_bcr_read (struct pcn_softc *, int); 118 static void pcn_bcr_write (struct pcn_softc *, int, int); 119 120 static int pcn_probe (device_t); 121 static int pcn_attach (device_t); 122 static int pcn_detach (device_t); 123 124 static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *); 125 static int pcn_encap (struct pcn_softc *, 126 struct mbuf *, u_int32_t *); 127 static void pcn_rxeof (struct pcn_softc *); 128 static void pcn_txeof (struct pcn_softc *); 129 static void pcn_intr (void *); 130 static void pcn_tick (void *); 131 static void pcn_start (struct ifnet *); 132 static int pcn_ioctl (struct ifnet *, u_long, caddr_t, 133 struct ucred *); 134 static void pcn_init (void *); 135 static void pcn_stop (struct pcn_softc *); 136 static void pcn_watchdog (struct ifnet *); 137 static void pcn_shutdown (device_t); 138 static int pcn_ifmedia_upd (struct ifnet *); 139 static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *); 140 141 static int pcn_miibus_readreg (device_t, int, int); 142 static int pcn_miibus_writereg (device_t, int, int, int); 143 static void pcn_miibus_statchg (device_t); 144 145 static void pcn_setfilt (struct ifnet *); 146 static void pcn_setmulti (struct pcn_softc *); 147 static u_int32_t pcn_crc (caddr_t); 148 static void pcn_reset (struct pcn_softc *); 149 static int pcn_list_rx_init (struct pcn_softc *); 150 static int pcn_list_tx_init (struct pcn_softc *); 151 152 #ifdef PCN_USEIOSPACE 153 #define PCN_RES SYS_RES_IOPORT 154 #define PCN_RID PCN_PCI_LOIO 155 #else 156 #define PCN_RES SYS_RES_MEMORY 157 #define PCN_RID PCN_PCI_LOMEM 158 #endif 159 160 static device_method_t pcn_methods[] = { 161 /* Device interface */ 162 DEVMETHOD(device_probe, pcn_probe), 163 DEVMETHOD(device_attach, pcn_attach), 164 DEVMETHOD(device_detach, pcn_detach), 165 DEVMETHOD(device_shutdown, pcn_shutdown), 166 167 /* bus interface */ 168 DEVMETHOD(bus_print_child, bus_generic_print_child), 169 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 170 171 /* MII interface */ 172 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 173 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 174 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 175 176 { 0, 0 } 177 }; 178 179 static driver_t pcn_driver = { 180 "pcn", 181 pcn_methods, 182 sizeof(struct pcn_softc) 183 }; 184 185 static devclass_t pcn_devclass; 186 187 DECLARE_DUMMY_MODULE(if_pcn); 188 DRIVER_MODULE(if_pcn, pci, pcn_driver, pcn_devclass, 0, 0); 189 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 190 191 #define PCN_CSR_SETBIT(sc, reg, x) \ 192 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 193 194 #define PCN_CSR_CLRBIT(sc, reg, x) \ 195 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 196 197 #define PCN_BCR_SETBIT(sc, reg, x) \ 198 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 199 200 #define PCN_BCR_CLRBIT(sc, reg, x) \ 201 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 202 203 static u_int32_t 204 pcn_csr_read(struct pcn_softc *sc, int reg) 205 { 206 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 207 return(CSR_READ_4(sc, PCN_IO32_RDP)); 208 } 209 210 static u_int16_t 211 pcn_csr_read16(struct pcn_softc *sc, int reg) 212 { 213 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 214 return(CSR_READ_2(sc, PCN_IO16_RDP)); 215 } 216 217 static void 218 pcn_csr_write(struct pcn_softc *sc, int reg, int val) 219 { 220 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 221 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 222 return; 223 } 224 225 static u_int32_t 226 pcn_bcr_read(struct pcn_softc *sc, int reg) 227 { 228 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 229 return(CSR_READ_4(sc, PCN_IO32_BDP)); 230 } 231 232 static u_int16_t 233 pcn_bcr_read16(struct pcn_softc *sc, int reg) 234 { 235 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 236 return(CSR_READ_2(sc, PCN_IO16_BDP)); 237 } 238 239 static void 240 pcn_bcr_write(struct pcn_softc *sc, int reg, int val) 241 { 242 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 243 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 244 return; 245 } 246 247 static int 248 pcn_miibus_readreg(device_t dev, int phy, int reg) 249 { 250 struct pcn_softc *sc; 251 int val; 252 253 sc = device_get_softc(dev); 254 255 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 256 return(0); 257 258 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 259 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 260 if (val == 0xFFFF) 261 return(0); 262 263 sc->pcn_phyaddr = phy; 264 265 return(val); 266 } 267 268 static int 269 pcn_miibus_writereg(device_t dev, int phy, int reg, int data) 270 { 271 struct pcn_softc *sc; 272 273 sc = device_get_softc(dev); 274 275 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 276 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 277 278 return(0); 279 } 280 281 static void 282 pcn_miibus_statchg(device_t dev) 283 { 284 struct pcn_softc *sc; 285 struct mii_data *mii; 286 287 sc = device_get_softc(dev); 288 mii = device_get_softc(sc->pcn_miibus); 289 290 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 291 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 292 } else { 293 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 294 } 295 296 return; 297 } 298 299 #define DC_POLY 0xEDB88320 300 301 static u_int32_t 302 pcn_crc(caddr_t addr) 303 { 304 u_int32_t idx, bit, data, crc; 305 306 /* Compute CRC for the address value. */ 307 crc = 0xFFFFFFFF; /* initial value */ 308 309 for (idx = 0; idx < 6; idx++) { 310 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 311 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 312 } 313 314 return ((crc >> 26) & 0x3F); 315 } 316 317 static void 318 pcn_setmulti(struct pcn_softc *sc) 319 { 320 struct ifnet *ifp; 321 struct ifmultiaddr *ifma; 322 u_int32_t h, i; 323 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 324 325 ifp = &sc->arpcom.ac_if; 326 327 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 328 329 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 330 for (i = 0; i < 4; i++) 331 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 332 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 333 return; 334 } 335 336 /* first, zot all the existing hash bits */ 337 for (i = 0; i < 4; i++) 338 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 339 340 /* now program new ones */ 341 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 342 if (ifma->ifma_addr->sa_family != AF_LINK) 343 continue; 344 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 345 hashes[h >> 4] |= 1 << (h & 0xF); 346 } 347 348 for (i = 0; i < 4; i++) 349 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 350 351 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 352 353 return; 354 } 355 356 static void 357 pcn_reset(struct pcn_softc *sc) 358 { 359 /* 360 * Issue a reset by reading from the RESET register. 361 * Note that we don't know if the chip is operating in 362 * 16-bit or 32-bit mode at this point, so we attempt 363 * to reset the chip both ways. If one fails, the other 364 * will succeed. 365 */ 366 CSR_READ_2(sc, PCN_IO16_RESET); 367 CSR_READ_4(sc, PCN_IO32_RESET); 368 369 /* Wait a little while for the chip to get its brains in order. */ 370 DELAY(1000); 371 372 /* Select 32-bit (DWIO) mode */ 373 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 374 375 /* Select software style 3. */ 376 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 377 378 return; 379 } 380 381 /* 382 * Probe for an AMD chip. Check the PCI vendor and device 383 * IDs against our list and return a device name if we find a match. 384 */ 385 static int 386 pcn_probe(device_t dev) 387 { 388 struct pcn_type *t; 389 struct pcn_softc *sc; 390 int rid; 391 u_int32_t chip_id; 392 393 t = pcn_devs; 394 sc = device_get_softc(dev); 395 396 while(t->pcn_name != NULL) { 397 if ((pci_get_vendor(dev) == t->pcn_vid) && 398 (pci_get_device(dev) == t->pcn_did)) { 399 /* 400 * Temporarily map the I/O space 401 * so we can read the chip ID register. 402 */ 403 rid = PCN_RID; 404 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, 405 &rid, RF_ACTIVE); 406 if (sc->pcn_res == NULL) { 407 device_printf(dev, 408 "couldn't map ports/memory\n"); 409 return(ENXIO); 410 } 411 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 412 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 413 /* 414 * Note: we can *NOT* put the chip into 415 * 32-bit mode yet. The lnc driver will only 416 * work in 16-bit mode, and once the chip 417 * goes into 32-bit mode, the only way to 418 * get it out again is with a hardware reset. 419 * So if pcn_probe() is called before the 420 * lnc driver's probe routine, the chip will 421 * be locked into 32-bit operation and the lnc 422 * driver will be unable to attach to it. 423 * Note II: if the chip happens to already 424 * be in 32-bit mode, we still need to check 425 * the chip ID, but first we have to detect 426 * 32-bit mode using only 16-bit operations. 427 * The safest way to do this is to read the 428 * PCI subsystem ID from BCR23/24 and compare 429 * that with the value read from PCI config 430 * space. 431 */ 432 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 433 chip_id <<= 16; 434 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 435 /* 436 * Note III: the test for 0x10001000 is a hack to 437 * pacify VMware, who's pseudo-PCnet interface is 438 * broken. Reading the subsystem register from PCI 439 * config space yeilds 0x00000000 while reading the 440 * same value from I/O space yeilds 0x10001000. It's 441 * not supposed to be that way. 442 */ 443 if (chip_id == pci_read_config(dev, 444 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 445 /* We're in 16-bit mode. */ 446 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 447 chip_id <<= 16; 448 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 449 } else { 450 /* We're in 32-bit mode. */ 451 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 452 chip_id <<= 16; 453 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 454 } 455 bus_release_resource(dev, PCN_RES, 456 PCN_RID, sc->pcn_res); 457 chip_id >>= 12; 458 sc->pcn_type = chip_id & PART_MASK; 459 switch(sc->pcn_type) { 460 case Am79C971: 461 case Am79C972: 462 case Am79C973: 463 case Am79C975: 464 case Am79C976: 465 case Am79C978: 466 break; 467 default: 468 return(ENXIO); 469 break; 470 } 471 device_set_desc(dev, t->pcn_name); 472 return(0); 473 } 474 t++; 475 } 476 477 return(ENXIO); 478 } 479 480 /* 481 * Attach the interface. Allocate softc structures, do ifmedia 482 * setup and ethernet/BPF attach. 483 */ 484 static int 485 pcn_attach(device_t dev) 486 { 487 uint8_t eaddr[ETHER_ADDR_LEN]; 488 u_int32_t command; 489 struct pcn_softc *sc; 490 struct ifnet *ifp; 491 int unit, error = 0, rid; 492 493 sc = device_get_softc(dev); 494 unit = device_get_unit(dev); 495 496 /* 497 * Handle power management nonsense. 498 */ 499 500 command = pci_read_config(dev, PCN_PCI_CAPID, 4) & 0x000000FF; 501 if (command == 0x01) { 502 503 command = pci_read_config(dev, PCN_PCI_PWRMGMTCTRL, 4); 504 if (command & PCN_PSTATE_MASK) { 505 u_int32_t iobase, membase, irq; 506 507 /* Save important PCI config data. */ 508 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 509 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 510 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 511 512 /* Reset the power state. */ 513 printf("pcn%d: chip is in D%d power mode " 514 "-- setting to D0\n", unit, command & PCN_PSTATE_MASK); 515 command &= 0xFFFFFFFC; 516 pci_write_config(dev, PCN_PCI_PWRMGMTCTRL, command, 4); 517 518 /* Restore PCI config data. */ 519 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 520 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 521 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 522 } 523 } 524 525 /* 526 * Map control/status registers. 527 */ 528 command = pci_read_config(dev, PCIR_COMMAND, 4); 529 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 530 pci_write_config(dev, PCIR_COMMAND, command, 4); 531 command = pci_read_config(dev, PCIR_COMMAND, 4); 532 533 #ifdef PCN_USEIOSPACE 534 if (!(command & PCIM_CMD_PORTEN)) { 535 printf("pcn%d: failed to enable I/O ports!\n", unit); 536 error = ENXIO; 537 return(error); 538 } 539 #else 540 if (!(command & PCIM_CMD_MEMEN)) { 541 printf("pcn%d: failed to enable memory mapping!\n", unit); 542 error = ENXIO; 543 return(error); 544 } 545 #endif 546 547 rid = PCN_RID; 548 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE); 549 550 if (sc->pcn_res == NULL) { 551 printf("pcn%d: couldn't map ports/memory\n", unit); 552 error = ENXIO; 553 return(error); 554 } 555 556 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 557 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 558 559 /* Allocate interrupt */ 560 rid = 0; 561 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 562 RF_SHAREABLE | RF_ACTIVE); 563 564 if (sc->pcn_irq == NULL) { 565 printf("pcn%d: couldn't map interrupt\n", unit); 566 error = ENXIO; 567 goto fail; 568 } 569 570 /* Reset the adapter. */ 571 pcn_reset(sc); 572 573 /* 574 * Get station address from the EEPROM. 575 */ 576 *(uint32_t *)eaddr = CSR_READ_4(sc, PCN_IO32_APROM00); 577 *(uint16_t *)(eaddr + 4) = CSR_READ_2(sc, PCN_IO32_APROM01); 578 579 sc->pcn_unit = unit; 580 callout_init(&sc->pcn_stat_timer); 581 582 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 583 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 584 585 if (sc->pcn_ldata == NULL) { 586 printf("pcn%d: no memory for list buffers!\n", unit); 587 error = ENXIO; 588 goto fail; 589 } 590 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 591 592 ifp = &sc->arpcom.ac_if; 593 ifp->if_softc = sc; 594 if_initname(ifp, "pcn", unit); 595 ifp->if_mtu = ETHERMTU; 596 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 597 ifp->if_ioctl = pcn_ioctl; 598 ifp->if_start = pcn_start; 599 ifp->if_watchdog = pcn_watchdog; 600 ifp->if_init = pcn_init; 601 ifp->if_baudrate = 10000000; 602 ifq_set_maxlen(&ifp->if_snd, PCN_TX_LIST_CNT - 1); 603 ifq_set_ready(&ifp->if_snd); 604 605 /* 606 * Do MII setup. 607 */ 608 if (mii_phy_probe(dev, &sc->pcn_miibus, 609 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 610 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 611 error = ENXIO; 612 goto fail; 613 } 614 615 /* 616 * Call MI attach routine. 617 */ 618 ether_ifattach(ifp, eaddr, NULL); 619 620 error = bus_setup_intr(dev, sc->pcn_irq, INTR_NETSAFE, 621 pcn_intr, sc, &sc->pcn_intrhand, 622 ifp->if_serializer); 623 if (error) { 624 ether_ifdetach(ifp); 625 device_printf(dev, "couldn't set up irq\n"); 626 goto fail; 627 } 628 629 return (0); 630 fail: 631 pcn_detach(dev); 632 return(error); 633 } 634 635 static int 636 pcn_detach(device_t dev) 637 { 638 struct pcn_softc *sc = device_get_softc(dev); 639 struct ifnet *ifp = &sc->arpcom.ac_if; 640 641 if (device_is_attached(dev)) { 642 lwkt_serialize_enter(ifp->if_serializer); 643 pcn_reset(sc); 644 pcn_stop(sc); 645 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 646 lwkt_serialize_exit(ifp->if_serializer); 647 648 ether_ifdetach(ifp); 649 } 650 651 if (sc->pcn_miibus != NULL) 652 device_delete_child(dev, sc->pcn_miibus); 653 bus_generic_detach(dev); 654 655 if (sc->pcn_irq) 656 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 657 if (sc->pcn_res) 658 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 659 660 if (sc->pcn_ldata) { 661 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 662 M_DEVBUF); 663 } 664 665 return(0); 666 } 667 668 /* 669 * Initialize the transmit descriptors. 670 */ 671 static int 672 pcn_list_tx_init(struct pcn_softc *sc) 673 { 674 struct pcn_list_data *ld; 675 struct pcn_ring_data *cd; 676 int i; 677 678 cd = &sc->pcn_cdata; 679 ld = sc->pcn_ldata; 680 681 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 682 cd->pcn_tx_chain[i] = NULL; 683 ld->pcn_tx_list[i].pcn_tbaddr = 0; 684 ld->pcn_tx_list[i].pcn_txctl = 0; 685 ld->pcn_tx_list[i].pcn_txstat = 0; 686 } 687 688 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 689 690 return(0); 691 } 692 693 694 /* 695 * Initialize the RX descriptors and allocate mbufs for them. 696 */ 697 static int 698 pcn_list_rx_init(struct pcn_softc *sc) 699 { 700 struct pcn_list_data *ld; 701 struct pcn_ring_data *cd; 702 int i; 703 704 ld = sc->pcn_ldata; 705 cd = &sc->pcn_cdata; 706 707 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 708 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 709 return(ENOBUFS); 710 } 711 712 cd->pcn_rx_prod = 0; 713 714 return(0); 715 } 716 717 /* 718 * Initialize an RX descriptor and attach an MBUF cluster. 719 */ 720 static int 721 pcn_newbuf(struct pcn_softc *sc, int idx, struct mbuf *m) 722 { 723 struct mbuf *m_new = NULL; 724 struct pcn_rx_desc *c; 725 726 c = &sc->pcn_ldata->pcn_rx_list[idx]; 727 728 if (m == NULL) { 729 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 730 if (m_new == NULL) 731 return(ENOBUFS); 732 733 MCLGET(m_new, MB_DONTWAIT); 734 if (!(m_new->m_flags & M_EXT)) { 735 m_freem(m_new); 736 return(ENOBUFS); 737 } 738 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 739 } else { 740 m_new = m; 741 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 742 m_new->m_data = m_new->m_ext.ext_buf; 743 } 744 745 m_adj(m_new, ETHER_ALIGN); 746 747 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 748 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 749 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 750 c->pcn_bufsz |= PCN_RXLEN_MBO; 751 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 752 753 return(0); 754 } 755 756 /* 757 * A frame has been uploaded: pass the resulting mbuf chain up to 758 * the higher level protocols. 759 */ 760 static void 761 pcn_rxeof(struct pcn_softc *sc) 762 { 763 struct mbuf *m; 764 struct ifnet *ifp; 765 struct pcn_rx_desc *cur_rx; 766 int i; 767 768 ifp = &sc->arpcom.ac_if; 769 i = sc->pcn_cdata.pcn_rx_prod; 770 771 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 772 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 773 m = sc->pcn_cdata.pcn_rx_chain[i]; 774 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 775 776 /* 777 * If an error occurs, update stats, clear the 778 * status word and leave the mbuf cluster in place: 779 * it should simply get re-used next time this descriptor 780 * comes up in the ring. 781 */ 782 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 783 ifp->if_ierrors++; 784 pcn_newbuf(sc, i, m); 785 PCN_INC(i, PCN_RX_LIST_CNT); 786 continue; 787 } 788 789 if (pcn_newbuf(sc, i, NULL)) { 790 /* Ran out of mbufs; recycle this one. */ 791 pcn_newbuf(sc, i, m); 792 ifp->if_ierrors++; 793 PCN_INC(i, PCN_RX_LIST_CNT); 794 continue; 795 } 796 797 PCN_INC(i, PCN_RX_LIST_CNT); 798 799 /* No errors; receive the packet. */ 800 ifp->if_ipackets++; 801 m->m_len = m->m_pkthdr.len = 802 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 803 m->m_pkthdr.rcvif = ifp; 804 805 ifp->if_input(ifp, m); 806 } 807 808 sc->pcn_cdata.pcn_rx_prod = i; 809 810 return; 811 } 812 813 /* 814 * A frame was downloaded to the chip. It's safe for us to clean up 815 * the list buffers. 816 */ 817 818 static void 819 pcn_txeof(struct pcn_softc *sc) 820 { 821 struct pcn_tx_desc *cur_tx = NULL; 822 struct ifnet *ifp; 823 u_int32_t idx; 824 825 ifp = &sc->arpcom.ac_if; 826 827 /* 828 * Go through our tx list and free mbufs for those 829 * frames that have been transmitted. 830 */ 831 idx = sc->pcn_cdata.pcn_tx_cons; 832 while (idx != sc->pcn_cdata.pcn_tx_prod) { 833 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 834 835 if (!PCN_OWN_TXDESC(cur_tx)) 836 break; 837 838 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 839 sc->pcn_cdata.pcn_tx_cnt--; 840 PCN_INC(idx, PCN_TX_LIST_CNT); 841 continue; 842 } 843 844 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 845 ifp->if_oerrors++; 846 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 847 ifp->if_collisions++; 848 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 849 ifp->if_collisions++; 850 } 851 852 ifp->if_collisions += 853 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 854 855 ifp->if_opackets++; 856 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 857 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 858 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 859 } 860 861 sc->pcn_cdata.pcn_tx_cnt--; 862 PCN_INC(idx, PCN_TX_LIST_CNT); 863 } 864 865 if (idx != sc->pcn_cdata.pcn_tx_cons) { 866 /* Some buffers have been freed. */ 867 sc->pcn_cdata.pcn_tx_cons = idx; 868 ifp->if_flags &= ~IFF_OACTIVE; 869 } 870 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 871 872 return; 873 } 874 875 static void 876 pcn_tick(void *xsc) 877 { 878 struct pcn_softc *sc = xsc; 879 struct mii_data *mii; 880 struct ifnet *ifp = &sc->arpcom.ac_if; 881 882 lwkt_serialize_enter(ifp->if_serializer); 883 884 mii = device_get_softc(sc->pcn_miibus); 885 mii_tick(mii); 886 887 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 888 sc->pcn_link = 0; 889 890 if (!sc->pcn_link) { 891 mii_pollstat(mii); 892 if (mii->mii_media_status & IFM_ACTIVE && 893 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 894 sc->pcn_link++; 895 if (!ifq_is_empty(&ifp->if_snd)) 896 pcn_start(ifp); 897 } 898 callout_reset(&sc->pcn_stat_timer, hz, pcn_tick, sc); 899 900 lwkt_serialize_exit(ifp->if_serializer); 901 } 902 903 static void 904 pcn_intr(void *arg) 905 { 906 struct pcn_softc *sc; 907 struct ifnet *ifp; 908 u_int32_t status; 909 910 sc = arg; 911 ifp = &sc->arpcom.ac_if; 912 913 /* Supress unwanted interrupts */ 914 if (!(ifp->if_flags & IFF_UP)) { 915 pcn_stop(sc); 916 return; 917 } 918 919 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 920 921 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 922 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 923 924 if (status & PCN_CSR_RINT) 925 pcn_rxeof(sc); 926 927 if (status & PCN_CSR_TINT) 928 pcn_txeof(sc); 929 930 if (status & PCN_CSR_ERR) { 931 pcn_init(sc); 932 break; 933 } 934 } 935 936 if (!ifq_is_empty(&ifp->if_snd)) 937 pcn_start(ifp); 938 939 return; 940 } 941 942 /* 943 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 944 * pointers to the fragment pointers. 945 */ 946 static int 947 pcn_encap(struct pcn_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 948 { 949 struct pcn_tx_desc *f = NULL; 950 struct mbuf *m; 951 int frag, cur, cnt = 0; 952 953 /* 954 * Start packing the mbufs in this chain into 955 * the fragment pointers. Stop when we run out 956 * of fragments or hit the end of the mbuf chain. 957 */ 958 m = m_head; 959 cur = frag = *txidx; 960 961 for (m = m_head; m != NULL; m = m->m_next) { 962 if (m->m_len != 0) { 963 if ((PCN_TX_LIST_CNT - 964 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 965 return(ENOBUFS); 966 f = &sc->pcn_ldata->pcn_tx_list[frag]; 967 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 968 f->pcn_txctl |= PCN_TXCTL_MBO; 969 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 970 if (cnt == 0) 971 f->pcn_txctl |= PCN_TXCTL_STP; 972 else 973 f->pcn_txctl |= PCN_TXCTL_OWN; 974 cur = frag; 975 PCN_INC(frag, PCN_TX_LIST_CNT); 976 cnt++; 977 } 978 } 979 980 if (m != NULL) 981 return(ENOBUFS); 982 983 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 984 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 985 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 986 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 987 sc->pcn_cdata.pcn_tx_cnt += cnt; 988 *txidx = frag; 989 990 return(0); 991 } 992 993 /* 994 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 995 * to the mbuf data regions directly in the transmit lists. We also save a 996 * copy of the pointers since the transmit list fragment pointers are 997 * physical addresses. 998 */ 999 static void 1000 pcn_start(struct ifnet *ifp) 1001 { 1002 struct pcn_softc *sc; 1003 struct mbuf *m_head = NULL; 1004 u_int32_t idx; 1005 int need_trans; 1006 1007 sc = ifp->if_softc; 1008 1009 if (!sc->pcn_link) 1010 return; 1011 1012 idx = sc->pcn_cdata.pcn_tx_prod; 1013 1014 if (ifp->if_flags & IFF_OACTIVE) 1015 return; 1016 1017 need_trans = 0; 1018 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1019 m_head = ifq_poll(&ifp->if_snd); 1020 if (m_head == NULL) 1021 break; 1022 1023 if (pcn_encap(sc, m_head, &idx)) { 1024 ifp->if_flags |= IFF_OACTIVE; 1025 break; 1026 } 1027 ifq_dequeue(&ifp->if_snd, m_head); 1028 need_trans = 1; 1029 1030 BPF_MTAP(ifp, m_head); 1031 } 1032 1033 if (!need_trans) 1034 return; 1035 1036 /* Transmit */ 1037 sc->pcn_cdata.pcn_tx_prod = idx; 1038 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1039 1040 /* 1041 * Set a timeout in case the chip goes out to lunch. 1042 */ 1043 ifp->if_timer = 5; 1044 } 1045 1046 void 1047 pcn_setfilt(struct ifnet *ifp) 1048 { 1049 struct pcn_softc *sc; 1050 1051 sc = ifp->if_softc; 1052 1053 /* If we want promiscuous mode, set the allframes bit. */ 1054 if (ifp->if_flags & IFF_PROMISC) { 1055 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1056 } else { 1057 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1058 } 1059 1060 /* Set the capture broadcast bit to capture broadcast frames. */ 1061 if (ifp->if_flags & IFF_BROADCAST) { 1062 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1063 } else { 1064 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1065 } 1066 1067 return; 1068 } 1069 1070 static void 1071 pcn_init(void *xsc) 1072 { 1073 struct pcn_softc *sc = xsc; 1074 struct ifnet *ifp = &sc->arpcom.ac_if; 1075 struct mii_data *mii = NULL; 1076 1077 /* 1078 * Cancel pending I/O and free all RX/TX buffers. 1079 */ 1080 pcn_stop(sc); 1081 pcn_reset(sc); 1082 1083 mii = device_get_softc(sc->pcn_miibus); 1084 1085 /* Set MAC address */ 1086 pcn_csr_write(sc, PCN_CSR_PAR0, 1087 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1088 pcn_csr_write(sc, PCN_CSR_PAR1, 1089 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1090 pcn_csr_write(sc, PCN_CSR_PAR2, 1091 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1092 1093 /* Init circular RX list. */ 1094 if (pcn_list_rx_init(sc) == ENOBUFS) { 1095 printf("pcn%d: initialization failed: no " 1096 "memory for rx buffers\n", sc->pcn_unit); 1097 pcn_stop(sc); 1098 1099 return; 1100 } 1101 1102 /* Set up RX filter. */ 1103 pcn_setfilt(ifp); 1104 1105 /* 1106 * Init tx descriptors. 1107 */ 1108 pcn_list_tx_init(sc); 1109 1110 /* Set up the mode register. */ 1111 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1112 1113 /* 1114 * Load the multicast filter. 1115 */ 1116 pcn_setmulti(sc); 1117 1118 /* 1119 * Load the addresses of the RX and TX lists. 1120 */ 1121 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1122 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1123 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1124 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1125 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1126 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1127 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1128 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1129 1130 /* Set the RX and TX ring sizes. */ 1131 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1132 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1133 1134 /* We're not using the initialization block. */ 1135 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1136 1137 /* Enable fast suspend mode. */ 1138 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1139 1140 /* 1141 * Enable burst read and write. Also set the no underflow 1142 * bit. This will avoid transmit underruns in certain 1143 * conditions while still providing decent performance. 1144 */ 1145 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1146 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1147 1148 /* Enable graceful recovery from underflow. */ 1149 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1150 1151 /* Enable auto-padding of short TX frames. */ 1152 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1153 1154 /* Disable MII autoneg (we handle this ourselves). */ 1155 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1156 1157 if (sc->pcn_type == Am79C978) 1158 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1159 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1160 1161 /* Enable interrupts and start the controller running. */ 1162 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1163 1164 mii_mediachg(mii); 1165 1166 ifp->if_flags |= IFF_RUNNING; 1167 ifp->if_flags &= ~IFF_OACTIVE; 1168 1169 callout_reset(&sc->pcn_stat_timer, hz, pcn_tick, sc); 1170 } 1171 1172 /* 1173 * Set media options. 1174 */ 1175 static int 1176 pcn_ifmedia_upd(struct ifnet *ifp) 1177 { 1178 struct pcn_softc *sc; 1179 struct mii_data *mii; 1180 1181 sc = ifp->if_softc; 1182 mii = device_get_softc(sc->pcn_miibus); 1183 1184 sc->pcn_link = 0; 1185 if (mii->mii_instance) { 1186 struct mii_softc *miisc; 1187 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1188 miisc = LIST_NEXT(miisc, mii_list)) 1189 mii_phy_reset(miisc); 1190 } 1191 mii_mediachg(mii); 1192 1193 return(0); 1194 } 1195 1196 /* 1197 * Report current media status. 1198 */ 1199 static void 1200 pcn_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1201 { 1202 struct pcn_softc *sc; 1203 struct mii_data *mii; 1204 1205 sc = ifp->if_softc; 1206 1207 mii = device_get_softc(sc->pcn_miibus); 1208 mii_pollstat(mii); 1209 ifmr->ifm_active = mii->mii_media_active; 1210 ifmr->ifm_status = mii->mii_media_status; 1211 1212 return; 1213 } 1214 1215 static int 1216 pcn_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1217 { 1218 struct pcn_softc *sc = ifp->if_softc; 1219 struct ifreq *ifr = (struct ifreq *) data; 1220 struct mii_data *mii = NULL; 1221 int error = 0; 1222 1223 switch(command) { 1224 case SIOCSIFFLAGS: 1225 if (ifp->if_flags & IFF_UP) { 1226 if (ifp->if_flags & IFF_RUNNING && 1227 ifp->if_flags & IFF_PROMISC && 1228 !(sc->pcn_if_flags & IFF_PROMISC)) { 1229 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1230 PCN_EXTCTL1_SPND); 1231 pcn_setfilt(ifp); 1232 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1233 PCN_EXTCTL1_SPND); 1234 pcn_csr_write(sc, PCN_CSR_CSR, 1235 PCN_CSR_INTEN|PCN_CSR_START); 1236 } else if (ifp->if_flags & IFF_RUNNING && 1237 !(ifp->if_flags & IFF_PROMISC) && 1238 sc->pcn_if_flags & IFF_PROMISC) { 1239 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1240 PCN_EXTCTL1_SPND); 1241 pcn_setfilt(ifp); 1242 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1243 PCN_EXTCTL1_SPND); 1244 pcn_csr_write(sc, PCN_CSR_CSR, 1245 PCN_CSR_INTEN|PCN_CSR_START); 1246 } else if (!(ifp->if_flags & IFF_RUNNING)) 1247 pcn_init(sc); 1248 } else { 1249 if (ifp->if_flags & IFF_RUNNING) 1250 pcn_stop(sc); 1251 } 1252 sc->pcn_if_flags = ifp->if_flags; 1253 error = 0; 1254 break; 1255 case SIOCADDMULTI: 1256 case SIOCDELMULTI: 1257 pcn_setmulti(sc); 1258 error = 0; 1259 break; 1260 case SIOCGIFMEDIA: 1261 case SIOCSIFMEDIA: 1262 mii = device_get_softc(sc->pcn_miibus); 1263 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1264 break; 1265 default: 1266 error = ether_ioctl(ifp, command, data); 1267 break; 1268 } 1269 return(error); 1270 } 1271 1272 static void 1273 pcn_watchdog(struct ifnet *ifp) 1274 { 1275 struct pcn_softc *sc; 1276 1277 sc = ifp->if_softc; 1278 1279 ifp->if_oerrors++; 1280 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1281 1282 pcn_stop(sc); 1283 pcn_reset(sc); 1284 pcn_init(sc); 1285 1286 if (!ifq_is_empty(&ifp->if_snd)) 1287 pcn_start(ifp); 1288 1289 return; 1290 } 1291 1292 /* 1293 * Stop the adapter and free any mbufs allocated to the 1294 * RX and TX lists. 1295 */ 1296 static void 1297 pcn_stop(struct pcn_softc *sc) 1298 { 1299 int i; 1300 struct ifnet *ifp; 1301 1302 ifp = &sc->arpcom.ac_if; 1303 ifp->if_timer = 0; 1304 1305 callout_stop(&sc->pcn_stat_timer); 1306 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1307 sc->pcn_link = 0; 1308 1309 /* 1310 * Free data in the RX lists. 1311 */ 1312 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1313 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1314 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1315 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1316 } 1317 } 1318 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1319 sizeof(sc->pcn_ldata->pcn_rx_list)); 1320 1321 /* 1322 * Free the TX list buffers. 1323 */ 1324 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1325 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1326 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1327 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1328 } 1329 } 1330 1331 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1332 sizeof(sc->pcn_ldata->pcn_tx_list)); 1333 1334 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1335 1336 return; 1337 } 1338 1339 /* 1340 * Stop all chip I/O so that the kernel's probe routines don't 1341 * get confused by errant DMAs when rebooting. 1342 */ 1343 static void 1344 pcn_shutdown(device_t dev) 1345 { 1346 struct pcn_softc *sc = device_get_softc(dev); 1347 struct ifnet *ifp = &sc->arpcom.ac_if; 1348 1349 lwkt_serialize_enter(ifp->if_serializer); 1350 pcn_reset(sc); 1351 pcn_stop(sc); 1352 lwkt_serialize_exit(ifp->if_serializer); 1353 } 1354 1355