1 /* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/pci/if_pcn.c,v 1.5.2.10 2003/03/05 18:42:33 njl Exp $ 34 */ 35 36 /* 37 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 38 * from http://www.amd.com. 39 * 40 * Written by Bill Paul <wpaul@osd.bsdi.com> 41 */ 42 43 /* 44 * The AMD PCnet/PCI controllers are more advanced and functional 45 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 46 * backwards compatibility with the LANCE and thus can be made 47 * to work with older LANCE drivers. This is in fact how the 48 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 49 * is that the PCnet/PCI devices offer several performance enhancements 50 * which can't be exploited in LANCE compatibility mode. Chief among 51 * these enhancements is the ability to perform PCI DMA operations 52 * using 32-bit addressing (which eliminates the need for ISA 53 * bounce-buffering), and special receive buffer alignment (which 54 * allows the receive handler to pass packets to the upper protocol 55 * layers without copying on both the x86 and alpha platforms). 56 */ 57 58 #include <sys/param.h> 59 #include <sys/systm.h> 60 #include <sys/sockio.h> 61 #include <sys/mbuf.h> 62 #include <sys/malloc.h> 63 #include <sys/kernel.h> 64 #include <sys/interrupt.h> 65 #include <sys/socket.h> 66 #include <sys/serialize.h> 67 #include <sys/bus.h> 68 #include <sys/rman.h> 69 70 #include <net/if.h> 71 #include <net/ifq_var.h> 72 #include <net/if_arp.h> 73 #include <net/ethernet.h> 74 #include <net/if_dl.h> 75 #include <net/if_media.h> 76 77 #include <net/bpf.h> 78 79 #include <vm/vm.h> /* for vtophys */ 80 #include <vm/pmap.h> /* for vtophys */ 81 82 #include <machine/clock.h> /* for DELAY */ 83 84 #include "../mii_layer/mii.h" 85 #include "../mii_layer/miivar.h" 86 87 #include "pcidevs.h" 88 #include <bus/pci/pcireg.h> 89 #include <bus/pci/pcivar.h> 90 91 #define PCN_USEIOSPACE 92 93 #include "if_pcnreg.h" 94 95 /* "controller miibus0" required. See GENERIC if you get errors here. */ 96 #include "miibus_if.h" 97 98 /* 99 * Various supported device vendors/types and their names. 100 */ 101 static struct pcn_type pcn_devs[] = { 102 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PCNET_PCI, 103 "AMD PCnet/PCI 10/100BaseTX" }, 104 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PCNET_HOME, 105 "AMD PCnet/Home HomePNA" }, 106 { 0, 0, NULL } 107 }; 108 109 static u_int32_t pcn_csr_read (struct pcn_softc *, int); 110 static u_int16_t pcn_csr_read16 (struct pcn_softc *, int); 111 static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int); 112 static void pcn_csr_write (struct pcn_softc *, int, int); 113 static u_int32_t pcn_bcr_read (struct pcn_softc *, int); 114 static void pcn_bcr_write (struct pcn_softc *, int, int); 115 116 static int pcn_probe (device_t); 117 static int pcn_attach (device_t); 118 static int pcn_detach (device_t); 119 120 static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *); 121 static int pcn_encap (struct pcn_softc *, 122 struct mbuf *, u_int32_t *); 123 static void pcn_rxeof (struct pcn_softc *); 124 static void pcn_txeof (struct pcn_softc *); 125 static void pcn_intr (void *); 126 static void pcn_tick (void *); 127 static void pcn_start (struct ifnet *, struct ifaltq_subque *); 128 static int pcn_ioctl (struct ifnet *, u_long, caddr_t, 129 struct ucred *); 130 static void pcn_init (void *); 131 static void pcn_stop (struct pcn_softc *); 132 static void pcn_watchdog (struct ifnet *); 133 static void pcn_shutdown (device_t); 134 static int pcn_ifmedia_upd (struct ifnet *); 135 static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *); 136 137 static int pcn_miibus_readreg (device_t, int, int); 138 static int pcn_miibus_writereg (device_t, int, int, int); 139 static void pcn_miibus_statchg (device_t); 140 141 static void pcn_setfilt (struct ifnet *); 142 static void pcn_setmulti (struct pcn_softc *); 143 static u_int32_t pcn_crc (caddr_t); 144 static void pcn_reset (struct pcn_softc *); 145 static int pcn_list_rx_init (struct pcn_softc *); 146 static int pcn_list_tx_init (struct pcn_softc *); 147 148 #ifdef PCN_USEIOSPACE 149 #define PCN_RES SYS_RES_IOPORT 150 #define PCN_RID PCN_PCI_LOIO 151 #else 152 #define PCN_RES SYS_RES_MEMORY 153 #define PCN_RID PCN_PCI_LOMEM 154 #endif 155 156 static device_method_t pcn_methods[] = { 157 /* Device interface */ 158 DEVMETHOD(device_probe, pcn_probe), 159 DEVMETHOD(device_attach, pcn_attach), 160 DEVMETHOD(device_detach, pcn_detach), 161 DEVMETHOD(device_shutdown, pcn_shutdown), 162 163 /* bus interface */ 164 DEVMETHOD(bus_print_child, bus_generic_print_child), 165 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 166 167 /* MII interface */ 168 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 169 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 170 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 171 172 DEVMETHOD_END 173 }; 174 175 static driver_t pcn_driver = { 176 "pcn", 177 pcn_methods, 178 sizeof(struct pcn_softc) 179 }; 180 181 static devclass_t pcn_devclass; 182 183 DECLARE_DUMMY_MODULE(if_pcn); 184 DRIVER_MODULE(if_pcn, pci, pcn_driver, pcn_devclass, NULL, NULL); 185 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, NULL, NULL); 186 187 #define PCN_CSR_SETBIT(sc, reg, x) \ 188 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 189 190 #define PCN_CSR_CLRBIT(sc, reg, x) \ 191 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 192 193 #define PCN_BCR_SETBIT(sc, reg, x) \ 194 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 195 196 #define PCN_BCR_CLRBIT(sc, reg, x) \ 197 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 198 199 static u_int32_t 200 pcn_csr_read(struct pcn_softc *sc, int reg) 201 { 202 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 203 return(CSR_READ_4(sc, PCN_IO32_RDP)); 204 } 205 206 static u_int16_t 207 pcn_csr_read16(struct pcn_softc *sc, int reg) 208 { 209 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 210 return(CSR_READ_2(sc, PCN_IO16_RDP)); 211 } 212 213 static void 214 pcn_csr_write(struct pcn_softc *sc, int reg, int val) 215 { 216 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 217 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 218 return; 219 } 220 221 static u_int32_t 222 pcn_bcr_read(struct pcn_softc *sc, int reg) 223 { 224 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 225 return(CSR_READ_4(sc, PCN_IO32_BDP)); 226 } 227 228 static u_int16_t 229 pcn_bcr_read16(struct pcn_softc *sc, int reg) 230 { 231 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 232 return(CSR_READ_2(sc, PCN_IO16_BDP)); 233 } 234 235 static void 236 pcn_bcr_write(struct pcn_softc *sc, int reg, int val) 237 { 238 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 239 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 240 return; 241 } 242 243 static int 244 pcn_miibus_readreg(device_t dev, int phy, int reg) 245 { 246 struct pcn_softc *sc; 247 int val; 248 249 sc = device_get_softc(dev); 250 251 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 252 return(0); 253 254 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 255 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 256 if (val == 0xFFFF) 257 return(0); 258 259 sc->pcn_phyaddr = phy; 260 261 return(val); 262 } 263 264 static int 265 pcn_miibus_writereg(device_t dev, int phy, int reg, int data) 266 { 267 struct pcn_softc *sc; 268 269 sc = device_get_softc(dev); 270 271 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 272 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 273 274 return(0); 275 } 276 277 static void 278 pcn_miibus_statchg(device_t dev) 279 { 280 struct pcn_softc *sc; 281 struct mii_data *mii; 282 283 sc = device_get_softc(dev); 284 mii = device_get_softc(sc->pcn_miibus); 285 286 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 287 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 288 } else { 289 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 290 } 291 292 return; 293 } 294 295 #define DC_POLY 0xEDB88320 296 297 static u_int32_t 298 pcn_crc(caddr_t addr) 299 { 300 u_int32_t idx, bit, data, crc; 301 302 /* Compute CRC for the address value. */ 303 crc = 0xFFFFFFFF; /* initial value */ 304 305 for (idx = 0; idx < 6; idx++) { 306 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 307 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 308 } 309 310 return ((crc >> 26) & 0x3F); 311 } 312 313 static void 314 pcn_setmulti(struct pcn_softc *sc) 315 { 316 struct ifnet *ifp; 317 struct ifmultiaddr *ifma; 318 u_int32_t h, i; 319 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 320 321 ifp = &sc->arpcom.ac_if; 322 323 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 324 325 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 326 for (i = 0; i < 4; i++) 327 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 328 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 329 return; 330 } 331 332 /* first, zot all the existing hash bits */ 333 for (i = 0; i < 4; i++) 334 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 335 336 /* now program new ones */ 337 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 338 if (ifma->ifma_addr->sa_family != AF_LINK) 339 continue; 340 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 341 hashes[h >> 4] |= 1 << (h & 0xF); 342 } 343 344 for (i = 0; i < 4; i++) 345 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 346 347 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 348 349 return; 350 } 351 352 static void 353 pcn_reset(struct pcn_softc *sc) 354 { 355 /* 356 * Issue a reset by reading from the RESET register. 357 * Note that we don't know if the chip is operating in 358 * 16-bit or 32-bit mode at this point, so we attempt 359 * to reset the chip both ways. If one fails, the other 360 * will succeed. 361 */ 362 CSR_READ_2(sc, PCN_IO16_RESET); 363 CSR_READ_4(sc, PCN_IO32_RESET); 364 365 /* Wait a little while for the chip to get its brains in order. */ 366 DELAY(1000); 367 368 /* Select 32-bit (DWIO) mode */ 369 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 370 371 /* Select software style 3. */ 372 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 373 374 return; 375 } 376 377 /* 378 * Probe for an AMD chip. Check the PCI vendor and device 379 * IDs against our list and return a device name if we find a match. 380 */ 381 static int 382 pcn_probe(device_t dev) 383 { 384 struct pcn_type *t; 385 struct pcn_softc *sc; 386 int rid; 387 u_int32_t chip_id; 388 389 t = pcn_devs; 390 sc = device_get_softc(dev); 391 392 while(t->pcn_name != NULL) { 393 if ((pci_get_vendor(dev) == t->pcn_vid) && 394 (pci_get_device(dev) == t->pcn_did)) { 395 /* 396 * Temporarily map the I/O space 397 * so we can read the chip ID register. 398 */ 399 rid = PCN_RID; 400 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, 401 &rid, RF_ACTIVE); 402 if (sc->pcn_res == NULL) { 403 device_printf(dev, 404 "couldn't map ports/memory\n"); 405 return(ENXIO); 406 } 407 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 408 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 409 /* 410 * Note: we can *NOT* put the chip into 411 * 32-bit mode yet. The lnc driver will only 412 * work in 16-bit mode, and once the chip 413 * goes into 32-bit mode, the only way to 414 * get it out again is with a hardware reset. 415 * So if pcn_probe() is called before the 416 * lnc driver's probe routine, the chip will 417 * be locked into 32-bit operation and the lnc 418 * driver will be unable to attach to it. 419 * Note II: if the chip happens to already 420 * be in 32-bit mode, we still need to check 421 * the chip ID, but first we have to detect 422 * 32-bit mode using only 16-bit operations. 423 * The safest way to do this is to read the 424 * PCI subsystem ID from BCR23/24 and compare 425 * that with the value read from PCI config 426 * space. 427 */ 428 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 429 chip_id <<= 16; 430 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 431 /* 432 * Note III: the test for 0x10001000 is a hack to 433 * pacify VMware, who's pseudo-PCnet interface is 434 * broken. Reading the subsystem register from PCI 435 * config space yeilds 0x00000000 while reading the 436 * same value from I/O space yeilds 0x10001000. It's 437 * not supposed to be that way. 438 */ 439 if (chip_id == pci_read_config(dev, 440 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 441 /* We're in 16-bit mode. */ 442 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 443 chip_id <<= 16; 444 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 445 } else { 446 /* We're in 32-bit mode. */ 447 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 448 chip_id <<= 16; 449 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 450 } 451 bus_release_resource(dev, PCN_RES, 452 PCN_RID, sc->pcn_res); 453 chip_id >>= 12; 454 sc->pcn_type = chip_id & PART_MASK; 455 switch(sc->pcn_type) { 456 case Am79C971: 457 case Am79C972: 458 case Am79C973: 459 case Am79C975: 460 case Am79C976: 461 case Am79C978: 462 break; 463 default: 464 return(ENXIO); 465 break; 466 } 467 device_set_desc(dev, t->pcn_name); 468 return(0); 469 } 470 t++; 471 } 472 473 return(ENXIO); 474 } 475 476 /* 477 * Attach the interface. Allocate softc structures, do ifmedia 478 * setup and ethernet/BPF attach. 479 */ 480 static int 481 pcn_attach(device_t dev) 482 { 483 uint8_t eaddr[ETHER_ADDR_LEN]; 484 u_int32_t command; 485 struct pcn_softc *sc; 486 struct ifnet *ifp; 487 int unit, error = 0, rid; 488 489 sc = device_get_softc(dev); 490 unit = device_get_unit(dev); 491 492 /* 493 * Handle power management nonsense. 494 */ 495 496 command = pci_read_config(dev, PCN_PCI_CAPID, 4) & 0x000000FF; 497 if (command == 0x01) { 498 499 command = pci_read_config(dev, PCN_PCI_PWRMGMTCTRL, 4); 500 if (command & PCN_PSTATE_MASK) { 501 u_int32_t iobase, membase, irq; 502 503 /* Save important PCI config data. */ 504 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 505 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 506 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 507 508 /* Reset the power state. */ 509 kprintf("pcn%d: chip is in D%d power mode " 510 "-- setting to D0\n", unit, command & PCN_PSTATE_MASK); 511 command &= 0xFFFFFFFC; 512 pci_write_config(dev, PCN_PCI_PWRMGMTCTRL, command, 4); 513 514 /* Restore PCI config data. */ 515 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 516 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 517 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 518 } 519 } 520 521 /* 522 * Map control/status registers. 523 */ 524 command = pci_read_config(dev, PCIR_COMMAND, 4); 525 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 526 pci_write_config(dev, PCIR_COMMAND, command, 4); 527 command = pci_read_config(dev, PCIR_COMMAND, 4); 528 529 #ifdef PCN_USEIOSPACE 530 if (!(command & PCIM_CMD_PORTEN)) { 531 kprintf("pcn%d: failed to enable I/O ports!\n", unit); 532 error = ENXIO; 533 return(error); 534 } 535 #else 536 if (!(command & PCIM_CMD_MEMEN)) { 537 kprintf("pcn%d: failed to enable memory mapping!\n", unit); 538 error = ENXIO; 539 return(error); 540 } 541 #endif 542 543 rid = PCN_RID; 544 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE); 545 546 if (sc->pcn_res == NULL) { 547 kprintf("pcn%d: couldn't map ports/memory\n", unit); 548 error = ENXIO; 549 return(error); 550 } 551 552 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 553 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 554 555 /* Allocate interrupt */ 556 rid = 0; 557 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 558 RF_SHAREABLE | RF_ACTIVE); 559 560 if (sc->pcn_irq == NULL) { 561 kprintf("pcn%d: couldn't map interrupt\n", unit); 562 error = ENXIO; 563 goto fail; 564 } 565 566 /* Reset the adapter. */ 567 pcn_reset(sc); 568 569 /* 570 * Get station address from the EEPROM. 571 */ 572 *(uint32_t *)eaddr = CSR_READ_4(sc, PCN_IO32_APROM00); 573 *(uint16_t *)(eaddr + 4) = CSR_READ_2(sc, PCN_IO32_APROM01); 574 575 sc->pcn_unit = unit; 576 callout_init(&sc->pcn_stat_timer); 577 578 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 579 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 580 581 if (sc->pcn_ldata == NULL) { 582 kprintf("pcn%d: no memory for list buffers!\n", unit); 583 error = ENXIO; 584 goto fail; 585 } 586 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 587 588 ifp = &sc->arpcom.ac_if; 589 ifp->if_softc = sc; 590 if_initname(ifp, "pcn", unit); 591 ifp->if_mtu = ETHERMTU; 592 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 593 ifp->if_ioctl = pcn_ioctl; 594 ifp->if_start = pcn_start; 595 ifp->if_watchdog = pcn_watchdog; 596 ifp->if_init = pcn_init; 597 ifp->if_baudrate = 10000000; 598 ifq_set_maxlen(&ifp->if_snd, PCN_TX_LIST_CNT - 1); 599 ifq_set_ready(&ifp->if_snd); 600 601 /* 602 * Do MII setup. 603 */ 604 if (mii_phy_probe(dev, &sc->pcn_miibus, 605 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 606 kprintf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 607 error = ENXIO; 608 goto fail; 609 } 610 611 /* 612 * Call MI attach routine. 613 */ 614 ether_ifattach(ifp, eaddr, NULL); 615 616 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->pcn_irq)); 617 618 error = bus_setup_intr(dev, sc->pcn_irq, INTR_MPSAFE, 619 pcn_intr, sc, &sc->pcn_intrhand, 620 ifp->if_serializer); 621 if (error) { 622 ether_ifdetach(ifp); 623 device_printf(dev, "couldn't set up irq\n"); 624 goto fail; 625 } 626 627 return (0); 628 fail: 629 pcn_detach(dev); 630 return(error); 631 } 632 633 static int 634 pcn_detach(device_t dev) 635 { 636 struct pcn_softc *sc = device_get_softc(dev); 637 struct ifnet *ifp = &sc->arpcom.ac_if; 638 639 if (device_is_attached(dev)) { 640 lwkt_serialize_enter(ifp->if_serializer); 641 pcn_reset(sc); 642 pcn_stop(sc); 643 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 644 lwkt_serialize_exit(ifp->if_serializer); 645 646 ether_ifdetach(ifp); 647 } 648 649 if (sc->pcn_miibus != NULL) 650 device_delete_child(dev, sc->pcn_miibus); 651 bus_generic_detach(dev); 652 653 if (sc->pcn_irq) 654 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 655 if (sc->pcn_res) 656 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 657 658 if (sc->pcn_ldata) { 659 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 660 M_DEVBUF); 661 } 662 663 return(0); 664 } 665 666 /* 667 * Initialize the transmit descriptors. 668 */ 669 static int 670 pcn_list_tx_init(struct pcn_softc *sc) 671 { 672 struct pcn_list_data *ld; 673 struct pcn_ring_data *cd; 674 int i; 675 676 cd = &sc->pcn_cdata; 677 ld = sc->pcn_ldata; 678 679 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 680 cd->pcn_tx_chain[i] = NULL; 681 ld->pcn_tx_list[i].pcn_tbaddr = 0; 682 ld->pcn_tx_list[i].pcn_txctl = 0; 683 ld->pcn_tx_list[i].pcn_txstat = 0; 684 } 685 686 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 687 688 return(0); 689 } 690 691 692 /* 693 * Initialize the RX descriptors and allocate mbufs for them. 694 */ 695 static int 696 pcn_list_rx_init(struct pcn_softc *sc) 697 { 698 struct pcn_ring_data *cd; 699 int i; 700 701 cd = &sc->pcn_cdata; 702 703 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 704 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 705 return(ENOBUFS); 706 } 707 708 cd->pcn_rx_prod = 0; 709 710 return(0); 711 } 712 713 /* 714 * Initialize an RX descriptor and attach an MBUF cluster. 715 */ 716 static int 717 pcn_newbuf(struct pcn_softc *sc, int idx, struct mbuf *m) 718 { 719 struct mbuf *m_new = NULL; 720 struct pcn_rx_desc *c; 721 722 c = &sc->pcn_ldata->pcn_rx_list[idx]; 723 724 if (m == NULL) { 725 MGETHDR(m_new, M_NOWAIT, MT_DATA); 726 if (m_new == NULL) 727 return(ENOBUFS); 728 729 MCLGET(m_new, M_NOWAIT); 730 if (!(m_new->m_flags & M_EXT)) { 731 m_freem(m_new); 732 return(ENOBUFS); 733 } 734 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 735 } else { 736 m_new = m; 737 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 738 m_new->m_data = m_new->m_ext.ext_buf; 739 } 740 741 m_adj(m_new, ETHER_ALIGN); 742 743 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 744 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 745 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 746 c->pcn_bufsz |= PCN_RXLEN_MBO; 747 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 748 749 return(0); 750 } 751 752 /* 753 * A frame has been uploaded: pass the resulting mbuf chain up to 754 * the higher level protocols. 755 */ 756 static void 757 pcn_rxeof(struct pcn_softc *sc) 758 { 759 struct mbuf *m; 760 struct ifnet *ifp; 761 struct pcn_rx_desc *cur_rx; 762 int i; 763 764 ifp = &sc->arpcom.ac_if; 765 i = sc->pcn_cdata.pcn_rx_prod; 766 767 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 768 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 769 m = sc->pcn_cdata.pcn_rx_chain[i]; 770 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 771 772 /* 773 * If an error occurs, update stats, clear the 774 * status word and leave the mbuf cluster in place: 775 * it should simply get re-used next time this descriptor 776 * comes up in the ring. 777 */ 778 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 779 IFNET_STAT_INC(ifp, ierrors, 1); 780 pcn_newbuf(sc, i, m); 781 PCN_INC(i, PCN_RX_LIST_CNT); 782 continue; 783 } 784 785 if (pcn_newbuf(sc, i, NULL)) { 786 /* Ran out of mbufs; recycle this one. */ 787 pcn_newbuf(sc, i, m); 788 IFNET_STAT_INC(ifp, ierrors, 1); 789 PCN_INC(i, PCN_RX_LIST_CNT); 790 continue; 791 } 792 793 PCN_INC(i, PCN_RX_LIST_CNT); 794 795 /* No errors; receive the packet. */ 796 IFNET_STAT_INC(ifp, ipackets, 1); 797 m->m_len = m->m_pkthdr.len = 798 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 799 m->m_pkthdr.rcvif = ifp; 800 801 ifp->if_input(ifp, m, NULL, -1); 802 } 803 804 sc->pcn_cdata.pcn_rx_prod = i; 805 806 return; 807 } 808 809 /* 810 * A frame was downloaded to the chip. It's safe for us to clean up 811 * the list buffers. 812 */ 813 814 static void 815 pcn_txeof(struct pcn_softc *sc) 816 { 817 struct pcn_tx_desc *cur_tx = NULL; 818 struct ifnet *ifp; 819 u_int32_t idx; 820 821 ifp = &sc->arpcom.ac_if; 822 823 /* 824 * Go through our tx list and free mbufs for those 825 * frames that have been transmitted. 826 */ 827 idx = sc->pcn_cdata.pcn_tx_cons; 828 while (idx != sc->pcn_cdata.pcn_tx_prod) { 829 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 830 831 if (!PCN_OWN_TXDESC(cur_tx)) 832 break; 833 834 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 835 sc->pcn_cdata.pcn_tx_cnt--; 836 PCN_INC(idx, PCN_TX_LIST_CNT); 837 continue; 838 } 839 840 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 841 IFNET_STAT_INC(ifp, oerrors, 1); 842 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 843 IFNET_STAT_INC(ifp, collisions, 1); 844 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 845 IFNET_STAT_INC(ifp, collisions, 1); 846 } 847 848 IFNET_STAT_INC(ifp, collisions, 849 cur_tx->pcn_txstat & PCN_TXSTAT_TRC); 850 851 IFNET_STAT_INC(ifp, opackets, 1); 852 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 853 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 854 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 855 } 856 857 sc->pcn_cdata.pcn_tx_cnt--; 858 PCN_INC(idx, PCN_TX_LIST_CNT); 859 } 860 861 if (idx != sc->pcn_cdata.pcn_tx_cons) { 862 /* Some buffers have been freed. */ 863 sc->pcn_cdata.pcn_tx_cons = idx; 864 ifq_clr_oactive(&ifp->if_snd); 865 } 866 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 867 868 return; 869 } 870 871 static void 872 pcn_tick(void *xsc) 873 { 874 struct pcn_softc *sc = xsc; 875 struct mii_data *mii; 876 struct ifnet *ifp = &sc->arpcom.ac_if; 877 878 lwkt_serialize_enter(ifp->if_serializer); 879 880 mii = device_get_softc(sc->pcn_miibus); 881 mii_tick(mii); 882 883 if (sc->pcn_link && !(mii->mii_media_status & IFM_ACTIVE)) 884 sc->pcn_link = 0; 885 886 if (!sc->pcn_link) { 887 mii_pollstat(mii); 888 if (mii->mii_media_status & IFM_ACTIVE && 889 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 890 sc->pcn_link++; 891 if (!ifq_is_empty(&ifp->if_snd)) 892 if_devstart(ifp); 893 } 894 } 895 callout_reset(&sc->pcn_stat_timer, hz, pcn_tick, sc); 896 897 lwkt_serialize_exit(ifp->if_serializer); 898 } 899 900 static void 901 pcn_intr(void *arg) 902 { 903 struct pcn_softc *sc; 904 struct ifnet *ifp; 905 u_int32_t status; 906 907 sc = arg; 908 ifp = &sc->arpcom.ac_if; 909 910 /* Supress unwanted interrupts */ 911 if (!(ifp->if_flags & IFF_UP)) { 912 pcn_stop(sc); 913 return; 914 } 915 916 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 917 918 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 919 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 920 921 if (status & PCN_CSR_RINT) 922 pcn_rxeof(sc); 923 924 if (status & PCN_CSR_TINT) 925 pcn_txeof(sc); 926 927 if (status & PCN_CSR_ERR) { 928 pcn_init(sc); 929 break; 930 } 931 } 932 933 if (!ifq_is_empty(&ifp->if_snd)) 934 if_devstart(ifp); 935 } 936 937 /* 938 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 939 * pointers to the fragment pointers. 940 */ 941 static int 942 pcn_encap(struct pcn_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 943 { 944 struct pcn_tx_desc *f = NULL; 945 struct mbuf *m; 946 int frag, cur, cnt = 0; 947 948 /* 949 * Start packing the mbufs in this chain into 950 * the fragment pointers. Stop when we run out 951 * of fragments or hit the end of the mbuf chain. 952 */ 953 cur = frag = *txidx; 954 955 for (m = m_head; m != NULL; m = m->m_next) { 956 if (m->m_len != 0) { 957 if ((PCN_TX_LIST_CNT - 958 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 959 break; 960 f = &sc->pcn_ldata->pcn_tx_list[frag]; 961 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 962 f->pcn_txctl |= PCN_TXCTL_MBO; 963 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 964 if (cnt == 0) 965 f->pcn_txctl |= PCN_TXCTL_STP; 966 else 967 f->pcn_txctl |= PCN_TXCTL_OWN; 968 cur = frag; 969 PCN_INC(frag, PCN_TX_LIST_CNT); 970 cnt++; 971 } 972 } 973 /* Caller should make sure that 'm_head' is not excessive fragmented */ 974 KASSERT(m == NULL, ("too many fragments")); 975 976 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 977 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 978 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 979 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 980 sc->pcn_cdata.pcn_tx_cnt += cnt; 981 *txidx = frag; 982 983 return(0); 984 } 985 986 /* 987 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 988 * to the mbuf data regions directly in the transmit lists. We also save a 989 * copy of the pointers since the transmit list fragment pointers are 990 * physical addresses. 991 */ 992 static void 993 pcn_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 994 { 995 struct pcn_softc *sc; 996 struct mbuf *m_head = NULL, *m_defragged; 997 u_int32_t idx; 998 int need_trans; 999 1000 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1001 1002 sc = ifp->if_softc; 1003 1004 if (!sc->pcn_link) { 1005 ifq_purge(&ifp->if_snd); 1006 return; 1007 } 1008 1009 idx = sc->pcn_cdata.pcn_tx_prod; 1010 1011 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 1012 return; 1013 1014 need_trans = 0; 1015 while (sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1016 struct mbuf *m; 1017 int cnt; 1018 1019 m_defragged = NULL; 1020 m_head = ifq_dequeue(&ifp->if_snd); 1021 if (m_head == NULL) 1022 break; 1023 1024 again: 1025 cnt = 0; 1026 for (m = m_head; m != NULL; m = m->m_next) 1027 ++cnt; 1028 if ((PCN_TX_LIST_CNT - 1029 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) { 1030 if (m_defragged != NULL) { 1031 /* 1032 * Even after defragmentation, there 1033 * are still too many fragments, so 1034 * drop this packet. 1035 */ 1036 m_freem(m_head); 1037 ifq_set_oactive(&ifp->if_snd); 1038 break; 1039 } 1040 1041 m_defragged = m_defrag(m_head, M_NOWAIT); 1042 if (m_defragged == NULL) { 1043 m_freem(m_head); 1044 continue; 1045 } 1046 m_head = m_defragged; 1047 1048 /* Recount # of fragments */ 1049 goto again; 1050 } 1051 1052 pcn_encap(sc, m_head, &idx); 1053 need_trans = 1; 1054 1055 BPF_MTAP(ifp, m_head); 1056 } 1057 1058 if (!need_trans) 1059 return; 1060 1061 /* Transmit */ 1062 sc->pcn_cdata.pcn_tx_prod = idx; 1063 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1064 1065 /* 1066 * Set a timeout in case the chip goes out to lunch. 1067 */ 1068 ifp->if_timer = 5; 1069 } 1070 1071 static void 1072 pcn_setfilt(struct ifnet *ifp) 1073 { 1074 struct pcn_softc *sc; 1075 1076 sc = ifp->if_softc; 1077 1078 /* If we want promiscuous mode, set the allframes bit. */ 1079 if (ifp->if_flags & IFF_PROMISC) { 1080 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1081 } else { 1082 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1083 } 1084 1085 /* Set the capture broadcast bit to capture broadcast frames. */ 1086 if (ifp->if_flags & IFF_BROADCAST) { 1087 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1088 } else { 1089 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1090 } 1091 1092 return; 1093 } 1094 1095 static void 1096 pcn_init(void *xsc) 1097 { 1098 struct pcn_softc *sc = xsc; 1099 struct ifnet *ifp = &sc->arpcom.ac_if; 1100 struct mii_data *mii = NULL; 1101 1102 /* 1103 * Cancel pending I/O and free all RX/TX buffers. 1104 */ 1105 pcn_stop(sc); 1106 pcn_reset(sc); 1107 1108 mii = device_get_softc(sc->pcn_miibus); 1109 1110 /* Set MAC address */ 1111 pcn_csr_write(sc, PCN_CSR_PAR0, 1112 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1113 pcn_csr_write(sc, PCN_CSR_PAR1, 1114 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1115 pcn_csr_write(sc, PCN_CSR_PAR2, 1116 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1117 1118 /* Init circular RX list. */ 1119 if (pcn_list_rx_init(sc) == ENOBUFS) { 1120 kprintf("pcn%d: initialization failed: no " 1121 "memory for rx buffers\n", sc->pcn_unit); 1122 pcn_stop(sc); 1123 1124 return; 1125 } 1126 1127 /* Set up RX filter. */ 1128 pcn_setfilt(ifp); 1129 1130 /* 1131 * Init tx descriptors. 1132 */ 1133 pcn_list_tx_init(sc); 1134 1135 /* Set up the mode register. */ 1136 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1137 1138 /* 1139 * Load the multicast filter. 1140 */ 1141 pcn_setmulti(sc); 1142 1143 /* 1144 * Load the addresses of the RX and TX lists. 1145 */ 1146 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1147 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1148 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1149 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1150 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1151 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1152 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1153 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1154 1155 /* Set the RX and TX ring sizes. */ 1156 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1157 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1158 1159 /* We're not using the initialization block. */ 1160 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1161 1162 /* Enable fast suspend mode. */ 1163 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1164 1165 /* 1166 * Enable burst read and write. Also set the no underflow 1167 * bit. This will avoid transmit underruns in certain 1168 * conditions while still providing decent performance. 1169 */ 1170 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1171 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1172 1173 /* Enable graceful recovery from underflow. */ 1174 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1175 1176 /* Enable auto-padding of short TX frames. */ 1177 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1178 1179 /* Disable MII autoneg (we handle this ourselves). */ 1180 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1181 1182 if (sc->pcn_type == Am79C978) 1183 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1184 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1185 1186 /* Enable interrupts and start the controller running. */ 1187 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1188 1189 mii_mediachg(mii); 1190 1191 ifp->if_flags |= IFF_RUNNING; 1192 ifq_clr_oactive(&ifp->if_snd); 1193 1194 callout_reset(&sc->pcn_stat_timer, hz, pcn_tick, sc); 1195 } 1196 1197 /* 1198 * Set media options. 1199 */ 1200 static int 1201 pcn_ifmedia_upd(struct ifnet *ifp) 1202 { 1203 struct pcn_softc *sc; 1204 struct mii_data *mii; 1205 1206 sc = ifp->if_softc; 1207 mii = device_get_softc(sc->pcn_miibus); 1208 1209 sc->pcn_link = 0; 1210 if (mii->mii_instance) { 1211 struct mii_softc *miisc; 1212 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1213 miisc = LIST_NEXT(miisc, mii_list)) 1214 mii_phy_reset(miisc); 1215 } 1216 mii_mediachg(mii); 1217 1218 return(0); 1219 } 1220 1221 /* 1222 * Report current media status. 1223 */ 1224 static void 1225 pcn_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1226 { 1227 struct pcn_softc *sc; 1228 struct mii_data *mii; 1229 1230 sc = ifp->if_softc; 1231 1232 mii = device_get_softc(sc->pcn_miibus); 1233 mii_pollstat(mii); 1234 ifmr->ifm_active = mii->mii_media_active; 1235 ifmr->ifm_status = mii->mii_media_status; 1236 1237 return; 1238 } 1239 1240 static int 1241 pcn_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1242 { 1243 struct pcn_softc *sc = ifp->if_softc; 1244 struct ifreq *ifr = (struct ifreq *) data; 1245 struct mii_data *mii = NULL; 1246 int error = 0; 1247 1248 switch(command) { 1249 case SIOCSIFFLAGS: 1250 if (ifp->if_flags & IFF_UP) { 1251 if (ifp->if_flags & IFF_RUNNING && 1252 ifp->if_flags & IFF_PROMISC && 1253 !(sc->pcn_if_flags & IFF_PROMISC)) { 1254 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1255 PCN_EXTCTL1_SPND); 1256 pcn_setfilt(ifp); 1257 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1258 PCN_EXTCTL1_SPND); 1259 pcn_csr_write(sc, PCN_CSR_CSR, 1260 PCN_CSR_INTEN|PCN_CSR_START); 1261 } else if (ifp->if_flags & IFF_RUNNING && 1262 !(ifp->if_flags & IFF_PROMISC) && 1263 sc->pcn_if_flags & IFF_PROMISC) { 1264 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1265 PCN_EXTCTL1_SPND); 1266 pcn_setfilt(ifp); 1267 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1268 PCN_EXTCTL1_SPND); 1269 pcn_csr_write(sc, PCN_CSR_CSR, 1270 PCN_CSR_INTEN|PCN_CSR_START); 1271 } else if (!(ifp->if_flags & IFF_RUNNING)) 1272 pcn_init(sc); 1273 } else { 1274 if (ifp->if_flags & IFF_RUNNING) 1275 pcn_stop(sc); 1276 } 1277 sc->pcn_if_flags = ifp->if_flags; 1278 error = 0; 1279 break; 1280 case SIOCADDMULTI: 1281 case SIOCDELMULTI: 1282 pcn_setmulti(sc); 1283 error = 0; 1284 break; 1285 case SIOCGIFMEDIA: 1286 case SIOCSIFMEDIA: 1287 mii = device_get_softc(sc->pcn_miibus); 1288 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1289 break; 1290 default: 1291 error = ether_ioctl(ifp, command, data); 1292 break; 1293 } 1294 return(error); 1295 } 1296 1297 static void 1298 pcn_watchdog(struct ifnet *ifp) 1299 { 1300 struct pcn_softc *sc; 1301 1302 sc = ifp->if_softc; 1303 1304 IFNET_STAT_INC(ifp, oerrors, 1); 1305 kprintf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1306 1307 pcn_stop(sc); 1308 pcn_reset(sc); 1309 pcn_init(sc); 1310 1311 if (!ifq_is_empty(&ifp->if_snd)) 1312 if_devstart(ifp); 1313 } 1314 1315 /* 1316 * Stop the adapter and free any mbufs allocated to the 1317 * RX and TX lists. 1318 */ 1319 static void 1320 pcn_stop(struct pcn_softc *sc) 1321 { 1322 int i; 1323 struct ifnet *ifp; 1324 1325 ifp = &sc->arpcom.ac_if; 1326 ifp->if_timer = 0; 1327 1328 callout_stop(&sc->pcn_stat_timer); 1329 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1330 sc->pcn_link = 0; 1331 1332 /* 1333 * Free data in the RX lists. 1334 */ 1335 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1336 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1337 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1338 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1339 } 1340 } 1341 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1342 sizeof(sc->pcn_ldata->pcn_rx_list)); 1343 1344 /* 1345 * Free the TX list buffers. 1346 */ 1347 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1348 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1349 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1350 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1351 } 1352 } 1353 1354 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1355 sizeof(sc->pcn_ldata->pcn_tx_list)); 1356 1357 ifp->if_flags &= ~IFF_RUNNING; 1358 ifq_clr_oactive(&ifp->if_snd); 1359 1360 return; 1361 } 1362 1363 /* 1364 * Stop all chip I/O so that the kernel's probe routines don't 1365 * get confused by errant DMAs when rebooting. 1366 */ 1367 static void 1368 pcn_shutdown(device_t dev) 1369 { 1370 struct pcn_softc *sc = device_get_softc(dev); 1371 struct ifnet *ifp = &sc->arpcom.ac_if; 1372 1373 lwkt_serialize_enter(ifp->if_serializer); 1374 pcn_reset(sc); 1375 pcn_stop(sc); 1376 lwkt_serialize_exit(ifp->if_serializer); 1377 } 1378 1379