1 /* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/pci/if_pcn.c,v 1.5.2.10 2003/03/05 18:42:33 njl Exp $ 34 * $DragonFly: src/sys/dev/netif/pcn/if_pcn.c,v 1.35 2008/08/22 08:38:15 swildner Exp $ 35 */ 36 37 /* 38 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 39 * from http://www.amd.com. 40 * 41 * Written by Bill Paul <wpaul@osd.bsdi.com> 42 */ 43 44 /* 45 * The AMD PCnet/PCI controllers are more advanced and functional 46 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 47 * backwards compatibility with the LANCE and thus can be made 48 * to work with older LANCE drivers. This is in fact how the 49 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 50 * is that the PCnet/PCI devices offer several performance enhancements 51 * which can't be exploited in LANCE compatibility mode. Chief among 52 * these enhancements is the ability to perform PCI DMA operations 53 * using 32-bit addressing (which eliminates the need for ISA 54 * bounce-buffering), and special receive buffer alignment (which 55 * allows the receive handler to pass packets to the upper protocol 56 * layers without copying on both the x86 and alpha platforms). 57 */ 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/sockio.h> 62 #include <sys/mbuf.h> 63 #include <sys/malloc.h> 64 #include <sys/kernel.h> 65 #include <sys/interrupt.h> 66 #include <sys/socket.h> 67 #include <sys/serialize.h> 68 #include <sys/bus.h> 69 #include <sys/rman.h> 70 #include <sys/thread2.h> 71 72 #include <net/if.h> 73 #include <net/ifq_var.h> 74 #include <net/if_arp.h> 75 #include <net/ethernet.h> 76 #include <net/if_dl.h> 77 #include <net/if_media.h> 78 79 #include <net/bpf.h> 80 81 #include <vm/vm.h> /* for vtophys */ 82 #include <vm/pmap.h> /* for vtophys */ 83 84 #include <machine/clock.h> /* for DELAY */ 85 86 #include "../mii_layer/mii.h" 87 #include "../mii_layer/miivar.h" 88 89 #include <bus/pci/pcidevs.h> 90 #include <bus/pci/pcireg.h> 91 #include <bus/pci/pcivar.h> 92 93 #define PCN_USEIOSPACE 94 95 #include "if_pcnreg.h" 96 97 /* "controller miibus0" required. See GENERIC if you get errors here. */ 98 #include "miibus_if.h" 99 100 /* 101 * Various supported device vendors/types and their names. 102 */ 103 static struct pcn_type pcn_devs[] = { 104 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PCNET_PCI, 105 "AMD PCnet/PCI 10/100BaseTX" }, 106 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PCNET_HOME, 107 "AMD PCnet/Home HomePNA" }, 108 { 0, 0, NULL } 109 }; 110 111 static u_int32_t pcn_csr_read (struct pcn_softc *, int); 112 static u_int16_t pcn_csr_read16 (struct pcn_softc *, int); 113 static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int); 114 static void pcn_csr_write (struct pcn_softc *, int, int); 115 static u_int32_t pcn_bcr_read (struct pcn_softc *, int); 116 static void pcn_bcr_write (struct pcn_softc *, int, int); 117 118 static int pcn_probe (device_t); 119 static int pcn_attach (device_t); 120 static int pcn_detach (device_t); 121 122 static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *); 123 static int pcn_encap (struct pcn_softc *, 124 struct mbuf *, u_int32_t *); 125 static void pcn_rxeof (struct pcn_softc *); 126 static void pcn_txeof (struct pcn_softc *); 127 static void pcn_intr (void *); 128 static void pcn_tick (void *); 129 static void pcn_start (struct ifnet *); 130 static int pcn_ioctl (struct ifnet *, u_long, caddr_t, 131 struct ucred *); 132 static void pcn_init (void *); 133 static void pcn_stop (struct pcn_softc *); 134 static void pcn_watchdog (struct ifnet *); 135 static void pcn_shutdown (device_t); 136 static int pcn_ifmedia_upd (struct ifnet *); 137 static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *); 138 139 static int pcn_miibus_readreg (device_t, int, int); 140 static int pcn_miibus_writereg (device_t, int, int, int); 141 static void pcn_miibus_statchg (device_t); 142 143 static void pcn_setfilt (struct ifnet *); 144 static void pcn_setmulti (struct pcn_softc *); 145 static u_int32_t pcn_crc (caddr_t); 146 static void pcn_reset (struct pcn_softc *); 147 static int pcn_list_rx_init (struct pcn_softc *); 148 static int pcn_list_tx_init (struct pcn_softc *); 149 150 #ifdef PCN_USEIOSPACE 151 #define PCN_RES SYS_RES_IOPORT 152 #define PCN_RID PCN_PCI_LOIO 153 #else 154 #define PCN_RES SYS_RES_MEMORY 155 #define PCN_RID PCN_PCI_LOMEM 156 #endif 157 158 static device_method_t pcn_methods[] = { 159 /* Device interface */ 160 DEVMETHOD(device_probe, pcn_probe), 161 DEVMETHOD(device_attach, pcn_attach), 162 DEVMETHOD(device_detach, pcn_detach), 163 DEVMETHOD(device_shutdown, pcn_shutdown), 164 165 /* bus interface */ 166 DEVMETHOD(bus_print_child, bus_generic_print_child), 167 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 168 169 /* MII interface */ 170 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 171 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 172 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 173 174 { 0, 0 } 175 }; 176 177 static driver_t pcn_driver = { 178 "pcn", 179 pcn_methods, 180 sizeof(struct pcn_softc) 181 }; 182 183 static devclass_t pcn_devclass; 184 185 DECLARE_DUMMY_MODULE(if_pcn); 186 DRIVER_MODULE(if_pcn, pci, pcn_driver, pcn_devclass, 0, 0); 187 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 188 189 #define PCN_CSR_SETBIT(sc, reg, x) \ 190 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 191 192 #define PCN_CSR_CLRBIT(sc, reg, x) \ 193 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 194 195 #define PCN_BCR_SETBIT(sc, reg, x) \ 196 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 197 198 #define PCN_BCR_CLRBIT(sc, reg, x) \ 199 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 200 201 static u_int32_t 202 pcn_csr_read(struct pcn_softc *sc, int reg) 203 { 204 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 205 return(CSR_READ_4(sc, PCN_IO32_RDP)); 206 } 207 208 static u_int16_t 209 pcn_csr_read16(struct pcn_softc *sc, int reg) 210 { 211 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 212 return(CSR_READ_2(sc, PCN_IO16_RDP)); 213 } 214 215 static void 216 pcn_csr_write(struct pcn_softc *sc, int reg, int val) 217 { 218 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 219 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 220 return; 221 } 222 223 static u_int32_t 224 pcn_bcr_read(struct pcn_softc *sc, int reg) 225 { 226 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 227 return(CSR_READ_4(sc, PCN_IO32_BDP)); 228 } 229 230 static u_int16_t 231 pcn_bcr_read16(struct pcn_softc *sc, int reg) 232 { 233 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 234 return(CSR_READ_2(sc, PCN_IO16_BDP)); 235 } 236 237 static void 238 pcn_bcr_write(struct pcn_softc *sc, int reg, int val) 239 { 240 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 241 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 242 return; 243 } 244 245 static int 246 pcn_miibus_readreg(device_t dev, int phy, int reg) 247 { 248 struct pcn_softc *sc; 249 int val; 250 251 sc = device_get_softc(dev); 252 253 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 254 return(0); 255 256 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 257 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 258 if (val == 0xFFFF) 259 return(0); 260 261 sc->pcn_phyaddr = phy; 262 263 return(val); 264 } 265 266 static int 267 pcn_miibus_writereg(device_t dev, int phy, int reg, int data) 268 { 269 struct pcn_softc *sc; 270 271 sc = device_get_softc(dev); 272 273 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 274 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 275 276 return(0); 277 } 278 279 static void 280 pcn_miibus_statchg(device_t dev) 281 { 282 struct pcn_softc *sc; 283 struct mii_data *mii; 284 285 sc = device_get_softc(dev); 286 mii = device_get_softc(sc->pcn_miibus); 287 288 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 289 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 290 } else { 291 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 292 } 293 294 return; 295 } 296 297 #define DC_POLY 0xEDB88320 298 299 static u_int32_t 300 pcn_crc(caddr_t addr) 301 { 302 u_int32_t idx, bit, data, crc; 303 304 /* Compute CRC for the address value. */ 305 crc = 0xFFFFFFFF; /* initial value */ 306 307 for (idx = 0; idx < 6; idx++) { 308 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 309 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 310 } 311 312 return ((crc >> 26) & 0x3F); 313 } 314 315 static void 316 pcn_setmulti(struct pcn_softc *sc) 317 { 318 struct ifnet *ifp; 319 struct ifmultiaddr *ifma; 320 u_int32_t h, i; 321 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 322 323 ifp = &sc->arpcom.ac_if; 324 325 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 326 327 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 328 for (i = 0; i < 4; i++) 329 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 330 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 331 return; 332 } 333 334 /* first, zot all the existing hash bits */ 335 for (i = 0; i < 4; i++) 336 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 337 338 /* now program new ones */ 339 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 340 if (ifma->ifma_addr->sa_family != AF_LINK) 341 continue; 342 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 343 hashes[h >> 4] |= 1 << (h & 0xF); 344 } 345 346 for (i = 0; i < 4; i++) 347 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 348 349 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 350 351 return; 352 } 353 354 static void 355 pcn_reset(struct pcn_softc *sc) 356 { 357 /* 358 * Issue a reset by reading from the RESET register. 359 * Note that we don't know if the chip is operating in 360 * 16-bit or 32-bit mode at this point, so we attempt 361 * to reset the chip both ways. If one fails, the other 362 * will succeed. 363 */ 364 CSR_READ_2(sc, PCN_IO16_RESET); 365 CSR_READ_4(sc, PCN_IO32_RESET); 366 367 /* Wait a little while for the chip to get its brains in order. */ 368 DELAY(1000); 369 370 /* Select 32-bit (DWIO) mode */ 371 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 372 373 /* Select software style 3. */ 374 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 375 376 return; 377 } 378 379 /* 380 * Probe for an AMD chip. Check the PCI vendor and device 381 * IDs against our list and return a device name if we find a match. 382 */ 383 static int 384 pcn_probe(device_t dev) 385 { 386 struct pcn_type *t; 387 struct pcn_softc *sc; 388 int rid; 389 u_int32_t chip_id; 390 391 t = pcn_devs; 392 sc = device_get_softc(dev); 393 394 while(t->pcn_name != NULL) { 395 if ((pci_get_vendor(dev) == t->pcn_vid) && 396 (pci_get_device(dev) == t->pcn_did)) { 397 /* 398 * Temporarily map the I/O space 399 * so we can read the chip ID register. 400 */ 401 rid = PCN_RID; 402 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, 403 &rid, RF_ACTIVE); 404 if (sc->pcn_res == NULL) { 405 device_printf(dev, 406 "couldn't map ports/memory\n"); 407 return(ENXIO); 408 } 409 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 410 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 411 /* 412 * Note: we can *NOT* put the chip into 413 * 32-bit mode yet. The lnc driver will only 414 * work in 16-bit mode, and once the chip 415 * goes into 32-bit mode, the only way to 416 * get it out again is with a hardware reset. 417 * So if pcn_probe() is called before the 418 * lnc driver's probe routine, the chip will 419 * be locked into 32-bit operation and the lnc 420 * driver will be unable to attach to it. 421 * Note II: if the chip happens to already 422 * be in 32-bit mode, we still need to check 423 * the chip ID, but first we have to detect 424 * 32-bit mode using only 16-bit operations. 425 * The safest way to do this is to read the 426 * PCI subsystem ID from BCR23/24 and compare 427 * that with the value read from PCI config 428 * space. 429 */ 430 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 431 chip_id <<= 16; 432 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 433 /* 434 * Note III: the test for 0x10001000 is a hack to 435 * pacify VMware, who's pseudo-PCnet interface is 436 * broken. Reading the subsystem register from PCI 437 * config space yeilds 0x00000000 while reading the 438 * same value from I/O space yeilds 0x10001000. It's 439 * not supposed to be that way. 440 */ 441 if (chip_id == pci_read_config(dev, 442 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 443 /* We're in 16-bit mode. */ 444 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 445 chip_id <<= 16; 446 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 447 } else { 448 /* We're in 32-bit mode. */ 449 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 450 chip_id <<= 16; 451 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 452 } 453 bus_release_resource(dev, PCN_RES, 454 PCN_RID, sc->pcn_res); 455 chip_id >>= 12; 456 sc->pcn_type = chip_id & PART_MASK; 457 switch(sc->pcn_type) { 458 case Am79C971: 459 case Am79C972: 460 case Am79C973: 461 case Am79C975: 462 case Am79C976: 463 case Am79C978: 464 break; 465 default: 466 return(ENXIO); 467 break; 468 } 469 device_set_desc(dev, t->pcn_name); 470 return(0); 471 } 472 t++; 473 } 474 475 return(ENXIO); 476 } 477 478 /* 479 * Attach the interface. Allocate softc structures, do ifmedia 480 * setup and ethernet/BPF attach. 481 */ 482 static int 483 pcn_attach(device_t dev) 484 { 485 uint8_t eaddr[ETHER_ADDR_LEN]; 486 u_int32_t command; 487 struct pcn_softc *sc; 488 struct ifnet *ifp; 489 int unit, error = 0, rid; 490 491 sc = device_get_softc(dev); 492 unit = device_get_unit(dev); 493 494 /* 495 * Handle power management nonsense. 496 */ 497 498 command = pci_read_config(dev, PCN_PCI_CAPID, 4) & 0x000000FF; 499 if (command == 0x01) { 500 501 command = pci_read_config(dev, PCN_PCI_PWRMGMTCTRL, 4); 502 if (command & PCN_PSTATE_MASK) { 503 u_int32_t iobase, membase, irq; 504 505 /* Save important PCI config data. */ 506 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 507 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 508 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 509 510 /* Reset the power state. */ 511 kprintf("pcn%d: chip is in D%d power mode " 512 "-- setting to D0\n", unit, command & PCN_PSTATE_MASK); 513 command &= 0xFFFFFFFC; 514 pci_write_config(dev, PCN_PCI_PWRMGMTCTRL, command, 4); 515 516 /* Restore PCI config data. */ 517 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 518 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 519 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 520 } 521 } 522 523 /* 524 * Map control/status registers. 525 */ 526 command = pci_read_config(dev, PCIR_COMMAND, 4); 527 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 528 pci_write_config(dev, PCIR_COMMAND, command, 4); 529 command = pci_read_config(dev, PCIR_COMMAND, 4); 530 531 #ifdef PCN_USEIOSPACE 532 if (!(command & PCIM_CMD_PORTEN)) { 533 kprintf("pcn%d: failed to enable I/O ports!\n", unit); 534 error = ENXIO; 535 return(error); 536 } 537 #else 538 if (!(command & PCIM_CMD_MEMEN)) { 539 kprintf("pcn%d: failed to enable memory mapping!\n", unit); 540 error = ENXIO; 541 return(error); 542 } 543 #endif 544 545 rid = PCN_RID; 546 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE); 547 548 if (sc->pcn_res == NULL) { 549 kprintf("pcn%d: couldn't map ports/memory\n", unit); 550 error = ENXIO; 551 return(error); 552 } 553 554 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 555 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 556 557 /* Allocate interrupt */ 558 rid = 0; 559 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 560 RF_SHAREABLE | RF_ACTIVE); 561 562 if (sc->pcn_irq == NULL) { 563 kprintf("pcn%d: couldn't map interrupt\n", unit); 564 error = ENXIO; 565 goto fail; 566 } 567 568 /* Reset the adapter. */ 569 pcn_reset(sc); 570 571 /* 572 * Get station address from the EEPROM. 573 */ 574 *(uint32_t *)eaddr = CSR_READ_4(sc, PCN_IO32_APROM00); 575 *(uint16_t *)(eaddr + 4) = CSR_READ_2(sc, PCN_IO32_APROM01); 576 577 sc->pcn_unit = unit; 578 callout_init(&sc->pcn_stat_timer); 579 580 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 581 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 582 583 if (sc->pcn_ldata == NULL) { 584 kprintf("pcn%d: no memory for list buffers!\n", unit); 585 error = ENXIO; 586 goto fail; 587 } 588 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 589 590 ifp = &sc->arpcom.ac_if; 591 ifp->if_softc = sc; 592 if_initname(ifp, "pcn", unit); 593 ifp->if_mtu = ETHERMTU; 594 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 595 ifp->if_ioctl = pcn_ioctl; 596 ifp->if_start = pcn_start; 597 ifp->if_watchdog = pcn_watchdog; 598 ifp->if_init = pcn_init; 599 ifp->if_baudrate = 10000000; 600 ifq_set_maxlen(&ifp->if_snd, PCN_TX_LIST_CNT - 1); 601 ifq_set_ready(&ifp->if_snd); 602 603 /* 604 * Do MII setup. 605 */ 606 if (mii_phy_probe(dev, &sc->pcn_miibus, 607 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 608 kprintf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 609 error = ENXIO; 610 goto fail; 611 } 612 613 /* 614 * Call MI attach routine. 615 */ 616 ether_ifattach(ifp, eaddr, NULL); 617 618 error = bus_setup_intr(dev, sc->pcn_irq, INTR_MPSAFE, 619 pcn_intr, sc, &sc->pcn_intrhand, 620 ifp->if_serializer); 621 if (error) { 622 ether_ifdetach(ifp); 623 device_printf(dev, "couldn't set up irq\n"); 624 goto fail; 625 } 626 627 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->pcn_irq)); 628 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 629 630 return (0); 631 fail: 632 pcn_detach(dev); 633 return(error); 634 } 635 636 static int 637 pcn_detach(device_t dev) 638 { 639 struct pcn_softc *sc = device_get_softc(dev); 640 struct ifnet *ifp = &sc->arpcom.ac_if; 641 642 if (device_is_attached(dev)) { 643 lwkt_serialize_enter(ifp->if_serializer); 644 pcn_reset(sc); 645 pcn_stop(sc); 646 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 647 lwkt_serialize_exit(ifp->if_serializer); 648 649 ether_ifdetach(ifp); 650 } 651 652 if (sc->pcn_miibus != NULL) 653 device_delete_child(dev, sc->pcn_miibus); 654 bus_generic_detach(dev); 655 656 if (sc->pcn_irq) 657 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 658 if (sc->pcn_res) 659 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 660 661 if (sc->pcn_ldata) { 662 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 663 M_DEVBUF); 664 } 665 666 return(0); 667 } 668 669 /* 670 * Initialize the transmit descriptors. 671 */ 672 static int 673 pcn_list_tx_init(struct pcn_softc *sc) 674 { 675 struct pcn_list_data *ld; 676 struct pcn_ring_data *cd; 677 int i; 678 679 cd = &sc->pcn_cdata; 680 ld = sc->pcn_ldata; 681 682 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 683 cd->pcn_tx_chain[i] = NULL; 684 ld->pcn_tx_list[i].pcn_tbaddr = 0; 685 ld->pcn_tx_list[i].pcn_txctl = 0; 686 ld->pcn_tx_list[i].pcn_txstat = 0; 687 } 688 689 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 690 691 return(0); 692 } 693 694 695 /* 696 * Initialize the RX descriptors and allocate mbufs for them. 697 */ 698 static int 699 pcn_list_rx_init(struct pcn_softc *sc) 700 { 701 struct pcn_ring_data *cd; 702 int i; 703 704 cd = &sc->pcn_cdata; 705 706 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 707 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 708 return(ENOBUFS); 709 } 710 711 cd->pcn_rx_prod = 0; 712 713 return(0); 714 } 715 716 /* 717 * Initialize an RX descriptor and attach an MBUF cluster. 718 */ 719 static int 720 pcn_newbuf(struct pcn_softc *sc, int idx, struct mbuf *m) 721 { 722 struct mbuf *m_new = NULL; 723 struct pcn_rx_desc *c; 724 725 c = &sc->pcn_ldata->pcn_rx_list[idx]; 726 727 if (m == NULL) { 728 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 729 if (m_new == NULL) 730 return(ENOBUFS); 731 732 MCLGET(m_new, MB_DONTWAIT); 733 if (!(m_new->m_flags & M_EXT)) { 734 m_freem(m_new); 735 return(ENOBUFS); 736 } 737 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 738 } else { 739 m_new = m; 740 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 741 m_new->m_data = m_new->m_ext.ext_buf; 742 } 743 744 m_adj(m_new, ETHER_ALIGN); 745 746 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 747 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 748 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 749 c->pcn_bufsz |= PCN_RXLEN_MBO; 750 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 751 752 return(0); 753 } 754 755 /* 756 * A frame has been uploaded: pass the resulting mbuf chain up to 757 * the higher level protocols. 758 */ 759 static void 760 pcn_rxeof(struct pcn_softc *sc) 761 { 762 struct mbuf *m; 763 struct ifnet *ifp; 764 struct pcn_rx_desc *cur_rx; 765 int i; 766 767 ifp = &sc->arpcom.ac_if; 768 i = sc->pcn_cdata.pcn_rx_prod; 769 770 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 771 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 772 m = sc->pcn_cdata.pcn_rx_chain[i]; 773 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 774 775 /* 776 * If an error occurs, update stats, clear the 777 * status word and leave the mbuf cluster in place: 778 * it should simply get re-used next time this descriptor 779 * comes up in the ring. 780 */ 781 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 782 ifp->if_ierrors++; 783 pcn_newbuf(sc, i, m); 784 PCN_INC(i, PCN_RX_LIST_CNT); 785 continue; 786 } 787 788 if (pcn_newbuf(sc, i, NULL)) { 789 /* Ran out of mbufs; recycle this one. */ 790 pcn_newbuf(sc, i, m); 791 ifp->if_ierrors++; 792 PCN_INC(i, PCN_RX_LIST_CNT); 793 continue; 794 } 795 796 PCN_INC(i, PCN_RX_LIST_CNT); 797 798 /* No errors; receive the packet. */ 799 ifp->if_ipackets++; 800 m->m_len = m->m_pkthdr.len = 801 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 802 m->m_pkthdr.rcvif = ifp; 803 804 ifp->if_input(ifp, m); 805 } 806 807 sc->pcn_cdata.pcn_rx_prod = i; 808 809 return; 810 } 811 812 /* 813 * A frame was downloaded to the chip. It's safe for us to clean up 814 * the list buffers. 815 */ 816 817 static void 818 pcn_txeof(struct pcn_softc *sc) 819 { 820 struct pcn_tx_desc *cur_tx = NULL; 821 struct ifnet *ifp; 822 u_int32_t idx; 823 824 ifp = &sc->arpcom.ac_if; 825 826 /* 827 * Go through our tx list and free mbufs for those 828 * frames that have been transmitted. 829 */ 830 idx = sc->pcn_cdata.pcn_tx_cons; 831 while (idx != sc->pcn_cdata.pcn_tx_prod) { 832 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 833 834 if (!PCN_OWN_TXDESC(cur_tx)) 835 break; 836 837 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 838 sc->pcn_cdata.pcn_tx_cnt--; 839 PCN_INC(idx, PCN_TX_LIST_CNT); 840 continue; 841 } 842 843 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 844 ifp->if_oerrors++; 845 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 846 ifp->if_collisions++; 847 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 848 ifp->if_collisions++; 849 } 850 851 ifp->if_collisions += 852 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 853 854 ifp->if_opackets++; 855 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 856 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 857 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 858 } 859 860 sc->pcn_cdata.pcn_tx_cnt--; 861 PCN_INC(idx, PCN_TX_LIST_CNT); 862 } 863 864 if (idx != sc->pcn_cdata.pcn_tx_cons) { 865 /* Some buffers have been freed. */ 866 sc->pcn_cdata.pcn_tx_cons = idx; 867 ifp->if_flags &= ~IFF_OACTIVE; 868 } 869 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 870 871 return; 872 } 873 874 static void 875 pcn_tick(void *xsc) 876 { 877 struct pcn_softc *sc = xsc; 878 struct mii_data *mii; 879 struct ifnet *ifp = &sc->arpcom.ac_if; 880 881 lwkt_serialize_enter(ifp->if_serializer); 882 883 mii = device_get_softc(sc->pcn_miibus); 884 mii_tick(mii); 885 886 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 887 sc->pcn_link = 0; 888 889 if (!sc->pcn_link) { 890 mii_pollstat(mii); 891 if (mii->mii_media_status & IFM_ACTIVE && 892 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 893 sc->pcn_link++; 894 if (!ifq_is_empty(&ifp->if_snd)) 895 if_devstart(ifp); 896 } 897 callout_reset(&sc->pcn_stat_timer, hz, pcn_tick, sc); 898 899 lwkt_serialize_exit(ifp->if_serializer); 900 } 901 902 static void 903 pcn_intr(void *arg) 904 { 905 struct pcn_softc *sc; 906 struct ifnet *ifp; 907 u_int32_t status; 908 909 sc = arg; 910 ifp = &sc->arpcom.ac_if; 911 912 /* Supress unwanted interrupts */ 913 if (!(ifp->if_flags & IFF_UP)) { 914 pcn_stop(sc); 915 return; 916 } 917 918 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 919 920 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 921 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 922 923 if (status & PCN_CSR_RINT) 924 pcn_rxeof(sc); 925 926 if (status & PCN_CSR_TINT) 927 pcn_txeof(sc); 928 929 if (status & PCN_CSR_ERR) { 930 pcn_init(sc); 931 break; 932 } 933 } 934 935 if (!ifq_is_empty(&ifp->if_snd)) 936 if_devstart(ifp); 937 } 938 939 /* 940 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 941 * pointers to the fragment pointers. 942 */ 943 static int 944 pcn_encap(struct pcn_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 945 { 946 struct pcn_tx_desc *f = NULL; 947 struct mbuf *m; 948 int frag, cur, cnt = 0; 949 950 /* 951 * Start packing the mbufs in this chain into 952 * the fragment pointers. Stop when we run out 953 * of fragments or hit the end of the mbuf chain. 954 */ 955 cur = frag = *txidx; 956 957 for (m = m_head; m != NULL; m = m->m_next) { 958 if (m->m_len != 0) { 959 if ((PCN_TX_LIST_CNT - 960 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 961 break; 962 f = &sc->pcn_ldata->pcn_tx_list[frag]; 963 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 964 f->pcn_txctl |= PCN_TXCTL_MBO; 965 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 966 if (cnt == 0) 967 f->pcn_txctl |= PCN_TXCTL_STP; 968 else 969 f->pcn_txctl |= PCN_TXCTL_OWN; 970 cur = frag; 971 PCN_INC(frag, PCN_TX_LIST_CNT); 972 cnt++; 973 } 974 } 975 /* Caller should make sure that 'm_head' is not excessive fragmented */ 976 KASSERT(m == NULL, ("too many fragments\n")); 977 978 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 979 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 980 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 981 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 982 sc->pcn_cdata.pcn_tx_cnt += cnt; 983 *txidx = frag; 984 985 return(0); 986 } 987 988 /* 989 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 990 * to the mbuf data regions directly in the transmit lists. We also save a 991 * copy of the pointers since the transmit list fragment pointers are 992 * physical addresses. 993 */ 994 static void 995 pcn_start(struct ifnet *ifp) 996 { 997 struct pcn_softc *sc; 998 struct mbuf *m_head = NULL, *m_defragged; 999 u_int32_t idx; 1000 int need_trans; 1001 1002 sc = ifp->if_softc; 1003 1004 if (!sc->pcn_link) { 1005 ifq_purge(&ifp->if_snd); 1006 return; 1007 } 1008 1009 idx = sc->pcn_cdata.pcn_tx_prod; 1010 1011 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 1012 return; 1013 1014 need_trans = 0; 1015 while (sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1016 struct mbuf *m; 1017 int cnt; 1018 1019 m_defragged = NULL; 1020 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1021 if (m_head == NULL) 1022 break; 1023 1024 again: 1025 cnt = 0; 1026 for (m = m_head; m != NULL; m = m->m_next) 1027 ++cnt; 1028 if ((PCN_TX_LIST_CNT - 1029 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) { 1030 if (m_defragged != NULL) { 1031 /* 1032 * Even after defragmentation, there 1033 * are still too many fragments, so 1034 * drop this packet. 1035 */ 1036 m_freem(m_head); 1037 ifp->if_flags |= IFF_OACTIVE; 1038 break; 1039 } 1040 1041 m_defragged = m_defrag(m_head, MB_DONTWAIT); 1042 if (m_defragged == NULL) { 1043 m_freem(m_head); 1044 continue; 1045 } 1046 m_head = m_defragged; 1047 1048 /* Recount # of fragments */ 1049 goto again; 1050 } 1051 1052 pcn_encap(sc, m_head, &idx); 1053 need_trans = 1; 1054 1055 BPF_MTAP(ifp, m_head); 1056 } 1057 1058 if (!need_trans) 1059 return; 1060 1061 /* Transmit */ 1062 sc->pcn_cdata.pcn_tx_prod = idx; 1063 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1064 1065 /* 1066 * Set a timeout in case the chip goes out to lunch. 1067 */ 1068 ifp->if_timer = 5; 1069 } 1070 1071 void 1072 pcn_setfilt(struct ifnet *ifp) 1073 { 1074 struct pcn_softc *sc; 1075 1076 sc = ifp->if_softc; 1077 1078 /* If we want promiscuous mode, set the allframes bit. */ 1079 if (ifp->if_flags & IFF_PROMISC) { 1080 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1081 } else { 1082 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1083 } 1084 1085 /* Set the capture broadcast bit to capture broadcast frames. */ 1086 if (ifp->if_flags & IFF_BROADCAST) { 1087 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1088 } else { 1089 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1090 } 1091 1092 return; 1093 } 1094 1095 static void 1096 pcn_init(void *xsc) 1097 { 1098 struct pcn_softc *sc = xsc; 1099 struct ifnet *ifp = &sc->arpcom.ac_if; 1100 struct mii_data *mii = NULL; 1101 1102 /* 1103 * Cancel pending I/O and free all RX/TX buffers. 1104 */ 1105 pcn_stop(sc); 1106 pcn_reset(sc); 1107 1108 mii = device_get_softc(sc->pcn_miibus); 1109 1110 /* Set MAC address */ 1111 pcn_csr_write(sc, PCN_CSR_PAR0, 1112 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1113 pcn_csr_write(sc, PCN_CSR_PAR1, 1114 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1115 pcn_csr_write(sc, PCN_CSR_PAR2, 1116 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1117 1118 /* Init circular RX list. */ 1119 if (pcn_list_rx_init(sc) == ENOBUFS) { 1120 kprintf("pcn%d: initialization failed: no " 1121 "memory for rx buffers\n", sc->pcn_unit); 1122 pcn_stop(sc); 1123 1124 return; 1125 } 1126 1127 /* Set up RX filter. */ 1128 pcn_setfilt(ifp); 1129 1130 /* 1131 * Init tx descriptors. 1132 */ 1133 pcn_list_tx_init(sc); 1134 1135 /* Set up the mode register. */ 1136 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1137 1138 /* 1139 * Load the multicast filter. 1140 */ 1141 pcn_setmulti(sc); 1142 1143 /* 1144 * Load the addresses of the RX and TX lists. 1145 */ 1146 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1147 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1148 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1149 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1150 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1151 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1152 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1153 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1154 1155 /* Set the RX and TX ring sizes. */ 1156 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1157 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1158 1159 /* We're not using the initialization block. */ 1160 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1161 1162 /* Enable fast suspend mode. */ 1163 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1164 1165 /* 1166 * Enable burst read and write. Also set the no underflow 1167 * bit. This will avoid transmit underruns in certain 1168 * conditions while still providing decent performance. 1169 */ 1170 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1171 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1172 1173 /* Enable graceful recovery from underflow. */ 1174 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1175 1176 /* Enable auto-padding of short TX frames. */ 1177 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1178 1179 /* Disable MII autoneg (we handle this ourselves). */ 1180 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1181 1182 if (sc->pcn_type == Am79C978) 1183 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1184 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1185 1186 /* Enable interrupts and start the controller running. */ 1187 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1188 1189 mii_mediachg(mii); 1190 1191 ifp->if_flags |= IFF_RUNNING; 1192 ifp->if_flags &= ~IFF_OACTIVE; 1193 1194 callout_reset(&sc->pcn_stat_timer, hz, pcn_tick, sc); 1195 } 1196 1197 /* 1198 * Set media options. 1199 */ 1200 static int 1201 pcn_ifmedia_upd(struct ifnet *ifp) 1202 { 1203 struct pcn_softc *sc; 1204 struct mii_data *mii; 1205 1206 sc = ifp->if_softc; 1207 mii = device_get_softc(sc->pcn_miibus); 1208 1209 sc->pcn_link = 0; 1210 if (mii->mii_instance) { 1211 struct mii_softc *miisc; 1212 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1213 miisc = LIST_NEXT(miisc, mii_list)) 1214 mii_phy_reset(miisc); 1215 } 1216 mii_mediachg(mii); 1217 1218 return(0); 1219 } 1220 1221 /* 1222 * Report current media status. 1223 */ 1224 static void 1225 pcn_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1226 { 1227 struct pcn_softc *sc; 1228 struct mii_data *mii; 1229 1230 sc = ifp->if_softc; 1231 1232 mii = device_get_softc(sc->pcn_miibus); 1233 mii_pollstat(mii); 1234 ifmr->ifm_active = mii->mii_media_active; 1235 ifmr->ifm_status = mii->mii_media_status; 1236 1237 return; 1238 } 1239 1240 static int 1241 pcn_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1242 { 1243 struct pcn_softc *sc = ifp->if_softc; 1244 struct ifreq *ifr = (struct ifreq *) data; 1245 struct mii_data *mii = NULL; 1246 int error = 0; 1247 1248 switch(command) { 1249 case SIOCSIFFLAGS: 1250 if (ifp->if_flags & IFF_UP) { 1251 if (ifp->if_flags & IFF_RUNNING && 1252 ifp->if_flags & IFF_PROMISC && 1253 !(sc->pcn_if_flags & IFF_PROMISC)) { 1254 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1255 PCN_EXTCTL1_SPND); 1256 pcn_setfilt(ifp); 1257 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1258 PCN_EXTCTL1_SPND); 1259 pcn_csr_write(sc, PCN_CSR_CSR, 1260 PCN_CSR_INTEN|PCN_CSR_START); 1261 } else if (ifp->if_flags & IFF_RUNNING && 1262 !(ifp->if_flags & IFF_PROMISC) && 1263 sc->pcn_if_flags & IFF_PROMISC) { 1264 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1265 PCN_EXTCTL1_SPND); 1266 pcn_setfilt(ifp); 1267 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1268 PCN_EXTCTL1_SPND); 1269 pcn_csr_write(sc, PCN_CSR_CSR, 1270 PCN_CSR_INTEN|PCN_CSR_START); 1271 } else if (!(ifp->if_flags & IFF_RUNNING)) 1272 pcn_init(sc); 1273 } else { 1274 if (ifp->if_flags & IFF_RUNNING) 1275 pcn_stop(sc); 1276 } 1277 sc->pcn_if_flags = ifp->if_flags; 1278 error = 0; 1279 break; 1280 case SIOCADDMULTI: 1281 case SIOCDELMULTI: 1282 pcn_setmulti(sc); 1283 error = 0; 1284 break; 1285 case SIOCGIFMEDIA: 1286 case SIOCSIFMEDIA: 1287 mii = device_get_softc(sc->pcn_miibus); 1288 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1289 break; 1290 default: 1291 error = ether_ioctl(ifp, command, data); 1292 break; 1293 } 1294 return(error); 1295 } 1296 1297 static void 1298 pcn_watchdog(struct ifnet *ifp) 1299 { 1300 struct pcn_softc *sc; 1301 1302 sc = ifp->if_softc; 1303 1304 ifp->if_oerrors++; 1305 kprintf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1306 1307 pcn_stop(sc); 1308 pcn_reset(sc); 1309 pcn_init(sc); 1310 1311 if (!ifq_is_empty(&ifp->if_snd)) 1312 if_devstart(ifp); 1313 } 1314 1315 /* 1316 * Stop the adapter and free any mbufs allocated to the 1317 * RX and TX lists. 1318 */ 1319 static void 1320 pcn_stop(struct pcn_softc *sc) 1321 { 1322 int i; 1323 struct ifnet *ifp; 1324 1325 ifp = &sc->arpcom.ac_if; 1326 ifp->if_timer = 0; 1327 1328 callout_stop(&sc->pcn_stat_timer); 1329 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1330 sc->pcn_link = 0; 1331 1332 /* 1333 * Free data in the RX lists. 1334 */ 1335 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1336 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1337 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1338 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1339 } 1340 } 1341 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1342 sizeof(sc->pcn_ldata->pcn_rx_list)); 1343 1344 /* 1345 * Free the TX list buffers. 1346 */ 1347 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1348 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1349 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1350 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1351 } 1352 } 1353 1354 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1355 sizeof(sc->pcn_ldata->pcn_tx_list)); 1356 1357 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1358 1359 return; 1360 } 1361 1362 /* 1363 * Stop all chip I/O so that the kernel's probe routines don't 1364 * get confused by errant DMAs when rebooting. 1365 */ 1366 static void 1367 pcn_shutdown(device_t dev) 1368 { 1369 struct pcn_softc *sc = device_get_softc(dev); 1370 struct ifnet *ifp = &sc->arpcom.ac_if; 1371 1372 lwkt_serialize_enter(ifp->if_serializer); 1373 pcn_reset(sc); 1374 pcn_stop(sc); 1375 lwkt_serialize_exit(ifp->if_serializer); 1376 } 1377 1378