1 /* $FreeBSD: head/sys/dev/ral/rt2560reg.h 178354 2008-04-20 20:35:46Z sam $ */ 2 3 /*- 4 * Copyright (c) 2005, 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define RT2560_DEFAULT_RSSI_CORR 0x79 21 #define RT2560_NOISE_FLOOR -95 22 23 #define RT2560_TX_RING_COUNT 48 24 #define RT2560_ATIM_RING_COUNT 4 25 #define RT2560_PRIO_RING_COUNT 16 26 #define RT2560_BEACON_RING_COUNT 1 27 #define RT2560_RX_RING_COUNT 32 28 29 #define RT2560_TX_DESC_SIZE (sizeof (struct rt2560_tx_desc)) 30 #define RT2560_RX_DESC_SIZE (sizeof (struct rt2560_rx_desc)) 31 32 #define RT2560_MAX_SCATTER 1 33 34 /* 35 * Control and status registers. 36 */ 37 #define RT2560_CSR0 0x0000 /* ASIC version number */ 38 #define RT2560_CSR1 0x0004 /* System control */ 39 #define RT2560_CSR3 0x000c /* STA MAC address 0 */ 40 #define RT2560_CSR4 0x0010 /* STA MAC address 1 */ 41 #define RT2560_CSR5 0x0014 /* BSSID 0 */ 42 #define RT2560_CSR6 0x0018 /* BSSID 1 */ 43 #define RT2560_CSR7 0x001c /* Interrupt source */ 44 #define RT2560_CSR8 0x0020 /* Interrupt mask */ 45 #define RT2560_CSR9 0x0024 /* Maximum frame length */ 46 #define RT2560_SECCSR0 0x0028 /* WEP control */ 47 #define RT2560_CSR11 0x002c /* Back-off control */ 48 #define RT2560_CSR12 0x0030 /* Synchronization configuration 0 */ 49 #define RT2560_CSR13 0x0034 /* Synchronization configuration 1 */ 50 #define RT2560_CSR14 0x0038 /* Synchronization control */ 51 #define RT2560_CSR15 0x003c /* Synchronization status */ 52 #define RT2560_CSR16 0x0040 /* TSF timer 0 */ 53 #define RT2560_CSR17 0x0044 /* TSF timer 1 */ 54 #define RT2560_CSR18 0x0048 /* IFS timer 0 */ 55 #define RT2560_CSR19 0x004c /* IFS timer 1 */ 56 #define RT2560_CSR20 0x0050 /* WAKEUP timer */ 57 #define RT2560_CSR21 0x0054 /* EEPROM control */ 58 #define RT2560_CSR22 0x0058 /* CFP control */ 59 #define RT2560_TXCSR0 0x0060 /* TX control */ 60 #define RT2560_TXCSR1 0x0064 /* TX configuration */ 61 #define RT2560_TXCSR2 0x0068 /* TX descriptor configuration */ 62 #define RT2560_TXCSR3 0x006c /* TX ring base address */ 63 #define RT2560_TXCSR4 0x0070 /* TX ATIM ring base address */ 64 #define RT2560_TXCSR5 0x0074 /* TX PRIO ring base address */ 65 #define RT2560_TXCSR6 0x0078 /* Beacon base address */ 66 #define RT2560_TXCSR7 0x007c /* AutoResponder control */ 67 #define RT2560_RXCSR0 0x0080 /* RX control */ 68 #define RT2560_RXCSR1 0x0084 /* RX descriptor configuration */ 69 #define RT2560_RXCSR2 0x0088 /* RX ring base address */ 70 #define RT2560_PCICSR 0x008c /* PCI control */ 71 #define RT2560_RXCSR3 0x0090 /* BBP ID 0 */ 72 #define RT2560_TXCSR9 0x0094 /* OFDM TX BBP */ 73 #define RT2560_ARSP_PLCP_0 0x0098 /* Auto Responder PLCP address */ 74 #define RT2560_ARSP_PLCP_1 0x009c /* Auto Responder Basic Rate mask */ 75 #define RT2560_CNT0 0x00a0 /* FCS error counter */ 76 #define RT2560_CNT1 0x00ac /* PLCP error counter */ 77 #define RT2560_CNT2 0x00b0 /* Long error counter */ 78 #define RT2560_CNT3 0x00b8 /* CCA false alarm counter */ 79 #define RT2560_CNT4 0x00bc /* RX FIFO Overflow counter */ 80 #define RT2560_CNT5 0x00c0 /* Tx FIFO Underrun counter */ 81 #define RT2560_PWRCSR0 0x00c4 /* Power mode configuration */ 82 #define RT2560_PSCSR0 0x00c8 /* Power state transition time */ 83 #define RT2560_PSCSR1 0x00cc /* Power state transition time */ 84 #define RT2560_PSCSR2 0x00d0 /* Power state transition time */ 85 #define RT2560_PSCSR3 0x00d4 /* Power state transition time */ 86 #define RT2560_PWRCSR1 0x00d8 /* Manual power control/status */ 87 #define RT2560_TIMECSR 0x00dc /* Timer control */ 88 #define RT2560_MACCSR0 0x00e0 /* MAC configuration */ 89 #define RT2560_MACCSR1 0x00e4 /* MAC configuration */ 90 #define RT2560_RALINKCSR 0x00e8 /* Ralink RX auto-reset BBCR */ 91 #define RT2560_BCNCSR 0x00ec /* Beacon interval control */ 92 #define RT2560_BBPCSR 0x00f0 /* BBP serial control */ 93 #define RT2560_RFCSR 0x00f4 /* RF serial control */ 94 #define RT2560_LEDCSR 0x00f8 /* LED control */ 95 #define RT2560_SECCSR3 0x00fc /* XXX not documented */ 96 #define RT2560_DMACSR0 0x0100 /* Current RX ring address */ 97 #define RT2560_DMACSR1 0x0104 /* Current Tx ring address */ 98 #define RT2560_DMACSR2 0x0104 /* Current Priority ring address */ 99 #define RT2560_DMACSR3 0x0104 /* Current ATIM ring address */ 100 #define RT2560_TXACKCSR0 0x0110 /* XXX not documented */ 101 #define RT2560_GPIOCSR 0x0120 /* */ 102 #define RT2560_BBBPPCSR 0x0124 /* BBP Pin Control */ 103 #define RT2560_FIFOCSR0 0x0128 /* TX FIFO pointer */ 104 #define RT2560_FIFOCSR1 0x012c /* RX FIFO pointer */ 105 #define RT2560_BCNOCSR 0x0130 /* Beacon time offset */ 106 #define RT2560_RLPWCSR 0x0134 /* RX_PE Low Width */ 107 #define RT2560_TESTCSR 0x0138 /* Test Mode Select */ 108 #define RT2560_PLCP1MCSR 0x013c /* Signal/Service/Length of ACK @1M */ 109 #define RT2560_PLCP2MCSR 0x0140 /* Signal/Service/Length of ACK @2M */ 110 #define RT2560_PLCP5p5MCSR 0x0144 /* Signal/Service/Length of ACK @5.5M */ 111 #define RT2560_PLCP11MCSR 0x0148 /* Signal/Service/Length of ACK @11M */ 112 #define RT2560_ACKPCTCSR 0x014c /* ACK/CTS padload consume time */ 113 #define RT2560_ARTCSR1 0x0150 /* ACK/CTS padload consume time */ 114 #define RT2560_ARTCSR2 0x0154 /* ACK/CTS padload consume time */ 115 #define RT2560_SECCSR1 0x0158 /* WEP control */ 116 #define RT2560_BBPCSR1 0x015c /* BBP TX Configuration */ 117 118 119 /* possible flags for register RXCSR0 */ 120 #define RT2560_DISABLE_RX (1 << 0) 121 #define RT2560_DROP_CRC_ERROR (1 << 1) 122 #define RT2560_DROP_PHY_ERROR (1 << 2) 123 #define RT2560_DROP_CTL (1 << 3) 124 #define RT2560_DROP_NOT_TO_ME (1 << 4) 125 #define RT2560_DROP_TODS (1 << 5) 126 #define RT2560_DROP_VERSION_ERROR (1 << 6) 127 128 /* possible flags for register CSR1 */ 129 #define RT2560_RESET_ASIC (1 << 0) 130 #define RT2560_RESET_BBP (1 << 1) 131 #define RT2560_HOST_READY (1 << 2) 132 133 /* possible flags for register CSR14 */ 134 #define RT2560_ENABLE_TSF (1 << 0) 135 #define RT2560_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1) 136 #define RT2560_ENABLE_TBCN (1 << 3) 137 #define RT2560_ENABLE_BEACON_GENERATOR (1 << 6) 138 139 /* possible flags for register CSR21 */ 140 #define RT2560_C (1 << 1) 141 #define RT2560_S (1 << 2) 142 #define RT2560_D (1 << 3) 143 #define RT2560_Q (1 << 4) 144 #define RT2560_93C46 (1 << 5) 145 146 #define RT2560_SHIFT_D 3 147 #define RT2560_SHIFT_Q 4 148 149 /* possible flags for register TXCSR0 */ 150 #define RT2560_KICK_TX (1 << 0) 151 #define RT2560_KICK_ATIM (1 << 1) 152 #define RT2560_KICK_PRIO (1 << 2) 153 #define RT2560_ABORT_TX (1 << 3) 154 155 /* possible flags for register SECCSR0 */ 156 #define RT2560_KICK_DECRYPT (1 << 0) 157 158 /* possible flags for register SECCSR1 */ 159 #define RT2560_KICK_ENCRYPT (1 << 0) 160 161 /* possible flags for register CSR7 */ 162 #define RT2560_BEACON_EXPIRE 0x00000001 163 #define RT2560_WAKEUP_EXPIRE 0x00000002 164 #define RT2560_ATIM_EXPIRE 0x00000004 165 #define RT2560_TX_DONE 0x00000008 166 #define RT2560_ATIM_DONE 0x00000010 167 #define RT2560_PRIO_DONE 0x00000020 168 #define RT2560_RX_DONE 0x00000040 169 #define RT2560_DECRYPTION_DONE 0x00000080 170 #define RT2560_ENCRYPTION_DONE 0x00000100 171 172 #define RT2560_INTR_MASK \ 173 (~(RT2560_BEACON_EXPIRE | RT2560_WAKEUP_EXPIRE | RT2560_TX_DONE | \ 174 RT2560_PRIO_DONE | RT2560_RX_DONE | RT2560_DECRYPTION_DONE | \ 175 RT2560_ENCRYPTION_DONE)) 176 177 /* Tx descriptor */ 178 struct rt2560_tx_desc { 179 uint32_t flags; 180 #define RT2560_TX_BUSY (1 << 0) 181 #define RT2560_TX_VALID (1 << 1) 182 183 #define RT2560_TX_RESULT_MASK 0x0000001c 184 #define RT2560_TX_SUCCESS (0 << 2) 185 #define RT2560_TX_SUCCESS_RETRY (1 << 2) 186 #define RT2560_TX_FAIL_RETRY (2 << 2) 187 #define RT2560_TX_FAIL_INVALID (3 << 2) 188 #define RT2560_TX_FAIL_OTHER (4 << 2) 189 190 #define RT2560_TX_MORE_FRAG (1 << 8) 191 #define RT2560_TX_ACK (1 << 9) 192 #define RT2560_TX_TIMESTAMP (1 << 10) 193 #define RT2560_TX_OFDM (1 << 11) 194 #define RT2560_TX_CIPHER_BUSY (1 << 12) 195 196 #define RT2560_TX_IFS_MASK 0x00006000 197 #define RT2560_TX_IFS_BACKOFF (0 << 13) 198 #define RT2560_TX_IFS_SIFS (1 << 13) 199 #define RT2560_TX_IFS_NEWBACKOFF (2 << 13) 200 #define RT2560_TX_IFS_NONE (3 << 13) 201 202 #define RT2560_TX_LONG_RETRY (1 << 15) 203 204 #define RT2560_TX_CIPHER_MASK 0xe0000000 205 #define RT2560_TX_CIPHER_NONE (0 << 29) 206 #define RT2560_TX_CIPHER_WEP40 (1 << 29) 207 #define RT2560_TX_CIPHER_WEP104 (2 << 29) 208 #define RT2560_TX_CIPHER_TKIP (3 << 29) 209 #define RT2560_TX_CIPHER_AES (4 << 29) 210 211 #define RT2560_TX_RETRYCNT(v) (((v) >> 5) & 0x7) 212 213 uint32_t physaddr; 214 uint16_t wme; 215 #define RT2560_LOGCWMAX(x) (((x) & 0xf) << 12) 216 #define RT2560_LOGCWMIN(x) (((x) & 0xf) << 8) 217 #define RT2560_AIFSN(x) (((x) & 0x3) << 6) 218 #define RT2560_IVOFFSET(x) (((x) & 0x3f)) 219 220 uint16_t reserved1; 221 uint8_t plcp_signal; 222 uint8_t plcp_service; 223 #define RT2560_PLCP_LENGEXT 0x80 224 225 uint8_t plcp_length_lo; 226 uint8_t plcp_length_hi; 227 uint32_t iv; 228 uint32_t eiv; 229 uint8_t key[IEEE80211_KEYBUF_SIZE]; 230 uint32_t reserved2[2]; 231 } __packed; 232 233 /* Rx descriptor */ 234 struct rt2560_rx_desc { 235 uint32_t flags; 236 #define RT2560_RX_BUSY (1 << 0) 237 #define RT2560_RX_CRC_ERROR (1 << 5) 238 #define RT2560_RX_OFDM (1 << 6) 239 #define RT2560_RX_PHY_ERROR (1 << 7) 240 #define RT2560_RX_CIPHER_BUSY (1 << 8) 241 #define RT2560_RX_ICV_ERROR (1 << 9) 242 243 #define RT2560_RX_CIPHER_MASK 0xe0000000 244 #define RT2560_RX_CIPHER_NONE (0 << 29) 245 #define RT2560_RX_CIPHER_WEP40 (1 << 29) 246 #define RT2560_RX_CIPHER_WEP104 (2 << 29) 247 #define RT2560_RX_CIPHER_TKIP (3 << 29) 248 #define RT2560_RX_CIPHER_AES (4 << 29) 249 250 uint32_t physaddr; 251 uint8_t rate; 252 uint8_t rssi; 253 uint8_t ta[IEEE80211_ADDR_LEN]; 254 uint32_t iv; 255 uint32_t eiv; 256 uint8_t key[IEEE80211_KEYBUF_SIZE]; 257 uint32_t reserved[2]; 258 } __packed; 259 260 #define RAL_RF1 0 261 #define RAL_RF2 2 262 #define RAL_RF3 1 263 #define RAL_RF4 3 264 265 #define RT2560_RF1_AUTOTUNE 0x08000 266 #define RT2560_RF3_AUTOTUNE 0x00040 267 268 #define RT2560_BBP_BUSY (1 << 15) 269 #define RT2560_BBP_WRITE (1 << 16) 270 #define RT2560_RF_20BIT (20 << 24) 271 #define RT2560_RF_BUSY (1 << 31) 272 273 #define RT2560_RF_2522 0x00 274 #define RT2560_RF_2523 0x01 275 #define RT2560_RF_2524 0x02 276 #define RT2560_RF_2525 0x03 277 #define RT2560_RF_2525E 0x04 278 #define RT2560_RF_2526 0x05 279 /* dual-band RF */ 280 #define RT2560_RF_5222 0x10 281 282 #define RT2560_BBP_VERSION 0 283 #define RT2560_BBP_TX 2 284 #define RT2560_BBP_RX 14 285 286 #define RT2560_BBP_ANTA 0x00 287 #define RT2560_BBP_DIVERSITY 0x01 288 #define RT2560_BBP_ANTB 0x02 289 #define RT2560_BBP_ANTMASK 0x03 290 #define RT2560_BBP_FLIPIQ 0x04 291 292 #define RT2560_LED_MODE_DEFAULT 0 293 #define RT2560_LED_MODE_TXRX_ACTIVITY 1 294 #define RT2560_LED_MODE_SINGLE 2 295 #define RT2560_LED_MODE_ASUS 3 296 297 #define RT2560_JAPAN_FILTER 0x8 298 299 #define RT2560_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 300 301 #define RT2560_EEPROM_CONFIG0 16 302 #define RT2560_EEPROM_BBP_BASE 19 303 #define RT2560_EEPROM_TXPOWER 35 304 #define RT2560_EEPROM_CALIBRATE 62 305 306 /* 307 * control and status registers access macros 308 */ 309 #define RAL_READ(sc, reg) \ 310 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 311 312 #define RAL_WRITE(sc, reg, val) \ 313 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 314 315 /* 316 * EEPROM access macro 317 */ 318 #define RT2560_EEPROM_CTL(sc, val) do { \ 319 RAL_WRITE((sc), RT2560_CSR21, (val)); \ 320 DELAY(RT2560_EEPROM_DELAY); \ 321 } while (/* CONSTCOND */0) 322 323 /* 324 * Default values for MAC registers; values taken from the reference driver. 325 */ 326 #define RT2560_DEF_MAC \ 327 { RT2560_PSCSR0, 0x00020002 }, \ 328 { RT2560_PSCSR1, 0x00000002 }, \ 329 { RT2560_PSCSR2, 0x00020002 }, \ 330 { RT2560_PSCSR3, 0x00000002 }, \ 331 { RT2560_TIMECSR, 0x00003f21 }, \ 332 { RT2560_CSR9, 0x00000780 }, \ 333 { RT2560_CSR11, 0x07041483 }, \ 334 { RT2560_CNT3, 0x00000000 }, \ 335 { RT2560_TXCSR1, 0x07614562 }, \ 336 { RT2560_ARSP_PLCP_0, 0x8c8d8b8a }, \ 337 { RT2560_ACKPCTCSR, 0x7038140a }, \ 338 { RT2560_ARTCSR1, 0x21212929 }, \ 339 { RT2560_ARTCSR2, 0x1d1d1d1d }, \ 340 { RT2560_RXCSR0, 0xffffffff }, \ 341 { RT2560_RXCSR3, 0xb3aab3af }, \ 342 { RT2560_PCICSR, 0x000003b8 }, \ 343 { RT2560_PWRCSR0, 0x3f3b3100 }, \ 344 { RT2560_GPIOCSR, 0x0000ff00 }, \ 345 { RT2560_TESTCSR, 0x000000f0 }, \ 346 { RT2560_PWRCSR1, 0x000001ff }, \ 347 { RT2560_MACCSR0, 0x00213223 }, \ 348 { RT2560_MACCSR1, 0x00235518 }, \ 349 { RT2560_RLPWCSR, 0x00000040 }, \ 350 { RT2560_RALINKCSR, 0x9a009a11 }, \ 351 { RT2560_CSR7, 0xffffffff }, \ 352 { RT2560_BBPCSR1, 0x82188200 }, \ 353 { RT2560_TXACKCSR0, 0x00000020 }, \ 354 { RT2560_SECCSR3, 0x0000e78f } 355 356 /* 357 * Default values for BBP registers; values taken from the reference driver. 358 */ 359 #define RT2560_DEF_BBP \ 360 { 3, 0x02 }, \ 361 { 4, 0x19 }, \ 362 { 14, 0x1c }, \ 363 { 15, 0x30 }, \ 364 { 16, 0xac }, \ 365 { 17, 0x48 }, \ 366 { 18, 0x18 }, \ 367 { 19, 0xff }, \ 368 { 20, 0x1e }, \ 369 { 21, 0x08 }, \ 370 { 22, 0x08 }, \ 371 { 23, 0x08 }, \ 372 { 24, 0x80 }, \ 373 { 25, 0x50 }, \ 374 { 26, 0x08 }, \ 375 { 27, 0x23 }, \ 376 { 30, 0x10 }, \ 377 { 31, 0x2b }, \ 378 { 32, 0xb9 }, \ 379 { 34, 0x12 }, \ 380 { 35, 0x50 }, \ 381 { 39, 0xc4 }, \ 382 { 40, 0x02 }, \ 383 { 41, 0x60 }, \ 384 { 53, 0x10 }, \ 385 { 54, 0x18 }, \ 386 { 56, 0x08 }, \ 387 { 57, 0x10 }, \ 388 { 58, 0x08 }, \ 389 { 61, 0x60 }, \ 390 { 62, 0x10 }, \ 391 { 75, 0xff } 392 393 /* 394 * Default values for RF register R2 indexed by channel numbers; values taken 395 * from the reference driver. 396 */ 397 #define RT2560_RF2522_R2 \ 398 { \ 399 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, \ 400 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e \ 401 } 402 403 #define RT2560_RF2523_R2 \ 404 { \ 405 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, \ 406 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 \ 407 } 408 409 #define RT2560_RF2524_R2 \ 410 { \ 411 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, \ 412 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 \ 413 } 414 415 #define RT2560_RF2525_R2 \ 416 { \ 417 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, \ 418 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 \ 419 } 420 421 #define RT2560_RF2525_HI_R2 \ 422 { \ 423 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, \ 424 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e \ 425 } 426 427 #define RT2560_RF2525E_R2 \ 428 { \ 429 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, \ 430 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b \ 431 } 432 433 #define RT2560_RF2526_HI_R2 \ 434 { \ 435 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, \ 436 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 \ 437 } 438 439 #define RT2560_RF2526_R2 \ 440 { \ 441 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, \ 442 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d \ 443 } 444 445 /* 446 * For dual-band RF, RF registers R1 and R4 also depend on channel number; 447 * values taken from the reference driver. 448 */ 449 #define RT2560_RF5222 \ 450 { 1, 0x08808, 0x0044d, 0x00282 }, \ 451 { 2, 0x08808, 0x0044e, 0x00282 }, \ 452 { 3, 0x08808, 0x0044f, 0x00282 }, \ 453 { 4, 0x08808, 0x00460, 0x00282 }, \ 454 { 5, 0x08808, 0x00461, 0x00282 }, \ 455 { 6, 0x08808, 0x00462, 0x00282 }, \ 456 { 7, 0x08808, 0x00463, 0x00282 }, \ 457 { 8, 0x08808, 0x00464, 0x00282 }, \ 458 { 9, 0x08808, 0x00465, 0x00282 }, \ 459 { 10, 0x08808, 0x00466, 0x00282 }, \ 460 { 11, 0x08808, 0x00467, 0x00282 }, \ 461 { 12, 0x08808, 0x00468, 0x00282 }, \ 462 { 13, 0x08808, 0x00469, 0x00282 }, \ 463 { 14, 0x08808, 0x0046b, 0x00286 }, \ 464 \ 465 { 36, 0x08804, 0x06225, 0x00287 }, \ 466 { 40, 0x08804, 0x06226, 0x00287 }, \ 467 { 44, 0x08804, 0x06227, 0x00287 }, \ 468 { 48, 0x08804, 0x06228, 0x00287 }, \ 469 { 52, 0x08804, 0x06229, 0x00287 }, \ 470 { 56, 0x08804, 0x0622a, 0x00287 }, \ 471 { 60, 0x08804, 0x0622b, 0x00287 }, \ 472 { 64, 0x08804, 0x0622c, 0x00287 }, \ 473 \ 474 { 100, 0x08804, 0x02200, 0x00283 }, \ 475 { 104, 0x08804, 0x02201, 0x00283 }, \ 476 { 108, 0x08804, 0x02202, 0x00283 }, \ 477 { 112, 0x08804, 0x02203, 0x00283 }, \ 478 { 116, 0x08804, 0x02204, 0x00283 }, \ 479 { 120, 0x08804, 0x02205, 0x00283 }, \ 480 { 124, 0x08804, 0x02206, 0x00283 }, \ 481 { 128, 0x08804, 0x02207, 0x00283 }, \ 482 { 132, 0x08804, 0x02208, 0x00283 }, \ 483 { 136, 0x08804, 0x02209, 0x00283 }, \ 484 { 140, 0x08804, 0x0220a, 0x00283 }, \ 485 \ 486 { 149, 0x08808, 0x02429, 0x00281 }, \ 487 { 153, 0x08808, 0x0242b, 0x00281 }, \ 488 { 157, 0x08808, 0x0242d, 0x00281 }, \ 489 { 161, 0x08808, 0x0242f, 0x00281 } 490