1 /* $FreeBSD: head/sys/dev/ral/rt2661.c 195618 2009-07-11 15:02:45Z rpaulo $ */ 2 3 /*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD: head/sys/dev/ral/rt2661.c 195618 2009-07-11 15:02:45Z rpaulo $ 20 * $DragonFly$ 21 */ 22 23 /*- 24 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28 #include <sys/param.h> 29 #include <sys/sysctl.h> 30 #include <sys/sockio.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 #include <sys/endian.h> 41 #include <sys/firmware.h> 42 #include <sys/rman.h> 43 44 #include <net/bpf.h> 45 #include <net/if.h> 46 #include <net/if_arp.h> 47 #include <net/ethernet.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 #include <net/if_types.h> 51 #include <net/ifq_var.h> 52 53 #include <netproto/802_11/ieee80211_var.h> 54 #include <netproto/802_11/ieee80211_radiotap.h> 55 #include <netproto/802_11/ieee80211_regdomain.h> 56 #include <netproto/802_11/ieee80211_ratectl.h> 57 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 #include <netinet/if_ether.h> 63 64 #include <dev/netif/ral/rt2661reg.h> 65 #include <dev/netif/ral/rt2661var.h> 66 67 #define RAL_DEBUG 68 #ifdef RAL_DEBUG 69 #define DPRINTF(sc, fmt, ...) do { \ 70 if (sc->sc_debug > 0) \ 71 kprintf(fmt, __VA_ARGS__); \ 72 } while (0) 73 #define DPRINTFN(sc, n, fmt, ...) do { \ 74 if (sc->sc_debug >= (n)) \ 75 kprintf(fmt, __VA_ARGS__); \ 76 } while (0) 77 #else 78 #define DPRINTF(sc, fmt, ...) 79 #define DPRINTFN(sc, n, fmt, ...) 80 #endif 81 82 static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *, 83 const char name[IFNAMSIZ], int unit, int opmode, 84 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 85 const uint8_t mac[IEEE80211_ADDR_LEN]); 86 static void rt2661_vap_delete(struct ieee80211vap *); 87 static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, 88 int); 89 static int rt2661_alloc_tx_ring(struct rt2661_softc *, 90 struct rt2661_tx_ring *, int); 91 static void rt2661_reset_tx_ring(struct rt2661_softc *, 92 struct rt2661_tx_ring *); 93 static void rt2661_free_tx_ring(struct rt2661_softc *, 94 struct rt2661_tx_ring *); 95 static int rt2661_alloc_rx_ring(struct rt2661_softc *, 96 struct rt2661_rx_ring *, int); 97 static void rt2661_reset_rx_ring(struct rt2661_softc *, 98 struct rt2661_rx_ring *); 99 static void rt2661_free_rx_ring(struct rt2661_softc *, 100 struct rt2661_rx_ring *); 101 static void rt2661_newassoc(struct ieee80211_node *, int); 102 static int rt2661_newstate(struct ieee80211vap *, 103 enum ieee80211_state, int); 104 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 105 static void rt2661_rx_intr(struct rt2661_softc *); 106 static void rt2661_tx_intr(struct rt2661_softc *); 107 static void rt2661_tx_dma_intr(struct rt2661_softc *, 108 struct rt2661_tx_ring *); 109 static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 110 static void rt2661_mcu_wakeup(struct rt2661_softc *); 111 static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 112 static void rt2661_scan_start(struct ieee80211com *); 113 static void rt2661_scan_end(struct ieee80211com *); 114 static void rt2661_set_channel(struct ieee80211com *); 115 static void rt2661_setup_tx_desc(struct rt2661_softc *, 116 struct rt2661_tx_desc *, uint32_t, uint16_t, int, 117 int, const bus_dma_segment_t *, int, int); 118 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 119 struct ieee80211_node *, int); 120 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 121 struct ieee80211_node *); 122 static void rt2661_start_locked(struct ifnet *); 123 static void rt2661_start(struct ifnet *); 124 static int rt2661_raw_xmit(struct ieee80211_node *, struct mbuf *, 125 const struct ieee80211_bpf_params *); 126 static void rt2661_watchdog_callout(void *); 127 static int rt2661_ioctl(struct ifnet *, u_long, caddr_t, 128 struct ucred *); 129 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, 130 uint8_t); 131 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 132 static void rt2661_rf_write(struct rt2661_softc *, uint8_t, 133 uint32_t); 134 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, 135 uint16_t); 136 static void rt2661_select_antenna(struct rt2661_softc *); 137 static void rt2661_enable_mrr(struct rt2661_softc *); 138 static void rt2661_set_txpreamble(struct rt2661_softc *); 139 static void rt2661_set_basicrates(struct rt2661_softc *, 140 const struct ieee80211_rateset *); 141 static void rt2661_select_band(struct rt2661_softc *, 142 struct ieee80211_channel *); 143 static void rt2661_set_chan(struct rt2661_softc *, 144 struct ieee80211_channel *); 145 static void rt2661_set_bssid(struct rt2661_softc *, 146 const uint8_t *); 147 static void rt2661_set_macaddr(struct rt2661_softc *, 148 const uint8_t *); 149 static void rt2661_update_promisc(struct ifnet *); 150 static int rt2661_wme_update(struct ieee80211com *) __unused; 151 static void rt2661_update_slot(struct ifnet *); 152 static const char *rt2661_get_rf(int); 153 static void rt2661_read_eeprom(struct rt2661_softc *, 154 uint8_t macaddr[IEEE80211_ADDR_LEN]); 155 static int rt2661_bbp_init(struct rt2661_softc *); 156 static void rt2661_init_locked(struct rt2661_softc *); 157 static void rt2661_init(void *); 158 static void rt2661_stop_locked(struct rt2661_softc *); 159 static void rt2661_stop(void *); 160 static int rt2661_load_microcode(struct rt2661_softc *); 161 #ifdef notyet 162 static void rt2661_rx_tune(struct rt2661_softc *); 163 static void rt2661_radar_start(struct rt2661_softc *); 164 static int rt2661_radar_stop(struct rt2661_softc *); 165 #endif 166 static int rt2661_prepare_beacon(struct rt2661_softc *, 167 struct ieee80211vap *); 168 static void rt2661_enable_tsf_sync(struct rt2661_softc *); 169 static void rt2661_enable_tsf(struct rt2661_softc *); 170 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 171 172 static const struct { 173 uint32_t reg; 174 uint32_t val; 175 } rt2661_def_mac[] = { 176 RT2661_DEF_MAC 177 }; 178 179 static const struct { 180 uint8_t reg; 181 uint8_t val; 182 } rt2661_def_bbp[] = { 183 RT2661_DEF_BBP 184 }; 185 186 static const struct rfprog { 187 uint8_t chan; 188 uint32_t r1, r2, r3, r4; 189 } rt2661_rf5225_1[] = { 190 RT2661_RF5225_1 191 }, rt2661_rf5225_2[] = { 192 RT2661_RF5225_2 193 }; 194 195 int 196 rt2661_attach(device_t dev, int id) 197 { 198 struct rt2661_softc *sc = device_get_softc(dev); 199 struct ieee80211com *ic; 200 struct ifnet *ifp; 201 uint32_t val; 202 int error, ac, ntries; 203 uint8_t bands; 204 uint8_t macaddr[IEEE80211_ADDR_LEN]; 205 struct sysctl_ctx_list *ctx; 206 struct sysctl_oid *tree; 207 208 sc->sc_id = id; 209 sc->sc_dev = dev; 210 211 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 212 if (ifp == NULL) { 213 device_printf(sc->sc_dev, "can not if_alloc()\n"); 214 return ENOMEM; 215 } 216 ic = ifp->if_l2com; 217 218 callout_init(&sc->watchdog_ch); 219 220 /* wait for NIC to initialize */ 221 for (ntries = 0; ntries < 1000; ntries++) { 222 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 223 break; 224 DELAY(1000); 225 } 226 if (ntries == 1000) { 227 device_printf(sc->sc_dev, 228 "timeout waiting for NIC to initialize\n"); 229 error = EIO; 230 goto fail1; 231 } 232 233 /* retrieve RF rev. no and various other things from EEPROM */ 234 rt2661_read_eeprom(sc, macaddr); 235 236 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val, 237 rt2661_get_rf(sc->rf_rev)); 238 239 /* 240 * Allocate Tx and Rx rings. 241 */ 242 for (ac = 0; ac < 4; ac++) { 243 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 244 RT2661_TX_RING_COUNT); 245 if (error != 0) { 246 device_printf(sc->sc_dev, 247 "could not allocate Tx ring %d\n", ac); 248 goto fail2; 249 } 250 } 251 252 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 253 if (error != 0) { 254 device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); 255 goto fail2; 256 } 257 258 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 259 if (error != 0) { 260 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 261 goto fail3; 262 } 263 264 ifp->if_softc = sc; 265 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 266 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 267 ifp->if_init = rt2661_init; 268 ifp->if_ioctl = rt2661_ioctl; 269 ifp->if_start = rt2661_start; 270 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 271 ifq_set_ready(&ifp->if_snd); 272 273 ic->ic_ifp = ifp; 274 ic->ic_opmode = IEEE80211_M_STA; 275 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 276 277 /* set device capabilities */ 278 ic->ic_caps = 279 IEEE80211_C_STA /* station mode */ 280 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 281 | IEEE80211_C_HOSTAP /* hostap mode */ 282 | IEEE80211_C_MONITOR /* monitor mode */ 283 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 284 | IEEE80211_C_WDS /* 4-address traffic works */ 285 | IEEE80211_C_MBSS /* mesh point link mode */ 286 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 287 | IEEE80211_C_SHSLOT /* short slot time supported */ 288 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 289 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 290 #ifdef notyet 291 | IEEE80211_C_TXFRAG /* handle tx frags */ 292 | IEEE80211_C_WME /* 802.11e */ 293 #endif 294 ; 295 296 bands = 0; 297 setbit(&bands, IEEE80211_MODE_11B); 298 setbit(&bands, IEEE80211_MODE_11G); 299 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) 300 setbit(&bands, IEEE80211_MODE_11A); 301 ieee80211_init_channels(ic, NULL, &bands); 302 303 ieee80211_ifattach(ic, macaddr); 304 ic->ic_newassoc = rt2661_newassoc; 305 #if 0 306 ic->ic_wme.wme_update = rt2661_wme_update; 307 #endif 308 ic->ic_scan_start = rt2661_scan_start; 309 ic->ic_scan_end = rt2661_scan_end; 310 ic->ic_set_channel = rt2661_set_channel; 311 ic->ic_updateslot = rt2661_update_slot; 312 ic->ic_update_promisc = rt2661_update_promisc; 313 ic->ic_raw_xmit = rt2661_raw_xmit; 314 315 ic->ic_vap_create = rt2661_vap_create; 316 ic->ic_vap_delete = rt2661_vap_delete; 317 318 ieee80211_radiotap_attach(ic, 319 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 320 RT2661_TX_RADIOTAP_PRESENT, 321 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 322 RT2661_RX_RADIOTAP_PRESENT); 323 324 ctx = &sc->sc_sysctl_ctx; 325 sysctl_ctx_init(ctx); 326 tree = SYSCTL_ADD_NODE(ctx, SYSCTL_STATIC_CHILDREN(_hw), 327 OID_AUTO, 328 device_get_nameunit(sc->sc_dev), 329 CTLFLAG_RD, 0, ""); 330 if (tree == NULL) { 331 device_printf(sc->sc_dev, "can't add sysctl node\n"); 332 return 0; 333 } 334 #ifdef RAL_DEBUG 335 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 336 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 337 #endif 338 if (bootverbose) 339 ieee80211_announce(ic); 340 341 return 0; 342 343 fail3: rt2661_free_tx_ring(sc, &sc->mgtq); 344 fail2: while (--ac >= 0) 345 rt2661_free_tx_ring(sc, &sc->txq[ac]); 346 fail1: 347 if_free(ifp); 348 return error; 349 } 350 351 int 352 rt2661_detach(void *xsc) 353 { 354 struct rt2661_softc *sc = xsc; 355 struct ifnet *ifp = sc->sc_ifp; 356 struct ieee80211com *ic = ifp->if_l2com; 357 358 rt2661_stop_locked(sc); 359 360 ieee80211_ifdetach(ic); 361 362 rt2661_free_tx_ring(sc, &sc->txq[0]); 363 rt2661_free_tx_ring(sc, &sc->txq[1]); 364 rt2661_free_tx_ring(sc, &sc->txq[2]); 365 rt2661_free_tx_ring(sc, &sc->txq[3]); 366 rt2661_free_tx_ring(sc, &sc->mgtq); 367 rt2661_free_rx_ring(sc, &sc->rxq); 368 369 if_free(ifp); 370 371 return 0; 372 } 373 374 static struct ieee80211vap * 375 rt2661_vap_create(struct ieee80211com *ic, 376 const char name[IFNAMSIZ], int unit, int opmode, int flags, 377 const uint8_t bssid[IEEE80211_ADDR_LEN], 378 const uint8_t mac[IEEE80211_ADDR_LEN]) 379 { 380 struct ifnet *ifp = ic->ic_ifp; 381 struct rt2661_vap *rvp; 382 struct ieee80211vap *vap; 383 384 switch (opmode) { 385 case IEEE80211_M_STA: 386 case IEEE80211_M_IBSS: 387 case IEEE80211_M_AHDEMO: 388 case IEEE80211_M_MONITOR: 389 case IEEE80211_M_HOSTAP: 390 case IEEE80211_M_MBSS: 391 /* XXXRP: TBD */ 392 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 393 if_printf(ifp, "only 1 vap supported\n"); 394 return NULL; 395 } 396 if (opmode == IEEE80211_M_STA) 397 flags |= IEEE80211_CLONE_NOBEACONS; 398 break; 399 case IEEE80211_M_WDS: 400 if (TAILQ_EMPTY(&ic->ic_vaps) || 401 ic->ic_opmode != IEEE80211_M_HOSTAP) { 402 if_printf(ifp, "wds only supported in ap mode\n"); 403 return NULL; 404 } 405 /* 406 * Silently remove any request for a unique 407 * bssid; WDS vap's always share the local 408 * mac address. 409 */ 410 flags &= ~IEEE80211_CLONE_BSSID; 411 break; 412 default: 413 if_printf(ifp, "unknown opmode %d\n", opmode); 414 return NULL; 415 } 416 rvp = (struct rt2661_vap *) kmalloc(sizeof(struct rt2661_vap), 417 M_80211_VAP, M_INTWAIT | M_ZERO); 418 if (rvp == NULL) 419 return NULL; 420 vap = &rvp->ral_vap; 421 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 422 423 /* override state transition machine */ 424 rvp->ral_newstate = vap->iv_newstate; 425 vap->iv_newstate = rt2661_newstate; 426 #if 0 427 vap->iv_update_beacon = rt2661_beacon_update; 428 #endif 429 430 ieee80211_ratectl_init(vap); 431 /* complete setup */ 432 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 433 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 434 ic->ic_opmode = opmode; 435 return vap; 436 } 437 438 static void 439 rt2661_vap_delete(struct ieee80211vap *vap) 440 { 441 struct rt2661_vap *rvp = RT2661_VAP(vap); 442 443 ieee80211_ratectl_deinit(vap); 444 ieee80211_vap_detach(vap); 445 kfree(rvp, M_80211_VAP); 446 } 447 448 void 449 rt2661_shutdown(void *xsc) 450 { 451 struct rt2661_softc *sc = xsc; 452 453 rt2661_stop(sc); 454 } 455 456 void 457 rt2661_suspend(void *xsc) 458 { 459 struct rt2661_softc *sc = xsc; 460 461 rt2661_stop(sc); 462 } 463 464 void 465 rt2661_resume(void *xsc) 466 { 467 struct rt2661_softc *sc = xsc; 468 struct ifnet *ifp = sc->sc_ifp; 469 470 if (ifp->if_flags & IFF_UP) 471 rt2661_init(sc); 472 } 473 474 static void 475 rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 476 { 477 if (error != 0) 478 return; 479 480 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 481 482 *(bus_addr_t *)arg = segs[0].ds_addr; 483 } 484 485 static int 486 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 487 int count) 488 { 489 int i, error; 490 491 ring->count = count; 492 ring->queued = 0; 493 ring->cur = ring->next = ring->stat = 0; 494 495 error = bus_dma_tag_create(ring->desc_dmat, 4, 0, 496 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 497 count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE, 498 0, &ring->desc_dmat); 499 if (error != 0) { 500 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 501 goto fail; 502 } 503 504 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 505 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 506 if (error != 0) { 507 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 508 goto fail; 509 } 510 511 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 512 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 513 0); 514 if (error != 0) { 515 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 516 goto fail; 517 } 518 519 ring->data = kmalloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 520 M_INTWAIT | M_ZERO); 521 if (ring->data == NULL) { 522 device_printf(sc->sc_dev, "could not allocate soft data\n"); 523 error = ENOMEM; 524 goto fail; 525 } 526 527 error = bus_dma_tag_create(ring->data_dmat, 1, 0, 528 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 529 RT2661_MAX_SCATTER, MCLBYTES, 0, &ring->data_dmat); 530 if (error != 0) { 531 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 532 goto fail; 533 } 534 535 for (i = 0; i < count; i++) { 536 error = bus_dmamap_create(ring->data_dmat, 0, 537 &ring->data[i].map); 538 if (error != 0) { 539 device_printf(sc->sc_dev, "could not create DMA map\n"); 540 goto fail; 541 } 542 } 543 544 return 0; 545 546 fail: rt2661_free_tx_ring(sc, ring); 547 return error; 548 } 549 550 static void 551 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 552 { 553 struct rt2661_tx_desc *desc; 554 struct rt2661_tx_data *data; 555 int i; 556 557 for (i = 0; i < ring->count; i++) { 558 desc = &ring->desc[i]; 559 data = &ring->data[i]; 560 561 if (data->m != NULL) { 562 bus_dmamap_sync(ring->data_dmat, data->map, 563 BUS_DMASYNC_POSTWRITE); 564 bus_dmamap_unload(ring->data_dmat, data->map); 565 m_freem(data->m); 566 data->m = NULL; 567 } 568 569 if (data->ni != NULL) { 570 ieee80211_free_node(data->ni); 571 data->ni = NULL; 572 } 573 574 desc->flags = 0; 575 } 576 577 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 578 579 ring->queued = 0; 580 ring->cur = ring->next = ring->stat = 0; 581 } 582 583 static void 584 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 585 { 586 struct rt2661_tx_data *data; 587 int i; 588 589 if (ring->desc != NULL) { 590 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 591 BUS_DMASYNC_POSTWRITE); 592 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 593 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 594 } 595 596 if (ring->desc_dmat != NULL) 597 bus_dma_tag_destroy(ring->desc_dmat); 598 599 if (ring->data != NULL) { 600 for (i = 0; i < ring->count; i++) { 601 data = &ring->data[i]; 602 603 if (data->m != NULL) { 604 bus_dmamap_sync(ring->data_dmat, data->map, 605 BUS_DMASYNC_POSTWRITE); 606 bus_dmamap_unload(ring->data_dmat, data->map); 607 m_freem(data->m); 608 } 609 610 if (data->ni != NULL) 611 ieee80211_free_node(data->ni); 612 613 if (data->map != NULL) 614 bus_dmamap_destroy(ring->data_dmat, data->map); 615 } 616 617 kfree(ring->data, M_DEVBUF); 618 } 619 620 if (ring->data_dmat != NULL) 621 bus_dma_tag_destroy(ring->data_dmat); 622 } 623 624 static int 625 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 626 int count) 627 { 628 struct rt2661_rx_desc *desc; 629 struct rt2661_rx_data *data; 630 bus_addr_t physaddr; 631 int i, error; 632 633 ring->count = count; 634 ring->cur = ring->next = 0; 635 636 error = bus_dma_tag_create(ring->desc_dmat, 4, 0, 637 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 638 count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE, 639 0, &ring->desc_dmat); 640 if (error != 0) { 641 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 642 goto fail; 643 } 644 645 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 646 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 647 if (error != 0) { 648 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 649 goto fail; 650 } 651 652 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 653 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 654 0); 655 if (error != 0) { 656 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 657 goto fail; 658 } 659 660 ring->data = kmalloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 661 M_INTWAIT | M_ZERO); 662 if (ring->data == NULL) { 663 device_printf(sc->sc_dev, "could not allocate soft data\n"); 664 error = ENOMEM; 665 goto fail; 666 } 667 668 /* 669 * Pre-allocate Rx buffers and populate Rx ring. 670 */ 671 error = bus_dma_tag_create(ring->data_dmat, 1, 0, 672 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 673 1, MCLBYTES, 0, &ring->data_dmat); 674 if (error != 0) { 675 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 676 goto fail; 677 } 678 679 for (i = 0; i < count; i++) { 680 desc = &sc->rxq.desc[i]; 681 data = &sc->rxq.data[i]; 682 683 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 684 if (error != 0) { 685 device_printf(sc->sc_dev, "could not create DMA map\n"); 686 goto fail; 687 } 688 689 data->m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 690 if (data->m == NULL) { 691 device_printf(sc->sc_dev, 692 "could not allocate rx mbuf\n"); 693 error = ENOMEM; 694 goto fail; 695 } 696 697 error = bus_dmamap_load(ring->data_dmat, data->map, 698 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, 699 &physaddr, 0); 700 if (error != 0) { 701 device_printf(sc->sc_dev, 702 "could not load rx buf DMA map"); 703 goto fail; 704 } 705 706 desc->flags = htole32(RT2661_RX_BUSY); 707 desc->physaddr = htole32(physaddr); 708 } 709 710 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 711 712 return 0; 713 714 fail: rt2661_free_rx_ring(sc, ring); 715 return error; 716 } 717 718 static void 719 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 720 { 721 int i; 722 723 for (i = 0; i < ring->count; i++) 724 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 725 726 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 727 728 ring->cur = ring->next = 0; 729 } 730 731 static void 732 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 733 { 734 struct rt2661_rx_data *data; 735 int i; 736 737 if (ring->desc != NULL) { 738 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 739 BUS_DMASYNC_POSTWRITE); 740 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 741 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 742 } 743 744 if (ring->desc_dmat != NULL) 745 bus_dma_tag_destroy(ring->desc_dmat); 746 747 if (ring->data != NULL) { 748 for (i = 0; i < ring->count; i++) { 749 data = &ring->data[i]; 750 751 if (data->m != NULL) { 752 bus_dmamap_sync(ring->data_dmat, data->map, 753 BUS_DMASYNC_POSTREAD); 754 bus_dmamap_unload(ring->data_dmat, data->map); 755 m_freem(data->m); 756 } 757 758 if (data->map != NULL) 759 bus_dmamap_destroy(ring->data_dmat, data->map); 760 } 761 762 kfree(ring->data, M_DEVBUF); 763 } 764 765 if (ring->data_dmat != NULL) 766 bus_dma_tag_destroy(ring->data_dmat); 767 } 768 769 static void 770 rt2661_newassoc(struct ieee80211_node *ni, int isnew) 771 { 772 ieee80211_ratectl_node_deinit(ni); 773 ieee80211_ratectl_node_init(ni); 774 } 775 776 static int 777 rt2661_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 778 { 779 struct rt2661_vap *rvp = RT2661_VAP(vap); 780 struct ieee80211com *ic = vap->iv_ic; 781 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 782 int error; 783 784 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 785 uint32_t tmp; 786 787 /* abort TSF synchronization */ 788 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 789 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 790 } 791 792 error = rvp->ral_newstate(vap, nstate, arg); 793 794 if (error == 0 && nstate == IEEE80211_S_RUN) { 795 struct ieee80211_node *ni = vap->iv_bss; 796 797 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 798 rt2661_enable_mrr(sc); 799 rt2661_set_txpreamble(sc); 800 rt2661_set_basicrates(sc, &ni->ni_rates); 801 rt2661_set_bssid(sc, ni->ni_bssid); 802 } 803 804 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 805 vap->iv_opmode == IEEE80211_M_IBSS || 806 vap->iv_opmode == IEEE80211_M_MBSS) { 807 error = rt2661_prepare_beacon(sc, vap); 808 if (error != 0) 809 return error; 810 } 811 if (vap->iv_opmode != IEEE80211_M_MONITOR) 812 rt2661_enable_tsf_sync(sc); 813 else 814 rt2661_enable_tsf(sc); 815 } 816 return error; 817 } 818 819 /* 820 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 821 * 93C66). 822 */ 823 static uint16_t 824 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 825 { 826 uint32_t tmp; 827 uint16_t val; 828 int n; 829 830 /* clock C once before the first command */ 831 RT2661_EEPROM_CTL(sc, 0); 832 833 RT2661_EEPROM_CTL(sc, RT2661_S); 834 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 835 RT2661_EEPROM_CTL(sc, RT2661_S); 836 837 /* write start bit (1) */ 838 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 839 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 840 841 /* write READ opcode (10) */ 842 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 843 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 844 RT2661_EEPROM_CTL(sc, RT2661_S); 845 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 846 847 /* write address (A5-A0 or A7-A0) */ 848 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 849 for (; n >= 0; n--) { 850 RT2661_EEPROM_CTL(sc, RT2661_S | 851 (((addr >> n) & 1) << RT2661_SHIFT_D)); 852 RT2661_EEPROM_CTL(sc, RT2661_S | 853 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 854 } 855 856 RT2661_EEPROM_CTL(sc, RT2661_S); 857 858 /* read data Q15-Q0 */ 859 val = 0; 860 for (n = 15; n >= 0; n--) { 861 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 862 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 863 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 864 RT2661_EEPROM_CTL(sc, RT2661_S); 865 } 866 867 RT2661_EEPROM_CTL(sc, 0); 868 869 /* clear Chip Select and clock C */ 870 RT2661_EEPROM_CTL(sc, RT2661_S); 871 RT2661_EEPROM_CTL(sc, 0); 872 RT2661_EEPROM_CTL(sc, RT2661_C); 873 874 return val; 875 } 876 877 static void 878 rt2661_tx_intr(struct rt2661_softc *sc) 879 { 880 struct ifnet *ifp = sc->sc_ifp; 881 struct rt2661_tx_ring *txq; 882 struct rt2661_tx_data *data; 883 uint32_t val; 884 int qid, retrycnt; 885 struct ieee80211vap *vap; 886 887 for (;;) { 888 struct ieee80211_node *ni; 889 struct mbuf *m; 890 891 val = RAL_READ(sc, RT2661_STA_CSR4); 892 if (!(val & RT2661_TX_STAT_VALID)) 893 break; 894 895 /* retrieve the queue in which this frame was sent */ 896 qid = RT2661_TX_QID(val); 897 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 898 899 /* retrieve rate control algorithm context */ 900 data = &txq->data[txq->stat]; 901 m = data->m; 902 data->m = NULL; 903 904 ni = data->ni; 905 data->ni = NULL; 906 907 /* if no frame has been sent, ignore */ 908 if (ni == NULL) 909 continue; 910 911 vap = ni->ni_vap; 912 913 switch (RT2661_TX_RESULT(val)) { 914 case RT2661_TX_SUCCESS: 915 retrycnt = RT2661_TX_RETRYCNT(val); 916 917 DPRINTFN(sc, 10, "data frame sent successfully after " 918 "%d retries\n", retrycnt); 919 if (data->rix != IEEE80211_FIXED_RATE_NONE) 920 ieee80211_ratectl_tx_complete(vap, ni, 921 IEEE80211_RATECTL_TX_SUCCESS, 922 &retrycnt, NULL); 923 ifp->if_opackets++; 924 break; 925 926 case RT2661_TX_RETRY_FAIL: 927 retrycnt = RT2661_TX_RETRYCNT(val); 928 929 DPRINTFN(sc, 9, "%s\n", 930 "sending data frame failed (too much retries)"); 931 if (data->rix != IEEE80211_FIXED_RATE_NONE) 932 ieee80211_ratectl_tx_complete(vap, ni, 933 IEEE80211_RATECTL_TX_FAILURE, 934 &retrycnt, NULL); 935 ifp->if_oerrors++; 936 break; 937 938 default: 939 /* other failure */ 940 device_printf(sc->sc_dev, 941 "sending data frame failed 0x%08x\n", val); 942 ifp->if_oerrors++; 943 } 944 945 DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat); 946 947 txq->queued--; 948 if (++txq->stat >= txq->count) /* faster than % count */ 949 txq->stat = 0; 950 951 if (m->m_flags & M_TXCB) 952 ieee80211_process_callback(ni, m, 953 RT2661_TX_RESULT(val) != RT2661_TX_SUCCESS); 954 m_freem(m); 955 ieee80211_free_node(ni); 956 } 957 958 sc->sc_tx_timer = 0; 959 ifp->if_flags &= ~IFF_OACTIVE; 960 961 rt2661_start_locked(ifp); 962 } 963 964 static void 965 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 966 { 967 struct rt2661_tx_desc *desc; 968 struct rt2661_tx_data *data; 969 970 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); 971 972 for (;;) { 973 desc = &txq->desc[txq->next]; 974 data = &txq->data[txq->next]; 975 976 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 977 !(le32toh(desc->flags) & RT2661_TX_VALID)) 978 break; 979 980 bus_dmamap_sync(txq->data_dmat, data->map, 981 BUS_DMASYNC_POSTWRITE); 982 bus_dmamap_unload(txq->data_dmat, data->map); 983 984 /* descriptor is no longer valid */ 985 desc->flags &= ~htole32(RT2661_TX_VALID); 986 987 DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next); 988 989 if (++txq->next >= txq->count) /* faster than % count */ 990 txq->next = 0; 991 } 992 993 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 994 } 995 996 static void 997 rt2661_rx_intr(struct rt2661_softc *sc) 998 { 999 struct ifnet *ifp = sc->sc_ifp; 1000 struct ieee80211com *ic = ifp->if_l2com; 1001 struct rt2661_rx_desc *desc; 1002 struct rt2661_rx_data *data; 1003 bus_addr_t physaddr; 1004 struct ieee80211_frame *wh; 1005 struct ieee80211_node *ni; 1006 struct mbuf *mnew, *m; 1007 int error; 1008 1009 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1010 BUS_DMASYNC_POSTREAD); 1011 1012 for (;;) { 1013 int8_t rssi, nf; 1014 1015 desc = &sc->rxq.desc[sc->rxq.cur]; 1016 data = &sc->rxq.data[sc->rxq.cur]; 1017 1018 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1019 break; 1020 1021 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1022 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1023 /* 1024 * This should not happen since we did not request 1025 * to receive those frames when we filled TXRX_CSR0. 1026 */ 1027 DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n", 1028 le32toh(desc->flags)); 1029 ifp->if_ierrors++; 1030 goto skip; 1031 } 1032 1033 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1034 ifp->if_ierrors++; 1035 goto skip; 1036 } 1037 1038 /* 1039 * Try to allocate a new mbuf for this ring element and load it 1040 * before processing the current mbuf. If the ring element 1041 * cannot be loaded, drop the received packet and reuse the old 1042 * mbuf. In the unlikely case that the old mbuf can't be 1043 * reloaded either, explicitly panic. 1044 */ 1045 mnew = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1046 if (mnew == NULL) { 1047 ifp->if_ierrors++; 1048 goto skip; 1049 } 1050 1051 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1052 BUS_DMASYNC_POSTREAD); 1053 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1054 1055 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1056 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, 1057 &physaddr, 0); 1058 if (error != 0) { 1059 m_freem(mnew); 1060 1061 /* try to reload the old mbuf */ 1062 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1063 mtod(data->m, void *), MCLBYTES, 1064 rt2661_dma_map_addr, &physaddr, 0); 1065 if (error != 0) { 1066 /* very unlikely that it will fail... */ 1067 panic("%s: could not load old rx mbuf", 1068 device_get_name(sc->sc_dev)); 1069 } 1070 ifp->if_ierrors++; 1071 goto skip; 1072 } 1073 1074 /* 1075 * New mbuf successfully loaded, update Rx ring and continue 1076 * processing. 1077 */ 1078 m = data->m; 1079 data->m = mnew; 1080 desc->physaddr = htole32(physaddr); 1081 1082 /* finalize mbuf */ 1083 m->m_pkthdr.rcvif = ifp; 1084 m->m_pkthdr.len = m->m_len = 1085 (le32toh(desc->flags) >> 16) & 0xfff; 1086 1087 rssi = rt2661_get_rssi(sc, desc->rssi); 1088 /* Error happened during RSSI conversion. */ 1089 if (rssi < 0) 1090 rssi = -30; /* XXX ignored by net80211 */ 1091 nf = RT2661_NOISE_FLOOR; 1092 1093 if (ieee80211_radiotap_active(ic)) { 1094 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1095 uint32_t tsf_lo, tsf_hi; 1096 1097 /* get timestamp (low and high 32 bits) */ 1098 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1099 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1100 1101 tap->wr_tsf = 1102 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1103 tap->wr_flags = 0; 1104 tap->wr_rate = ieee80211_plcp2rate(desc->rate, 1105 (desc->flags & htole32(RT2661_RX_OFDM)) ? 1106 IEEE80211_T_OFDM : IEEE80211_T_CCK); 1107 tap->wr_antsignal = nf + rssi; 1108 tap->wr_antnoise = nf; 1109 } 1110 sc->sc_flags |= RAL_INPUT_RUNNING; 1111 wh = mtod(m, struct ieee80211_frame *); 1112 1113 /* send the frame to the 802.11 layer */ 1114 ni = ieee80211_find_rxnode(ic, 1115 (struct ieee80211_frame_min *)wh); 1116 if (ni != NULL) { 1117 (void) ieee80211_input(ni, m, rssi, nf); 1118 ieee80211_free_node(ni); 1119 } else 1120 (void) ieee80211_input_all(ic, m, rssi, nf); 1121 1122 sc->sc_flags &= ~RAL_INPUT_RUNNING; 1123 1124 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1125 1126 DPRINTFN(sc, 15, "rx intr idx=%u\n", sc->rxq.cur); 1127 1128 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1129 } 1130 1131 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1132 BUS_DMASYNC_PREWRITE); 1133 } 1134 1135 /* ARGSUSED */ 1136 static void 1137 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1138 { 1139 /* do nothing */ 1140 } 1141 1142 static void 1143 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1144 { 1145 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1146 1147 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1148 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1149 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1150 1151 /* send wakeup command to MCU */ 1152 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1153 } 1154 1155 static void 1156 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1157 { 1158 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1159 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1160 } 1161 1162 void 1163 rt2661_intr(void *arg) 1164 { 1165 struct rt2661_softc *sc = arg; 1166 struct ifnet *ifp = sc->sc_ifp; 1167 uint32_t r1, r2; 1168 1169 /* disable MAC and MCU interrupts */ 1170 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1171 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1172 1173 /* don't re-enable interrupts if we're shutting down */ 1174 if (!(ifp->if_flags & IFF_RUNNING)) { 1175 return; 1176 } 1177 1178 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1179 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1180 1181 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1182 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1183 1184 if (r1 & RT2661_MGT_DONE) 1185 rt2661_tx_dma_intr(sc, &sc->mgtq); 1186 1187 if (r1 & RT2661_RX_DONE) 1188 rt2661_rx_intr(sc); 1189 1190 if (r1 & RT2661_TX0_DMA_DONE) 1191 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1192 1193 if (r1 & RT2661_TX1_DMA_DONE) 1194 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1195 1196 if (r1 & RT2661_TX2_DMA_DONE) 1197 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1198 1199 if (r1 & RT2661_TX3_DMA_DONE) 1200 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1201 1202 if (r1 & RT2661_TX_DONE) 1203 rt2661_tx_intr(sc); 1204 1205 if (r2 & RT2661_MCU_CMD_DONE) 1206 rt2661_mcu_cmd_intr(sc); 1207 1208 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1209 rt2661_mcu_beacon_expire(sc); 1210 1211 if (r2 & RT2661_MCU_WAKEUP) 1212 rt2661_mcu_wakeup(sc); 1213 1214 /* re-enable MAC and MCU interrupts */ 1215 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1216 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1217 1218 } 1219 1220 static uint8_t 1221 rt2661_plcp_signal(int rate) 1222 { 1223 switch (rate) { 1224 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1225 case 12: return 0xb; 1226 case 18: return 0xf; 1227 case 24: return 0xa; 1228 case 36: return 0xe; 1229 case 48: return 0x9; 1230 case 72: return 0xd; 1231 case 96: return 0x8; 1232 case 108: return 0xc; 1233 1234 /* CCK rates (NB: not IEEE std, device-specific) */ 1235 case 2: return 0x0; 1236 case 4: return 0x1; 1237 case 11: return 0x2; 1238 case 22: return 0x3; 1239 } 1240 return 0xff; /* XXX unsupported/unknown rate */ 1241 } 1242 1243 static void 1244 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1245 uint32_t flags, uint16_t xflags, int len, int rate, 1246 const bus_dma_segment_t *segs, int nsegs, int ac) 1247 { 1248 struct ifnet *ifp = sc->sc_ifp; 1249 struct ieee80211com *ic = ifp->if_l2com; 1250 uint16_t plcp_length; 1251 int i, remainder; 1252 1253 desc->flags = htole32(flags); 1254 desc->flags |= htole32(len << 16); 1255 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1256 1257 desc->xflags = htole16(xflags); 1258 desc->xflags |= htole16(nsegs << 13); 1259 1260 desc->wme = htole16( 1261 RT2661_QID(ac) | 1262 RT2661_AIFSN(2) | 1263 RT2661_LOGCWMIN(4) | 1264 RT2661_LOGCWMAX(10)); 1265 1266 /* 1267 * Remember in which queue this frame was sent. This field is driver 1268 * private data only. It will be made available by the NIC in STA_CSR4 1269 * on Tx interrupts. 1270 */ 1271 desc->qid = ac; 1272 1273 /* setup PLCP fields */ 1274 desc->plcp_signal = rt2661_plcp_signal(rate); 1275 desc->plcp_service = 4; 1276 1277 len += IEEE80211_CRC_LEN; 1278 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 1279 desc->flags |= htole32(RT2661_TX_OFDM); 1280 1281 plcp_length = len & 0xfff; 1282 desc->plcp_length_hi = plcp_length >> 6; 1283 desc->plcp_length_lo = plcp_length & 0x3f; 1284 } else { 1285 plcp_length = (16 * len + rate - 1) / rate; 1286 if (rate == 22) { 1287 remainder = (16 * len) % 22; 1288 if (remainder != 0 && remainder < 7) 1289 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1290 } 1291 desc->plcp_length_hi = plcp_length >> 8; 1292 desc->plcp_length_lo = plcp_length & 0xff; 1293 1294 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1295 desc->plcp_signal |= 0x08; 1296 } 1297 1298 /* RT2x61 supports scatter with up to 5 segments */ 1299 for (i = 0; i < nsegs; i++) { 1300 desc->addr[i] = htole32(segs[i].ds_addr); 1301 desc->len [i] = htole16(segs[i].ds_len); 1302 } 1303 } 1304 1305 static int 1306 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1307 struct ieee80211_node *ni) 1308 { 1309 struct ieee80211vap *vap = ni->ni_vap; 1310 struct ieee80211com *ic = ni->ni_ic; 1311 struct rt2661_tx_desc *desc; 1312 struct rt2661_tx_data *data; 1313 struct ieee80211_frame *wh; 1314 struct ieee80211_key *k; 1315 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1316 uint16_t dur; 1317 uint32_t flags = 0; /* XXX HWSEQ */ 1318 int nsegs, rate, error; 1319 1320 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1321 data = &sc->mgtq.data[sc->mgtq.cur]; 1322 1323 rate = vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)].mgmtrate; 1324 1325 wh = mtod(m0, struct ieee80211_frame *); 1326 1327 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1328 k = ieee80211_crypto_encap(ni, m0); 1329 if (k == NULL) { 1330 m_freem(m0); 1331 return ENOBUFS; 1332 } 1333 } 1334 1335 error = bus_dmamap_load_mbuf_segment(sc->mgtq.data_dmat, data->map, m0, 1336 segs, 1, &nsegs, BUS_DMA_NOWAIT); 1337 if (error != 0) { 1338 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1339 error); 1340 m_freem(m0); 1341 return error; 1342 } 1343 1344 if (ieee80211_radiotap_active_vap(vap)) { 1345 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1346 1347 tap->wt_flags = 0; 1348 tap->wt_rate = rate; 1349 1350 ieee80211_radiotap_tx(vap, m0); 1351 } 1352 1353 data->m = m0; 1354 data->ni = ni; 1355 /* management frames are not taken into account for amrr */ 1356 data->rix = IEEE80211_FIXED_RATE_NONE; 1357 1358 wh = mtod(m0, struct ieee80211_frame *); 1359 1360 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1361 flags |= RT2661_TX_NEED_ACK; 1362 1363 dur = ieee80211_ack_duration(ic->ic_rt, 1364 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1365 *(uint16_t *)wh->i_dur = htole16(dur); 1366 1367 /* tell hardware to add timestamp in probe responses */ 1368 if ((wh->i_fc[0] & 1369 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1370 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1371 flags |= RT2661_TX_TIMESTAMP; 1372 } 1373 1374 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1375 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT); 1376 1377 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1378 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, 1379 BUS_DMASYNC_PREWRITE); 1380 1381 DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n", 1382 m0->m_pkthdr.len, sc->mgtq.cur, rate); 1383 1384 /* kick mgt */ 1385 sc->mgtq.queued++; 1386 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1387 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1388 1389 return 0; 1390 } 1391 1392 static int 1393 rt2661_sendprot(struct rt2661_softc *sc, int ac, 1394 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1395 { 1396 struct ieee80211com *ic = ni->ni_ic; 1397 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1398 const struct ieee80211_frame *wh; 1399 struct rt2661_tx_desc *desc; 1400 struct rt2661_tx_data *data; 1401 struct mbuf *mprot; 1402 int protrate, ackrate, pktlen, flags, isshort, error; 1403 uint16_t dur; 1404 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1405 int nsegs; 1406 1407 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1408 ("protection %d", prot)); 1409 1410 wh = mtod(m, const struct ieee80211_frame *); 1411 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1412 1413 protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1414 ackrate = ieee80211_ack_rate(ic->ic_rt, rate); 1415 1416 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1417 dur = ieee80211_compute_duration(ic->ic_rt, pktlen, rate, isshort) 1418 + ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1419 flags = RT2661_TX_MORE_FRAG; 1420 if (prot == IEEE80211_PROT_RTSCTS) { 1421 /* NB: CTS is the same size as an ACK */ 1422 dur += ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1423 flags |= RT2661_TX_NEED_ACK; 1424 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1425 } else { 1426 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1427 } 1428 if (mprot == NULL) { 1429 /* XXX stat + msg */ 1430 return ENOBUFS; 1431 } 1432 1433 data = &txq->data[txq->cur]; 1434 desc = &txq->desc[txq->cur]; 1435 1436 error = bus_dmamap_load_mbuf_segment(txq->data_dmat, data->map, mprot, segs, 1437 1, &nsegs, BUS_DMA_NOWAIT); 1438 if (error != 0) { 1439 device_printf(sc->sc_dev, 1440 "could not map mbuf (error %d)\n", error); 1441 m_freem(mprot); 1442 return error; 1443 } 1444 1445 data->m = mprot; 1446 data->ni = ieee80211_ref_node(ni); 1447 /* ctl frames are not taken into account for amrr */ 1448 data->rix = IEEE80211_FIXED_RATE_NONE; 1449 1450 rt2661_setup_tx_desc(sc, desc, flags, 0, mprot->m_pkthdr.len, 1451 protrate, segs, 1, ac); 1452 1453 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1454 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1455 1456 txq->queued++; 1457 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1458 1459 return 0; 1460 } 1461 1462 static int 1463 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1464 struct ieee80211_node *ni, int ac) 1465 { 1466 struct ieee80211vap *vap = ni->ni_vap; 1467 struct ifnet *ifp = sc->sc_ifp; 1468 struct ieee80211com *ic = ifp->if_l2com; 1469 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1470 struct rt2661_tx_desc *desc; 1471 struct rt2661_tx_data *data; 1472 struct ieee80211_frame *wh; 1473 const struct ieee80211_txparam *tp; 1474 struct ieee80211_key *k; 1475 const struct chanAccParams *cap; 1476 struct mbuf *mnew; 1477 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1478 uint16_t dur; 1479 uint32_t flags; 1480 int error, nsegs, rate, noack = 0; 1481 1482 wh = mtod(m0, struct ieee80211_frame *); 1483 1484 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1485 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1486 rate = tp->mcastrate; 1487 } else if (m0->m_flags & M_EAPOL) { 1488 rate = tp->mgmtrate; 1489 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1490 rate = tp->ucastrate; 1491 } else { 1492 ieee80211_ratectl_rate(ni, NULL, 0); 1493 rate = ni->ni_txrate; 1494 } 1495 rate &= IEEE80211_RATE_VAL; 1496 1497 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 1498 cap = &ic->ic_wme.wme_chanParams; 1499 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 1500 } 1501 1502 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1503 k = ieee80211_crypto_encap(ni, m0); 1504 if (k == NULL) { 1505 m_freem(m0); 1506 return ENOBUFS; 1507 } 1508 1509 /* packet header may have moved, reset our local pointer */ 1510 wh = mtod(m0, struct ieee80211_frame *); 1511 } 1512 1513 flags = 0; 1514 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1515 int prot = IEEE80211_PROT_NONE; 1516 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1517 prot = IEEE80211_PROT_RTSCTS; 1518 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1519 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1520 prot = ic->ic_protmode; 1521 if (prot != IEEE80211_PROT_NONE) { 1522 error = rt2661_sendprot(sc, ac, m0, ni, prot, rate); 1523 if (error) { 1524 m_freem(m0); 1525 return error; 1526 } 1527 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1528 } 1529 } 1530 1531 data = &txq->data[txq->cur]; 1532 desc = &txq->desc[txq->cur]; 1533 1534 error = bus_dmamap_load_mbuf_segment(txq->data_dmat, data->map, m0, segs, 1535 1, &nsegs, BUS_DMA_NOWAIT); 1536 if (error != 0 && error != EFBIG) { 1537 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1538 error); 1539 m_freem(m0); 1540 return error; 1541 } 1542 if (error != 0) { 1543 mnew = m_defrag(m0, MB_DONTWAIT); 1544 if (mnew == NULL) { 1545 device_printf(sc->sc_dev, 1546 "could not defragment mbuf\n"); 1547 m_freem(m0); 1548 return ENOBUFS; 1549 } 1550 m0 = mnew; 1551 1552 error = bus_dmamap_load_mbuf_segment(txq->data_dmat, data->map, m0, 1553 segs, 1, &nsegs, BUS_DMA_NOWAIT); 1554 if (error != 0) { 1555 device_printf(sc->sc_dev, 1556 "could not map mbuf (error %d)\n", error); 1557 m_freem(m0); 1558 return error; 1559 } 1560 1561 /* packet header have moved, reset our local pointer */ 1562 wh = mtod(m0, struct ieee80211_frame *); 1563 } 1564 1565 if (ieee80211_radiotap_active_vap(vap)) { 1566 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1567 1568 tap->wt_flags = 0; 1569 tap->wt_rate = rate; 1570 1571 ieee80211_radiotap_tx(vap, m0); 1572 } 1573 1574 data->m = m0; 1575 data->ni = ni; 1576 1577 /* remember link conditions for rate adaptation algorithm */ 1578 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) { 1579 data->rix = ni->ni_txrate; 1580 /* XXX probably need last rssi value and not avg */ 1581 data->rssi = ic->ic_node_getrssi(ni); 1582 } else 1583 data->rix = IEEE80211_FIXED_RATE_NONE; 1584 1585 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1586 flags |= RT2661_TX_NEED_ACK; 1587 1588 dur = ieee80211_ack_duration(ic->ic_rt, 1589 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1590 *(uint16_t *)wh->i_dur = htole16(dur); 1591 } 1592 1593 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs, 1594 nsegs, ac); 1595 1596 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1597 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1598 1599 DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n", 1600 m0->m_pkthdr.len, txq->cur, rate); 1601 1602 /* kick Tx */ 1603 txq->queued++; 1604 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1605 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); 1606 1607 return 0; 1608 } 1609 1610 static void 1611 rt2661_start_locked(struct ifnet *ifp) 1612 { 1613 struct rt2661_softc *sc = ifp->if_softc; 1614 struct mbuf *m; 1615 struct ieee80211_node *ni; 1616 int ac; 1617 1618 /* prevent management frames from being sent if we're not ready */ 1619 if (!(ifp->if_flags & IFF_RUNNING) || sc->sc_invalid) 1620 return; 1621 1622 for (;;) { 1623 IF_DEQUEUE(&ifp->if_snd, m); 1624 if (m == NULL) 1625 break; 1626 1627 ac = M_WME_GETAC(m); 1628 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { 1629 /* there is no place left in this ring */ 1630 IF_PREPEND(&ifp->if_snd, m); 1631 ifp->if_flags |= IFF_OACTIVE; 1632 break; 1633 } 1634 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1635 if (rt2661_tx_data(sc, m, ni, ac) != 0) { 1636 ieee80211_free_node(ni); 1637 ifp->if_oerrors++; 1638 break; 1639 } 1640 1641 sc->sc_tx_timer = 5; 1642 } 1643 } 1644 1645 static void 1646 rt2661_start(struct ifnet *ifp) 1647 { 1648 rt2661_start_locked(ifp); 1649 } 1650 1651 static int 1652 rt2661_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1653 const struct ieee80211_bpf_params *params) 1654 { 1655 struct ieee80211com *ic = ni->ni_ic; 1656 struct ifnet *ifp = ic->ic_ifp; 1657 struct rt2661_softc *sc = ifp->if_softc; 1658 1659 /* prevent management frames from being sent if we're not ready */ 1660 if (!(ifp->if_flags & IFF_RUNNING)) { 1661 m_freem(m); 1662 ieee80211_free_node(ni); 1663 return ENETDOWN; 1664 } 1665 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1666 ifp->if_flags |= IFF_OACTIVE; 1667 m_freem(m); 1668 ieee80211_free_node(ni); 1669 return ENOBUFS; /* XXX */ 1670 } 1671 1672 ifp->if_opackets++; 1673 1674 /* 1675 * Legacy path; interpret frame contents to decide 1676 * precisely how to send the frame. 1677 * XXX raw path 1678 */ 1679 if (rt2661_tx_mgt(sc, m, ni) != 0) 1680 goto bad; 1681 sc->sc_tx_timer = 5; 1682 1683 return 0; 1684 bad: 1685 ifp->if_oerrors++; 1686 ieee80211_free_node(ni); 1687 return EIO; /* XXX */ 1688 } 1689 1690 static void 1691 rt2661_watchdog_callout(void *arg) 1692 { 1693 struct rt2661_softc *sc = (struct rt2661_softc *)arg; 1694 struct ifnet *ifp = sc->sc_ifp; 1695 1696 KASSERT(ifp->if_flags & IFF_RUNNING, ("not running")); 1697 1698 if (sc->sc_invalid) /* card ejected */ 1699 return; 1700 1701 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1702 if_printf(ifp, "device timeout\n"); 1703 rt2661_init_locked(sc); 1704 ifp->if_oerrors++; 1705 /* NB: callout is reset in rt2661_init() */ 1706 return; 1707 } 1708 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog_callout, sc); 1709 1710 } 1711 1712 static int 1713 rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *ucred) 1714 { 1715 struct rt2661_softc *sc = ifp->if_softc; 1716 struct ieee80211com *ic = ifp->if_l2com; 1717 struct ifreq *ifr = (struct ifreq *) data; 1718 int error = 0, startall = 0; 1719 1720 switch (cmd) { 1721 case SIOCSIFFLAGS: 1722 if (ifp->if_flags & IFF_UP) { 1723 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1724 rt2661_init_locked(sc); 1725 startall = 1; 1726 } else 1727 rt2661_update_promisc(ifp); 1728 } else { 1729 if (ifp->if_flags & IFF_RUNNING) 1730 rt2661_stop_locked(sc); 1731 } 1732 if (startall) 1733 ieee80211_start_all(ic); 1734 break; 1735 case SIOCGIFMEDIA: 1736 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1737 break; 1738 case SIOCGIFADDR: 1739 error = ether_ioctl(ifp, cmd, data); 1740 break; 1741 default: 1742 error = EINVAL; 1743 break; 1744 } 1745 return error; 1746 } 1747 1748 static void 1749 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1750 { 1751 uint32_t tmp; 1752 int ntries; 1753 1754 for (ntries = 0; ntries < 100; ntries++) { 1755 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1756 break; 1757 DELAY(1); 1758 } 1759 if (ntries == 100) { 1760 device_printf(sc->sc_dev, "could not write to BBP\n"); 1761 return; 1762 } 1763 1764 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1765 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1766 1767 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val); 1768 } 1769 1770 static uint8_t 1771 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 1772 { 1773 uint32_t val; 1774 int ntries; 1775 1776 for (ntries = 0; ntries < 100; ntries++) { 1777 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1778 break; 1779 DELAY(1); 1780 } 1781 if (ntries == 100) { 1782 device_printf(sc->sc_dev, "could not read from BBP\n"); 1783 return 0; 1784 } 1785 1786 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 1787 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 1788 1789 for (ntries = 0; ntries < 100; ntries++) { 1790 val = RAL_READ(sc, RT2661_PHY_CSR3); 1791 if (!(val & RT2661_BBP_BUSY)) 1792 return val & 0xff; 1793 DELAY(1); 1794 } 1795 1796 device_printf(sc->sc_dev, "could not read from BBP\n"); 1797 return 0; 1798 } 1799 1800 static void 1801 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 1802 { 1803 uint32_t tmp; 1804 int ntries; 1805 1806 for (ntries = 0; ntries < 100; ntries++) { 1807 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 1808 break; 1809 DELAY(1); 1810 } 1811 if (ntries == 100) { 1812 device_printf(sc->sc_dev, "could not write to RF\n"); 1813 return; 1814 } 1815 1816 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 1817 (reg & 3); 1818 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 1819 1820 /* remember last written value in sc */ 1821 sc->rf_regs[reg] = val; 1822 1823 DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff); 1824 } 1825 1826 static int 1827 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 1828 { 1829 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 1830 return EIO; /* there is already a command pending */ 1831 1832 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 1833 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 1834 1835 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 1836 1837 return 0; 1838 } 1839 1840 static void 1841 rt2661_select_antenna(struct rt2661_softc *sc) 1842 { 1843 uint8_t bbp4, bbp77; 1844 uint32_t tmp; 1845 1846 bbp4 = rt2661_bbp_read(sc, 4); 1847 bbp77 = rt2661_bbp_read(sc, 77); 1848 1849 /* TBD */ 1850 1851 /* make sure Rx is disabled before switching antenna */ 1852 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 1853 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 1854 1855 rt2661_bbp_write(sc, 4, bbp4); 1856 rt2661_bbp_write(sc, 77, bbp77); 1857 1858 /* restore Rx filter */ 1859 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 1860 } 1861 1862 /* 1863 * Enable multi-rate retries for frames sent at OFDM rates. 1864 * In 802.11b/g mode, allow fallback to CCK rates. 1865 */ 1866 static void 1867 rt2661_enable_mrr(struct rt2661_softc *sc) 1868 { 1869 struct ifnet *ifp = sc->sc_ifp; 1870 struct ieee80211com *ic = ifp->if_l2com; 1871 uint32_t tmp; 1872 1873 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1874 1875 tmp &= ~RT2661_MRR_CCK_FALLBACK; 1876 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan)) 1877 tmp |= RT2661_MRR_CCK_FALLBACK; 1878 tmp |= RT2661_MRR_ENABLED; 1879 1880 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1881 } 1882 1883 static void 1884 rt2661_set_txpreamble(struct rt2661_softc *sc) 1885 { 1886 struct ifnet *ifp = sc->sc_ifp; 1887 struct ieee80211com *ic = ifp->if_l2com; 1888 uint32_t tmp; 1889 1890 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1891 1892 tmp &= ~RT2661_SHORT_PREAMBLE; 1893 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1894 tmp |= RT2661_SHORT_PREAMBLE; 1895 1896 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1897 } 1898 1899 static void 1900 rt2661_set_basicrates(struct rt2661_softc *sc, 1901 const struct ieee80211_rateset *rs) 1902 { 1903 #define RV(r) ((r) & IEEE80211_RATE_VAL) 1904 struct ifnet *ifp = sc->sc_ifp; 1905 struct ieee80211com *ic = ifp->if_l2com; 1906 uint32_t mask = 0; 1907 uint8_t rate; 1908 int i, j; 1909 1910 for (i = 0; i < rs->rs_nrates; i++) { 1911 rate = rs->rs_rates[i]; 1912 1913 if (!(rate & IEEE80211_RATE_BASIC)) 1914 continue; 1915 1916 /* 1917 * Find h/w rate index. We know it exists because the rate 1918 * set has already been negotiated. 1919 */ 1920 for (j = 0; ic->ic_sup_rates[IEEE80211_MODE_11G].rs_rates[j] != RV(rate); j++); 1921 1922 mask |= 1 << j; 1923 } 1924 1925 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 1926 1927 DPRINTF(sc, "Setting basic rate mask to 0x%x\n", mask); 1928 #undef RV 1929 } 1930 1931 /* 1932 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 1933 * driver. 1934 */ 1935 static void 1936 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 1937 { 1938 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 1939 uint32_t tmp; 1940 1941 /* update all BBP registers that depend on the band */ 1942 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 1943 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 1944 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1945 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 1946 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 1947 } 1948 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1949 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1950 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 1951 } 1952 1953 rt2661_bbp_write(sc, 17, bbp17); 1954 rt2661_bbp_write(sc, 96, bbp96); 1955 rt2661_bbp_write(sc, 104, bbp104); 1956 1957 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1958 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1959 rt2661_bbp_write(sc, 75, 0x80); 1960 rt2661_bbp_write(sc, 86, 0x80); 1961 rt2661_bbp_write(sc, 88, 0x80); 1962 } 1963 1964 rt2661_bbp_write(sc, 35, bbp35); 1965 rt2661_bbp_write(sc, 97, bbp97); 1966 rt2661_bbp_write(sc, 98, bbp98); 1967 1968 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 1969 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 1970 if (IEEE80211_IS_CHAN_2GHZ(c)) 1971 tmp |= RT2661_PA_PE_2GHZ; 1972 else 1973 tmp |= RT2661_PA_PE_5GHZ; 1974 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 1975 } 1976 1977 static void 1978 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 1979 { 1980 struct ifnet *ifp = sc->sc_ifp; 1981 struct ieee80211com *ic = ifp->if_l2com; 1982 const struct rfprog *rfprog; 1983 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 1984 int8_t power; 1985 u_int i, chan; 1986 1987 chan = ieee80211_chan2ieee(ic, c); 1988 KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan)); 1989 1990 /* select the appropriate RF settings based on what EEPROM says */ 1991 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 1992 1993 /* find the settings for this channel (we know it exists) */ 1994 for (i = 0; rfprog[i].chan != chan; i++); 1995 1996 power = sc->txpow[i]; 1997 if (power < 0) { 1998 bbp94 += power; 1999 power = 0; 2000 } else if (power > 31) { 2001 bbp94 += power - 31; 2002 power = 31; 2003 } 2004 2005 /* 2006 * If we are switching from the 2GHz band to the 5GHz band or 2007 * vice-versa, BBP registers need to be reprogrammed. 2008 */ 2009 if (c->ic_flags != sc->sc_curchan->ic_flags) { 2010 rt2661_select_band(sc, c); 2011 rt2661_select_antenna(sc); 2012 } 2013 sc->sc_curchan = c; 2014 2015 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2016 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2017 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2018 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2019 2020 DELAY(200); 2021 2022 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2023 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2024 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2025 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2026 2027 DELAY(200); 2028 2029 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2030 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2031 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2032 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2033 2034 /* enable smart mode for MIMO-capable RFs */ 2035 bbp3 = rt2661_bbp_read(sc, 3); 2036 2037 bbp3 &= ~RT2661_SMART_MODE; 2038 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2039 bbp3 |= RT2661_SMART_MODE; 2040 2041 rt2661_bbp_write(sc, 3, bbp3); 2042 2043 if (bbp94 != RT2661_BBPR94_DEFAULT) 2044 rt2661_bbp_write(sc, 94, bbp94); 2045 2046 /* 5GHz radio needs a 1ms delay here */ 2047 if (IEEE80211_IS_CHAN_5GHZ(c)) 2048 DELAY(1000); 2049 } 2050 2051 static void 2052 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2053 { 2054 uint32_t tmp; 2055 2056 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2057 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2058 2059 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2060 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2061 } 2062 2063 static void 2064 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2065 { 2066 uint32_t tmp; 2067 2068 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2069 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2070 2071 tmp = addr[4] | addr[5] << 8; 2072 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2073 } 2074 2075 static void 2076 rt2661_update_promisc(struct ifnet *ifp) 2077 { 2078 struct rt2661_softc *sc = ifp->if_softc; 2079 uint32_t tmp; 2080 2081 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2082 2083 tmp &= ~RT2661_DROP_NOT_TO_ME; 2084 if (!(ifp->if_flags & IFF_PROMISC)) 2085 tmp |= RT2661_DROP_NOT_TO_ME; 2086 2087 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2088 2089 DPRINTF(sc, "%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2090 "entering" : "leaving"); 2091 } 2092 2093 /* 2094 * Update QoS (802.11e) settings for each h/w Tx ring. 2095 */ 2096 static int 2097 rt2661_wme_update(struct ieee80211com *ic) 2098 { 2099 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2100 const struct wmeParams *wmep; 2101 2102 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2103 2104 /* XXX: not sure about shifts. */ 2105 /* XXX: the reference driver plays with AC_VI settings too. */ 2106 2107 /* update TxOp */ 2108 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2109 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2110 wmep[WME_AC_BK].wmep_txopLimit); 2111 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2112 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2113 wmep[WME_AC_VO].wmep_txopLimit); 2114 2115 /* update CWmin */ 2116 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2117 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2118 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2119 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2120 wmep[WME_AC_VO].wmep_logcwmin); 2121 2122 /* update CWmax */ 2123 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2124 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2125 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2126 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2127 wmep[WME_AC_VO].wmep_logcwmax); 2128 2129 /* update Aifsn */ 2130 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2131 wmep[WME_AC_BE].wmep_aifsn << 12 | 2132 wmep[WME_AC_BK].wmep_aifsn << 8 | 2133 wmep[WME_AC_VI].wmep_aifsn << 4 | 2134 wmep[WME_AC_VO].wmep_aifsn); 2135 2136 return 0; 2137 } 2138 2139 static void 2140 rt2661_update_slot(struct ifnet *ifp) 2141 { 2142 struct rt2661_softc *sc = ifp->if_softc; 2143 struct ieee80211com *ic = ifp->if_l2com; 2144 uint8_t slottime; 2145 uint32_t tmp; 2146 2147 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2148 2149 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2150 tmp = (tmp & ~0xff) | slottime; 2151 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2152 } 2153 2154 static const char * 2155 rt2661_get_rf(int rev) 2156 { 2157 switch (rev) { 2158 case RT2661_RF_5225: return "RT5225"; 2159 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2160 case RT2661_RF_2527: return "RT2527"; 2161 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2162 default: return "unknown"; 2163 } 2164 } 2165 2166 static void 2167 rt2661_read_eeprom(struct rt2661_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 2168 { 2169 uint16_t val; 2170 int i; 2171 2172 /* read MAC address */ 2173 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2174 macaddr[0] = val & 0xff; 2175 macaddr[1] = val >> 8; 2176 2177 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2178 macaddr[2] = val & 0xff; 2179 macaddr[3] = val >> 8; 2180 2181 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2182 macaddr[4] = val & 0xff; 2183 macaddr[5] = val >> 8; 2184 2185 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2186 /* XXX: test if different from 0xffff? */ 2187 sc->rf_rev = (val >> 11) & 0x1f; 2188 sc->hw_radio = (val >> 10) & 0x1; 2189 sc->rx_ant = (val >> 4) & 0x3; 2190 sc->tx_ant = (val >> 2) & 0x3; 2191 sc->nb_ant = val & 0x3; 2192 2193 DPRINTF(sc, "RF revision=%d\n", sc->rf_rev); 2194 2195 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2196 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2197 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2198 2199 DPRINTF(sc, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2200 sc->ext_2ghz_lna, sc->ext_5ghz_lna); 2201 2202 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2203 if ((val & 0xff) != 0xff) 2204 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2205 2206 /* Only [-10, 10] is valid */ 2207 if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10) 2208 sc->rssi_2ghz_corr = 0; 2209 2210 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2211 if ((val & 0xff) != 0xff) 2212 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2213 2214 /* Only [-10, 10] is valid */ 2215 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10) 2216 sc->rssi_5ghz_corr = 0; 2217 2218 /* adjust RSSI correction for external low-noise amplifier */ 2219 if (sc->ext_2ghz_lna) 2220 sc->rssi_2ghz_corr -= 14; 2221 if (sc->ext_5ghz_lna) 2222 sc->rssi_5ghz_corr -= 14; 2223 2224 DPRINTF(sc, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2225 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr); 2226 2227 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2228 if ((val >> 8) != 0xff) 2229 sc->rfprog = (val >> 8) & 0x3; 2230 if ((val & 0xff) != 0xff) 2231 sc->rffreq = val & 0xff; 2232 2233 DPRINTF(sc, "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq); 2234 2235 /* read Tx power for all a/b/g channels */ 2236 for (i = 0; i < 19; i++) { 2237 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2238 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2239 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2240 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]); 2241 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2242 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2243 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]); 2244 } 2245 2246 /* read vendor-specific BBP values */ 2247 for (i = 0; i < 16; i++) { 2248 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2249 if (val == 0 || val == 0xffff) 2250 continue; /* skip invalid entries */ 2251 sc->bbp_prom[i].reg = val >> 8; 2252 sc->bbp_prom[i].val = val & 0xff; 2253 DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2254 sc->bbp_prom[i].val); 2255 } 2256 } 2257 2258 static int 2259 rt2661_bbp_init(struct rt2661_softc *sc) 2260 { 2261 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2262 int i, ntries; 2263 uint8_t val; 2264 2265 /* wait for BBP to be ready */ 2266 for (ntries = 0; ntries < 100; ntries++) { 2267 val = rt2661_bbp_read(sc, 0); 2268 if (val != 0 && val != 0xff) 2269 break; 2270 DELAY(100); 2271 } 2272 if (ntries == 100) { 2273 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2274 return EIO; 2275 } 2276 2277 /* initialize BBP registers to default values */ 2278 for (i = 0; i < N(rt2661_def_bbp); i++) { 2279 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2280 rt2661_def_bbp[i].val); 2281 } 2282 2283 /* write vendor-specific BBP values (from EEPROM) */ 2284 for (i = 0; i < 16; i++) { 2285 if (sc->bbp_prom[i].reg == 0) 2286 continue; 2287 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2288 } 2289 2290 return 0; 2291 #undef N 2292 } 2293 2294 static void 2295 rt2661_init_locked(struct rt2661_softc *sc) 2296 { 2297 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2298 struct ifnet *ifp = sc->sc_ifp; 2299 struct ieee80211com *ic = ifp->if_l2com; 2300 uint32_t tmp, sta[3]; 2301 int i, error, ntries; 2302 2303 if ((sc->sc_flags & RAL_FW_LOADED) == 0) { 2304 error = rt2661_load_microcode(sc); 2305 if (error != 0) { 2306 if_printf(ifp, 2307 "%s: could not load 8051 microcode, error %d\n", 2308 __func__, error); 2309 return; 2310 } 2311 sc->sc_flags |= RAL_FW_LOADED; 2312 } 2313 2314 rt2661_stop_locked(sc); 2315 2316 /* initialize Tx rings */ 2317 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2318 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2319 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2320 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2321 2322 /* initialize Mgt ring */ 2323 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2324 2325 /* initialize Rx ring */ 2326 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2327 2328 /* initialize Tx rings sizes */ 2329 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2330 RT2661_TX_RING_COUNT << 24 | 2331 RT2661_TX_RING_COUNT << 16 | 2332 RT2661_TX_RING_COUNT << 8 | 2333 RT2661_TX_RING_COUNT); 2334 2335 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2336 RT2661_TX_DESC_WSIZE << 16 | 2337 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2338 RT2661_MGT_RING_COUNT); 2339 2340 /* initialize Rx rings */ 2341 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2342 RT2661_RX_DESC_BACK << 16 | 2343 RT2661_RX_DESC_WSIZE << 8 | 2344 RT2661_RX_RING_COUNT); 2345 2346 /* XXX: some magic here */ 2347 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2348 2349 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2350 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2351 2352 /* load base address of Rx ring */ 2353 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2354 2355 /* initialize MAC registers to default values */ 2356 for (i = 0; i < N(rt2661_def_mac); i++) 2357 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2358 2359 rt2661_set_macaddr(sc, IF_LLADDR(ifp)); 2360 2361 /* set host ready */ 2362 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2363 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2364 2365 /* wait for BBP/RF to wakeup */ 2366 for (ntries = 0; ntries < 1000; ntries++) { 2367 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2368 break; 2369 DELAY(1000); 2370 } 2371 if (ntries == 1000) { 2372 kprintf("timeout waiting for BBP/RF to wakeup\n"); 2373 rt2661_stop_locked(sc); 2374 return; 2375 } 2376 2377 if (rt2661_bbp_init(sc) != 0) { 2378 rt2661_stop_locked(sc); 2379 return; 2380 } 2381 2382 /* select default channel */ 2383 sc->sc_curchan = ic->ic_curchan; 2384 rt2661_select_band(sc, sc->sc_curchan); 2385 rt2661_select_antenna(sc); 2386 rt2661_set_chan(sc, sc->sc_curchan); 2387 2388 /* update Rx filter */ 2389 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2390 2391 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2392 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2393 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2394 RT2661_DROP_ACKCTS; 2395 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 2396 ic->ic_opmode != IEEE80211_M_MBSS) 2397 tmp |= RT2661_DROP_TODS; 2398 if (!(ifp->if_flags & IFF_PROMISC)) 2399 tmp |= RT2661_DROP_NOT_TO_ME; 2400 } 2401 2402 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2403 2404 /* clear STA registers */ 2405 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta)); 2406 2407 /* initialize ASIC */ 2408 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2409 2410 /* clear any pending interrupt */ 2411 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2412 2413 /* enable interrupts */ 2414 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2415 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2416 2417 /* kick Rx */ 2418 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2419 2420 ifp->if_flags &= ~IFF_OACTIVE; 2421 ifp->if_flags |= IFF_RUNNING; 2422 2423 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog_callout, sc); 2424 #undef N 2425 } 2426 2427 static void 2428 rt2661_init(void *priv) 2429 { 2430 struct rt2661_softc *sc = priv; 2431 struct ifnet *ifp = sc->sc_ifp; 2432 struct ieee80211com *ic = ifp->if_l2com; 2433 2434 rt2661_init_locked(sc); 2435 2436 if (ifp->if_flags & IFF_RUNNING) 2437 ieee80211_start_all(ic); /* start all vap's */ 2438 } 2439 2440 void 2441 rt2661_stop_locked(struct rt2661_softc *sc) 2442 { 2443 struct ifnet *ifp = sc->sc_ifp; 2444 uint32_t tmp; 2445 volatile int *flags = &sc->sc_flags; 2446 2447 while (*flags & RAL_INPUT_RUNNING) 2448 zsleep(sc, &wlan_global_serializer, 0, "ralrunning", hz/10); 2449 2450 callout_stop(&sc->watchdog_ch); 2451 sc->sc_tx_timer = 0; 2452 2453 if (ifp->if_flags & IFF_RUNNING) { 2454 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2455 2456 /* abort Tx (for all 5 Tx rings) */ 2457 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2458 2459 /* disable Rx (value remains after reset!) */ 2460 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2461 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2462 2463 /* reset ASIC */ 2464 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2465 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2466 2467 /* disable interrupts */ 2468 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); 2469 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2470 2471 /* clear any pending interrupt */ 2472 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2473 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2474 2475 /* reset Tx and Rx rings */ 2476 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2477 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2478 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2479 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2480 rt2661_reset_tx_ring(sc, &sc->mgtq); 2481 rt2661_reset_rx_ring(sc, &sc->rxq); 2482 } 2483 } 2484 2485 void 2486 rt2661_stop(void *priv) 2487 { 2488 struct rt2661_softc *sc = priv; 2489 2490 rt2661_stop_locked(sc); 2491 } 2492 2493 static int 2494 rt2661_load_microcode(struct rt2661_softc *sc) 2495 { 2496 struct ifnet *ifp = sc->sc_ifp; 2497 const struct firmware *fp; 2498 const char *imagename; 2499 int ntries, error; 2500 2501 switch (sc->sc_id) { 2502 case 0x0301: imagename = "rt2561sfw"; break; 2503 case 0x0302: imagename = "rt2561fw"; break; 2504 case 0x0401: imagename = "rt2661fw"; break; 2505 default: 2506 if_printf(ifp, "%s: unexpected pci device id 0x%x, " 2507 "don't know how to retrieve firmware\n", 2508 __func__, sc->sc_id); 2509 return EINVAL; 2510 } 2511 fp = firmware_get(imagename); 2512 if (fp == NULL) { 2513 if_printf(ifp, "%s: unable to retrieve firmware image %s\n", 2514 __func__, imagename); 2515 return EINVAL; 2516 } 2517 2518 /* 2519 * Load 8051 microcode into NIC. 2520 */ 2521 /* reset 8051 */ 2522 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2523 2524 /* cancel any pending Host to MCU command */ 2525 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2526 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2527 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2528 2529 /* write 8051's microcode */ 2530 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2531 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, fp->data, fp->datasize); 2532 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2533 2534 /* kick 8051's ass */ 2535 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2536 2537 /* wait for 8051 to initialize */ 2538 for (ntries = 0; ntries < 500; ntries++) { 2539 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2540 break; 2541 DELAY(100); 2542 } 2543 if (ntries == 500) { 2544 if_printf(ifp, "%s: timeout waiting for MCU to initialize\n", 2545 __func__); 2546 error = EIO; 2547 } else 2548 error = 0; 2549 2550 firmware_put(fp, FIRMWARE_UNLOAD); 2551 return error; 2552 } 2553 2554 #ifdef notyet 2555 /* 2556 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2557 * false CCA count. This function is called periodically (every seconds) when 2558 * in the RUN state. Values taken from the reference driver. 2559 */ 2560 static void 2561 rt2661_rx_tune(struct rt2661_softc *sc) 2562 { 2563 uint8_t bbp17; 2564 uint16_t cca; 2565 int lo, hi, dbm; 2566 2567 /* 2568 * Tuning range depends on operating band and on the presence of an 2569 * external low-noise amplifier. 2570 */ 2571 lo = 0x20; 2572 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2573 lo += 0x08; 2574 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2575 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2576 lo += 0x10; 2577 hi = lo + 0x20; 2578 2579 /* retrieve false CCA count since last call (clear on read) */ 2580 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2581 2582 if (dbm >= -35) { 2583 bbp17 = 0x60; 2584 } else if (dbm >= -58) { 2585 bbp17 = hi; 2586 } else if (dbm >= -66) { 2587 bbp17 = lo + 0x10; 2588 } else if (dbm >= -74) { 2589 bbp17 = lo + 0x08; 2590 } else { 2591 /* RSSI < -74dBm, tune using false CCA count */ 2592 2593 bbp17 = sc->bbp17; /* current value */ 2594 2595 hi -= 2 * (-74 - dbm); 2596 if (hi < lo) 2597 hi = lo; 2598 2599 if (bbp17 > hi) { 2600 bbp17 = hi; 2601 2602 } else if (cca > 512) { 2603 if (++bbp17 > hi) 2604 bbp17 = hi; 2605 } else if (cca < 100) { 2606 if (--bbp17 < lo) 2607 bbp17 = lo; 2608 } 2609 } 2610 2611 if (bbp17 != sc->bbp17) { 2612 rt2661_bbp_write(sc, 17, bbp17); 2613 sc->bbp17 = bbp17; 2614 } 2615 } 2616 2617 /* 2618 * Enter/Leave radar detection mode. 2619 * This is for 802.11h additional regulatory domains. 2620 */ 2621 static void 2622 rt2661_radar_start(struct rt2661_softc *sc) 2623 { 2624 uint32_t tmp; 2625 2626 /* disable Rx */ 2627 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2628 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2629 2630 rt2661_bbp_write(sc, 82, 0x20); 2631 rt2661_bbp_write(sc, 83, 0x00); 2632 rt2661_bbp_write(sc, 84, 0x40); 2633 2634 /* save current BBP registers values */ 2635 sc->bbp18 = rt2661_bbp_read(sc, 18); 2636 sc->bbp21 = rt2661_bbp_read(sc, 21); 2637 sc->bbp22 = rt2661_bbp_read(sc, 22); 2638 sc->bbp16 = rt2661_bbp_read(sc, 16); 2639 sc->bbp17 = rt2661_bbp_read(sc, 17); 2640 sc->bbp64 = rt2661_bbp_read(sc, 64); 2641 2642 rt2661_bbp_write(sc, 18, 0xff); 2643 rt2661_bbp_write(sc, 21, 0x3f); 2644 rt2661_bbp_write(sc, 22, 0x3f); 2645 rt2661_bbp_write(sc, 16, 0xbd); 2646 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2647 rt2661_bbp_write(sc, 64, 0x21); 2648 2649 /* restore Rx filter */ 2650 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2651 } 2652 2653 static int 2654 rt2661_radar_stop(struct rt2661_softc *sc) 2655 { 2656 uint8_t bbp66; 2657 2658 /* read radar detection result */ 2659 bbp66 = rt2661_bbp_read(sc, 66); 2660 2661 /* restore BBP registers values */ 2662 rt2661_bbp_write(sc, 16, sc->bbp16); 2663 rt2661_bbp_write(sc, 17, sc->bbp17); 2664 rt2661_bbp_write(sc, 18, sc->bbp18); 2665 rt2661_bbp_write(sc, 21, sc->bbp21); 2666 rt2661_bbp_write(sc, 22, sc->bbp22); 2667 rt2661_bbp_write(sc, 64, sc->bbp64); 2668 2669 return bbp66 == 1; 2670 } 2671 #endif 2672 2673 static int 2674 rt2661_prepare_beacon(struct rt2661_softc *sc, struct ieee80211vap *vap) 2675 { 2676 struct ieee80211com *ic = vap->iv_ic; 2677 struct ieee80211_beacon_offsets bo; 2678 struct rt2661_tx_desc desc; 2679 struct mbuf *m0; 2680 int rate; 2681 2682 m0 = ieee80211_beacon_alloc(vap->iv_bss, &bo); 2683 if (m0 == NULL) { 2684 device_printf(sc->sc_dev, "could not allocate beacon frame\n"); 2685 return ENOBUFS; 2686 } 2687 2688 /* send beacons at the lowest available rate */ 2689 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 12 : 2; 2690 2691 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2692 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2693 2694 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2695 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2696 2697 /* copy beacon header and payload into NIC memory */ 2698 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2699 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2700 2701 m_freem(m0); 2702 2703 return 0; 2704 } 2705 2706 /* 2707 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2708 * and HostAP operating modes. 2709 */ 2710 static void 2711 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2712 { 2713 struct ifnet *ifp = sc->sc_ifp; 2714 struct ieee80211com *ic = ifp->if_l2com; 2715 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2716 uint32_t tmp; 2717 2718 if (vap->iv_opmode != IEEE80211_M_STA) { 2719 /* 2720 * Change default 16ms TBTT adjustment to 8ms. 2721 * Must be done before enabling beacon generation. 2722 */ 2723 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2724 } 2725 2726 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2727 2728 /* set beacon interval (in 1/16ms unit) */ 2729 tmp |= vap->iv_bss->ni_intval * 16; 2730 2731 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2732 if (vap->iv_opmode == IEEE80211_M_STA) 2733 tmp |= RT2661_TSF_MODE(1); 2734 else 2735 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2736 2737 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2738 } 2739 2740 static void 2741 rt2661_enable_tsf(struct rt2661_softc *sc) 2742 { 2743 RAL_WRITE(sc, RT2661_TXRX_CSR9, 2744 (RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000) 2745 | RT2661_TSF_TICKING | RT2661_TSF_MODE(2)); 2746 } 2747 2748 /* 2749 * Retrieve the "Received Signal Strength Indicator" from the raw values 2750 * contained in Rx descriptors. The computation depends on which band the 2751 * frame was received. Correction values taken from the reference driver. 2752 */ 2753 static int 2754 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 2755 { 2756 int lna, agc, rssi; 2757 2758 lna = (raw >> 5) & 0x3; 2759 agc = raw & 0x1f; 2760 2761 if (lna == 0) { 2762 /* 2763 * No mapping available. 2764 * 2765 * NB: Since RSSI is relative to noise floor, -1 is 2766 * adequate for caller to know error happened. 2767 */ 2768 return -1; 2769 } 2770 2771 rssi = (2 * agc) - RT2661_NOISE_FLOOR; 2772 2773 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 2774 rssi += sc->rssi_2ghz_corr; 2775 2776 if (lna == 1) 2777 rssi -= 64; 2778 else if (lna == 2) 2779 rssi -= 74; 2780 else if (lna == 3) 2781 rssi -= 90; 2782 } else { 2783 rssi += sc->rssi_5ghz_corr; 2784 2785 if (lna == 1) 2786 rssi -= 64; 2787 else if (lna == 2) 2788 rssi -= 86; 2789 else if (lna == 3) 2790 rssi -= 100; 2791 } 2792 return rssi; 2793 } 2794 2795 static void 2796 rt2661_scan_start(struct ieee80211com *ic) 2797 { 2798 struct ifnet *ifp = ic->ic_ifp; 2799 struct rt2661_softc *sc = ifp->if_softc; 2800 uint32_t tmp; 2801 2802 /* abort TSF synchronization */ 2803 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 2804 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff); 2805 rt2661_set_bssid(sc, ifp->if_broadcastaddr); 2806 } 2807 2808 static void 2809 rt2661_scan_end(struct ieee80211com *ic) 2810 { 2811 struct ifnet *ifp = ic->ic_ifp; 2812 struct rt2661_softc *sc = ifp->if_softc; 2813 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2814 2815 rt2661_enable_tsf_sync(sc); 2816 /* XXX keep local copy */ 2817 rt2661_set_bssid(sc, vap->iv_bss->ni_bssid); 2818 } 2819 2820 static void 2821 rt2661_set_channel(struct ieee80211com *ic) 2822 { 2823 struct ifnet *ifp = ic->ic_ifp; 2824 struct rt2661_softc *sc = ifp->if_softc; 2825 2826 rt2661_set_chan(sc, ic->ic_curchan); 2827 } 2828