1 /* 2 * Copyright (c) 2006 3 * Damien Bergamini <damien.bergamini@free.fr> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: src/sys/dev/ral/rt2661.c,v 1.4 2006/03/21 21:15:43 damien Exp $ 18 * $DragonFly: src/sys/dev/netif/ral/rt2661.c,v 1.30 2008/05/14 11:59:21 sephe Exp $ 19 */ 20 21 /* 22 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 23 * http://www.ralinktech.com/ 24 */ 25 26 #include <sys/param.h> 27 #include <sys/bus.h> 28 #include <sys/endian.h> 29 #include <sys/kernel.h> 30 #include <sys/interrupt.h> 31 #include <sys/malloc.h> 32 #include <sys/mbuf.h> 33 #include <sys/module.h> 34 #include <sys/queue.h> 35 #include <sys/rman.h> 36 #include <sys/socket.h> 37 #include <sys/sockio.h> 38 #include <sys/sysctl.h> 39 #include <sys/serialize.h> 40 41 #include <net/bpf.h> 42 #include <net/if.h> 43 #include <net/if_arp.h> 44 #include <net/ethernet.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/ifq_var.h> 48 49 #include <netproto/802_11/ieee80211_var.h> 50 #include <netproto/802_11/ieee80211_radiotap.h> 51 #include <netproto/802_11/wlan_ratectl/onoe/ieee80211_onoe_param.h> 52 #include <netproto/802_11/wlan_ratectl/sample/ieee80211_sample_param.h> 53 54 #include <dev/netif/ral/rt2661reg.h> 55 #include <dev/netif/ral/rt2661var.h> 56 #include <dev/netif/ral/rt2661_ucode.h> 57 58 #ifdef RAL_DEBUG 59 #define DPRINTF(sc, x) \ 60 do { if ((sc)->sc_debug > 0) kprintf x; } while (0) 61 #define DPRINTFN(sc, n, x) \ 62 do { if ((sc)->sc_debug >= (n)) kprintf x; } while (0) 63 #else 64 #define DPRINTF(sc, x) 65 #define DPRINTFN(sc, n, x) 66 #endif 67 68 MALLOC_DEFINE(M_RT2661, "rt2661_ratectl", "rt2661 rate control data"); 69 70 static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, 71 int); 72 static void rt2661_dma_map_mbuf(void *, bus_dma_segment_t *, int, 73 bus_size_t, int); 74 static int rt2661_alloc_tx_ring(struct rt2661_softc *, 75 struct rt2661_tx_ring *, int); 76 static void rt2661_reset_tx_ring(struct rt2661_softc *, 77 struct rt2661_tx_ring *); 78 static void rt2661_free_tx_ring(struct rt2661_softc *, 79 struct rt2661_tx_ring *); 80 static int rt2661_alloc_rx_ring(struct rt2661_softc *, 81 struct rt2661_rx_ring *, int); 82 static void rt2661_reset_rx_ring(struct rt2661_softc *, 83 struct rt2661_rx_ring *); 84 static void rt2661_free_rx_ring(struct rt2661_softc *, 85 struct rt2661_rx_ring *); 86 static int rt2661_media_change(struct ifnet *); 87 static void rt2661_next_scan(void *); 88 static int rt2661_newstate(struct ieee80211com *, 89 enum ieee80211_state, int); 90 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 91 static void rt2661_rx_intr(struct rt2661_softc *); 92 static void rt2661_tx_intr(struct rt2661_softc *); 93 static void rt2661_tx_dma_intr(struct rt2661_softc *, 94 struct rt2661_tx_ring *); 95 static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 96 static void rt2661_mcu_wakeup(struct rt2661_softc *); 97 static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 98 static uint8_t rt2661_rxrate(struct rt2661_rx_desc *); 99 static uint8_t rt2661_plcp_signal(int); 100 static void rt2661_setup_tx_desc(struct rt2661_softc *, 101 struct rt2661_tx_desc *, uint32_t, uint16_t, int, 102 int, const bus_dma_segment_t *, int, int, int, 103 const struct ieee80211_key *, void *, 104 const struct ieee80211_crypto_iv *); 105 static struct mbuf * rt2661_get_rts(struct rt2661_softc *, 106 struct ieee80211_frame *, uint16_t); 107 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 108 struct ieee80211_node *, int); 109 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 110 struct ieee80211_node *); 111 static void rt2661_start(struct ifnet *); 112 static void rt2661_watchdog(struct ifnet *); 113 static int rt2661_reset(struct ifnet *); 114 static int rt2661_ioctl(struct ifnet *, u_long, caddr_t, 115 struct ucred *); 116 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, 117 uint8_t); 118 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 119 static void rt2661_rf_write(struct rt2661_softc *, uint8_t, 120 uint32_t); 121 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, 122 uint16_t); 123 static void rt2661_select_antenna(struct rt2661_softc *); 124 static void rt2661_enable_mrr(struct rt2661_softc *); 125 static void rt2661_set_txpreamble(struct rt2661_softc *); 126 static void rt2661_set_ackrates(struct rt2661_softc *, 127 const struct ieee80211_rateset *); 128 static void rt2661_select_band(struct rt2661_softc *, 129 struct ieee80211_channel *); 130 static void rt2661_set_chan(struct rt2661_softc *, 131 struct ieee80211_channel *); 132 static void rt2661_set_bssid(struct rt2661_softc *, 133 const uint8_t *); 134 static void rt2661_set_macaddr(struct rt2661_softc *, 135 const uint8_t *); 136 static void rt2661_update_promisc(struct rt2661_softc *); 137 static int rt2661_wme_update(struct ieee80211com *) __unused; 138 static void rt2661_update_slot(struct ifnet *); 139 static const char *rt2661_get_rf(int); 140 static void rt2661_read_config(struct rt2661_softc *); 141 static void rt2661_read_txpower_config(struct rt2661_softc *, 142 uint8_t, int, int *); 143 static int rt2661_bbp_init(struct rt2661_softc *); 144 static void rt2661_init(void *); 145 static void rt2661_stop(void *); 146 static void rt2661_intr(void *); 147 static int rt2661_load_microcode(struct rt2661_softc *, 148 const uint8_t *, int); 149 static int rt2661_prepare_beacon(struct rt2661_softc *); 150 static void rt2661_enable_tsf_sync(struct rt2661_softc *); 151 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t, int); 152 static void rt2661_led_newstate(struct rt2661_softc *, 153 enum ieee80211_state); 154 static int rt2661_key_alloc(struct ieee80211com *, 155 const struct ieee80211_key *, 156 ieee80211_keyix *, ieee80211_keyix *); 157 static int rt2661_key_delete(struct ieee80211com *, 158 const struct ieee80211_key *); 159 static int rt2661_key_set(struct ieee80211com *, 160 const struct ieee80211_key *, 161 const uint8_t mac[IEEE80211_ADDR_LEN]); 162 static void *rt2661_ratectl_attach(struct ieee80211com *, u_int); 163 static void rt2661_set_txpower(struct rt2661_softc *, int8_t); 164 static void rt2661_calibrate(void *); 165 static void rt2661_calib_txpower(struct rt2661_softc *); 166 static void rt2661_calib_rxsensibility(struct rt2661_softc *, 167 uint32_t); 168 169 /* 170 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 171 */ 172 static const struct ieee80211_rateset rt2661_rateset_11a = 173 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 174 175 static const struct ieee80211_rateset rt2661_rateset_11b = 176 { 4, { 2, 4, 11, 22 } }; 177 178 static const struct ieee80211_rateset rt2661_rateset_11g = 179 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 180 181 static const struct { 182 uint32_t reg; 183 uint32_t val; 184 } rt2661_def_mac[] = { 185 RT2661_DEF_MAC 186 }; 187 188 static const struct { 189 uint8_t reg; 190 uint8_t val; 191 } rt2661_def_bbp[] = { 192 RT2661_DEF_BBP 193 }; 194 195 static const struct rt2661_rfprog rt2661_rf5225_1[] = { RT2661_RF5225_1 }; 196 static const struct rt2661_rfprog rt2661_rf5225_2[] = { RT2661_RF5225_2 }; 197 198 #define LED_EE2MCU(bit) { \ 199 .ee_bit = RT2661_EE_LED_##bit, \ 200 .mcu_bit = RT2661_MCU_LED_##bit \ 201 } 202 static const struct { 203 uint16_t ee_bit; 204 uint16_t mcu_bit; 205 } led_ee2mcu[] = { 206 LED_EE2MCU(RDYG), 207 LED_EE2MCU(RDYA), 208 LED_EE2MCU(ACT), 209 LED_EE2MCU(GPIO0), 210 LED_EE2MCU(GPIO1), 211 LED_EE2MCU(GPIO2), 212 LED_EE2MCU(GPIO3), 213 LED_EE2MCU(GPIO4) 214 }; 215 #undef LED_EE2MCU 216 217 struct rt2661_dmamap { 218 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 219 int nseg; 220 }; 221 222 static __inline int 223 rt2661_cipher(const struct ieee80211_key *k) 224 { 225 switch (k->wk_cipher->ic_cipher) { 226 case IEEE80211_CIPHER_WEP: 227 if (k->wk_keylen == (40 / NBBY)) 228 return RT2661_CIPHER_WEP40; 229 else 230 return RT2661_CIPHER_WEP104; 231 case IEEE80211_CIPHER_TKIP: 232 return RT2661_CIPHER_TKIP; 233 case IEEE80211_CIPHER_AES_CCM: 234 return RT2661_CIPHER_AES; 235 default: 236 return RT2661_CIPHER_NONE; 237 } 238 } 239 240 static __inline int8_t 241 rt2661_txpower(const struct rt2661_softc *sc, int8_t power) 242 { 243 if (sc->sc_txpwr_corr > 0) { 244 if (power > sc->sc_txpwr_corr) 245 power -= sc->sc_txpwr_corr; 246 else 247 power = 0; 248 } 249 return power; 250 } 251 252 static __inline int 253 rt2661_avgrssi(const struct rt2661_softc *sc) 254 { 255 int rssi_dbm; 256 257 rssi_dbm = sc->avg_rssi[0] + RT2661_NOISE_FLOOR; 258 if (sc->rf_rev == RT2661_RF_2529) { 259 if (sc->avg_rssi[1] > sc->avg_rssi[0]) 260 rssi_dbm = sc->avg_rssi[0] + RT2661_NOISE_FLOOR; 261 } 262 return rssi_dbm; 263 } 264 265 int 266 rt2661_attach(device_t dev, int id) 267 { 268 struct rt2661_softc *sc = device_get_softc(dev); 269 struct ieee80211com *ic = &sc->sc_ic; 270 struct ifnet *ifp = &ic->ic_if; 271 uint32_t val, bbp_type; 272 const uint8_t *ucode = NULL; 273 int error, i, ac, ntries, size = 0; 274 275 callout_init(&sc->scan_ch); 276 callout_init(&sc->calib_ch); 277 #ifdef RAL_DEBUG 278 sc->sc_debug = 1; 279 #endif 280 281 sc->sc_irq_rid = 0; 282 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irq_rid, 283 RF_ACTIVE | RF_SHAREABLE); 284 if (sc->sc_irq == NULL) { 285 device_printf(dev, "could not allocate interrupt resource\n"); 286 return ENXIO; 287 } 288 289 /* wait for NIC to initialize */ 290 for (ntries = 0; ntries < 1000; ntries++) { 291 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 292 break; 293 DELAY(1000); 294 } 295 if (ntries == 1000) { 296 device_printf(sc->sc_dev, 297 "timeout waiting for NIC to initialize\n"); 298 error = EIO; 299 goto fail; 300 } 301 bbp_type = val; 302 303 /* retrieve RF rev. no and various other things from EEPROM */ 304 rt2661_read_config(sc); 305 306 device_printf(dev, "MAC/BBP RT%X, RF %s\n", bbp_type, 307 rt2661_get_rf(sc->rf_rev)); 308 309 /* 310 * Load 8051 microcode into NIC. 311 */ 312 switch (id) { 313 case 0x0301: 314 ucode = rt2561s_ucode; 315 size = sizeof rt2561s_ucode; 316 break; 317 case 0x0302: 318 ucode = rt2561_ucode; 319 size = sizeof rt2561_ucode; 320 break; 321 case 0x0401: 322 ucode = rt2661_ucode; 323 size = sizeof rt2661_ucode; 324 break; 325 } 326 327 error = rt2661_load_microcode(sc, ucode, size); 328 if (error != 0) { 329 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 330 goto fail; 331 } 332 333 /* 334 * Allocate Tx and Rx rings. 335 */ 336 for (ac = 0; ac < 4; ac++) { 337 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 338 RT2661_TX_RING_COUNT); 339 if (error != 0) { 340 device_printf(sc->sc_dev, 341 "could not allocate Tx ring %d\n", ac); 342 goto fail; 343 } 344 } 345 346 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 347 if (error != 0) { 348 device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); 349 goto fail; 350 } 351 352 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 353 if (error != 0) { 354 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 355 goto fail; 356 } 357 358 STAILQ_INIT(&sc->tx_ratectl); 359 360 sysctl_ctx_init(&sc->sysctl_ctx); 361 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 362 SYSCTL_STATIC_CHILDREN(_hw), 363 OID_AUTO, 364 device_get_nameunit(dev), 365 CTLFLAG_RD, 0, ""); 366 if (sc->sysctl_tree == NULL) { 367 device_printf(dev, "could not add sysctl node\n"); 368 error = ENXIO; 369 goto fail; 370 } 371 372 ifp->if_softc = sc; 373 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 374 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 375 ifp->if_init = rt2661_init; 376 ifp->if_ioctl = rt2661_ioctl; 377 ifp->if_start = rt2661_start; 378 ifp->if_watchdog = rt2661_watchdog; 379 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 380 ifq_set_ready(&ifp->if_snd); 381 382 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 383 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 384 ic->ic_state = IEEE80211_S_INIT; 385 rt2661_led_newstate(sc, IEEE80211_S_INIT); 386 387 IEEE80211_ONOE_PARAM_SETUP(&sc->sc_onoe_param); 388 ic->ic_ratectl.rc_st_ratectl_cap = IEEE80211_RATECTL_CAP_ONOE; 389 if (bbp_type == RT2661_BBP_2661D) { 390 ic->ic_ratectl.rc_st_ratectl = IEEE80211_RATECTL_ONOE; 391 } else { 392 IEEE80211_SAMPLE_PARAM_SETUP(&sc->sc_sample_param); 393 ic->ic_ratectl.rc_st_ratectl_cap |= 394 IEEE80211_RATECTL_CAP_SAMPLE; 395 ic->ic_ratectl.rc_st_ratectl = IEEE80211_RATECTL_SAMPLE; 396 } 397 ic->ic_ratectl.rc_st_attach = rt2661_ratectl_attach; 398 399 /* set device capabilities */ 400 ic->ic_caps = 401 IEEE80211_C_IBSS | /* IBSS mode supported */ 402 IEEE80211_C_MONITOR | /* monitor mode supported */ 403 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 404 IEEE80211_C_TXPMGT | /* tx power management */ 405 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 406 IEEE80211_C_SHSLOT | /* short slot time supported */ 407 #ifdef notyet 408 IEEE80211_C_WME | /* 802.11e */ 409 #endif 410 IEEE80211_C_WPA; /* 802.11i */ 411 412 /* Set hardware crypto capabilities. */ 413 ic->ic_caps |= IEEE80211_C_WEP | 414 IEEE80211_C_TKIP | 415 IEEE80211_C_TKIPMIC | 416 IEEE80211_C_AES_CCM; 417 418 ic->ic_caps_ext = IEEE80211_CEXT_CRYPTO_HDR | 419 IEEE80211_CEXT_STRIP_MIC; 420 421 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) { 422 /* set supported .11a rates */ 423 ic->ic_sup_rates[IEEE80211_MODE_11A] = rt2661_rateset_11a; 424 425 /* set supported .11a channels */ 426 for (i = 36; i <= 64; i += 4) { 427 ic->ic_channels[i].ic_freq = 428 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 429 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 430 } 431 for (i = 100; i <= 140; i += 4) { 432 ic->ic_channels[i].ic_freq = 433 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 434 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 435 } 436 for (i = 149; i <= 165; i += 4) { 437 ic->ic_channels[i].ic_freq = 438 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 439 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 440 } 441 } 442 443 /* set supported .11b and .11g rates */ 444 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2661_rateset_11b; 445 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2661_rateset_11g; 446 447 /* set supported .11b and .11g channels (1 through 14) */ 448 for (i = 1; i <= 14; i++) { 449 ic->ic_channels[i].ic_freq = 450 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 451 ic->ic_channels[i].ic_flags = 452 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 453 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 454 } 455 456 sc->sc_sifs = IEEE80211_DUR_SIFS; /* Default SIFS */ 457 458 ieee80211_ifattach(ic); 459 /* ic->ic_wme.wme_update = rt2661_wme_update;*/ 460 ic->ic_updateslot = rt2661_update_slot; 461 ic->ic_reset = rt2661_reset; 462 /* enable s/w bmiss handling in sta mode */ 463 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS; 464 465 sc->sc_key_alloc = ic->ic_crypto.cs_key_alloc; 466 sc->sc_key_delete = ic->ic_crypto.cs_key_delete; 467 sc->sc_key_set = ic->ic_crypto.cs_key_set; 468 469 ic->ic_crypto.cs_max_keyix = RT2661_KEY_MAX; 470 ic->ic_crypto.cs_key_alloc = rt2661_key_alloc; 471 ic->ic_crypto.cs_key_delete = rt2661_key_delete; 472 ic->ic_crypto.cs_key_set = rt2661_key_set; 473 474 /* override state transition machine */ 475 sc->sc_newstate = ic->ic_newstate; 476 ic->ic_newstate = rt2661_newstate; 477 ieee80211_media_init(ic, rt2661_media_change, ieee80211_media_status); 478 479 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO, 480 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 481 482 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 483 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 484 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 485 486 sc->sc_txtap_len = sizeof sc->sc_txtapu; 487 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 488 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 489 490 /* 491 * Add a few sysctl knobs. 492 */ 493 sc->sc_dwelltime = 200; /* milliseconds */ 494 sc->sc_txpwr_corr = -1; /* Disable */ 495 sc->sc_calib_txpwr = 0; /* Disable */ 496 sc->sc_calib_rxsns = 0; /* Disable */ 497 498 SYSCTL_ADD_INT(&sc->sysctl_ctx, 499 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, "dwell", 500 CTLFLAG_RW, &sc->sc_dwelltime, 0, 501 "Channel dwell time (ms) for AP/station scanning"); 502 503 #ifdef RAL_DEBUG 504 SYSCTL_ADD_INT(&sc->sysctl_ctx, 505 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, "debug", 506 CTLFLAG_RW, &sc->sc_debug, 0, "debug level"); 507 #endif 508 509 SYSCTL_ADD_INT(&sc->sysctl_ctx, 510 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, "txpwr_corr", 511 CTLFLAG_RW, &sc->sc_txpwr_corr, 0, 512 "TX power correction value (<0 no correction)"); 513 514 SYSCTL_ADD_INT(&sc->sysctl_ctx, 515 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, "calib_txpwr", 516 CTLFLAG_RW, &sc->sc_calib_txpwr, 0, 517 "Enable TX power calibration (sta mode)"); 518 SYSCTL_ADD_INT(&sc->sysctl_ctx, 519 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, "calib_rxsns", 520 CTLFLAG_RW, &sc->sc_calib_rxsns, 0, 521 "Enable RX sensibility calibration (sta mode)"); 522 523 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE, rt2661_intr, 524 sc, &sc->sc_ih, ifp->if_serializer); 525 if (error != 0) { 526 device_printf(dev, "could not set up interrupt\n"); 527 bpfdetach(ifp); 528 ieee80211_ifdetach(ic); 529 goto fail; 530 } 531 532 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sc_irq)); 533 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 534 535 if (bootverbose) 536 ieee80211_announce(ic); 537 return 0; 538 fail: 539 rt2661_detach(sc); 540 return error; 541 } 542 543 int 544 rt2661_detach(void *xsc) 545 { 546 struct rt2661_softc *sc = xsc; 547 struct ieee80211com *ic = &sc->sc_ic; 548 struct ifnet *ifp = &ic->ic_if; 549 550 if (device_is_attached(sc->sc_dev)) { 551 lwkt_serialize_enter(ifp->if_serializer); 552 553 callout_stop(&sc->scan_ch); 554 rt2661_stop(sc); 555 bus_teardown_intr(sc->sc_dev, sc->sc_irq, sc->sc_ih); 556 557 lwkt_serialize_exit(ifp->if_serializer); 558 559 bpfdetach(ifp); 560 ieee80211_ifdetach(ic); 561 } 562 563 rt2661_free_tx_ring(sc, &sc->txq[0]); 564 rt2661_free_tx_ring(sc, &sc->txq[1]); 565 rt2661_free_tx_ring(sc, &sc->txq[2]); 566 rt2661_free_tx_ring(sc, &sc->txq[3]); 567 rt2661_free_tx_ring(sc, &sc->mgtq); 568 rt2661_free_rx_ring(sc, &sc->rxq); 569 570 if (sc->sc_irq != NULL) { 571 bus_release_resource(sc->sc_dev, SYS_RES_IRQ, sc->sc_irq_rid, 572 sc->sc_irq); 573 } 574 575 if (sc->sysctl_tree != NULL) 576 sysctl_ctx_free(&sc->sysctl_ctx); 577 578 return 0; 579 } 580 581 void 582 rt2661_shutdown(void *xsc) 583 { 584 struct rt2661_softc *sc = xsc; 585 struct ifnet *ifp = &sc->sc_ic.ic_if; 586 587 lwkt_serialize_enter(ifp->if_serializer); 588 rt2661_stop(sc); 589 lwkt_serialize_exit(ifp->if_serializer); 590 } 591 592 void 593 rt2661_suspend(void *xsc) 594 { 595 struct rt2661_softc *sc = xsc; 596 struct ifnet *ifp = &sc->sc_ic.ic_if; 597 598 lwkt_serialize_enter(ifp->if_serializer); 599 rt2661_stop(sc); 600 lwkt_serialize_exit(ifp->if_serializer); 601 } 602 603 void 604 rt2661_resume(void *xsc) 605 { 606 struct rt2661_softc *sc = xsc; 607 struct ifnet *ifp = sc->sc_ic.ic_ifp; 608 609 lwkt_serialize_enter(ifp->if_serializer); 610 if (ifp->if_flags & IFF_UP) { 611 ifp->if_init(ifp->if_softc); 612 if (ifp->if_flags & IFF_RUNNING) 613 ifp->if_start(ifp); 614 } 615 lwkt_serialize_exit(ifp->if_serializer); 616 } 617 618 static void 619 rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 620 { 621 if (error != 0) 622 return; 623 624 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 625 626 *(bus_addr_t *)arg = segs[0].ds_addr; 627 } 628 629 static int 630 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 631 int count) 632 { 633 int i, error; 634 635 ring->count = count; 636 ring->queued = 0; 637 ring->cur = ring->next = 0; 638 639 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 640 BUS_SPACE_MAXADDR, NULL, NULL, count * RT2661_TX_DESC_SIZE, 1, 641 count * RT2661_TX_DESC_SIZE, 0, &ring->desc_dmat); 642 if (error != 0) { 643 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 644 goto fail; 645 } 646 647 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 648 BUS_DMA_WAITOK | BUS_DMA_ZERO, &ring->desc_map); 649 if (error != 0) { 650 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 651 goto fail; 652 } 653 654 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 655 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 656 0); 657 if (error != 0) { 658 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 659 660 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 661 ring->desc = NULL; 662 goto fail; 663 } 664 665 ring->data = kmalloc(count * sizeof (struct rt2661_data), M_DEVBUF, 666 M_WAITOK | M_ZERO); 667 668 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 669 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * RT2661_MAX_SCATTER, 670 RT2661_MAX_SCATTER, MCLBYTES, 0, &ring->data_dmat); 671 if (error != 0) { 672 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 673 goto fail; 674 } 675 676 for (i = 0; i < count; i++) { 677 error = bus_dmamap_create(ring->data_dmat, 0, 678 &ring->data[i].map); 679 if (error != 0) { 680 device_printf(sc->sc_dev, "could not create DMA map\n"); 681 goto fail; 682 } 683 } 684 return 0; 685 686 fail: rt2661_free_tx_ring(sc, ring); 687 return error; 688 } 689 690 static void 691 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 692 { 693 struct rt2661_tx_desc *desc; 694 struct rt2661_data *data; 695 int i; 696 697 for (i = 0; i < ring->count; i++) { 698 desc = &ring->desc[i]; 699 data = &ring->data[i]; 700 701 if (data->m != NULL) { 702 bus_dmamap_sync(ring->data_dmat, data->map, 703 BUS_DMASYNC_POSTWRITE); 704 bus_dmamap_unload(ring->data_dmat, data->map); 705 m_freem(data->m); 706 data->m = NULL; 707 } 708 709 desc->flags = 0; 710 } 711 712 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 713 714 ring->queued = 0; 715 ring->cur = ring->next = 0; 716 } 717 718 static void 719 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 720 { 721 struct rt2661_data *data; 722 int i; 723 724 if (ring->desc != NULL) { 725 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 726 BUS_DMASYNC_POSTWRITE); 727 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 728 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 729 ring->desc = NULL; 730 } 731 732 if (ring->desc_dmat != NULL) { 733 bus_dma_tag_destroy(ring->desc_dmat); 734 ring->desc_dmat = NULL; 735 } 736 737 if (ring->data != NULL) { 738 for (i = 0; i < ring->count; i++) { 739 data = &ring->data[i]; 740 741 if (data->m != NULL) { 742 bus_dmamap_sync(ring->data_dmat, data->map, 743 BUS_DMASYNC_POSTWRITE); 744 bus_dmamap_unload(ring->data_dmat, data->map); 745 m_freem(data->m); 746 data->m = NULL; 747 } 748 749 if (data->map != NULL) { 750 bus_dmamap_destroy(ring->data_dmat, data->map); 751 data->map = NULL; 752 } 753 } 754 755 kfree(ring->data, M_DEVBUF); 756 ring->data = NULL; 757 } 758 759 if (ring->data_dmat != NULL) { 760 bus_dma_tag_destroy(ring->data_dmat); 761 ring->data_dmat = NULL; 762 } 763 } 764 765 static int 766 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 767 int count) 768 { 769 struct rt2661_rx_desc *desc; 770 struct rt2661_data *data; 771 bus_addr_t physaddr; 772 int i, error; 773 774 ring->count = count; 775 ring->cur = ring->next = 0; 776 777 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 778 BUS_SPACE_MAXADDR, NULL, NULL, count * RT2661_RX_DESC_SIZE, 1, 779 count * RT2661_RX_DESC_SIZE, 0, &ring->desc_dmat); 780 if (error != 0) { 781 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 782 goto fail; 783 } 784 785 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 786 BUS_DMA_WAITOK | BUS_DMA_ZERO, &ring->desc_map); 787 if (error != 0) { 788 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 789 goto fail; 790 } 791 792 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 793 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 794 0); 795 if (error != 0) { 796 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 797 798 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 799 ring->desc = NULL; 800 goto fail; 801 } 802 803 ring->data = kmalloc(count * sizeof (struct rt2661_data), M_DEVBUF, 804 M_WAITOK | M_ZERO); 805 806 /* 807 * Pre-allocate Rx buffers and populate Rx ring. 808 */ 809 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 810 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 811 &ring->data_dmat); 812 if (error != 0) { 813 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 814 goto fail; 815 } 816 817 for (i = 0; i < count; i++) { 818 desc = &sc->rxq.desc[i]; 819 data = &sc->rxq.data[i]; 820 821 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 822 if (error != 0) { 823 device_printf(sc->sc_dev, "could not create DMA map\n"); 824 goto fail; 825 } 826 827 data->m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 828 if (data->m == NULL) { 829 device_printf(sc->sc_dev, 830 "could not allocate rx mbuf\n"); 831 error = ENOMEM; 832 goto fail; 833 } 834 835 error = bus_dmamap_load(ring->data_dmat, data->map, 836 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, 837 &physaddr, 0); 838 if (error != 0) { 839 device_printf(sc->sc_dev, 840 "could not load rx buf DMA map"); 841 842 m_freem(data->m); 843 data->m = NULL; 844 goto fail; 845 } 846 847 desc->flags = htole32(RT2661_RX_BUSY); 848 desc->physaddr = htole32(physaddr); 849 } 850 851 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 852 853 return 0; 854 855 fail: rt2661_free_rx_ring(sc, ring); 856 return error; 857 } 858 859 static void 860 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 861 { 862 int i; 863 864 for (i = 0; i < ring->count; i++) 865 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 866 867 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 868 869 ring->cur = ring->next = 0; 870 } 871 872 static void 873 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 874 { 875 struct rt2661_data *data; 876 int i; 877 878 if (ring->desc != NULL) { 879 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 880 BUS_DMASYNC_POSTWRITE); 881 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 882 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 883 ring->desc = NULL; 884 } 885 886 if (ring->desc_dmat != NULL) { 887 bus_dma_tag_destroy(ring->desc_dmat); 888 ring->desc_dmat = NULL; 889 } 890 891 if (ring->data != NULL) { 892 for (i = 0; i < ring->count; i++) { 893 data = &ring->data[i]; 894 895 if (data->m != NULL) { 896 bus_dmamap_sync(ring->data_dmat, data->map, 897 BUS_DMASYNC_POSTREAD); 898 bus_dmamap_unload(ring->data_dmat, data->map); 899 m_freem(data->m); 900 data->m = NULL; 901 } 902 903 if (data->map != NULL) { 904 bus_dmamap_destroy(ring->data_dmat, data->map); 905 data->map = NULL; 906 } 907 } 908 909 kfree(ring->data, M_DEVBUF); 910 ring->data = NULL; 911 } 912 913 if (ring->data_dmat != NULL) { 914 bus_dma_tag_destroy(ring->data_dmat); 915 ring->data_dmat = NULL; 916 } 917 } 918 919 static int 920 rt2661_media_change(struct ifnet *ifp) 921 { 922 struct rt2661_softc *sc = ifp->if_softc; 923 int error; 924 925 error = ieee80211_media_change(ifp); 926 if (error != ENETRESET) 927 return error; 928 929 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 930 rt2661_init(sc); 931 return 0; 932 } 933 934 /* 935 * This function is called periodically (every 200ms) during scanning to 936 * switch from one channel to another. 937 */ 938 static void 939 rt2661_next_scan(void *arg) 940 { 941 struct rt2661_softc *sc = arg; 942 struct ieee80211com *ic = &sc->sc_ic; 943 struct ifnet *ifp = &ic->ic_if; 944 945 lwkt_serialize_enter(ifp->if_serializer); 946 if (ic->ic_state == IEEE80211_S_SCAN) 947 ieee80211_next_scan(ic); 948 lwkt_serialize_exit(ifp->if_serializer); 949 } 950 951 static int 952 rt2661_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 953 { 954 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 955 enum ieee80211_state ostate; 956 struct ieee80211_node *ni; 957 uint32_t tmp; 958 int error = 0; 959 960 ostate = ic->ic_state; 961 callout_stop(&sc->scan_ch); 962 callout_stop(&sc->calib_ch); 963 964 if (ostate != nstate) 965 rt2661_led_newstate(sc, nstate); 966 967 ieee80211_ratectl_newstate(ic, nstate); 968 969 switch (nstate) { 970 case IEEE80211_S_INIT: 971 if (ostate == IEEE80211_S_RUN) { 972 /* abort TSF synchronization */ 973 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 974 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 975 } 976 break; 977 978 case IEEE80211_S_SCAN: 979 rt2661_set_chan(sc, ic->ic_curchan); 980 callout_reset(&sc->scan_ch, (sc->sc_dwelltime * hz) / 1000, 981 rt2661_next_scan, sc); 982 break; 983 984 case IEEE80211_S_AUTH: 985 case IEEE80211_S_ASSOC: 986 rt2661_set_chan(sc, ic->ic_curchan); 987 break; 988 989 case IEEE80211_S_RUN: 990 RT2661_RESET_AVG_RSSI(sc); 991 992 rt2661_set_chan(sc, ic->ic_curchan); 993 994 ni = ic->ic_bss; 995 996 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 997 rt2661_enable_mrr(sc); 998 rt2661_set_txpreamble(sc); 999 rt2661_set_ackrates(sc, &ni->ni_rates); 1000 rt2661_set_bssid(sc, ni->ni_bssid); 1001 } 1002 1003 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 1004 ic->ic_opmode == IEEE80211_M_IBSS) { 1005 if ((error = rt2661_prepare_beacon(sc)) != 0) 1006 break; 1007 } 1008 1009 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1010 rt2661_enable_tsf_sync(sc); 1011 1012 if (ic->ic_opmode == IEEE80211_M_STA) { 1013 uint32_t sta[4]; 1014 1015 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 1016 /* clear STA registers */ 1017 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta)); 1018 #undef N 1019 sc->sc_txpwr_cnt = 0; 1020 callout_reset(&sc->calib_ch, hz, rt2661_calibrate, sc); 1021 } 1022 break; 1023 } 1024 1025 return (error != 0) ? error : sc->sc_newstate(ic, nstate, arg); 1026 } 1027 1028 /* 1029 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 1030 * 93C66). 1031 */ 1032 static uint16_t 1033 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 1034 { 1035 uint32_t tmp; 1036 uint16_t val; 1037 int n; 1038 1039 /* clock C once before the first command */ 1040 RT2661_EEPROM_CTL(sc, 0); 1041 1042 RT2661_EEPROM_CTL(sc, RT2661_S); 1043 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 1044 RT2661_EEPROM_CTL(sc, RT2661_S); 1045 1046 /* write start bit (1) */ 1047 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 1048 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 1049 1050 /* write READ opcode (10) */ 1051 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 1052 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 1053 RT2661_EEPROM_CTL(sc, RT2661_S); 1054 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 1055 1056 /* write address (A5-A0 or A7-A0) */ 1057 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 1058 for (; n >= 0; n--) { 1059 RT2661_EEPROM_CTL(sc, RT2661_S | 1060 (((addr >> n) & 1) << RT2661_SHIFT_D)); 1061 RT2661_EEPROM_CTL(sc, RT2661_S | 1062 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 1063 } 1064 1065 RT2661_EEPROM_CTL(sc, RT2661_S); 1066 1067 /* read data Q15-Q0 */ 1068 val = 0; 1069 for (n = 15; n >= 0; n--) { 1070 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 1071 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 1072 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 1073 RT2661_EEPROM_CTL(sc, RT2661_S); 1074 } 1075 1076 RT2661_EEPROM_CTL(sc, 0); 1077 1078 /* clear Chip Select and clock C */ 1079 RT2661_EEPROM_CTL(sc, RT2661_S); 1080 RT2661_EEPROM_CTL(sc, 0); 1081 RT2661_EEPROM_CTL(sc, RT2661_C); 1082 1083 return val; 1084 } 1085 1086 static void 1087 rt2661_tx_intr(struct rt2661_softc *sc) 1088 { 1089 struct ieee80211com *ic = &sc->sc_ic; 1090 struct ifnet *ifp = ic->ic_ifp; 1091 struct rt2661_tx_ratectl *rctl; 1092 uint32_t val, result; 1093 int retrycnt; 1094 1095 for (;;) { 1096 struct ieee80211_ratectl_res res; 1097 1098 val = RAL_READ(sc, RT2661_STA_CSR4); 1099 if (!(val & RT2661_TX_STAT_VALID)) 1100 break; 1101 1102 /* Gather statistics */ 1103 result = RT2661_TX_RESULT(val); 1104 if (result == RT2661_TX_SUCCESS) 1105 ifp->if_opackets++; 1106 else 1107 ifp->if_oerrors++; 1108 1109 /* No rate control */ 1110 if (RT2661_TX_QID(val) == 0) 1111 continue; 1112 1113 /* retrieve rate control algorithm context */ 1114 rctl = STAILQ_FIRST(&sc->tx_ratectl); 1115 if (rctl == NULL) { 1116 /* 1117 * XXX 1118 * This really should not happen. Maybe we should 1119 * use assertion here? But why should we rely on 1120 * hardware to do the correct things? Even the 1121 * reference driver (RT61?) provided by Ralink does 1122 * not provide enough clue that this kind of interrupt 1123 * is promised to be generated for each packet. So 1124 * just print a message and keep going ... 1125 */ 1126 if_printf(ifp, "WARNING: no rate control information\n"); 1127 continue; 1128 } 1129 STAILQ_REMOVE_HEAD(&sc->tx_ratectl, link); 1130 1131 retrycnt = 7; 1132 switch (result) { 1133 case RT2661_TX_SUCCESS: 1134 retrycnt = RT2661_TX_RETRYCNT(val); 1135 DPRINTFN(sc, 10, ("data frame sent successfully after " 1136 "%d retries\n", retrycnt)); 1137 break; 1138 1139 case RT2661_TX_RETRY_FAIL: 1140 DPRINTFN(sc, 9, ("sending data frame failed (too much " 1141 "retries)\n")); 1142 break; 1143 1144 default: 1145 /* other failure */ 1146 device_printf(sc->sc_dev, 1147 "sending data frame failed 0x%08x\n", val); 1148 break; 1149 } 1150 1151 res.rc_res_rateidx = rctl->rateidx; 1152 res.rc_res_tries = retrycnt + 1; 1153 ieee80211_ratectl_tx_complete(rctl->ni, rctl->len, &res, 1, 1154 retrycnt, 0, result != RT2661_TX_SUCCESS); 1155 1156 ieee80211_free_node(rctl->ni); 1157 rctl->ni = NULL; 1158 kfree(rctl, M_RT2661); 1159 } 1160 } 1161 1162 static void 1163 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 1164 { 1165 struct rt2661_tx_desc *desc; 1166 struct rt2661_data *data; 1167 1168 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); 1169 1170 for (;;) { 1171 desc = &txq->desc[txq->next]; 1172 data = &txq->data[txq->next]; 1173 1174 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 1175 !(le32toh(desc->flags) & RT2661_TX_VALID)) 1176 break; 1177 1178 bus_dmamap_sync(txq->data_dmat, data->map, 1179 BUS_DMASYNC_POSTWRITE); 1180 bus_dmamap_unload(txq->data_dmat, data->map); 1181 m_freem(data->m); 1182 data->m = NULL; 1183 1184 /* descriptor is no longer valid */ 1185 desc->flags &= ~htole32(RT2661_TX_VALID); 1186 1187 DPRINTFN(sc, 15, ("tx dma done q=%p idx=%u\n", txq, txq->next)); 1188 1189 txq->queued--; 1190 if (++txq->next >= txq->count) /* faster than % count */ 1191 txq->next = 0; 1192 } 1193 1194 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1195 1196 if (txq->queued < txq->count) { 1197 struct ifnet *ifp = &sc->sc_ic.ic_if; 1198 1199 sc->sc_tx_timer = 0; 1200 ifp->if_flags &= ~IFF_OACTIVE; 1201 ifp->if_start(ifp); 1202 } 1203 } 1204 1205 static void 1206 rt2661_rx_intr(struct rt2661_softc *sc) 1207 { 1208 struct ieee80211com *ic = &sc->sc_ic; 1209 struct ifnet *ifp = ic->ic_ifp; 1210 struct rt2661_rx_desc *desc; 1211 struct rt2661_data *data; 1212 bus_addr_t physaddr; 1213 struct ieee80211_frame_min *wh; 1214 struct ieee80211_node *ni; 1215 struct mbuf *mnew, *m; 1216 int error; 1217 1218 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1219 BUS_DMASYNC_POSTREAD); 1220 1221 for (;;) { 1222 uint32_t flags; 1223 int rssi; 1224 1225 desc = &sc->rxq.desc[sc->rxq.cur]; 1226 data = &sc->rxq.data[sc->rxq.cur]; 1227 flags = le32toh(desc->flags); 1228 1229 if (flags & RT2661_RX_BUSY) 1230 break; 1231 1232 if (flags & RT2661_RX_CRC_ERROR) { 1233 /* 1234 * This should not happen since we did not request 1235 * to receive those frames when we filled TXRX_CSR0. 1236 */ 1237 DPRINTFN(sc, 5, ("CRC error flags 0x%08x\n", flags)); 1238 ifp->if_ierrors++; 1239 goto skip; 1240 } 1241 1242 if (flags & RT2661_RX_CIPHER_MASK) { 1243 DPRINTFN(sc, 5, ("cipher error 0x%08x\n", flags)); 1244 ifp->if_ierrors++; 1245 goto skip; 1246 } 1247 1248 /* 1249 * Try to allocate a new mbuf for this ring element and load it 1250 * before processing the current mbuf. If the ring element 1251 * cannot be loaded, drop the received packet and reuse the old 1252 * mbuf. In the unlikely case that the old mbuf can't be 1253 * reloaded either, explicitly panic. 1254 */ 1255 mnew = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1256 if (mnew == NULL) { 1257 ifp->if_ierrors++; 1258 goto skip; 1259 } 1260 1261 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1262 BUS_DMASYNC_POSTREAD); 1263 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1264 1265 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1266 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, 1267 &physaddr, 0); 1268 if (error != 0) { 1269 m_freem(mnew); 1270 1271 /* try to reload the old mbuf */ 1272 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1273 mtod(data->m, void *), MCLBYTES, 1274 rt2661_dma_map_addr, &physaddr, 0); 1275 if (error != 0) { 1276 /* very unlikely that it will fail... */ 1277 panic("%s: could not load old rx mbuf", 1278 device_get_name(sc->sc_dev)); 1279 } 1280 ifp->if_ierrors++; 1281 goto skip; 1282 } 1283 1284 /* 1285 * New mbuf successfully loaded, update Rx ring and continue 1286 * processing. 1287 */ 1288 m = data->m; 1289 data->m = mnew; 1290 desc->physaddr = htole32(physaddr); 1291 1292 /* finalize mbuf */ 1293 m->m_pkthdr.rcvif = ifp; 1294 m->m_pkthdr.len = m->m_len = (flags >> 16) & 0xfff; 1295 1296 rssi = rt2661_get_rssi(sc, desc->rssi, 0); 1297 if (sc->rf_rev == RT2661_RF_2529) 1298 rt2661_get_rssi(sc, desc->rssi, 1); 1299 1300 wh = mtod(m, struct ieee80211_frame_min *); 1301 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 1302 DPRINTFN(sc, 5, ("keyix %d\n", RT2661_RX_KEYIX(flags))); 1303 1304 ni = ieee80211_find_rxnode(ic, wh); 1305 1306 /* Error happened during RSSI conversion. */ 1307 if (rssi < 0) 1308 rssi = ni->ni_rssi; 1309 1310 if (sc->sc_drvbpf != NULL) { 1311 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1312 uint32_t tsf_lo, tsf_hi; 1313 1314 /* get timestamp (low and high 32 bits) */ 1315 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1316 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1317 1318 tap->wr_tsf = 1319 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1320 tap->wr_flags = 0; 1321 tap->wr_rate = rt2661_rxrate(desc); 1322 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1323 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1324 tap->wr_antsignal = rssi; 1325 1326 bpf_ptap(sc->sc_drvbpf, m, tap, sc->sc_rxtap_len); 1327 } 1328 1329 /* send the frame to the 802.11 layer */ 1330 if (RT2661_RX_CIPHER(flags) != RT2661_CIPHER_NONE) { 1331 struct ieee80211_crypto_iv iv; 1332 1333 memcpy(iv.ic_iv, desc->iv, sizeof(iv.ic_iv)); 1334 memcpy(iv.ic_eiv, desc->eiv, sizeof(iv.ic_eiv)); 1335 ieee80211_input_withiv(ic, m, ni, rssi, 0, &iv); 1336 } else { 1337 ieee80211_input(ic, m, ni, rssi, 0); 1338 } 1339 1340 /* node is no longer needed */ 1341 ieee80211_free_node(ni); 1342 1343 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1344 1345 DPRINTFN(sc, 15, ("rx intr idx=%u\n", sc->rxq.cur)); 1346 1347 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1348 } 1349 1350 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1351 BUS_DMASYNC_PREWRITE); 1352 } 1353 1354 /* ARGSUSED */ 1355 static void 1356 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1357 { 1358 /* do nothing */ 1359 } 1360 1361 static void 1362 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1363 { 1364 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1365 1366 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1367 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1368 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1369 1370 /* send wakeup command to MCU */ 1371 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1372 } 1373 1374 static void 1375 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1376 { 1377 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1378 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1379 } 1380 1381 static void 1382 rt2661_intr(void *arg) 1383 { 1384 struct rt2661_softc *sc = arg; 1385 struct ifnet *ifp = &sc->sc_ic.ic_if; 1386 uint32_t r1, r2; 1387 1388 /* disable MAC and MCU interrupts */ 1389 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1390 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1391 1392 /* don't re-enable interrupts if we're shutting down */ 1393 if (!(ifp->if_flags & IFF_RUNNING)) 1394 return; 1395 1396 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1397 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1398 1399 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1400 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1401 1402 if (r1 & RT2661_MGT_DONE) 1403 rt2661_tx_dma_intr(sc, &sc->mgtq); 1404 1405 if (r1 & RT2661_RX_DONE) 1406 rt2661_rx_intr(sc); 1407 1408 if (r1 & RT2661_TX0_DMA_DONE) 1409 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1410 1411 if (r1 & RT2661_TX1_DMA_DONE) 1412 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1413 1414 if (r1 & RT2661_TX2_DMA_DONE) 1415 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1416 1417 if (r1 & RT2661_TX3_DMA_DONE) 1418 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1419 1420 if (r1 & RT2661_TX_DONE) 1421 rt2661_tx_intr(sc); 1422 1423 if (r2 & RT2661_MCU_CMD_DONE) 1424 rt2661_mcu_cmd_intr(sc); 1425 1426 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1427 rt2661_mcu_beacon_expire(sc); 1428 1429 if (r2 & RT2661_MCU_WAKEUP) 1430 rt2661_mcu_wakeup(sc); 1431 1432 /* re-enable MAC and MCU interrupts */ 1433 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1434 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1435 } 1436 1437 /* quickly determine if a given rate is CCK or OFDM */ 1438 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 1439 1440 #define RAL_ACK_SIZE (sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN) 1441 #define RAL_CTS_SIZE (sizeof(struct ieee80211_frame_cts) + IEEE80211_CRC_LEN) 1442 1443 /* 1444 * This function is only used by the Rx radiotap code. It returns the rate at 1445 * which a given frame was received. 1446 */ 1447 static uint8_t 1448 rt2661_rxrate(struct rt2661_rx_desc *desc) 1449 { 1450 if (le32toh(desc->flags) & RT2661_RX_OFDM) { 1451 /* reverse function of rt2661_plcp_signal */ 1452 switch (desc->rate & 0xf) { 1453 case 0xb: return 12; 1454 case 0xf: return 18; 1455 case 0xa: return 24; 1456 case 0xe: return 36; 1457 case 0x9: return 48; 1458 case 0xd: return 72; 1459 case 0x8: return 96; 1460 case 0xc: return 108; 1461 } 1462 } else { 1463 if (desc->rate == 10) 1464 return 2; 1465 if (desc->rate == 20) 1466 return 4; 1467 if (desc->rate == 55) 1468 return 11; 1469 if (desc->rate == 110) 1470 return 22; 1471 } 1472 return 2; /* should not get there */ 1473 } 1474 1475 static uint8_t 1476 rt2661_plcp_signal(int rate) 1477 { 1478 switch (rate) { 1479 /* CCK rates (returned values are device-dependent) */ 1480 case 2: return 0x0; 1481 case 4: return 0x1; 1482 case 11: return 0x2; 1483 case 22: return 0x3; 1484 1485 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1486 case 12: return 0xb; 1487 case 18: return 0xf; 1488 case 24: return 0xa; 1489 case 36: return 0xe; 1490 case 48: return 0x9; 1491 case 72: return 0xd; 1492 case 96: return 0x8; 1493 case 108: return 0xc; 1494 1495 /* unsupported rates (should not get there) */ 1496 default: return 0xff; 1497 } 1498 } 1499 1500 static void 1501 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1502 uint32_t flags, uint16_t xflags, int len, int rate, 1503 const bus_dma_segment_t *segs, int nsegs, int ac, int ratectl, 1504 const struct ieee80211_key *key, void *buf, 1505 const struct ieee80211_crypto_iv *iv) 1506 { 1507 const struct ieee80211_cipher *cip = NULL; 1508 struct ieee80211com *ic = &sc->sc_ic; 1509 uint16_t plcp_length; 1510 int i, remainder; 1511 1512 if (key != NULL) 1513 cip = key->wk_cipher; 1514 1515 desc->flags = htole32(flags); 1516 desc->flags |= htole32(len << 16); 1517 desc->flags |= htole32(RT2661_TX_VALID); 1518 if (key != NULL) { 1519 int cipher = rt2661_cipher(key); 1520 1521 desc->flags |= htole32(cipher << 29); 1522 desc->flags |= htole32(key->wk_keyix << 10); 1523 if (key->wk_keyix >= IEEE80211_WEP_NKID) 1524 desc->flags |= htole32(RT2661_TX_PAIRWISE_KEY); 1525 1526 /* XXX fragmentation */ 1527 desc->flags |= htole32(RT2661_TX_HWMIC); 1528 } 1529 1530 desc->xflags = htole16(xflags); 1531 desc->xflags |= htole16(nsegs << 13); 1532 if (key != NULL) { 1533 int hdrsize; 1534 1535 hdrsize = ieee80211_hdrspace(ic, buf); 1536 desc->xflags |= htole16(hdrsize); 1537 } 1538 1539 desc->wme = htole16( 1540 RT2661_QID(ac) | 1541 RT2661_AIFSN(2) | 1542 RT2661_LOGCWMIN(4) | 1543 RT2661_LOGCWMAX(10)); 1544 1545 if (key != NULL && iv != NULL) { 1546 memcpy(desc->iv, iv->ic_iv, sizeof(desc->iv)); 1547 memcpy(desc->eiv, iv->ic_eiv, sizeof(desc->eiv)); 1548 } 1549 1550 /* 1551 * Remember whether TX rate control information should be gathered. 1552 * This field is driver private data only. It will be made available 1553 * by the NIC in STA_CSR4 on Tx done interrupts. 1554 */ 1555 desc->qid = ratectl; 1556 1557 /* setup PLCP fields */ 1558 desc->plcp_signal = rt2661_plcp_signal(rate); 1559 desc->plcp_service = 4; 1560 1561 len += IEEE80211_CRC_LEN; 1562 if (cip != NULL) { 1563 len += cip->ic_header + cip->ic_trailer; 1564 1565 /* XXX fragmentation */ 1566 len += cip->ic_miclen; 1567 } 1568 1569 if (RAL_RATE_IS_OFDM(rate)) { 1570 desc->flags |= htole32(RT2661_TX_OFDM); 1571 1572 plcp_length = len & 0xfff; 1573 desc->plcp_length_hi = plcp_length >> 6; 1574 desc->plcp_length_lo = plcp_length & 0x3f; 1575 } else { 1576 plcp_length = (16 * len + rate - 1) / rate; 1577 if (rate == 22) { 1578 remainder = (16 * len) % 22; 1579 if (remainder != 0 && remainder < 7) 1580 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1581 } 1582 desc->plcp_length_hi = plcp_length >> 8; 1583 desc->plcp_length_lo = plcp_length & 0xff; 1584 1585 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1586 desc->plcp_signal |= 0x08; 1587 } 1588 1589 /* RT2x61 supports scatter with up to 5 segments */ 1590 for (i = 0; i < nsegs; i++) { 1591 desc->addr[i] = htole32(segs[i].ds_addr); 1592 desc->len [i] = htole16(segs[i].ds_len); 1593 } 1594 1595 desc->flags |= htole32(RT2661_TX_BUSY); 1596 } 1597 1598 static int 1599 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1600 struct ieee80211_node *ni) 1601 { 1602 struct ieee80211com *ic = &sc->sc_ic; 1603 struct rt2661_tx_desc *desc; 1604 struct rt2661_data *data; 1605 struct ieee80211_frame *wh; 1606 struct rt2661_dmamap map; 1607 uint16_t dur; 1608 uint32_t flags = 0; /* XXX HWSEQ */ 1609 int rate, error; 1610 1611 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1612 data = &sc->mgtq.data[sc->mgtq.cur]; 1613 1614 /* send mgt frames at the lowest available rate */ 1615 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1616 1617 error = bus_dmamap_load_mbuf(sc->mgtq.data_dmat, data->map, m0, 1618 rt2661_dma_map_mbuf, &map, 0); 1619 if (error != 0) { 1620 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1621 error); 1622 ieee80211_free_node(ni); 1623 m_freem(m0); 1624 return error; 1625 } 1626 1627 if (sc->sc_drvbpf != NULL) { 1628 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1629 1630 tap->wt_flags = 0; 1631 tap->wt_rate = rate; 1632 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1633 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1634 1635 bpf_ptap(sc->sc_drvbpf, m0, tap, sc->sc_txtap_len); 1636 } 1637 1638 data->m = m0; 1639 1640 wh = mtod(m0, struct ieee80211_frame *); 1641 1642 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1643 flags |= RT2661_TX_NEED_ACK; 1644 1645 dur = ieee80211_txtime(ni, RAL_ACK_SIZE, rate, ic->ic_flags) + 1646 sc->sc_sifs; 1647 *(uint16_t *)wh->i_dur = htole16(dur); 1648 1649 /* tell hardware to add timestamp in probe responses */ 1650 if ((wh->i_fc[0] & 1651 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1652 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1653 flags |= RT2661_TX_TIMESTAMP; 1654 } 1655 1656 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1657 m0->m_pkthdr.len, rate, map.segs, map.nseg, RT2661_QID_MGT, 0, NULL, NULL, NULL); 1658 1659 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1660 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, 1661 BUS_DMASYNC_PREWRITE); 1662 1663 DPRINTFN(sc, 10, ("sending mgt frame len=%u idx=%u rate=%u\n", 1664 m0->m_pkthdr.len, sc->mgtq.cur, rate)); 1665 1666 /* kick mgt */ 1667 sc->mgtq.queued++; 1668 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1669 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1670 1671 ieee80211_free_node(ni); 1672 1673 return 0; 1674 } 1675 1676 /* 1677 * Build a RTS control frame. 1678 */ 1679 static struct mbuf * 1680 rt2661_get_rts(struct rt2661_softc *sc, struct ieee80211_frame *wh, 1681 uint16_t dur) 1682 { 1683 struct ieee80211_frame_rts *rts; 1684 struct mbuf *m; 1685 1686 MGETHDR(m, MB_DONTWAIT, MT_DATA); 1687 if (m == NULL) { 1688 sc->sc_ic.ic_stats.is_tx_nobuf++; 1689 device_printf(sc->sc_dev, "could not allocate RTS frame\n"); 1690 return NULL; 1691 } 1692 1693 rts = mtod(m, struct ieee80211_frame_rts *); 1694 1695 rts->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL | 1696 IEEE80211_FC0_SUBTYPE_RTS; 1697 rts->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1698 *(uint16_t *)rts->i_dur = htole16(dur); 1699 IEEE80211_ADDR_COPY(rts->i_ra, wh->i_addr1); 1700 IEEE80211_ADDR_COPY(rts->i_ta, wh->i_addr2); 1701 1702 m->m_pkthdr.len = m->m_len = sizeof (struct ieee80211_frame_rts); 1703 1704 return m; 1705 } 1706 1707 static int 1708 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1709 struct ieee80211_node *ni, int ac) 1710 { 1711 struct ieee80211com *ic = &sc->sc_ic; 1712 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1713 struct rt2661_tx_desc *desc; 1714 struct rt2661_data *data; 1715 struct rt2661_tx_ratectl *rctl; 1716 struct ieee80211_frame *wh; 1717 struct ieee80211_key *k = NULL; 1718 const struct chanAccParams *cap; 1719 struct mbuf *mnew; 1720 struct rt2661_dmamap map; 1721 uint16_t dur; 1722 uint32_t flags = 0; 1723 int error, rate, ackrate, noack = 0, rateidx; 1724 struct ieee80211_crypto_iv iv, *ivp = NULL; 1725 1726 wh = mtod(m0, struct ieee80211_frame *); 1727 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 1728 cap = &ic->ic_wme.wme_chanParams; 1729 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 1730 } 1731 1732 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1733 k = ieee80211_crypto_findkey(ic, ni, m0); 1734 if (k == NULL) { 1735 m_freem(m0); 1736 return ENOBUFS; 1737 } 1738 1739 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1740 k = ieee80211_crypto_encap_withkey(ic, m0, k); 1741 } else { 1742 k = ieee80211_crypto_getiv(ic, &iv, k); 1743 ivp = &iv; 1744 } 1745 if (k == NULL) { 1746 m_freem(m0); 1747 return ENOBUFS; 1748 } 1749 1750 if (ivp == NULL) 1751 k = NULL; 1752 1753 /* packet header may have moved, reset our local pointer */ 1754 wh = mtod(m0, struct ieee80211_frame *); 1755 } 1756 1757 ieee80211_ratectl_findrate(ni, m0->m_pkthdr.len, &rateidx, 1); 1758 rate = IEEE80211_RS_RATE(&ni->ni_rates, rateidx); 1759 1760 ackrate = ieee80211_ack_rate(ni, rate); 1761 1762 /* 1763 * IEEE Std 802.11-1999, pp 82: "A STA shall use an RTS/CTS exchange 1764 * for directed frames only when the length of the MPDU is greater 1765 * than the length threshold indicated by [...]" ic_rtsthreshold. 1766 */ 1767 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1768 m0->m_pkthdr.len > ic->ic_rtsthreshold) { 1769 struct mbuf *m; 1770 uint16_t dur; 1771 int rtsrate; 1772 1773 rtsrate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1774 1775 /* XXX: noack (QoS)? */ 1776 dur = ieee80211_txtime(ni, m0->m_pkthdr.len + IEEE80211_CRC_LEN, 1777 rate, ic->ic_flags) + 1778 ieee80211_txtime(ni, RAL_CTS_SIZE, rtsrate, ic->ic_flags)+ 1779 ieee80211_txtime(ni, RAL_ACK_SIZE, ackrate, ic->ic_flags)+ 1780 3 * sc->sc_sifs; 1781 1782 m = rt2661_get_rts(sc, wh, dur); 1783 1784 desc = &txq->desc[txq->cur]; 1785 data = &txq->data[txq->cur]; 1786 1787 error = bus_dmamap_load_mbuf(txq->data_dmat, data->map, m, 1788 rt2661_dma_map_mbuf, &map, 0); 1789 if (error != 0) { 1790 device_printf(sc->sc_dev, 1791 "could not map mbuf (error %d)\n", error); 1792 m_freem(m); 1793 m_freem(m0); 1794 return error; 1795 } 1796 1797 data->m = m; 1798 1799 rt2661_setup_tx_desc(sc, desc, RT2661_TX_NEED_ACK | 1800 RT2661_TX_MORE_FRAG, 0, m->m_pkthdr.len, 1801 rtsrate, map.segs, map.nseg, ac, 0, NULL, NULL, NULL); 1802 1803 bus_dmamap_sync(txq->data_dmat, data->map, 1804 BUS_DMASYNC_PREWRITE); 1805 1806 txq->queued++; 1807 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1808 1809 /* 1810 * IEEE Std 802.11-1999: when an RTS/CTS exchange is used, the 1811 * asynchronous data frame shall be transmitted after the CTS 1812 * frame and a SIFS period. 1813 */ 1814 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1815 } 1816 1817 data = &txq->data[txq->cur]; 1818 desc = &txq->desc[txq->cur]; 1819 1820 error = bus_dmamap_load_mbuf(txq->data_dmat, data->map, m0, 1821 rt2661_dma_map_mbuf, &map, 0); 1822 if (error != 0 && error != EFBIG) { 1823 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1824 error); 1825 m_freem(m0); 1826 return error; 1827 } 1828 if (error != 0) { 1829 mnew = m_defrag(m0, MB_DONTWAIT); 1830 if (mnew == NULL) { 1831 device_printf(sc->sc_dev, 1832 "could not defragment mbuf\n"); 1833 m_freem(m0); 1834 return ENOBUFS; 1835 } 1836 m0 = mnew; 1837 1838 error = bus_dmamap_load_mbuf(txq->data_dmat, data->map, m0, 1839 rt2661_dma_map_mbuf, &map, 0); 1840 if (error != 0) { 1841 device_printf(sc->sc_dev, 1842 "could not map mbuf (error %d)\n", error); 1843 m_freem(m0); 1844 return error; 1845 } 1846 1847 /* packet header have moved, reset our local pointer */ 1848 wh = mtod(m0, struct ieee80211_frame *); 1849 } 1850 1851 if (sc->sc_drvbpf != NULL) { 1852 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1853 1854 tap->wt_flags = 0; 1855 tap->wt_rate = rate; 1856 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1857 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1858 1859 bpf_ptap(sc->sc_drvbpf, m0, tap, sc->sc_txtap_len); 1860 } 1861 1862 data->m = m0; 1863 1864 rctl = kmalloc(sizeof(*rctl), M_RT2661, M_NOWAIT); 1865 if (rctl != NULL) { 1866 rctl->ni = ni; 1867 rctl->len = m0->m_pkthdr.len; 1868 rctl->rateidx = rateidx; 1869 STAILQ_INSERT_TAIL(&sc->tx_ratectl, rctl, link); 1870 } 1871 1872 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1873 flags |= RT2661_TX_NEED_ACK; 1874 1875 dur = ieee80211_txtime(ni, RAL_ACK_SIZE, ackrate, ic->ic_flags)+ 1876 sc->sc_sifs; 1877 *(uint16_t *)wh->i_dur = htole16(dur); 1878 } 1879 1880 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, 1881 map.segs, map.nseg, ac, rctl != NULL, k, wh, ivp); 1882 1883 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1884 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1885 1886 DPRINTFN(sc, 10, ("sending data frame len=%u idx=%u rate=%u\n", 1887 m0->m_pkthdr.len, txq->cur, rate)); 1888 1889 /* kick Tx */ 1890 txq->queued++; 1891 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1892 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); 1893 1894 if (rctl == NULL) 1895 ieee80211_free_node(ni); 1896 1897 return 0; 1898 } 1899 1900 static void 1901 rt2661_start(struct ifnet *ifp) 1902 { 1903 struct rt2661_softc *sc = ifp->if_softc; 1904 struct ieee80211com *ic = &sc->sc_ic; 1905 struct mbuf *m0; 1906 struct ether_header *eh; 1907 struct ieee80211_node *ni; 1908 int ac; 1909 1910 /* prevent management frames from being sent if we're not ready */ 1911 if (!(ifp->if_flags & IFF_RUNNING)) 1912 return; 1913 1914 for (;;) { 1915 IF_POLL(&ic->ic_mgtq, m0); 1916 if (m0 != NULL) { 1917 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1918 ifp->if_flags |= IFF_OACTIVE; 1919 break; 1920 } 1921 IF_DEQUEUE(&ic->ic_mgtq, m0); 1922 1923 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 1924 m0->m_pkthdr.rcvif = NULL; 1925 1926 if (ic->ic_rawbpf != NULL) 1927 bpf_mtap(ic->ic_rawbpf, m0); 1928 1929 if (rt2661_tx_mgt(sc, m0, ni) != 0) 1930 break; 1931 } else { 1932 if (ic->ic_state != IEEE80211_S_RUN) { 1933 ifq_purge(&ifp->if_snd); 1934 break; 1935 } 1936 1937 m0 = ifq_dequeue(&ifp->if_snd, NULL); 1938 if (m0 == NULL) 1939 break; 1940 1941 if (m0->m_len < sizeof (struct ether_header) && 1942 !(m0 = m_pullup(m0, sizeof (struct ether_header)))) 1943 continue; 1944 1945 eh = mtod(m0, struct ether_header *); 1946 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1947 if (ni == NULL) { 1948 m_freem(m0); 1949 ifp->if_oerrors++; 1950 continue; 1951 } 1952 1953 /* classify mbuf so we can find which tx ring to use */ 1954 if (ieee80211_classify(ic, m0, ni) != 0) { 1955 m_freem(m0); 1956 ieee80211_free_node(ni); 1957 ifp->if_oerrors++; 1958 continue; 1959 } 1960 1961 /* no QoS encapsulation for EAPOL frames */ 1962 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 1963 M_WME_GETAC(m0) : WME_AC_BE; 1964 1965 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { 1966 /* there is no place left in this ring */ 1967 ifp->if_flags |= IFF_OACTIVE; 1968 m_freem(m0); 1969 ieee80211_free_node(ni); 1970 break; 1971 } 1972 1973 BPF_MTAP(ifp, m0); 1974 1975 m0 = ieee80211_encap(ic, m0, ni); 1976 if (m0 == NULL) { 1977 ieee80211_free_node(ni); 1978 ifp->if_oerrors++; 1979 continue; 1980 } 1981 1982 if (ic->ic_rawbpf != NULL) 1983 bpf_mtap(ic->ic_rawbpf, m0); 1984 1985 if (rt2661_tx_data(sc, m0, ni, ac) != 0) { 1986 ieee80211_free_node(ni); 1987 ifp->if_oerrors++; 1988 break; 1989 } 1990 } 1991 1992 sc->sc_tx_timer = 5; 1993 ifp->if_timer = 1; 1994 } 1995 } 1996 1997 static void 1998 rt2661_watchdog(struct ifnet *ifp) 1999 { 2000 struct rt2661_softc *sc = ifp->if_softc; 2001 struct ieee80211com *ic = &sc->sc_ic; 2002 2003 ifp->if_timer = 0; 2004 2005 if (sc->sc_tx_timer > 0) { 2006 if (--sc->sc_tx_timer == 0) { 2007 device_printf(sc->sc_dev, "device timeout\n"); 2008 rt2661_init(sc); 2009 ifp->if_oerrors++; 2010 return; 2011 } 2012 ifp->if_timer = 1; 2013 } 2014 2015 ieee80211_watchdog(ic); 2016 } 2017 2018 /* 2019 * This function allows for fast channel switching in monitor mode (used by 2020 * net-mgmt/kismet). In IBSS mode, we must explicitly reset the interface to 2021 * generate a new beacon frame. 2022 */ 2023 static int 2024 rt2661_reset(struct ifnet *ifp) 2025 { 2026 struct rt2661_softc *sc = ifp->if_softc; 2027 struct ieee80211com *ic = &sc->sc_ic; 2028 2029 if (ic->ic_opmode != IEEE80211_M_MONITOR) 2030 return ENETRESET; 2031 2032 rt2661_set_chan(sc, ic->ic_curchan); 2033 2034 return 0; 2035 } 2036 2037 static int 2038 rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 2039 { 2040 struct rt2661_softc *sc = ifp->if_softc; 2041 struct ieee80211com *ic = &sc->sc_ic; 2042 int error = 0; 2043 2044 switch (cmd) { 2045 case SIOCSIFFLAGS: 2046 if (ifp->if_flags & IFF_UP) { 2047 if (ifp->if_flags & IFF_RUNNING) 2048 rt2661_update_promisc(sc); 2049 else 2050 rt2661_init(sc); 2051 } else { 2052 if (ifp->if_flags & IFF_RUNNING) 2053 rt2661_stop(sc); 2054 } 2055 break; 2056 2057 default: 2058 error = ieee80211_ioctl(ic, cmd, data, cr); 2059 } 2060 2061 if (error == ENETRESET) { 2062 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2063 (IFF_UP | IFF_RUNNING) && 2064 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 2065 rt2661_init(sc); 2066 error = 0; 2067 } 2068 return error; 2069 } 2070 2071 static void 2072 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 2073 { 2074 uint32_t tmp; 2075 int ntries; 2076 2077 for (ntries = 0; ntries < 100; ntries++) { 2078 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2079 break; 2080 DELAY(1); 2081 } 2082 if (ntries == 100) { 2083 device_printf(sc->sc_dev, "could not write to BBP\n"); 2084 return; 2085 } 2086 2087 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 2088 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 2089 2090 DPRINTFN(sc, 15, ("BBP R%u <- 0x%02x\n", reg, val)); 2091 2092 /* XXX */ 2093 if (reg == 17) { 2094 DPRINTF(sc, ("record bbp17 %#x\n", val)); 2095 sc->bbp17 = val; 2096 } 2097 } 2098 2099 static uint8_t 2100 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 2101 { 2102 uint32_t val; 2103 int ntries; 2104 2105 for (ntries = 0; ntries < 100; ntries++) { 2106 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2107 break; 2108 DELAY(1); 2109 } 2110 if (ntries == 100) { 2111 device_printf(sc->sc_dev, "could not read from BBP\n"); 2112 return 0; 2113 } 2114 2115 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 2116 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 2117 2118 for (ntries = 0; ntries < 100; ntries++) { 2119 val = RAL_READ(sc, RT2661_PHY_CSR3); 2120 if (!(val & RT2661_BBP_BUSY)) 2121 return val & 0xff; 2122 DELAY(1); 2123 } 2124 2125 device_printf(sc->sc_dev, "could not read from BBP\n"); 2126 return 0; 2127 } 2128 2129 static void 2130 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 2131 { 2132 uint32_t tmp; 2133 int ntries; 2134 2135 for (ntries = 0; ntries < 100; ntries++) { 2136 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 2137 break; 2138 DELAY(1); 2139 } 2140 if (ntries == 100) { 2141 device_printf(sc->sc_dev, "could not write to RF\n"); 2142 return; 2143 } 2144 2145 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 2146 (reg & 3); 2147 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 2148 2149 /* remember last written value in sc */ 2150 sc->rf_regs[reg] = val; 2151 2152 DPRINTFN(sc, 15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff)); 2153 } 2154 2155 static int 2156 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 2157 { 2158 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 2159 return EIO; /* there is already a command pending */ 2160 2161 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 2162 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 2163 2164 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 2165 2166 return 0; 2167 } 2168 2169 static void 2170 rt2661_select_antenna(struct rt2661_softc *sc) 2171 { 2172 uint8_t bbp4, bbp77; 2173 uint32_t tmp; 2174 2175 bbp4 = rt2661_bbp_read(sc, 4); 2176 bbp77 = rt2661_bbp_read(sc, 77); 2177 2178 /* TBD */ 2179 2180 /* make sure Rx is disabled before switching antenna */ 2181 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2182 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2183 2184 rt2661_bbp_write(sc, 4, bbp4); 2185 rt2661_bbp_write(sc, 77, bbp77); 2186 2187 /* restore Rx filter */ 2188 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2189 } 2190 2191 /* 2192 * Enable multi-rate retries for frames sent at OFDM rates. 2193 * In 802.11b/g mode, allow fallback to CCK rates. 2194 */ 2195 static void 2196 rt2661_enable_mrr(struct rt2661_softc *sc) 2197 { 2198 struct ieee80211com *ic = &sc->sc_ic; 2199 uint32_t tmp; 2200 2201 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2202 2203 tmp &= ~RT2661_MRR_CCK_FALLBACK; 2204 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)) 2205 tmp |= RT2661_MRR_CCK_FALLBACK; 2206 tmp |= RT2661_MRR_ENABLED; 2207 tmp |= RT2661_SRETRY_LIMIT(7) | RT2661_LRETRY_LIMIT(4); 2208 2209 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2210 } 2211 2212 static void 2213 rt2661_set_txpreamble(struct rt2661_softc *sc) 2214 { 2215 uint32_t tmp; 2216 2217 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2218 2219 tmp &= ~RT2661_SHORT_PREAMBLE; 2220 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2221 tmp |= RT2661_SHORT_PREAMBLE; 2222 2223 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2224 } 2225 2226 static void 2227 rt2661_set_ackrates(struct rt2661_softc *sc, const struct ieee80211_rateset *rs) 2228 { 2229 #define RV(r) ((r) & IEEE80211_RATE_VAL) 2230 struct ieee80211com *ic = &sc->sc_ic; 2231 uint32_t mask = 0; 2232 uint8_t rate; 2233 int i, j; 2234 2235 for (i = 0; i < rs->rs_nrates; i++) { 2236 rate = rs->rs_rates[i]; 2237 2238 if (!(rate & IEEE80211_RATE_BASIC)) 2239 continue; 2240 2241 /* 2242 * Find h/w rate index. We know it exists because the rate 2243 * set has already been negotiated. 2244 */ 2245 for (j = 0; rt2661_rateset_11g.rs_rates[j] != RV(rate); j++) 2246 ; /* EMPTY */ 2247 2248 mask |= 1 << j; 2249 } 2250 2251 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) && 2252 ic->ic_curmode != IEEE80211_MODE_11B && 2253 ieee80211_iserp_rateset(ic, rs)) { 2254 /* 2255 * Always set following rates as ACK rates to conform 2256 * IEEE Std 802.11g-2003 clause 9.6 2257 * 2258 * 24Mbits/s 0x100 2259 * 12Mbits/s 0x040 2260 * 6Mbits/s 0x010 2261 */ 2262 mask |= 0x150; 2263 } 2264 2265 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 2266 2267 DPRINTF(sc, ("Setting ack rate mask to 0x%x\n", mask)); 2268 #undef RV 2269 } 2270 2271 /* 2272 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 2273 * driver. 2274 */ 2275 static void 2276 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 2277 { 2278 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 2279 uint32_t tmp; 2280 2281 /* update all BBP registers that depend on the band */ 2282 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 2283 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 2284 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2285 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 2286 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 2287 } 2288 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2289 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2290 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 2291 } 2292 2293 rt2661_bbp_write(sc, 17, bbp17); 2294 rt2661_bbp_write(sc, 96, bbp96); 2295 rt2661_bbp_write(sc, 104, bbp104); 2296 2297 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2298 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2299 rt2661_bbp_write(sc, 75, 0x80); 2300 rt2661_bbp_write(sc, 86, 0x80); 2301 rt2661_bbp_write(sc, 88, 0x80); 2302 } 2303 2304 rt2661_bbp_write(sc, 35, bbp35); 2305 rt2661_bbp_write(sc, 97, bbp97); 2306 rt2661_bbp_write(sc, 98, bbp98); 2307 2308 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2309 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2310 if (IEEE80211_IS_CHAN_2GHZ(c)) 2311 tmp |= RT2661_PA_PE_2GHZ; 2312 else 2313 tmp |= RT2661_PA_PE_5GHZ; 2314 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2315 } 2316 2317 static void 2318 rt2661_set_txpower(struct rt2661_softc *sc, int8_t power) 2319 { 2320 const struct rt2661_rfprog *rfprog = sc->rfprog; 2321 int i = sc->sc_curchan_idx; 2322 2323 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2324 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2325 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2326 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2327 2328 DELAY(200); 2329 2330 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2331 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2332 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2333 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2334 2335 DELAY(200); 2336 2337 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2338 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2339 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2340 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2341 2342 sc->sc_txpwr = power; 2343 } 2344 2345 static void 2346 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2347 { 2348 struct ieee80211com *ic = &sc->sc_ic; 2349 const struct rt2661_rfprog *rfprog = sc->rfprog; 2350 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2351 int8_t power; 2352 u_int i, chan; 2353 2354 chan = ieee80211_chan2ieee(ic, c); 2355 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 2356 return; 2357 2358 /* find the settings for this channel (we know it exists) */ 2359 for (i = 0; rfprog[i].chan != chan; i++) 2360 ; /* EMPTY */ 2361 KASSERT(i < RT2661_NCHAN_MAX, ("invalid channel %d\n", chan)); 2362 sc->sc_curchan_idx = i; 2363 2364 power = sc->txpow[i]; 2365 if (power < 0) { 2366 bbp94 += power; 2367 power = 0; 2368 } else if (power > 31) { 2369 bbp94 += power - 31; 2370 power = 31; 2371 } 2372 2373 power = rt2661_txpower(sc, power); 2374 2375 /* 2376 * If we are switching from the 2GHz band to the 5GHz band or 2377 * vice-versa, BBP registers need to be reprogrammed. 2378 */ 2379 if (c->ic_flags != sc->sc_curchan->ic_flags) { 2380 rt2661_select_band(sc, c); 2381 rt2661_select_antenna(sc); 2382 } 2383 sc->sc_curchan = c; 2384 2385 rt2661_set_txpower(sc, power); 2386 2387 /* enable smart mode for MIMO-capable RFs */ 2388 bbp3 = rt2661_bbp_read(sc, 3); 2389 2390 bbp3 &= ~RT2661_SMART_MODE; 2391 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2392 bbp3 |= RT2661_SMART_MODE; 2393 2394 rt2661_bbp_write(sc, 3, bbp3); 2395 2396 if (bbp94 != RT2661_BBPR94_DEFAULT) 2397 rt2661_bbp_write(sc, 94, bbp94); 2398 2399 /* 5GHz radio needs a 1ms delay here */ 2400 if (IEEE80211_IS_CHAN_5GHZ(c)) 2401 DELAY(1000); 2402 2403 sc->sc_sifs = IEEE80211_IS_CHAN_5GHZ(c) ? IEEE80211_DUR_OFDM_SIFS 2404 : IEEE80211_DUR_SIFS; 2405 } 2406 2407 static void 2408 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2409 { 2410 uint32_t tmp; 2411 2412 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2413 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2414 2415 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2416 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2417 } 2418 2419 static void 2420 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2421 { 2422 uint32_t tmp; 2423 2424 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2425 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2426 2427 tmp = addr[4] | addr[5] << 8; 2428 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2429 } 2430 2431 static void 2432 rt2661_update_promisc(struct rt2661_softc *sc) 2433 { 2434 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2435 uint32_t tmp; 2436 2437 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2438 2439 tmp &= ~RT2661_DROP_NOT_TO_ME; 2440 if (!(ifp->if_flags & IFF_PROMISC)) 2441 tmp |= RT2661_DROP_NOT_TO_ME; 2442 2443 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2444 2445 DPRINTF(sc, ("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2446 "entering" : "leaving")); 2447 } 2448 2449 /* 2450 * Update QoS (802.11e) settings for each h/w Tx ring. 2451 */ 2452 static int 2453 rt2661_wme_update(struct ieee80211com *ic) 2454 { 2455 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2456 const struct wmeParams *wmep; 2457 2458 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2459 2460 /* XXX: not sure about shifts. */ 2461 /* XXX: the reference driver plays with AC_VI settings too. */ 2462 2463 /* update TxOp */ 2464 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2465 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2466 wmep[WME_AC_BK].wmep_txopLimit); 2467 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2468 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2469 wmep[WME_AC_VO].wmep_txopLimit); 2470 2471 /* update CWmin */ 2472 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2473 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2474 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2475 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2476 wmep[WME_AC_VO].wmep_logcwmin); 2477 2478 /* update CWmax */ 2479 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2480 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2481 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2482 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2483 wmep[WME_AC_VO].wmep_logcwmax); 2484 2485 /* update Aifsn */ 2486 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2487 wmep[WME_AC_BE].wmep_aifsn << 12 | 2488 wmep[WME_AC_BK].wmep_aifsn << 8 | 2489 wmep[WME_AC_VI].wmep_aifsn << 4 | 2490 wmep[WME_AC_VO].wmep_aifsn); 2491 2492 return 0; 2493 } 2494 2495 static void 2496 rt2661_update_slot(struct ifnet *ifp) 2497 { 2498 struct rt2661_softc *sc = ifp->if_softc; 2499 struct ieee80211com *ic = &sc->sc_ic; 2500 uint8_t slottime; 2501 uint32_t tmp; 2502 2503 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2504 2505 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2506 tmp = (tmp & ~0xff) | slottime; 2507 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2508 } 2509 2510 static const char * 2511 rt2661_get_rf(int rev) 2512 { 2513 switch (rev) { 2514 case RT2661_RF_5225: return "RT5225"; 2515 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2516 case RT2661_RF_2527: return "RT2527"; 2517 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2518 default: return "unknown"; 2519 } 2520 } 2521 2522 static void 2523 rt2661_read_config(struct rt2661_softc *sc) 2524 { 2525 struct ieee80211com *ic = &sc->sc_ic; 2526 uint16_t val; 2527 uint8_t rfprog = 0; 2528 int i, start_chan; 2529 2530 /* read MAC address */ 2531 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2532 ic->ic_myaddr[0] = val & 0xff; 2533 ic->ic_myaddr[1] = val >> 8; 2534 2535 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2536 ic->ic_myaddr[2] = val & 0xff; 2537 ic->ic_myaddr[3] = val >> 8; 2538 2539 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2540 ic->ic_myaddr[4] = val & 0xff; 2541 ic->ic_myaddr[5] = val >> 8; 2542 2543 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2544 /* XXX: test if different from 0xffff? */ 2545 sc->rf_rev = (val >> 11) & 0x1f; 2546 sc->hw_radio = (val >> 10) & 0x1; 2547 sc->auto_txagc = (val >> 9) & 0x1; 2548 sc->rx_ant = (val >> 4) & 0x3; 2549 sc->tx_ant = (val >> 2) & 0x3; 2550 sc->nb_ant = val & 0x3; 2551 2552 DPRINTF(sc, ("RF revision=%d\n", sc->rf_rev)); 2553 DPRINTF(sc, ("Number of ant %d, rxant %d, txant %d\n", 2554 sc->nb_ant, sc->rx_ant, sc->tx_ant)); 2555 2556 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2557 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2558 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2559 2560 DPRINTF(sc, ("External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2561 sc->ext_2ghz_lna, sc->ext_5ghz_lna)); 2562 2563 if (sc->ext_2ghz_lna) { 2564 sc->bbp17_2ghz_min = 0x30; 2565 sc->bbp17_2ghz_max = 0x50; 2566 } else { 2567 sc->bbp17_2ghz_min = 0x20; 2568 sc->bbp17_2ghz_max = 0x40; 2569 } 2570 2571 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2572 sc->rssi_2ghz_corr[0] = (int8_t)(val & 0xff); /* signed */ 2573 sc->rssi_2ghz_corr[1] = (int8_t)(val >> 8); /* signed */ 2574 2575 /* Only [-10, 10] is valid */ 2576 for (i = 0; i < 2; ++i) { 2577 if (sc->rssi_2ghz_corr[i] < -10 || sc->rssi_2ghz_corr[i] > 10) 2578 sc->rssi_2ghz_corr[i] = 0; 2579 } 2580 2581 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2582 if ((val & 0xff) != 0xff) 2583 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2584 2585 /* Only [-10, 10] is valid */ 2586 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10) 2587 sc->rssi_5ghz_corr = 0; 2588 2589 /* adjust RSSI correction for external low-noise amplifier */ 2590 if (sc->ext_2ghz_lna) { 2591 sc->rssi_2ghz_corr[0] -= 14; 2592 sc->rssi_2ghz_corr[1] -= 14; 2593 } 2594 if (sc->ext_5ghz_lna) 2595 sc->rssi_5ghz_corr -= 14; 2596 2597 DPRINTF(sc, ("RSSI 2GHz corr0=%d corr1=%d\nRSSI 5GHz corr=%d\n", 2598 sc->rssi_2ghz_corr[0], sc->rssi_2ghz_corr[1], sc->rssi_5ghz_corr)); 2599 2600 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2601 if ((val >> 8) != 0xff) 2602 rfprog = (val >> 8) & 0x3; 2603 if ((val & 0xff) != 0xff) 2604 sc->rffreq = val & 0xff; 2605 2606 DPRINTF(sc, ("RF prog=%d\nRF freq=%d\n", rfprog, sc->rffreq)); 2607 2608 sc->rfprog = rfprog == 0 ? rt2661_rf5225_1 : rt2661_rf5225_2; 2609 2610 #define NCHAN_2GHZ 14 2611 #define NCHAN_5GHZ 24 2612 /* 2613 * Read channel TX power 2614 */ 2615 start_chan = 0; 2616 rt2661_read_txpower_config(sc, RT2661_EEPROM_TXPOWER_2GHZ, 2617 NCHAN_2GHZ, &start_chan); 2618 rt2661_read_txpower_config(sc, RT2661_EEPROM_TXPOWER_5GHZ, 2619 NCHAN_5GHZ, &start_chan); 2620 #undef NCHAN_2GHZ 2621 #undef NCHAN_5GHZ 2622 2623 /* read vendor-specific BBP values */ 2624 for (i = 0; i < 16; i++) { 2625 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2626 if (val == 0 || val == 0xffff) 2627 continue; /* skip invalid entries */ 2628 sc->bbp_prom[i].reg = val >> 8; 2629 sc->bbp_prom[i].val = val & 0xff; 2630 DPRINTF(sc, ("BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2631 sc->bbp_prom[i].val)); 2632 } 2633 2634 val = rt2661_eeprom_read(sc, RT2661_EEPROM_LED_OFFSET); 2635 DPRINTF(sc, ("LED %02x\n", val)); 2636 if (val == 0xffff) { 2637 sc->mcu_led = RT2661_MCU_LED_DEFAULT; 2638 } else { 2639 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 2640 2641 for (i = 0; i < N(led_ee2mcu); ++i) { 2642 if (val & led_ee2mcu[i].ee_bit) 2643 sc->mcu_led |= led_ee2mcu[i].mcu_bit; 2644 } 2645 2646 #undef N 2647 2648 sc->mcu_led |= ((val >> RT2661_EE_LED_MODE_SHIFT) & 2649 RT2661_EE_LED_MODE_MASK); 2650 } 2651 2652 /* TX power down step array */ 2653 val = rt2661_eeprom_read(sc, RT2661_EEPROM_2GHZ_TSSI1); 2654 sc->tssi_2ghz_down[3] = val & 0xff; 2655 sc->tssi_2ghz_down[2] = val >> 8; 2656 val = rt2661_eeprom_read(sc, RT2661_EEPROM_2GHZ_TSSI2); 2657 sc->tssi_2ghz_down[1] = val & 0xff; 2658 sc->tssi_2ghz_down[0] = val >> 8; 2659 DPRINTF(sc, ("2GHZ tssi down 0:%u 1:%u 2:%u 3:%u\n", 2660 sc->tssi_2ghz_down[0], sc->tssi_2ghz_down[1], 2661 sc->tssi_2ghz_down[2], sc->tssi_2ghz_down[3])); 2662 2663 /* TX power up step array */ 2664 val = rt2661_eeprom_read(sc, RT2661_EEPROM_2GHZ_TSSI3); 2665 sc->tssi_2ghz_up[0] = val & 0xff; 2666 sc->tssi_2ghz_up[1] = val >> 8; 2667 val = rt2661_eeprom_read(sc, RT2661_EEPROM_2GHZ_TSSI4); 2668 sc->tssi_2ghz_up[2] = val & 0xff; 2669 sc->tssi_2ghz_up[3] = val >> 8; 2670 DPRINTF(sc, ("2GHZ tssi up 0:%u 1:%u 2:%u 3:%u\n", 2671 sc->tssi_2ghz_up[0], sc->tssi_2ghz_up[1], 2672 sc->tssi_2ghz_up[2], sc->tssi_2ghz_up[3])); 2673 2674 /* TX power adjustment reference value and step */ 2675 val = rt2661_eeprom_read(sc, RT2661_EEPROM_2GHZ_TSSI5); 2676 sc->tssi_2ghz_ref = val & 0xff; 2677 sc->tssi_2ghz_step = val >> 8; 2678 DPRINTF(sc, ("2GHZ tssi ref %u, step %d\n", 2679 sc->tssi_2ghz_ref, sc->tssi_2ghz_step)); 2680 2681 if (sc->tssi_2ghz_ref == 0xff) 2682 sc->auto_txagc = 0; 2683 DPRINTF(sc, ("Auto TX AGC %d\n", sc->auto_txagc)); 2684 } 2685 2686 static int 2687 rt2661_bbp_init(struct rt2661_softc *sc) 2688 { 2689 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2690 int i, ntries; 2691 uint8_t val; 2692 2693 /* wait for BBP to be ready */ 2694 for (ntries = 0; ntries < 100; ntries++) { 2695 val = rt2661_bbp_read(sc, 0); 2696 if (val != 0 && val != 0xff) 2697 break; 2698 DELAY(100); 2699 } 2700 if (ntries == 100) { 2701 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2702 return EIO; 2703 } 2704 2705 /* initialize BBP registers to default values */ 2706 for (i = 0; i < N(rt2661_def_bbp); i++) { 2707 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2708 rt2661_def_bbp[i].val); 2709 } 2710 2711 /* write vendor-specific BBP values (from EEPROM) */ 2712 for (i = 0; i < 16; i++) { 2713 if (sc->bbp_prom[i].reg == 0) 2714 continue; 2715 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2716 } 2717 2718 return 0; 2719 #undef N 2720 } 2721 2722 static void 2723 rt2661_init(void *priv) 2724 { 2725 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2726 struct rt2661_softc *sc = priv; 2727 struct ieee80211com *ic = &sc->sc_ic; 2728 struct ifnet *ifp = ic->ic_ifp; 2729 uint32_t tmp, sta[3]; 2730 int i, ntries; 2731 2732 rt2661_stop(sc); 2733 2734 /* initialize Tx rings */ 2735 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2736 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2737 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2738 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2739 2740 /* initialize Mgt ring */ 2741 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2742 2743 /* initialize Rx ring */ 2744 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2745 2746 /* initialize Tx rings sizes */ 2747 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2748 RT2661_TX_RING_COUNT << 24 | 2749 RT2661_TX_RING_COUNT << 16 | 2750 RT2661_TX_RING_COUNT << 8 | 2751 RT2661_TX_RING_COUNT); 2752 2753 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2754 RT2661_TX_DESC_WSIZE << 16 | 2755 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2756 RT2661_MGT_RING_COUNT); 2757 2758 /* initialize Rx rings */ 2759 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2760 RT2661_RX_DESC_BACK << 16 | 2761 RT2661_RX_DESC_WSIZE << 8 | 2762 RT2661_RX_RING_COUNT); 2763 2764 /* XXX: some magic here */ 2765 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2766 2767 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2768 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2769 2770 /* load base address of Rx ring */ 2771 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2772 2773 /* initialize MAC registers to default values */ 2774 for (i = 0; i < N(rt2661_def_mac); i++) 2775 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2776 2777 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 2778 rt2661_set_macaddr(sc, ic->ic_myaddr); 2779 2780 /* set host ready */ 2781 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2782 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2783 2784 /* wait for BBP/RF to wakeup */ 2785 for (ntries = 0; ntries < 1000; ntries++) { 2786 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2787 break; 2788 DELAY(1000); 2789 } 2790 if (ntries == 1000) { 2791 kprintf("timeout waiting for BBP/RF to wakeup\n"); 2792 rt2661_stop(sc); 2793 return; 2794 } 2795 2796 if (rt2661_bbp_init(sc) != 0) { 2797 rt2661_stop(sc); 2798 return; 2799 } 2800 2801 /* select default channel */ 2802 sc->sc_curchan = ic->ic_curchan; 2803 rt2661_select_band(sc, sc->sc_curchan); 2804 rt2661_select_antenna(sc); 2805 rt2661_set_chan(sc, sc->sc_curchan); 2806 2807 /* update Rx filter */ 2808 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2809 2810 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2811 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2812 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2813 RT2661_DROP_ACKCTS; 2814 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2815 tmp |= RT2661_DROP_TODS; 2816 if (!(ifp->if_flags & IFF_PROMISC)) 2817 tmp |= RT2661_DROP_NOT_TO_ME; 2818 } 2819 2820 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2821 2822 /* clear STA registers */ 2823 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta)); 2824 2825 /* initialize ASIC */ 2826 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2827 2828 /* clear any pending interrupt */ 2829 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2830 2831 /* enable interrupts */ 2832 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2833 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2834 2835 /* kick Rx */ 2836 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2837 2838 ifp->if_flags &= ~IFF_OACTIVE; 2839 ifp->if_flags |= IFF_RUNNING; 2840 2841 for (i = 0; i < IEEE80211_WEP_NKID; ++i) { 2842 uint8_t mac[IEEE80211_ADDR_LEN]; 2843 const struct ieee80211_key *k = &ic->ic_nw_keys[i]; 2844 2845 if (k->wk_keyix != IEEE80211_KEYIX_NONE) 2846 rt2661_key_set(ic, k, mac); 2847 } 2848 2849 RT2661_RESET_AVG_RSSI(sc); 2850 2851 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2852 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 2853 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2854 } else { 2855 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2856 } 2857 #undef N 2858 } 2859 2860 void 2861 rt2661_stop(void *priv) 2862 { 2863 struct rt2661_softc *sc = priv; 2864 struct ieee80211com *ic = &sc->sc_ic; 2865 struct ifnet *ifp = ic->ic_ifp; 2866 struct rt2661_tx_ratectl *rctl; 2867 uint32_t tmp; 2868 2869 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2870 2871 sc->sc_tx_timer = 0; 2872 ifp->if_timer = 0; 2873 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2874 2875 /* abort Tx (for all 5 Tx rings) */ 2876 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2877 2878 /* disable Rx (value remains after reset!) */ 2879 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2880 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2881 2882 /* reset ASIC */ 2883 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2884 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2885 2886 /* disable interrupts */ 2887 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); 2888 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2889 2890 /* clear any pending interrupt */ 2891 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2892 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2893 2894 while ((rctl = STAILQ_FIRST(&sc->tx_ratectl)) != NULL) { 2895 STAILQ_REMOVE_HEAD(&sc->tx_ratectl, link); 2896 ieee80211_free_node(rctl->ni); 2897 rctl->ni = NULL; 2898 kfree(rctl, M_RT2661); 2899 } 2900 2901 /* reset Tx and Rx rings */ 2902 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2903 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2904 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2905 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2906 rt2661_reset_tx_ring(sc, &sc->mgtq); 2907 rt2661_reset_rx_ring(sc, &sc->rxq); 2908 2909 /* Clear key map. */ 2910 bzero(sc->sc_keymap, sizeof(sc->sc_keymap)); 2911 } 2912 2913 static int 2914 rt2661_load_microcode(struct rt2661_softc *sc, const uint8_t *ucode, int size) 2915 { 2916 int ntries; 2917 2918 /* reset 8051 */ 2919 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2920 2921 /* cancel any pending Host to MCU command */ 2922 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2923 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2924 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2925 2926 /* write 8051's microcode */ 2927 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2928 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, ucode, size); 2929 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2930 2931 /* kick 8051's ass */ 2932 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2933 2934 /* wait for 8051 to initialize */ 2935 for (ntries = 0; ntries < 500; ntries++) { 2936 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2937 break; 2938 DELAY(100); 2939 } 2940 if (ntries == 500) { 2941 kprintf("timeout waiting for MCU to initialize\n"); 2942 return EIO; 2943 } 2944 return 0; 2945 } 2946 2947 static int 2948 rt2661_prepare_beacon(struct rt2661_softc *sc) 2949 { 2950 struct ieee80211com *ic = &sc->sc_ic; 2951 struct ieee80211_beacon_offsets bo; 2952 struct rt2661_tx_desc desc; 2953 struct mbuf *m0; 2954 int rate; 2955 2956 m0 = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo); 2957 if (m0 == NULL) { 2958 device_printf(sc->sc_dev, "could not allocate beacon frame\n"); 2959 return ENOBUFS; 2960 } 2961 2962 /* send beacons at the lowest available rate */ 2963 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan) ? 12 : 2; 2964 2965 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2966 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT, 0, NULL, NULL, NULL); 2967 2968 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2969 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2970 2971 /* copy beacon header and payload into NIC memory */ 2972 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2973 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2974 2975 m_freem(m0); 2976 return 0; 2977 } 2978 2979 /* 2980 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2981 * and HostAP operating modes. 2982 */ 2983 static void 2984 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2985 { 2986 struct ieee80211com *ic = &sc->sc_ic; 2987 uint32_t tmp; 2988 2989 if (ic->ic_opmode != IEEE80211_M_STA) { 2990 /* 2991 * Change default 16ms TBTT adjustment to 8ms. 2992 * Must be done before enabling beacon generation. 2993 */ 2994 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2995 } 2996 2997 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2998 2999 /* set beacon interval (in 1/16ms unit) */ 3000 tmp |= ic->ic_bss->ni_intval * 16; 3001 3002 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 3003 if (ic->ic_opmode == IEEE80211_M_STA) 3004 tmp |= RT2661_TSF_MODE(1); 3005 else 3006 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 3007 3008 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 3009 } 3010 3011 /* 3012 * Retrieve the "Received Signal Strength Indicator" from the raw values 3013 * contained in Rx descriptors. The computation depends on which band the 3014 * frame was received. Correction values taken from the reference driver. 3015 */ 3016 static int 3017 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw, int i) 3018 { 3019 int lna, agc, rssi; 3020 3021 lna = (raw >> 5) & 0x3; 3022 agc = raw & 0x1f; 3023 3024 if (lna == 0) { 3025 /* 3026 * No RSSI mapping 3027 * 3028 * NB: Since RSSI is relative to noise floor, -1 is 3029 * adequate for caller to know error happened. 3030 */ 3031 return -1; 3032 } 3033 3034 rssi = (2 * agc) - RT2661_NOISE_FLOOR; 3035 3036 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 3037 rssi += sc->rssi_2ghz_corr[i]; 3038 3039 if (lna == 1) 3040 rssi -= 64; 3041 else if (lna == 2) 3042 rssi -= 74; 3043 else if (lna == 3) 3044 rssi -= 90; 3045 } else { 3046 rssi += sc->rssi_5ghz_corr; 3047 3048 if (lna == 1) 3049 rssi -= 64; 3050 else if (lna == 2) 3051 rssi -= 86; 3052 else if (lna == 3) 3053 rssi -= 100; 3054 } 3055 3056 if (sc->avg_rssi[i] < 0) { 3057 sc->avg_rssi[i] = rssi; 3058 } else { 3059 sc->avg_rssi[i] = 3060 ((sc->avg_rssi[i] << 3) - sc->avg_rssi[i] + rssi) >> 3; 3061 } 3062 return rssi; 3063 } 3064 3065 static void 3066 rt2661_dma_map_mbuf(void *arg, bus_dma_segment_t *seg, int nseg, 3067 bus_size_t map_size __unused, int error) 3068 { 3069 struct rt2661_dmamap *map = arg; 3070 3071 if (error) 3072 return; 3073 3074 KASSERT(nseg <= RT2661_MAX_SCATTER, ("too many DMA segments")); 3075 3076 bcopy(seg, map->segs, nseg * sizeof(bus_dma_segment_t)); 3077 map->nseg = nseg; 3078 } 3079 3080 static void 3081 rt2661_led_newstate(struct rt2661_softc *sc, enum ieee80211_state nstate) 3082 { 3083 struct ieee80211com *ic = &sc->sc_ic; 3084 uint32_t off, on; 3085 uint32_t mail = sc->mcu_led; 3086 3087 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) { 3088 DPRINTF(sc, ("%s failed\n", __func__)); 3089 return; 3090 } 3091 3092 switch (nstate) { 3093 case IEEE80211_S_INIT: 3094 mail &= ~(RT2661_MCU_LED_LINKA | RT2661_MCU_LED_LINKG | 3095 RT2661_MCU_LED_RF); 3096 break; 3097 default: 3098 if (ic->ic_curchan == NULL) 3099 return; 3100 3101 on = RT2661_MCU_LED_LINKG; 3102 off = RT2661_MCU_LED_LINKA; 3103 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) { 3104 on = RT2661_MCU_LED_LINKA; 3105 off = RT2661_MCU_LED_LINKG; 3106 } 3107 3108 mail |= RT2661_MCU_LED_RF | on; 3109 mail &= ~off; 3110 break; 3111 } 3112 3113 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 3114 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | mail); 3115 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | RT2661_MCU_SET_LED); 3116 } 3117 3118 static void 3119 rt2661_read_txpower_config(struct rt2661_softc *sc, uint8_t txpwr_ofs, 3120 int nchan, int *start_chan0) 3121 { 3122 int i, loop_max; 3123 int start_chan = *start_chan0; 3124 3125 KASSERT(nchan % 2 == 0, ("number of channels %d is not even\n", nchan)); 3126 KASSERT(start_chan + nchan <= RT2661_NCHAN_MAX, ("too many channels")); 3127 3128 loop_max = nchan / 2; 3129 3130 for (i = 0; i < loop_max; i++) { 3131 int chan_idx, j; 3132 uint16_t val; 3133 3134 val = rt2661_eeprom_read(sc, txpwr_ofs + i); 3135 chan_idx = i * 2 + start_chan; 3136 3137 for (j = 0; j < 2; ++j) { 3138 int8_t tx_power; /* signed */ 3139 3140 tx_power = (int8_t)((val >> (8 * j)) & 0xff); 3141 if (tx_power > RT2661_TXPOWER_MAX) 3142 tx_power = RT2661_TXPOWER_DEFAULT; 3143 3144 sc->txpow[chan_idx] = tx_power; 3145 DPRINTF(sc, ("Channel=%d Tx power=%d\n", 3146 rt2661_rf5225_1[chan_idx].chan, sc->txpow[chan_idx])); 3147 3148 ++chan_idx; 3149 } 3150 } 3151 *start_chan0 += nchan; 3152 } 3153 3154 static int 3155 rt2661_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *key, 3156 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 3157 { 3158 struct rt2661_softc *sc = ic->ic_if.if_softc; 3159 3160 DPRINTF(sc, ("%s: ", __func__)); 3161 3162 if (key->wk_flags & IEEE80211_KEY_SWCRYPT) { 3163 DPRINTF(sc, ("alloc sw key\n")); 3164 return sc->sc_key_alloc(ic, key, keyix, rxkeyix); 3165 } 3166 3167 if (key->wk_flags & IEEE80211_KEY_GROUP) { /* Global key */ 3168 DPRINTF(sc, ("alloc group key\n")); 3169 3170 KASSERT(key >= &ic->ic_nw_keys[0] && 3171 key < &ic->ic_nw_keys[IEEE80211_WEP_NKID], 3172 ("bogus group key\n")); 3173 3174 *keyix = *rxkeyix = key - ic->ic_nw_keys; 3175 return 1; 3176 } else { /* Pairwise key */ 3177 int i; 3178 3179 DPRINTF(sc, ("alloc pairwise key\n")); 3180 3181 for (i = IEEE80211_WEP_NKID; i < RT2661_KEY_MAX; ++i) { 3182 if (!RT2661_KEY_ISSET(sc, i)) 3183 break; 3184 } 3185 #ifndef MIXED_KEY_TEST 3186 if (i == RT2661_KEY_MAX) 3187 return 0; 3188 #else 3189 if (i != IEEE80211_WEP_NKID) 3190 return 0; 3191 #endif 3192 3193 RT2661_KEY_SET(sc, i); 3194 *keyix = *rxkeyix = i; 3195 return 1; 3196 } 3197 } 3198 3199 static int 3200 rt2661_key_delete(struct ieee80211com *ic, const struct ieee80211_key *key) 3201 { 3202 struct rt2661_softc *sc = ic->ic_if.if_softc; 3203 uint32_t val; 3204 3205 DPRINTF(sc, ("%s: keyix %d, rxkeyix %d, ", __func__, 3206 key->wk_keyix, key->wk_rxkeyix)); 3207 3208 if (key->wk_flags & IEEE80211_KEY_SWCRYPT) { 3209 DPRINTF(sc, ("delete sw key\n")); 3210 return sc->sc_key_delete(ic, key); 3211 } 3212 3213 if (key->wk_keyix < IEEE80211_WEP_NKID) { /* Global key */ 3214 DPRINTF(sc, ("delete global key\n")); 3215 val = RAL_READ(sc, RT2661_SEC_CSR0); 3216 val &= ~(1 << key->wk_keyix); 3217 RAL_WRITE(sc, RT2661_SEC_CSR0, val); 3218 } else { /* Pairwise key */ 3219 DPRINTF(sc, ("delete pairwise key\n")); 3220 3221 RT2661_KEY_CLR(sc, key->wk_keyix); 3222 if (key->wk_keyix < 32) { 3223 val = RAL_READ(sc, RT2661_SEC_CSR2); 3224 val &= ~(1 << key->wk_keyix); 3225 RAL_WRITE(sc, RT2661_SEC_CSR2, val); 3226 } else { 3227 val = RAL_READ(sc, RT2661_SEC_CSR3); 3228 val &= ~(1 << (key->wk_keyix - 32)); 3229 RAL_WRITE(sc, RT2661_SEC_CSR3, val); 3230 } 3231 } 3232 return 1; 3233 } 3234 3235 static int 3236 rt2661_key_set(struct ieee80211com *ic, const struct ieee80211_key *key, 3237 const uint8_t mac[IEEE80211_ADDR_LEN]) 3238 { 3239 struct rt2661_softc *sc = ic->ic_if.if_softc; 3240 uint32_t addr, val; 3241 3242 DPRINTF(sc, ("%s: keyix %d, rxkeyix %d, flags 0x%04x, ", __func__, 3243 key->wk_keyix, key->wk_rxkeyix, key->wk_flags)); 3244 3245 if (key->wk_flags & IEEE80211_KEY_SWCRYPT) { 3246 DPRINTF(sc, ("set sw key\n")); 3247 return sc->sc_key_set(ic, key, mac); 3248 } 3249 3250 if (key->wk_keyix < IEEE80211_WEP_NKID) { /* Global Key */ 3251 int cipher, keyix_shift; 3252 3253 DPRINTF(sc, ("set global key\n")); 3254 3255 /* 3256 * Install key content. 3257 */ 3258 addr = RT2661_GLOBAL_KEY_BASE + 3259 (key->wk_keyix * sizeof(key->wk_key)); 3260 RAL_WRITE_REGION_1(sc, addr, key->wk_key, sizeof(key->wk_key)); 3261 3262 /* 3263 * Set key cipher. 3264 */ 3265 cipher = rt2661_cipher(key); 3266 keyix_shift = key->wk_keyix * 4; 3267 3268 val = RAL_READ(sc, RT2661_SEC_CSR1); 3269 val &= ~(0xf << keyix_shift); 3270 val |= cipher << keyix_shift; 3271 RAL_WRITE(sc, RT2661_SEC_CSR1, val); 3272 3273 /* 3274 * Enable key slot. 3275 */ 3276 val = RAL_READ(sc, RT2661_SEC_CSR0); 3277 val |= 1 << key->wk_keyix; 3278 RAL_WRITE(sc, RT2661_SEC_CSR0, val); 3279 } else { /* Pairwise key */ 3280 uint8_t mac_cipher[IEEE80211_ADDR_LEN + 1]; 3281 3282 DPRINTF(sc, ("set pairwise key\n")); 3283 3284 /* 3285 * Install key content. 3286 */ 3287 addr = RT2661_PAIRWISE_KEY_BASE + 3288 (key->wk_keyix * sizeof(key->wk_key)); 3289 RAL_WRITE_REGION_1(sc, addr, key->wk_key, sizeof(key->wk_key)); 3290 3291 /* 3292 * Set target address and key cipher. 3293 */ 3294 memcpy(mac_cipher, mac, IEEE80211_ADDR_LEN); 3295 mac_cipher[IEEE80211_ADDR_LEN] = rt2661_cipher(key); 3296 3297 /* XXX Actually slot size is 1 byte bigger than mac_cipher */ 3298 addr = RT2661_TARGET_ADDR_BASE + 3299 (key->wk_keyix * (IEEE80211_ADDR_LEN + 2)); 3300 RAL_WRITE_REGION_1(sc, addr, mac_cipher, sizeof(mac_cipher)); 3301 3302 /* 3303 * Enable key slot. 3304 */ 3305 if (key->wk_keyix < 32) { 3306 val = RAL_READ(sc, RT2661_SEC_CSR2); 3307 val |= 1 << key->wk_keyix; 3308 RAL_WRITE(sc, RT2661_SEC_CSR2, val); 3309 } else { 3310 val = RAL_READ(sc, RT2661_SEC_CSR3); 3311 val |= 1 << (key->wk_keyix - 32); 3312 RAL_WRITE(sc, RT2661_SEC_CSR3, val); 3313 } 3314 3315 /* 3316 * Enable pairwise key looking up when RX. 3317 */ 3318 RAL_WRITE(sc, RT2661_SEC_CSR4, 1); 3319 } 3320 return 1; 3321 } 3322 3323 static void * 3324 rt2661_ratectl_attach(struct ieee80211com *ic, u_int rc) 3325 { 3326 struct rt2661_softc *sc = ic->ic_if.if_softc; 3327 3328 switch (rc) { 3329 case IEEE80211_RATECTL_ONOE: 3330 return &sc->sc_onoe_param; 3331 3332 case IEEE80211_RATECTL_SAMPLE: 3333 if ((ic->ic_ratectl.rc_st_ratectl_cap & 3334 IEEE80211_RATECTL_CAP_SAMPLE) == 0) 3335 panic("sample rate control algo is not supported\n"); 3336 return &sc->sc_sample_param; 3337 3338 case IEEE80211_RATECTL_NONE: 3339 /* This could only happen during detaching */ 3340 return NULL; 3341 3342 default: 3343 panic("unknown rate control algo %u\n", rc); 3344 return NULL; 3345 } 3346 } 3347 3348 static void 3349 rt2661_calib_txpower(struct rt2661_softc *sc) 3350 { 3351 int8_t txpower; 3352 int rssi_dbm; 3353 3354 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 3355 return; 3356 3357 txpower = sc->txpow[sc->sc_curchan_idx]; 3358 if (txpower < 0) 3359 txpower = 0; 3360 else if (txpower > 31) 3361 txpower = 31; 3362 txpower = rt2661_txpower(sc, txpower); 3363 3364 if (sc->auto_txagc) { 3365 /* 3366 * Compensate TX power according to temperature change 3367 */ 3368 if (sc->sc_txpwr_cnt++ % 4 == 0) { 3369 uint8_t bbp1; 3370 int i; 3371 3372 /* 3373 * Adjust compensation very 4 seconds 3374 */ 3375 bbp1 = rt2661_bbp_read(sc, 1); 3376 if (bbp1 > sc->tssi_2ghz_ref) { 3377 for (i = 0; i < RT2661_TSSI_LIMSZ; ++i) { 3378 if (bbp1 <= sc->tssi_2ghz_down[i]) 3379 break; 3380 } 3381 if (txpower > (sc->tssi_2ghz_step * i)) { 3382 sc->tssi_2ghz_comp = 3383 -(sc->tssi_2ghz_step * i); 3384 } else { 3385 sc->tssi_2ghz_comp = -txpower; 3386 } 3387 } else if (bbp1 < sc->tssi_2ghz_ref) { 3388 for (i = 0; i < RT2661_TSSI_LIMSZ; ++i) { 3389 if (bbp1 >= sc->tssi_2ghz_up[i]) 3390 break; 3391 } 3392 sc->tssi_2ghz_comp = sc->tssi_2ghz_step * i; 3393 } 3394 } 3395 txpower += sc->tssi_2ghz_comp; 3396 } 3397 3398 /* 3399 * Adjust TX power according to RSSI 3400 */ 3401 rssi_dbm = rt2661_avgrssi(sc); 3402 DPRINTF(sc, ("dbm %d, txpower %d\n", rssi_dbm, txpower)); 3403 3404 if (rssi_dbm > -30) { 3405 if (txpower > 16) 3406 txpower -= 16; 3407 else 3408 txpower = 0; 3409 } else if (rssi_dbm > -45) { 3410 if (txpower > 6) 3411 txpower -= 6; 3412 else 3413 txpower = 0; 3414 } 3415 3416 if (txpower != sc->sc_txpwr) 3417 rt2661_set_txpower(sc, txpower); 3418 } 3419 3420 static void 3421 rt2661_calib_rxsensibility(struct rt2661_softc *sc, uint32_t false_cca) 3422 { 3423 #define MIDRANGE_RSSI -74 3424 3425 uint8_t bbp17; 3426 int rssi_dbm; 3427 3428 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 3429 return; 3430 3431 rssi_dbm = rt2661_avgrssi(sc); 3432 3433 if (rssi_dbm >= MIDRANGE_RSSI) { 3434 if (rssi_dbm >= -35) 3435 bbp17 = 0x60; 3436 else if (rssi_dbm >= -58) 3437 bbp17 = sc->bbp17_2ghz_max; 3438 else if (rssi_dbm >= -66) 3439 bbp17 = sc->bbp17_2ghz_min + 0x10; 3440 else 3441 bbp17 = sc->bbp17_2ghz_min + 0x8; 3442 3443 if (sc->bbp17 != bbp17) 3444 rt2661_bbp_write(sc, 17, bbp17); 3445 return; 3446 } 3447 3448 bbp17 = sc->bbp17_2ghz_max - (2 * (MIDRANGE_RSSI - rssi_dbm)); 3449 if (bbp17 < sc->bbp17_2ghz_min) 3450 bbp17 = sc->bbp17_2ghz_min; 3451 3452 if (sc->bbp17 > bbp17) { 3453 rt2661_bbp_write(sc, 17, bbp17); 3454 return; 3455 } 3456 3457 DPRINTF(sc, ("calibrate according to false CCA\n")); 3458 3459 if (false_cca > 512 && sc->bbp17 > sc->bbp17_2ghz_min) 3460 rt2661_bbp_write(sc, 17, sc->bbp17 - 1); 3461 else if (false_cca < 100 && sc->bbp17 < bbp17) 3462 rt2661_bbp_write(sc, 17, sc->bbp17 + 1); 3463 3464 #undef MIDRANGE_RSSI 3465 } 3466 3467 static void 3468 rt2661_calibrate(void *xsc) 3469 { 3470 struct rt2661_softc *sc = xsc; 3471 struct ifnet *ifp = &sc->sc_ic.ic_if; 3472 uint32_t false_cca; 3473 3474 lwkt_serialize_enter(ifp->if_serializer); 3475 3476 false_cca = (RAL_READ(sc, RT2661_STA_CSR1) >> 16); 3477 DPRINTF(sc, ("false cca %u\n", false_cca)); 3478 3479 if (sc->sc_calib_rxsns) 3480 rt2661_calib_rxsensibility(sc, false_cca); 3481 3482 if (sc->sc_calib_txpwr) 3483 rt2661_calib_txpower(sc); 3484 3485 callout_reset(&sc->calib_ch, hz, rt2661_calibrate, sc); 3486 3487 lwkt_serialize_exit(ifp->if_serializer); 3488 } 3489