1 /* $FreeBSD: head/sys/dev/ral/rt2661.c 195618 2009-07-11 15:02:45Z rpaulo $ */ 2 3 /*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD: head/sys/dev/ral/rt2661.c 195618 2009-07-11 15:02:45Z rpaulo $ 20 */ 21 22 /*- 23 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 24 * http://www.ralinktech.com/ 25 */ 26 27 #include <sys/param.h> 28 #include <sys/sysctl.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/lock.h> 36 #include <sys/mutex.h> 37 #include <sys/module.h> 38 #include <sys/bus.h> 39 #include <sys/endian.h> 40 #include <sys/firmware.h> 41 #include <sys/rman.h> 42 43 #include <net/bpf.h> 44 #include <net/if.h> 45 #include <net/if_arp.h> 46 #include <net/ethernet.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 #include <net/ifq_var.h> 51 52 #include <netproto/802_11/ieee80211_var.h> 53 #include <netproto/802_11/ieee80211_radiotap.h> 54 #include <netproto/802_11/ieee80211_regdomain.h> 55 #include <netproto/802_11/ieee80211_ratectl.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #include <netinet/if_ether.h> 62 63 #include <dev/netif/ral/rt2661reg.h> 64 #include <dev/netif/ral/rt2661var.h> 65 66 #define RAL_DEBUG 67 #ifdef RAL_DEBUG 68 #define DPRINTF(sc, fmt, ...) do { \ 69 if (sc->sc_debug > 0) \ 70 kprintf(fmt, __VA_ARGS__); \ 71 } while (0) 72 #define DPRINTFN(sc, n, fmt, ...) do { \ 73 if (sc->sc_debug >= (n)) \ 74 kprintf(fmt, __VA_ARGS__); \ 75 } while (0) 76 #else 77 #define DPRINTF(sc, fmt, ...) 78 #define DPRINTFN(sc, n, fmt, ...) 79 #endif 80 81 static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *, 82 const char name[IFNAMSIZ], int unit, int opmode, 83 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 84 const uint8_t mac[IEEE80211_ADDR_LEN]); 85 static void rt2661_vap_delete(struct ieee80211vap *); 86 static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, 87 int); 88 static int rt2661_alloc_tx_ring(struct rt2661_softc *, 89 struct rt2661_tx_ring *, int); 90 static void rt2661_reset_tx_ring(struct rt2661_softc *, 91 struct rt2661_tx_ring *); 92 static void rt2661_free_tx_ring(struct rt2661_softc *, 93 struct rt2661_tx_ring *); 94 static int rt2661_alloc_rx_ring(struct rt2661_softc *, 95 struct rt2661_rx_ring *, int); 96 static void rt2661_reset_rx_ring(struct rt2661_softc *, 97 struct rt2661_rx_ring *); 98 static void rt2661_free_rx_ring(struct rt2661_softc *, 99 struct rt2661_rx_ring *); 100 static void rt2661_newassoc(struct ieee80211_node *, int); 101 static int rt2661_newstate(struct ieee80211vap *, 102 enum ieee80211_state, int); 103 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 104 static void rt2661_rx_intr(struct rt2661_softc *); 105 static void rt2661_tx_intr(struct rt2661_softc *); 106 static void rt2661_tx_dma_intr(struct rt2661_softc *, 107 struct rt2661_tx_ring *); 108 static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 109 static void rt2661_mcu_wakeup(struct rt2661_softc *); 110 static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 111 static void rt2661_scan_start(struct ieee80211com *); 112 static void rt2661_scan_end(struct ieee80211com *); 113 static void rt2661_set_channel(struct ieee80211com *); 114 static void rt2661_setup_tx_desc(struct rt2661_softc *, 115 struct rt2661_tx_desc *, uint32_t, uint16_t, int, 116 int, const bus_dma_segment_t *, int, int); 117 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 118 struct ieee80211_node *, int); 119 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 120 struct ieee80211_node *); 121 static void rt2661_start_locked(struct ifnet *); 122 static void rt2661_start(struct ifnet *, struct ifaltq_subque *); 123 static int rt2661_raw_xmit(struct ieee80211_node *, struct mbuf *, 124 const struct ieee80211_bpf_params *); 125 static void rt2661_watchdog_callout(void *); 126 static int rt2661_ioctl(struct ifnet *, u_long, caddr_t, 127 struct ucred *); 128 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, 129 uint8_t); 130 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 131 static void rt2661_rf_write(struct rt2661_softc *, uint8_t, 132 uint32_t); 133 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, 134 uint16_t); 135 static void rt2661_select_antenna(struct rt2661_softc *); 136 static void rt2661_enable_mrr(struct rt2661_softc *); 137 static void rt2661_set_txpreamble(struct rt2661_softc *); 138 static void rt2661_set_basicrates(struct rt2661_softc *, 139 const struct ieee80211_rateset *); 140 static void rt2661_select_band(struct rt2661_softc *, 141 struct ieee80211_channel *); 142 static void rt2661_set_chan(struct rt2661_softc *, 143 struct ieee80211_channel *); 144 static void rt2661_set_bssid(struct rt2661_softc *, 145 const uint8_t *); 146 static void rt2661_set_macaddr(struct rt2661_softc *, 147 const uint8_t *); 148 static void rt2661_update_promisc(struct ifnet *); 149 static int rt2661_wme_update(struct ieee80211com *) __unused; 150 static void rt2661_update_slot(struct ifnet *); 151 static const char *rt2661_get_rf(int); 152 static void rt2661_read_eeprom(struct rt2661_softc *, 153 uint8_t macaddr[IEEE80211_ADDR_LEN]); 154 static int rt2661_bbp_init(struct rt2661_softc *); 155 static void rt2661_init_locked(struct rt2661_softc *); 156 static void rt2661_init(void *); 157 static void rt2661_stop_locked(struct rt2661_softc *); 158 static void rt2661_stop(void *); 159 static int rt2661_load_microcode(struct rt2661_softc *); 160 #ifdef notyet 161 static void rt2661_rx_tune(struct rt2661_softc *); 162 static void rt2661_radar_start(struct rt2661_softc *); 163 static int rt2661_radar_stop(struct rt2661_softc *); 164 #endif 165 static int rt2661_prepare_beacon(struct rt2661_softc *, 166 struct ieee80211vap *); 167 static void rt2661_enable_tsf_sync(struct rt2661_softc *); 168 static void rt2661_enable_tsf(struct rt2661_softc *); 169 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 170 171 static const struct { 172 uint32_t reg; 173 uint32_t val; 174 } rt2661_def_mac[] = { 175 RT2661_DEF_MAC 176 }; 177 178 static const struct { 179 uint8_t reg; 180 uint8_t val; 181 } rt2661_def_bbp[] = { 182 RT2661_DEF_BBP 183 }; 184 185 static const struct rfprog { 186 uint8_t chan; 187 uint32_t r1, r2, r3, r4; 188 } rt2661_rf5225_1[] = { 189 RT2661_RF5225_1 190 }, rt2661_rf5225_2[] = { 191 RT2661_RF5225_2 192 }; 193 194 int 195 rt2661_attach(device_t dev, int id) 196 { 197 struct rt2661_softc *sc = device_get_softc(dev); 198 struct ieee80211com *ic; 199 struct ifnet *ifp; 200 uint32_t val; 201 int error, ac, ntries; 202 uint8_t bands; 203 uint8_t macaddr[IEEE80211_ADDR_LEN]; 204 struct sysctl_ctx_list *ctx; 205 struct sysctl_oid *tree; 206 207 sc->sc_id = id; 208 sc->sc_dev = dev; 209 210 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 211 if (ifp == NULL) { 212 device_printf(sc->sc_dev, "can not if_alloc()\n"); 213 return ENOMEM; 214 } 215 ic = ifp->if_l2com; 216 217 callout_init(&sc->watchdog_ch); 218 219 /* wait for NIC to initialize */ 220 for (ntries = 0; ntries < 1000; ntries++) { 221 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 222 break; 223 DELAY(1000); 224 } 225 if (ntries == 1000) { 226 device_printf(sc->sc_dev, 227 "timeout waiting for NIC to initialize\n"); 228 error = EIO; 229 goto fail1; 230 } 231 232 /* retrieve RF rev. no and various other things from EEPROM */ 233 rt2661_read_eeprom(sc, macaddr); 234 235 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val, 236 rt2661_get_rf(sc->rf_rev)); 237 238 /* 239 * Allocate Tx and Rx rings. 240 */ 241 for (ac = 0; ac < 4; ac++) { 242 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 243 RT2661_TX_RING_COUNT); 244 if (error != 0) { 245 device_printf(sc->sc_dev, 246 "could not allocate Tx ring %d\n", ac); 247 goto fail2; 248 } 249 } 250 251 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 252 if (error != 0) { 253 device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); 254 goto fail2; 255 } 256 257 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 258 if (error != 0) { 259 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 260 goto fail3; 261 } 262 263 ifp->if_softc = sc; 264 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 265 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 266 ifp->if_init = rt2661_init; 267 ifp->if_ioctl = rt2661_ioctl; 268 ifp->if_start = rt2661_start; 269 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 270 #ifdef notyet 271 ifq_set_ready(&ifp->if_snd); 272 #endif 273 274 ic->ic_ifp = ifp; 275 ic->ic_opmode = IEEE80211_M_STA; 276 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 277 278 /* set device capabilities */ 279 ic->ic_caps = 280 IEEE80211_C_STA /* station mode */ 281 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 282 | IEEE80211_C_HOSTAP /* hostap mode */ 283 | IEEE80211_C_MONITOR /* monitor mode */ 284 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 285 | IEEE80211_C_WDS /* 4-address traffic works */ 286 | IEEE80211_C_MBSS /* mesh point link mode */ 287 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 288 | IEEE80211_C_SHSLOT /* short slot time supported */ 289 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 290 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 291 #ifdef notyet 292 | IEEE80211_C_TXFRAG /* handle tx frags */ 293 | IEEE80211_C_WME /* 802.11e */ 294 #endif 295 ; 296 297 bands = 0; 298 setbit(&bands, IEEE80211_MODE_11B); 299 setbit(&bands, IEEE80211_MODE_11G); 300 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) 301 setbit(&bands, IEEE80211_MODE_11A); 302 ieee80211_init_channels(ic, NULL, &bands); 303 304 ieee80211_ifattach(ic, macaddr); 305 ic->ic_newassoc = rt2661_newassoc; 306 #if 0 307 ic->ic_wme.wme_update = rt2661_wme_update; 308 #endif 309 ic->ic_scan_start = rt2661_scan_start; 310 ic->ic_scan_end = rt2661_scan_end; 311 ic->ic_set_channel = rt2661_set_channel; 312 ic->ic_updateslot = rt2661_update_slot; 313 ic->ic_update_promisc = rt2661_update_promisc; 314 ic->ic_raw_xmit = rt2661_raw_xmit; 315 316 ic->ic_vap_create = rt2661_vap_create; 317 ic->ic_vap_delete = rt2661_vap_delete; 318 319 ieee80211_radiotap_attach(ic, 320 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 321 RT2661_TX_RADIOTAP_PRESENT, 322 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 323 RT2661_RX_RADIOTAP_PRESENT); 324 325 ctx = &sc->sc_sysctl_ctx; 326 sysctl_ctx_init(ctx); 327 tree = SYSCTL_ADD_NODE(ctx, SYSCTL_STATIC_CHILDREN(_hw), 328 OID_AUTO, 329 device_get_nameunit(sc->sc_dev), 330 CTLFLAG_RD, 0, ""); 331 if (tree == NULL) { 332 device_printf(sc->sc_dev, "can't add sysctl node\n"); 333 return 0; 334 } 335 #ifdef RAL_DEBUG 336 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 337 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 338 #endif 339 if (bootverbose) 340 ieee80211_announce(ic); 341 342 return 0; 343 344 fail3: rt2661_free_tx_ring(sc, &sc->mgtq); 345 fail2: while (--ac >= 0) 346 rt2661_free_tx_ring(sc, &sc->txq[ac]); 347 fail1: 348 if_free(ifp); 349 return error; 350 } 351 352 int 353 rt2661_detach(void *xsc) 354 { 355 struct rt2661_softc *sc = xsc; 356 struct ifnet *ifp = sc->sc_ifp; 357 struct ieee80211com *ic = ifp->if_l2com; 358 359 rt2661_stop_locked(sc); 360 361 ieee80211_ifdetach(ic); 362 363 rt2661_free_tx_ring(sc, &sc->txq[0]); 364 rt2661_free_tx_ring(sc, &sc->txq[1]); 365 rt2661_free_tx_ring(sc, &sc->txq[2]); 366 rt2661_free_tx_ring(sc, &sc->txq[3]); 367 rt2661_free_tx_ring(sc, &sc->mgtq); 368 rt2661_free_rx_ring(sc, &sc->rxq); 369 370 if_free(ifp); 371 372 return 0; 373 } 374 375 static struct ieee80211vap * 376 rt2661_vap_create(struct ieee80211com *ic, 377 const char name[IFNAMSIZ], int unit, int opmode, int flags, 378 const uint8_t bssid[IEEE80211_ADDR_LEN], 379 const uint8_t mac[IEEE80211_ADDR_LEN]) 380 { 381 struct ifnet *ifp = ic->ic_ifp; 382 struct rt2661_vap *rvp; 383 struct ieee80211vap *vap; 384 385 switch (opmode) { 386 case IEEE80211_M_STA: 387 case IEEE80211_M_IBSS: 388 case IEEE80211_M_AHDEMO: 389 case IEEE80211_M_MONITOR: 390 case IEEE80211_M_HOSTAP: 391 case IEEE80211_M_MBSS: 392 /* XXXRP: TBD */ 393 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 394 if_printf(ifp, "only 1 vap supported\n"); 395 return NULL; 396 } 397 if (opmode == IEEE80211_M_STA) 398 flags |= IEEE80211_CLONE_NOBEACONS; 399 break; 400 case IEEE80211_M_WDS: 401 if (TAILQ_EMPTY(&ic->ic_vaps) || 402 ic->ic_opmode != IEEE80211_M_HOSTAP) { 403 if_printf(ifp, "wds only supported in ap mode\n"); 404 return NULL; 405 } 406 /* 407 * Silently remove any request for a unique 408 * bssid; WDS vap's always share the local 409 * mac address. 410 */ 411 flags &= ~IEEE80211_CLONE_BSSID; 412 break; 413 default: 414 if_printf(ifp, "unknown opmode %d\n", opmode); 415 return NULL; 416 } 417 rvp = (struct rt2661_vap *) kmalloc(sizeof(struct rt2661_vap), 418 M_80211_VAP, M_INTWAIT | M_ZERO); 419 if (rvp == NULL) 420 return NULL; 421 vap = &rvp->ral_vap; 422 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 423 424 /* override state transition machine */ 425 rvp->ral_newstate = vap->iv_newstate; 426 vap->iv_newstate = rt2661_newstate; 427 #if 0 428 vap->iv_update_beacon = rt2661_beacon_update; 429 #endif 430 431 ieee80211_ratectl_init(vap); 432 /* complete setup */ 433 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 434 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 435 ic->ic_opmode = opmode; 436 return vap; 437 } 438 439 static void 440 rt2661_vap_delete(struct ieee80211vap *vap) 441 { 442 struct rt2661_vap *rvp = RT2661_VAP(vap); 443 444 ieee80211_ratectl_deinit(vap); 445 ieee80211_vap_detach(vap); 446 kfree(rvp, M_80211_VAP); 447 } 448 449 void 450 rt2661_shutdown(void *xsc) 451 { 452 struct rt2661_softc *sc = xsc; 453 454 rt2661_stop(sc); 455 } 456 457 void 458 rt2661_suspend(void *xsc) 459 { 460 struct rt2661_softc *sc = xsc; 461 462 rt2661_stop(sc); 463 } 464 465 void 466 rt2661_resume(void *xsc) 467 { 468 struct rt2661_softc *sc = xsc; 469 struct ifnet *ifp = sc->sc_ifp; 470 471 if (ifp->if_flags & IFF_UP) 472 rt2661_init(sc); 473 } 474 475 static void 476 rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 477 { 478 if (error != 0) 479 return; 480 481 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 482 483 *(bus_addr_t *)arg = segs[0].ds_addr; 484 } 485 486 static int 487 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 488 int count) 489 { 490 int i, error; 491 492 ring->count = count; 493 ring->queued = 0; 494 ring->cur = ring->next = ring->stat = 0; 495 496 error = bus_dma_tag_create(ring->desc_dmat, 4, 0, 497 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 498 count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE, 499 0, &ring->desc_dmat); 500 if (error != 0) { 501 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 502 goto fail; 503 } 504 505 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 506 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 507 if (error != 0) { 508 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 509 goto fail; 510 } 511 512 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 513 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 514 0); 515 if (error != 0) { 516 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 517 goto fail; 518 } 519 520 ring->data = kmalloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 521 M_INTWAIT | M_ZERO); 522 if (ring->data == NULL) { 523 device_printf(sc->sc_dev, "could not allocate soft data\n"); 524 error = ENOMEM; 525 goto fail; 526 } 527 528 error = bus_dma_tag_create(ring->data_dmat, 1, 0, 529 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 530 RT2661_MAX_SCATTER, MCLBYTES, 0, &ring->data_dmat); 531 if (error != 0) { 532 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 533 goto fail; 534 } 535 536 for (i = 0; i < count; i++) { 537 error = bus_dmamap_create(ring->data_dmat, 0, 538 &ring->data[i].map); 539 if (error != 0) { 540 device_printf(sc->sc_dev, "could not create DMA map\n"); 541 goto fail; 542 } 543 } 544 545 return 0; 546 547 fail: rt2661_free_tx_ring(sc, ring); 548 return error; 549 } 550 551 static void 552 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 553 { 554 struct rt2661_tx_desc *desc; 555 struct rt2661_tx_data *data; 556 int i; 557 558 for (i = 0; i < ring->count; i++) { 559 desc = &ring->desc[i]; 560 data = &ring->data[i]; 561 562 if (data->m != NULL) { 563 bus_dmamap_sync(ring->data_dmat, data->map, 564 BUS_DMASYNC_POSTWRITE); 565 bus_dmamap_unload(ring->data_dmat, data->map); 566 m_freem(data->m); 567 data->m = NULL; 568 } 569 570 if (data->ni != NULL) { 571 ieee80211_free_node(data->ni); 572 data->ni = NULL; 573 } 574 575 desc->flags = 0; 576 } 577 578 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 579 580 ring->queued = 0; 581 ring->cur = ring->next = ring->stat = 0; 582 } 583 584 static void 585 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 586 { 587 struct rt2661_tx_data *data; 588 int i; 589 590 if (ring->desc != NULL) { 591 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 592 BUS_DMASYNC_POSTWRITE); 593 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 594 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 595 } 596 597 if (ring->desc_dmat != NULL) 598 bus_dma_tag_destroy(ring->desc_dmat); 599 600 if (ring->data != NULL) { 601 for (i = 0; i < ring->count; i++) { 602 data = &ring->data[i]; 603 604 if (data->m != NULL) { 605 bus_dmamap_sync(ring->data_dmat, data->map, 606 BUS_DMASYNC_POSTWRITE); 607 bus_dmamap_unload(ring->data_dmat, data->map); 608 m_freem(data->m); 609 } 610 611 if (data->ni != NULL) 612 ieee80211_free_node(data->ni); 613 614 if (data->map != NULL) 615 bus_dmamap_destroy(ring->data_dmat, data->map); 616 } 617 618 kfree(ring->data, M_DEVBUF); 619 } 620 621 if (ring->data_dmat != NULL) 622 bus_dma_tag_destroy(ring->data_dmat); 623 } 624 625 static int 626 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 627 int count) 628 { 629 struct rt2661_rx_desc *desc; 630 struct rt2661_rx_data *data; 631 bus_addr_t physaddr; 632 int i, error; 633 634 ring->count = count; 635 ring->cur = ring->next = 0; 636 637 error = bus_dma_tag_create(ring->desc_dmat, 4, 0, 638 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 639 count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE, 640 0, &ring->desc_dmat); 641 if (error != 0) { 642 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 643 goto fail; 644 } 645 646 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 647 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 648 if (error != 0) { 649 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 650 goto fail; 651 } 652 653 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 654 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 655 0); 656 if (error != 0) { 657 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 658 goto fail; 659 } 660 661 ring->data = kmalloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 662 M_INTWAIT | M_ZERO); 663 if (ring->data == NULL) { 664 device_printf(sc->sc_dev, "could not allocate soft data\n"); 665 error = ENOMEM; 666 goto fail; 667 } 668 669 /* 670 * Pre-allocate Rx buffers and populate Rx ring. 671 */ 672 error = bus_dma_tag_create(ring->data_dmat, 1, 0, 673 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 674 1, MCLBYTES, 0, &ring->data_dmat); 675 if (error != 0) { 676 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 677 goto fail; 678 } 679 680 for (i = 0; i < count; i++) { 681 desc = &sc->rxq.desc[i]; 682 data = &sc->rxq.data[i]; 683 684 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 685 if (error != 0) { 686 device_printf(sc->sc_dev, "could not create DMA map\n"); 687 goto fail; 688 } 689 690 data->m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 691 if (data->m == NULL) { 692 device_printf(sc->sc_dev, 693 "could not allocate rx mbuf\n"); 694 error = ENOMEM; 695 goto fail; 696 } 697 698 error = bus_dmamap_load(ring->data_dmat, data->map, 699 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, 700 &physaddr, 0); 701 if (error != 0) { 702 device_printf(sc->sc_dev, 703 "could not load rx buf DMA map"); 704 goto fail; 705 } 706 707 desc->flags = htole32(RT2661_RX_BUSY); 708 desc->physaddr = htole32(physaddr); 709 } 710 711 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 712 713 return 0; 714 715 fail: rt2661_free_rx_ring(sc, ring); 716 return error; 717 } 718 719 static void 720 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 721 { 722 int i; 723 724 for (i = 0; i < ring->count; i++) 725 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 726 727 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 728 729 ring->cur = ring->next = 0; 730 } 731 732 static void 733 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 734 { 735 struct rt2661_rx_data *data; 736 int i; 737 738 if (ring->desc != NULL) { 739 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 740 BUS_DMASYNC_POSTWRITE); 741 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 742 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 743 } 744 745 if (ring->desc_dmat != NULL) 746 bus_dma_tag_destroy(ring->desc_dmat); 747 748 if (ring->data != NULL) { 749 for (i = 0; i < ring->count; i++) { 750 data = &ring->data[i]; 751 752 if (data->m != NULL) { 753 bus_dmamap_sync(ring->data_dmat, data->map, 754 BUS_DMASYNC_POSTREAD); 755 bus_dmamap_unload(ring->data_dmat, data->map); 756 m_freem(data->m); 757 } 758 759 if (data->map != NULL) 760 bus_dmamap_destroy(ring->data_dmat, data->map); 761 } 762 763 kfree(ring->data, M_DEVBUF); 764 } 765 766 if (ring->data_dmat != NULL) 767 bus_dma_tag_destroy(ring->data_dmat); 768 } 769 770 static void 771 rt2661_newassoc(struct ieee80211_node *ni, int isnew) 772 { 773 ieee80211_ratectl_node_deinit(ni); 774 ieee80211_ratectl_node_init(ni); 775 } 776 777 static int 778 rt2661_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 779 { 780 struct rt2661_vap *rvp = RT2661_VAP(vap); 781 struct ieee80211com *ic = vap->iv_ic; 782 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 783 int error; 784 785 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 786 uint32_t tmp; 787 788 /* abort TSF synchronization */ 789 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 790 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 791 } 792 793 error = rvp->ral_newstate(vap, nstate, arg); 794 795 if (error == 0 && nstate == IEEE80211_S_RUN) { 796 struct ieee80211_node *ni = vap->iv_bss; 797 798 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 799 rt2661_enable_mrr(sc); 800 rt2661_set_txpreamble(sc); 801 rt2661_set_basicrates(sc, &ni->ni_rates); 802 rt2661_set_bssid(sc, ni->ni_bssid); 803 } 804 805 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 806 vap->iv_opmode == IEEE80211_M_IBSS || 807 vap->iv_opmode == IEEE80211_M_MBSS) { 808 error = rt2661_prepare_beacon(sc, vap); 809 if (error != 0) 810 return error; 811 } 812 if (vap->iv_opmode != IEEE80211_M_MONITOR) 813 rt2661_enable_tsf_sync(sc); 814 else 815 rt2661_enable_tsf(sc); 816 } 817 return error; 818 } 819 820 /* 821 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 822 * 93C66). 823 */ 824 static uint16_t 825 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 826 { 827 uint32_t tmp; 828 uint16_t val; 829 int n; 830 831 /* clock C once before the first command */ 832 RT2661_EEPROM_CTL(sc, 0); 833 834 RT2661_EEPROM_CTL(sc, RT2661_S); 835 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 836 RT2661_EEPROM_CTL(sc, RT2661_S); 837 838 /* write start bit (1) */ 839 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 840 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 841 842 /* write READ opcode (10) */ 843 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 844 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 845 RT2661_EEPROM_CTL(sc, RT2661_S); 846 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 847 848 /* write address (A5-A0 or A7-A0) */ 849 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 850 for (; n >= 0; n--) { 851 RT2661_EEPROM_CTL(sc, RT2661_S | 852 (((addr >> n) & 1) << RT2661_SHIFT_D)); 853 RT2661_EEPROM_CTL(sc, RT2661_S | 854 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 855 } 856 857 RT2661_EEPROM_CTL(sc, RT2661_S); 858 859 /* read data Q15-Q0 */ 860 val = 0; 861 for (n = 15; n >= 0; n--) { 862 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 863 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 864 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 865 RT2661_EEPROM_CTL(sc, RT2661_S); 866 } 867 868 RT2661_EEPROM_CTL(sc, 0); 869 870 /* clear Chip Select and clock C */ 871 RT2661_EEPROM_CTL(sc, RT2661_S); 872 RT2661_EEPROM_CTL(sc, 0); 873 RT2661_EEPROM_CTL(sc, RT2661_C); 874 875 return val; 876 } 877 878 static void 879 rt2661_tx_intr(struct rt2661_softc *sc) 880 { 881 struct ifnet *ifp = sc->sc_ifp; 882 struct rt2661_tx_ring *txq; 883 struct rt2661_tx_data *data; 884 uint32_t val; 885 int qid, retrycnt; 886 struct ieee80211vap *vap; 887 888 for (;;) { 889 struct ieee80211_node *ni; 890 struct mbuf *m; 891 892 val = RAL_READ(sc, RT2661_STA_CSR4); 893 if (!(val & RT2661_TX_STAT_VALID)) 894 break; 895 896 /* retrieve the queue in which this frame was sent */ 897 qid = RT2661_TX_QID(val); 898 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 899 900 /* retrieve rate control algorithm context */ 901 data = &txq->data[txq->stat]; 902 m = data->m; 903 data->m = NULL; 904 905 ni = data->ni; 906 data->ni = NULL; 907 908 /* if no frame has been sent, ignore */ 909 if (ni == NULL) 910 continue; 911 912 vap = ni->ni_vap; 913 914 switch (RT2661_TX_RESULT(val)) { 915 case RT2661_TX_SUCCESS: 916 retrycnt = RT2661_TX_RETRYCNT(val); 917 918 DPRINTFN(sc, 10, "data frame sent successfully after " 919 "%d retries\n", retrycnt); 920 if (data->rix != IEEE80211_FIXED_RATE_NONE) 921 ieee80211_ratectl_tx_complete(vap, ni, 922 IEEE80211_RATECTL_TX_SUCCESS, 923 &retrycnt, NULL); 924 IFNET_STAT_INC(ifp, opackets, 1); 925 break; 926 927 case RT2661_TX_RETRY_FAIL: 928 retrycnt = RT2661_TX_RETRYCNT(val); 929 930 DPRINTFN(sc, 9, "%s\n", 931 "sending data frame failed (too much retries)"); 932 if (data->rix != IEEE80211_FIXED_RATE_NONE) 933 ieee80211_ratectl_tx_complete(vap, ni, 934 IEEE80211_RATECTL_TX_FAILURE, 935 &retrycnt, NULL); 936 IFNET_STAT_INC(ifp, oerrors, 1); 937 break; 938 939 default: 940 /* other failure */ 941 device_printf(sc->sc_dev, 942 "sending data frame failed 0x%08x\n", val); 943 IFNET_STAT_INC(ifp, oerrors, 1); 944 } 945 946 DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat); 947 948 txq->queued--; 949 if (++txq->stat >= txq->count) /* faster than % count */ 950 txq->stat = 0; 951 952 if (m->m_flags & M_TXCB) 953 ieee80211_process_callback(ni, m, 954 RT2661_TX_RESULT(val) != RT2661_TX_SUCCESS); 955 m_freem(m); 956 ieee80211_free_node(ni); 957 } 958 959 sc->sc_tx_timer = 0; 960 ifq_clr_oactive(&ifp->if_snd); 961 962 rt2661_start_locked(ifp); 963 } 964 965 static void 966 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 967 { 968 struct rt2661_tx_desc *desc; 969 struct rt2661_tx_data *data; 970 971 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); 972 973 for (;;) { 974 desc = &txq->desc[txq->next]; 975 data = &txq->data[txq->next]; 976 977 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 978 !(le32toh(desc->flags) & RT2661_TX_VALID)) 979 break; 980 981 bus_dmamap_sync(txq->data_dmat, data->map, 982 BUS_DMASYNC_POSTWRITE); 983 bus_dmamap_unload(txq->data_dmat, data->map); 984 985 /* descriptor is no longer valid */ 986 desc->flags &= ~htole32(RT2661_TX_VALID); 987 988 DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next); 989 990 if (++txq->next >= txq->count) /* faster than % count */ 991 txq->next = 0; 992 } 993 994 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 995 } 996 997 static void 998 rt2661_rx_intr(struct rt2661_softc *sc) 999 { 1000 struct ifnet *ifp = sc->sc_ifp; 1001 struct ieee80211com *ic = ifp->if_l2com; 1002 struct rt2661_rx_desc *desc; 1003 struct rt2661_rx_data *data; 1004 bus_addr_t physaddr; 1005 struct ieee80211_frame *wh; 1006 struct ieee80211_node *ni; 1007 struct mbuf *mnew, *m; 1008 int error; 1009 1010 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1011 BUS_DMASYNC_POSTREAD); 1012 1013 for (;;) { 1014 int8_t rssi, nf; 1015 1016 desc = &sc->rxq.desc[sc->rxq.cur]; 1017 data = &sc->rxq.data[sc->rxq.cur]; 1018 1019 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1020 break; 1021 1022 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1023 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1024 /* 1025 * This should not happen since we did not request 1026 * to receive those frames when we filled TXRX_CSR0. 1027 */ 1028 DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n", 1029 le32toh(desc->flags)); 1030 IFNET_STAT_INC(ifp, ierrors, 1); 1031 goto skip; 1032 } 1033 1034 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1035 IFNET_STAT_INC(ifp, ierrors, 1); 1036 goto skip; 1037 } 1038 1039 /* 1040 * Try to allocate a new mbuf for this ring element and load it 1041 * before processing the current mbuf. If the ring element 1042 * cannot be loaded, drop the received packet and reuse the old 1043 * mbuf. In the unlikely case that the old mbuf can't be 1044 * reloaded either, explicitly panic. 1045 */ 1046 mnew = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1047 if (mnew == NULL) { 1048 IFNET_STAT_INC(ifp, ierrors, 1); 1049 goto skip; 1050 } 1051 1052 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1053 BUS_DMASYNC_POSTREAD); 1054 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1055 1056 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1057 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, 1058 &physaddr, 0); 1059 if (error != 0) { 1060 m_freem(mnew); 1061 1062 /* try to reload the old mbuf */ 1063 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1064 mtod(data->m, void *), MCLBYTES, 1065 rt2661_dma_map_addr, &physaddr, 0); 1066 if (error != 0) { 1067 /* very unlikely that it will fail... */ 1068 panic("%s: could not load old rx mbuf", 1069 device_get_name(sc->sc_dev)); 1070 } 1071 IFNET_STAT_INC(ifp, ierrors, 1); 1072 goto skip; 1073 } 1074 1075 /* 1076 * New mbuf successfully loaded, update Rx ring and continue 1077 * processing. 1078 */ 1079 m = data->m; 1080 data->m = mnew; 1081 desc->physaddr = htole32(physaddr); 1082 1083 /* finalize mbuf */ 1084 m->m_pkthdr.rcvif = ifp; 1085 m->m_pkthdr.len = m->m_len = 1086 (le32toh(desc->flags) >> 16) & 0xfff; 1087 1088 rssi = rt2661_get_rssi(sc, desc->rssi); 1089 /* Error happened during RSSI conversion. */ 1090 if (rssi < 0) 1091 rssi = -30; /* XXX ignored by net80211 */ 1092 nf = RT2661_NOISE_FLOOR; 1093 1094 if (ieee80211_radiotap_active(ic)) { 1095 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1096 uint32_t tsf_lo, tsf_hi; 1097 1098 /* get timestamp (low and high 32 bits) */ 1099 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1100 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1101 1102 tap->wr_tsf = 1103 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1104 tap->wr_flags = 0; 1105 tap->wr_rate = ieee80211_plcp2rate(desc->rate, 1106 (desc->flags & htole32(RT2661_RX_OFDM)) ? 1107 IEEE80211_T_OFDM : IEEE80211_T_CCK); 1108 tap->wr_antsignal = nf + rssi; 1109 tap->wr_antnoise = nf; 1110 } 1111 sc->sc_flags |= RAL_INPUT_RUNNING; 1112 wh = mtod(m, struct ieee80211_frame *); 1113 1114 /* send the frame to the 802.11 layer */ 1115 ni = ieee80211_find_rxnode(ic, 1116 (struct ieee80211_frame_min *)wh); 1117 if (ni != NULL) { 1118 (void) ieee80211_input(ni, m, rssi, nf); 1119 ieee80211_free_node(ni); 1120 } else 1121 (void) ieee80211_input_all(ic, m, rssi, nf); 1122 1123 sc->sc_flags &= ~RAL_INPUT_RUNNING; 1124 1125 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1126 1127 DPRINTFN(sc, 15, "rx intr idx=%u\n", sc->rxq.cur); 1128 1129 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1130 } 1131 1132 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1133 BUS_DMASYNC_PREWRITE); 1134 } 1135 1136 /* ARGSUSED */ 1137 static void 1138 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1139 { 1140 /* do nothing */ 1141 } 1142 1143 static void 1144 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1145 { 1146 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1147 1148 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1149 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1150 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1151 1152 /* send wakeup command to MCU */ 1153 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1154 } 1155 1156 static void 1157 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1158 { 1159 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1160 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1161 } 1162 1163 void 1164 rt2661_intr(void *arg) 1165 { 1166 struct rt2661_softc *sc = arg; 1167 struct ifnet *ifp = sc->sc_ifp; 1168 uint32_t r1, r2; 1169 1170 /* disable MAC and MCU interrupts */ 1171 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1172 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1173 1174 /* don't re-enable interrupts if we're shutting down */ 1175 if (!(ifp->if_flags & IFF_RUNNING)) { 1176 return; 1177 } 1178 1179 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1180 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1181 1182 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1183 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1184 1185 if (r1 & RT2661_MGT_DONE) 1186 rt2661_tx_dma_intr(sc, &sc->mgtq); 1187 1188 if (r1 & RT2661_RX_DONE) 1189 rt2661_rx_intr(sc); 1190 1191 if (r1 & RT2661_TX0_DMA_DONE) 1192 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1193 1194 if (r1 & RT2661_TX1_DMA_DONE) 1195 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1196 1197 if (r1 & RT2661_TX2_DMA_DONE) 1198 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1199 1200 if (r1 & RT2661_TX3_DMA_DONE) 1201 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1202 1203 if (r1 & RT2661_TX_DONE) 1204 rt2661_tx_intr(sc); 1205 1206 if (r2 & RT2661_MCU_CMD_DONE) 1207 rt2661_mcu_cmd_intr(sc); 1208 1209 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1210 rt2661_mcu_beacon_expire(sc); 1211 1212 if (r2 & RT2661_MCU_WAKEUP) 1213 rt2661_mcu_wakeup(sc); 1214 1215 /* re-enable MAC and MCU interrupts */ 1216 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1217 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1218 1219 } 1220 1221 static uint8_t 1222 rt2661_plcp_signal(int rate) 1223 { 1224 switch (rate) { 1225 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1226 case 12: return 0xb; 1227 case 18: return 0xf; 1228 case 24: return 0xa; 1229 case 36: return 0xe; 1230 case 48: return 0x9; 1231 case 72: return 0xd; 1232 case 96: return 0x8; 1233 case 108: return 0xc; 1234 1235 /* CCK rates (NB: not IEEE std, device-specific) */ 1236 case 2: return 0x0; 1237 case 4: return 0x1; 1238 case 11: return 0x2; 1239 case 22: return 0x3; 1240 } 1241 return 0xff; /* XXX unsupported/unknown rate */ 1242 } 1243 1244 static void 1245 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1246 uint32_t flags, uint16_t xflags, int len, int rate, 1247 const bus_dma_segment_t *segs, int nsegs, int ac) 1248 { 1249 struct ifnet *ifp = sc->sc_ifp; 1250 struct ieee80211com *ic = ifp->if_l2com; 1251 uint16_t plcp_length; 1252 int i, remainder; 1253 1254 desc->flags = htole32(flags); 1255 desc->flags |= htole32(len << 16); 1256 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1257 1258 desc->xflags = htole16(xflags); 1259 desc->xflags |= htole16(nsegs << 13); 1260 1261 desc->wme = htole16( 1262 RT2661_QID(ac) | 1263 RT2661_AIFSN(2) | 1264 RT2661_LOGCWMIN(4) | 1265 RT2661_LOGCWMAX(10)); 1266 1267 /* 1268 * Remember in which queue this frame was sent. This field is driver 1269 * private data only. It will be made available by the NIC in STA_CSR4 1270 * on Tx interrupts. 1271 */ 1272 desc->qid = ac; 1273 1274 /* setup PLCP fields */ 1275 desc->plcp_signal = rt2661_plcp_signal(rate); 1276 desc->plcp_service = 4; 1277 1278 len += IEEE80211_CRC_LEN; 1279 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 1280 desc->flags |= htole32(RT2661_TX_OFDM); 1281 1282 plcp_length = len & 0xfff; 1283 desc->plcp_length_hi = plcp_length >> 6; 1284 desc->plcp_length_lo = plcp_length & 0x3f; 1285 } else { 1286 plcp_length = (16 * len + rate - 1) / rate; 1287 if (rate == 22) { 1288 remainder = (16 * len) % 22; 1289 if (remainder != 0 && remainder < 7) 1290 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1291 } 1292 desc->plcp_length_hi = plcp_length >> 8; 1293 desc->plcp_length_lo = plcp_length & 0xff; 1294 1295 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1296 desc->plcp_signal |= 0x08; 1297 } 1298 1299 /* RT2x61 supports scatter with up to 5 segments */ 1300 for (i = 0; i < nsegs; i++) { 1301 desc->addr[i] = htole32(segs[i].ds_addr); 1302 desc->len [i] = htole16(segs[i].ds_len); 1303 } 1304 } 1305 1306 static int 1307 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1308 struct ieee80211_node *ni) 1309 { 1310 struct ieee80211vap *vap = ni->ni_vap; 1311 struct ieee80211com *ic = ni->ni_ic; 1312 struct rt2661_tx_desc *desc; 1313 struct rt2661_tx_data *data; 1314 struct ieee80211_frame *wh; 1315 struct ieee80211_key *k; 1316 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1317 uint16_t dur; 1318 uint32_t flags = 0; /* XXX HWSEQ */ 1319 int nsegs, rate, error; 1320 1321 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1322 data = &sc->mgtq.data[sc->mgtq.cur]; 1323 1324 rate = vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)].mgmtrate; 1325 1326 wh = mtod(m0, struct ieee80211_frame *); 1327 1328 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1329 k = ieee80211_crypto_encap(ni, m0); 1330 if (k == NULL) { 1331 m_freem(m0); 1332 return ENOBUFS; 1333 } 1334 } 1335 1336 error = bus_dmamap_load_mbuf_segment(sc->mgtq.data_dmat, data->map, m0, 1337 segs, 1, &nsegs, BUS_DMA_NOWAIT); 1338 if (error != 0) { 1339 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1340 error); 1341 m_freem(m0); 1342 return error; 1343 } 1344 1345 if (ieee80211_radiotap_active_vap(vap)) { 1346 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1347 1348 tap->wt_flags = 0; 1349 tap->wt_rate = rate; 1350 1351 ieee80211_radiotap_tx(vap, m0); 1352 } 1353 1354 data->m = m0; 1355 data->ni = ni; 1356 /* management frames are not taken into account for amrr */ 1357 data->rix = IEEE80211_FIXED_RATE_NONE; 1358 1359 wh = mtod(m0, struct ieee80211_frame *); 1360 1361 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1362 flags |= RT2661_TX_NEED_ACK; 1363 1364 dur = ieee80211_ack_duration(ic->ic_rt, 1365 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1366 *(uint16_t *)wh->i_dur = htole16(dur); 1367 1368 /* tell hardware to add timestamp in probe responses */ 1369 if ((wh->i_fc[0] & 1370 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1371 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1372 flags |= RT2661_TX_TIMESTAMP; 1373 } 1374 1375 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1376 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT); 1377 1378 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1379 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, 1380 BUS_DMASYNC_PREWRITE); 1381 1382 DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n", 1383 m0->m_pkthdr.len, sc->mgtq.cur, rate); 1384 1385 /* kick mgt */ 1386 sc->mgtq.queued++; 1387 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1388 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1389 1390 return 0; 1391 } 1392 1393 static int 1394 rt2661_sendprot(struct rt2661_softc *sc, int ac, 1395 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1396 { 1397 struct ieee80211com *ic = ni->ni_ic; 1398 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1399 const struct ieee80211_frame *wh; 1400 struct rt2661_tx_desc *desc; 1401 struct rt2661_tx_data *data; 1402 struct mbuf *mprot; 1403 int protrate, pktlen, flags, isshort, error; 1404 uint16_t dur; 1405 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1406 int nsegs; 1407 1408 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1409 ("protection %d", prot)); 1410 1411 wh = mtod(m, const struct ieee80211_frame *); 1412 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1413 1414 protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1415 ieee80211_ack_rate(ic->ic_rt, rate); 1416 1417 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1418 dur = ieee80211_compute_duration(ic->ic_rt, pktlen, rate, isshort) 1419 + ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1420 flags = RT2661_TX_MORE_FRAG; 1421 if (prot == IEEE80211_PROT_RTSCTS) { 1422 /* NB: CTS is the same size as an ACK */ 1423 dur += ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1424 flags |= RT2661_TX_NEED_ACK; 1425 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1426 } else { 1427 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1428 } 1429 if (mprot == NULL) { 1430 /* XXX stat + msg */ 1431 return ENOBUFS; 1432 } 1433 1434 data = &txq->data[txq->cur]; 1435 desc = &txq->desc[txq->cur]; 1436 1437 error = bus_dmamap_load_mbuf_segment(txq->data_dmat, data->map, mprot, segs, 1438 1, &nsegs, BUS_DMA_NOWAIT); 1439 if (error != 0) { 1440 device_printf(sc->sc_dev, 1441 "could not map mbuf (error %d)\n", error); 1442 m_freem(mprot); 1443 return error; 1444 } 1445 1446 data->m = mprot; 1447 data->ni = ieee80211_ref_node(ni); 1448 /* ctl frames are not taken into account for amrr */ 1449 data->rix = IEEE80211_FIXED_RATE_NONE; 1450 1451 rt2661_setup_tx_desc(sc, desc, flags, 0, mprot->m_pkthdr.len, 1452 protrate, segs, 1, ac); 1453 1454 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1455 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1456 1457 txq->queued++; 1458 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1459 1460 return 0; 1461 } 1462 1463 static int 1464 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1465 struct ieee80211_node *ni, int ac) 1466 { 1467 struct ieee80211vap *vap = ni->ni_vap; 1468 struct ifnet *ifp = sc->sc_ifp; 1469 struct ieee80211com *ic = ifp->if_l2com; 1470 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1471 struct rt2661_tx_desc *desc; 1472 struct rt2661_tx_data *data; 1473 struct ieee80211_frame *wh; 1474 const struct ieee80211_txparam *tp; 1475 struct ieee80211_key *k; 1476 const struct chanAccParams *cap; 1477 struct mbuf *mnew; 1478 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1479 uint16_t dur; 1480 uint32_t flags; 1481 int error, nsegs, rate, noack = 0; 1482 1483 wh = mtod(m0, struct ieee80211_frame *); 1484 1485 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1486 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1487 rate = tp->mcastrate; 1488 } else if (m0->m_flags & M_EAPOL) { 1489 rate = tp->mgmtrate; 1490 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1491 rate = tp->ucastrate; 1492 } else { 1493 ieee80211_ratectl_rate(ni, NULL, 0); 1494 rate = ni->ni_txrate; 1495 } 1496 rate &= IEEE80211_RATE_VAL; 1497 1498 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 1499 cap = &ic->ic_wme.wme_chanParams; 1500 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 1501 } 1502 1503 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1504 k = ieee80211_crypto_encap(ni, m0); 1505 if (k == NULL) { 1506 m_freem(m0); 1507 return ENOBUFS; 1508 } 1509 1510 /* packet header may have moved, reset our local pointer */ 1511 wh = mtod(m0, struct ieee80211_frame *); 1512 } 1513 1514 flags = 0; 1515 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1516 int prot = IEEE80211_PROT_NONE; 1517 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1518 prot = IEEE80211_PROT_RTSCTS; 1519 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1520 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1521 prot = ic->ic_protmode; 1522 if (prot != IEEE80211_PROT_NONE) { 1523 error = rt2661_sendprot(sc, ac, m0, ni, prot, rate); 1524 if (error) { 1525 m_freem(m0); 1526 return error; 1527 } 1528 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1529 } 1530 } 1531 1532 data = &txq->data[txq->cur]; 1533 desc = &txq->desc[txq->cur]; 1534 1535 error = bus_dmamap_load_mbuf_segment(txq->data_dmat, data->map, m0, segs, 1536 1, &nsegs, BUS_DMA_NOWAIT); 1537 if (error != 0 && error != EFBIG) { 1538 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1539 error); 1540 m_freem(m0); 1541 return error; 1542 } 1543 if (error != 0) { 1544 mnew = m_defrag(m0, MB_DONTWAIT); 1545 if (mnew == NULL) { 1546 device_printf(sc->sc_dev, 1547 "could not defragment mbuf\n"); 1548 m_freem(m0); 1549 return ENOBUFS; 1550 } 1551 m0 = mnew; 1552 1553 error = bus_dmamap_load_mbuf_segment(txq->data_dmat, data->map, m0, 1554 segs, 1, &nsegs, BUS_DMA_NOWAIT); 1555 if (error != 0) { 1556 device_printf(sc->sc_dev, 1557 "could not map mbuf (error %d)\n", error); 1558 m_freem(m0); 1559 return error; 1560 } 1561 1562 /* packet header have moved, reset our local pointer */ 1563 wh = mtod(m0, struct ieee80211_frame *); 1564 } 1565 1566 if (ieee80211_radiotap_active_vap(vap)) { 1567 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1568 1569 tap->wt_flags = 0; 1570 tap->wt_rate = rate; 1571 1572 ieee80211_radiotap_tx(vap, m0); 1573 } 1574 1575 data->m = m0; 1576 data->ni = ni; 1577 1578 /* remember link conditions for rate adaptation algorithm */ 1579 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) { 1580 data->rix = ni->ni_txrate; 1581 /* XXX probably need last rssi value and not avg */ 1582 data->rssi = ic->ic_node_getrssi(ni); 1583 } else 1584 data->rix = IEEE80211_FIXED_RATE_NONE; 1585 1586 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1587 flags |= RT2661_TX_NEED_ACK; 1588 1589 dur = ieee80211_ack_duration(ic->ic_rt, 1590 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1591 *(uint16_t *)wh->i_dur = htole16(dur); 1592 } 1593 1594 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs, 1595 nsegs, ac); 1596 1597 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1598 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1599 1600 DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n", 1601 m0->m_pkthdr.len, txq->cur, rate); 1602 1603 /* kick Tx */ 1604 txq->queued++; 1605 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1606 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); 1607 1608 return 0; 1609 } 1610 1611 static void 1612 rt2661_start_locked(struct ifnet *ifp) 1613 { 1614 struct rt2661_softc *sc = ifp->if_softc; 1615 struct mbuf *m; 1616 struct ieee80211_node *ni; 1617 int ac; 1618 1619 /* prevent management frames from being sent if we're not ready */ 1620 if (!(ifp->if_flags & IFF_RUNNING) || sc->sc_invalid) 1621 return; 1622 1623 for (;;) { 1624 m = ifq_dequeue(&ifp->if_snd); 1625 if (m == NULL) 1626 break; 1627 1628 ac = M_WME_GETAC(m); 1629 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { 1630 /* there is no place left in this ring */ 1631 ifq_prepend(&ifp->if_snd, m); 1632 ifq_set_oactive(&ifp->if_snd); 1633 break; 1634 } 1635 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1636 if (rt2661_tx_data(sc, m, ni, ac) != 0) { 1637 ieee80211_free_node(ni); 1638 IFNET_STAT_INC(ifp, oerrors, 1); 1639 break; 1640 } 1641 1642 sc->sc_tx_timer = 5; 1643 } 1644 } 1645 1646 static void 1647 rt2661_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1648 { 1649 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1650 rt2661_start_locked(ifp); 1651 } 1652 1653 static int 1654 rt2661_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1655 const struct ieee80211_bpf_params *params) 1656 { 1657 struct ieee80211com *ic = ni->ni_ic; 1658 struct ifnet *ifp = ic->ic_ifp; 1659 struct rt2661_softc *sc = ifp->if_softc; 1660 1661 /* prevent management frames from being sent if we're not ready */ 1662 if (!(ifp->if_flags & IFF_RUNNING)) { 1663 m_freem(m); 1664 ieee80211_free_node(ni); 1665 return ENETDOWN; 1666 } 1667 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1668 ifq_set_oactive(&ifp->if_snd); 1669 m_freem(m); 1670 ieee80211_free_node(ni); 1671 return ENOBUFS; /* XXX */ 1672 } 1673 1674 IFNET_STAT_INC(ifp, opackets, 1); 1675 1676 /* 1677 * Legacy path; interpret frame contents to decide 1678 * precisely how to send the frame. 1679 * XXX raw path 1680 */ 1681 if (rt2661_tx_mgt(sc, m, ni) != 0) 1682 goto bad; 1683 sc->sc_tx_timer = 5; 1684 1685 return 0; 1686 bad: 1687 IFNET_STAT_INC(ifp, oerrors, 1); 1688 ieee80211_free_node(ni); 1689 return EIO; /* XXX */ 1690 } 1691 1692 static void 1693 rt2661_watchdog_callout(void *arg) 1694 { 1695 struct rt2661_softc *sc = (struct rt2661_softc *)arg; 1696 struct ifnet *ifp = sc->sc_ifp; 1697 1698 KASSERT(ifp->if_flags & IFF_RUNNING, ("not running")); 1699 1700 if (sc->sc_invalid) /* card ejected */ 1701 return; 1702 1703 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1704 if_printf(ifp, "device timeout\n"); 1705 rt2661_init_locked(sc); 1706 IFNET_STAT_INC(ifp, oerrors, 1); 1707 /* NB: callout is reset in rt2661_init() */ 1708 return; 1709 } 1710 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog_callout, sc); 1711 1712 } 1713 1714 static int 1715 rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *ucred) 1716 { 1717 struct rt2661_softc *sc = ifp->if_softc; 1718 struct ieee80211com *ic = ifp->if_l2com; 1719 struct ifreq *ifr = (struct ifreq *) data; 1720 int error = 0, startall = 0; 1721 1722 switch (cmd) { 1723 case SIOCSIFFLAGS: 1724 if (ifp->if_flags & IFF_UP) { 1725 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1726 rt2661_init_locked(sc); 1727 startall = 1; 1728 } else 1729 rt2661_update_promisc(ifp); 1730 } else { 1731 if (ifp->if_flags & IFF_RUNNING) 1732 rt2661_stop_locked(sc); 1733 } 1734 if (startall) 1735 ieee80211_start_all(ic); 1736 break; 1737 case SIOCGIFMEDIA: 1738 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1739 break; 1740 case SIOCGIFADDR: 1741 error = ether_ioctl(ifp, cmd, data); 1742 break; 1743 default: 1744 error = EINVAL; 1745 break; 1746 } 1747 return error; 1748 } 1749 1750 static void 1751 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1752 { 1753 uint32_t tmp; 1754 int ntries; 1755 1756 for (ntries = 0; ntries < 100; ntries++) { 1757 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1758 break; 1759 DELAY(1); 1760 } 1761 if (ntries == 100) { 1762 device_printf(sc->sc_dev, "could not write to BBP\n"); 1763 return; 1764 } 1765 1766 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1767 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1768 1769 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val); 1770 } 1771 1772 static uint8_t 1773 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 1774 { 1775 uint32_t val; 1776 int ntries; 1777 1778 for (ntries = 0; ntries < 100; ntries++) { 1779 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1780 break; 1781 DELAY(1); 1782 } 1783 if (ntries == 100) { 1784 device_printf(sc->sc_dev, "could not read from BBP\n"); 1785 return 0; 1786 } 1787 1788 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 1789 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 1790 1791 for (ntries = 0; ntries < 100; ntries++) { 1792 val = RAL_READ(sc, RT2661_PHY_CSR3); 1793 if (!(val & RT2661_BBP_BUSY)) 1794 return val & 0xff; 1795 DELAY(1); 1796 } 1797 1798 device_printf(sc->sc_dev, "could not read from BBP\n"); 1799 return 0; 1800 } 1801 1802 static void 1803 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 1804 { 1805 uint32_t tmp; 1806 int ntries; 1807 1808 for (ntries = 0; ntries < 100; ntries++) { 1809 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 1810 break; 1811 DELAY(1); 1812 } 1813 if (ntries == 100) { 1814 device_printf(sc->sc_dev, "could not write to RF\n"); 1815 return; 1816 } 1817 1818 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 1819 (reg & 3); 1820 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 1821 1822 /* remember last written value in sc */ 1823 sc->rf_regs[reg] = val; 1824 1825 DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff); 1826 } 1827 1828 static int 1829 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 1830 { 1831 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 1832 return EIO; /* there is already a command pending */ 1833 1834 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 1835 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 1836 1837 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 1838 1839 return 0; 1840 } 1841 1842 static void 1843 rt2661_select_antenna(struct rt2661_softc *sc) 1844 { 1845 uint8_t bbp4, bbp77; 1846 uint32_t tmp; 1847 1848 bbp4 = rt2661_bbp_read(sc, 4); 1849 bbp77 = rt2661_bbp_read(sc, 77); 1850 1851 /* TBD */ 1852 1853 /* make sure Rx is disabled before switching antenna */ 1854 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 1855 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 1856 1857 rt2661_bbp_write(sc, 4, bbp4); 1858 rt2661_bbp_write(sc, 77, bbp77); 1859 1860 /* restore Rx filter */ 1861 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 1862 } 1863 1864 /* 1865 * Enable multi-rate retries for frames sent at OFDM rates. 1866 * In 802.11b/g mode, allow fallback to CCK rates. 1867 */ 1868 static void 1869 rt2661_enable_mrr(struct rt2661_softc *sc) 1870 { 1871 struct ifnet *ifp = sc->sc_ifp; 1872 struct ieee80211com *ic = ifp->if_l2com; 1873 uint32_t tmp; 1874 1875 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1876 1877 tmp &= ~RT2661_MRR_CCK_FALLBACK; 1878 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan)) 1879 tmp |= RT2661_MRR_CCK_FALLBACK; 1880 tmp |= RT2661_MRR_ENABLED; 1881 1882 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1883 } 1884 1885 static void 1886 rt2661_set_txpreamble(struct rt2661_softc *sc) 1887 { 1888 struct ifnet *ifp = sc->sc_ifp; 1889 struct ieee80211com *ic = ifp->if_l2com; 1890 uint32_t tmp; 1891 1892 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1893 1894 tmp &= ~RT2661_SHORT_PREAMBLE; 1895 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1896 tmp |= RT2661_SHORT_PREAMBLE; 1897 1898 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1899 } 1900 1901 static void 1902 rt2661_set_basicrates(struct rt2661_softc *sc, 1903 const struct ieee80211_rateset *rs) 1904 { 1905 #define RV(r) ((r) & IEEE80211_RATE_VAL) 1906 struct ifnet *ifp = sc->sc_ifp; 1907 struct ieee80211com *ic = ifp->if_l2com; 1908 uint32_t mask = 0; 1909 uint8_t rate; 1910 int i, j; 1911 1912 for (i = 0; i < rs->rs_nrates; i++) { 1913 rate = rs->rs_rates[i]; 1914 1915 if (!(rate & IEEE80211_RATE_BASIC)) 1916 continue; 1917 1918 /* 1919 * Find h/w rate index. We know it exists because the rate 1920 * set has already been negotiated. 1921 */ 1922 for (j = 0; ic->ic_sup_rates[IEEE80211_MODE_11G].rs_rates[j] != RV(rate); j++); 1923 1924 mask |= 1 << j; 1925 } 1926 1927 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 1928 1929 DPRINTF(sc, "Setting basic rate mask to 0x%x\n", mask); 1930 #undef RV 1931 } 1932 1933 /* 1934 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 1935 * driver. 1936 */ 1937 static void 1938 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 1939 { 1940 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 1941 uint32_t tmp; 1942 1943 /* update all BBP registers that depend on the band */ 1944 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 1945 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 1946 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1947 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 1948 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 1949 } 1950 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1951 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1952 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 1953 } 1954 1955 rt2661_bbp_write(sc, 17, bbp17); 1956 rt2661_bbp_write(sc, 96, bbp96); 1957 rt2661_bbp_write(sc, 104, bbp104); 1958 1959 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1960 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1961 rt2661_bbp_write(sc, 75, 0x80); 1962 rt2661_bbp_write(sc, 86, 0x80); 1963 rt2661_bbp_write(sc, 88, 0x80); 1964 } 1965 1966 rt2661_bbp_write(sc, 35, bbp35); 1967 rt2661_bbp_write(sc, 97, bbp97); 1968 rt2661_bbp_write(sc, 98, bbp98); 1969 1970 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 1971 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 1972 if (IEEE80211_IS_CHAN_2GHZ(c)) 1973 tmp |= RT2661_PA_PE_2GHZ; 1974 else 1975 tmp |= RT2661_PA_PE_5GHZ; 1976 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 1977 } 1978 1979 static void 1980 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 1981 { 1982 struct ifnet *ifp = sc->sc_ifp; 1983 struct ieee80211com *ic = ifp->if_l2com; 1984 const struct rfprog *rfprog; 1985 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 1986 int8_t power; 1987 u_int i, chan; 1988 1989 chan = ieee80211_chan2ieee(ic, c); 1990 KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan)); 1991 1992 /* select the appropriate RF settings based on what EEPROM says */ 1993 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 1994 1995 /* find the settings for this channel (we know it exists) */ 1996 for (i = 0; rfprog[i].chan != chan; i++); 1997 1998 power = sc->txpow[i]; 1999 if (power < 0) { 2000 bbp94 += power; 2001 power = 0; 2002 } else if (power > 31) { 2003 bbp94 += power - 31; 2004 power = 31; 2005 } 2006 2007 /* 2008 * If we are switching from the 2GHz band to the 5GHz band or 2009 * vice-versa, BBP registers need to be reprogrammed. 2010 */ 2011 if (c->ic_flags != sc->sc_curchan->ic_flags) { 2012 rt2661_select_band(sc, c); 2013 rt2661_select_antenna(sc); 2014 } 2015 sc->sc_curchan = c; 2016 2017 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2018 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2019 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2020 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2021 2022 DELAY(200); 2023 2024 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2025 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2026 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2027 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2028 2029 DELAY(200); 2030 2031 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2032 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2033 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2034 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2035 2036 /* enable smart mode for MIMO-capable RFs */ 2037 bbp3 = rt2661_bbp_read(sc, 3); 2038 2039 bbp3 &= ~RT2661_SMART_MODE; 2040 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2041 bbp3 |= RT2661_SMART_MODE; 2042 2043 rt2661_bbp_write(sc, 3, bbp3); 2044 2045 if (bbp94 != RT2661_BBPR94_DEFAULT) 2046 rt2661_bbp_write(sc, 94, bbp94); 2047 2048 /* 5GHz radio needs a 1ms delay here */ 2049 if (IEEE80211_IS_CHAN_5GHZ(c)) 2050 DELAY(1000); 2051 } 2052 2053 static void 2054 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2055 { 2056 uint32_t tmp; 2057 2058 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2059 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2060 2061 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2062 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2063 } 2064 2065 static void 2066 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2067 { 2068 uint32_t tmp; 2069 2070 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2071 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2072 2073 tmp = addr[4] | addr[5] << 8; 2074 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2075 } 2076 2077 static void 2078 rt2661_update_promisc(struct ifnet *ifp) 2079 { 2080 struct rt2661_softc *sc = ifp->if_softc; 2081 uint32_t tmp; 2082 2083 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2084 2085 tmp &= ~RT2661_DROP_NOT_TO_ME; 2086 if (!(ifp->if_flags & IFF_PROMISC)) 2087 tmp |= RT2661_DROP_NOT_TO_ME; 2088 2089 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2090 2091 DPRINTF(sc, "%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2092 "entering" : "leaving"); 2093 } 2094 2095 /* 2096 * Update QoS (802.11e) settings for each h/w Tx ring. 2097 */ 2098 static int 2099 rt2661_wme_update(struct ieee80211com *ic) 2100 { 2101 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2102 const struct wmeParams *wmep; 2103 2104 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2105 2106 /* XXX: not sure about shifts. */ 2107 /* XXX: the reference driver plays with AC_VI settings too. */ 2108 2109 /* update TxOp */ 2110 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2111 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2112 wmep[WME_AC_BK].wmep_txopLimit); 2113 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2114 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2115 wmep[WME_AC_VO].wmep_txopLimit); 2116 2117 /* update CWmin */ 2118 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2119 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2120 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2121 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2122 wmep[WME_AC_VO].wmep_logcwmin); 2123 2124 /* update CWmax */ 2125 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2126 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2127 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2128 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2129 wmep[WME_AC_VO].wmep_logcwmax); 2130 2131 /* update Aifsn */ 2132 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2133 wmep[WME_AC_BE].wmep_aifsn << 12 | 2134 wmep[WME_AC_BK].wmep_aifsn << 8 | 2135 wmep[WME_AC_VI].wmep_aifsn << 4 | 2136 wmep[WME_AC_VO].wmep_aifsn); 2137 2138 return 0; 2139 } 2140 2141 static void 2142 rt2661_update_slot(struct ifnet *ifp) 2143 { 2144 struct rt2661_softc *sc = ifp->if_softc; 2145 struct ieee80211com *ic = ifp->if_l2com; 2146 uint8_t slottime; 2147 uint32_t tmp; 2148 2149 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2150 2151 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2152 tmp = (tmp & ~0xff) | slottime; 2153 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2154 } 2155 2156 static const char * 2157 rt2661_get_rf(int rev) 2158 { 2159 switch (rev) { 2160 case RT2661_RF_5225: return "RT5225"; 2161 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2162 case RT2661_RF_2527: return "RT2527"; 2163 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2164 default: return "unknown"; 2165 } 2166 } 2167 2168 static void 2169 rt2661_read_eeprom(struct rt2661_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 2170 { 2171 uint16_t val; 2172 int i; 2173 2174 /* read MAC address */ 2175 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2176 macaddr[0] = val & 0xff; 2177 macaddr[1] = val >> 8; 2178 2179 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2180 macaddr[2] = val & 0xff; 2181 macaddr[3] = val >> 8; 2182 2183 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2184 macaddr[4] = val & 0xff; 2185 macaddr[5] = val >> 8; 2186 2187 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2188 /* XXX: test if different from 0xffff? */ 2189 sc->rf_rev = (val >> 11) & 0x1f; 2190 sc->hw_radio = (val >> 10) & 0x1; 2191 sc->rx_ant = (val >> 4) & 0x3; 2192 sc->tx_ant = (val >> 2) & 0x3; 2193 sc->nb_ant = val & 0x3; 2194 2195 DPRINTF(sc, "RF revision=%d\n", sc->rf_rev); 2196 2197 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2198 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2199 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2200 2201 DPRINTF(sc, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2202 sc->ext_2ghz_lna, sc->ext_5ghz_lna); 2203 2204 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2205 if ((val & 0xff) != 0xff) 2206 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2207 2208 /* Only [-10, 10] is valid */ 2209 if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10) 2210 sc->rssi_2ghz_corr = 0; 2211 2212 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2213 if ((val & 0xff) != 0xff) 2214 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2215 2216 /* Only [-10, 10] is valid */ 2217 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10) 2218 sc->rssi_5ghz_corr = 0; 2219 2220 /* adjust RSSI correction for external low-noise amplifier */ 2221 if (sc->ext_2ghz_lna) 2222 sc->rssi_2ghz_corr -= 14; 2223 if (sc->ext_5ghz_lna) 2224 sc->rssi_5ghz_corr -= 14; 2225 2226 DPRINTF(sc, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2227 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr); 2228 2229 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2230 if ((val >> 8) != 0xff) 2231 sc->rfprog = (val >> 8) & 0x3; 2232 if ((val & 0xff) != 0xff) 2233 sc->rffreq = val & 0xff; 2234 2235 DPRINTF(sc, "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq); 2236 2237 /* read Tx power for all a/b/g channels */ 2238 for (i = 0; i < 19; i++) { 2239 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2240 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2241 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2242 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]); 2243 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2244 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2245 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]); 2246 } 2247 2248 /* read vendor-specific BBP values */ 2249 for (i = 0; i < 16; i++) { 2250 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2251 if (val == 0 || val == 0xffff) 2252 continue; /* skip invalid entries */ 2253 sc->bbp_prom[i].reg = val >> 8; 2254 sc->bbp_prom[i].val = val & 0xff; 2255 DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2256 sc->bbp_prom[i].val); 2257 } 2258 } 2259 2260 static int 2261 rt2661_bbp_init(struct rt2661_softc *sc) 2262 { 2263 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2264 int i, ntries; 2265 uint8_t val; 2266 2267 /* wait for BBP to be ready */ 2268 for (ntries = 0; ntries < 100; ntries++) { 2269 val = rt2661_bbp_read(sc, 0); 2270 if (val != 0 && val != 0xff) 2271 break; 2272 DELAY(100); 2273 } 2274 if (ntries == 100) { 2275 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2276 return EIO; 2277 } 2278 2279 /* initialize BBP registers to default values */ 2280 for (i = 0; i < N(rt2661_def_bbp); i++) { 2281 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2282 rt2661_def_bbp[i].val); 2283 } 2284 2285 /* write vendor-specific BBP values (from EEPROM) */ 2286 for (i = 0; i < 16; i++) { 2287 if (sc->bbp_prom[i].reg == 0) 2288 continue; 2289 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2290 } 2291 2292 return 0; 2293 #undef N 2294 } 2295 2296 static void 2297 rt2661_init_locked(struct rt2661_softc *sc) 2298 { 2299 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2300 struct ifnet *ifp = sc->sc_ifp; 2301 struct ieee80211com *ic = ifp->if_l2com; 2302 uint32_t tmp, sta[3]; 2303 int i, error, ntries; 2304 2305 if ((sc->sc_flags & RAL_FW_LOADED) == 0) { 2306 error = rt2661_load_microcode(sc); 2307 if (error != 0) { 2308 if_printf(ifp, 2309 "%s: could not load 8051 microcode, error %d\n", 2310 __func__, error); 2311 return; 2312 } 2313 sc->sc_flags |= RAL_FW_LOADED; 2314 } 2315 2316 rt2661_stop_locked(sc); 2317 2318 /* initialize Tx rings */ 2319 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2320 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2321 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2322 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2323 2324 /* initialize Mgt ring */ 2325 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2326 2327 /* initialize Rx ring */ 2328 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2329 2330 /* initialize Tx rings sizes */ 2331 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2332 RT2661_TX_RING_COUNT << 24 | 2333 RT2661_TX_RING_COUNT << 16 | 2334 RT2661_TX_RING_COUNT << 8 | 2335 RT2661_TX_RING_COUNT); 2336 2337 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2338 RT2661_TX_DESC_WSIZE << 16 | 2339 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2340 RT2661_MGT_RING_COUNT); 2341 2342 /* initialize Rx rings */ 2343 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2344 RT2661_RX_DESC_BACK << 16 | 2345 RT2661_RX_DESC_WSIZE << 8 | 2346 RT2661_RX_RING_COUNT); 2347 2348 /* XXX: some magic here */ 2349 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2350 2351 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2352 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2353 2354 /* load base address of Rx ring */ 2355 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2356 2357 /* initialize MAC registers to default values */ 2358 for (i = 0; i < N(rt2661_def_mac); i++) 2359 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2360 2361 rt2661_set_macaddr(sc, IF_LLADDR(ifp)); 2362 2363 /* set host ready */ 2364 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2365 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2366 2367 /* wait for BBP/RF to wakeup */ 2368 for (ntries = 0; ntries < 1000; ntries++) { 2369 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2370 break; 2371 DELAY(1000); 2372 } 2373 if (ntries == 1000) { 2374 kprintf("timeout waiting for BBP/RF to wakeup\n"); 2375 rt2661_stop_locked(sc); 2376 return; 2377 } 2378 2379 if (rt2661_bbp_init(sc) != 0) { 2380 rt2661_stop_locked(sc); 2381 return; 2382 } 2383 2384 /* select default channel */ 2385 sc->sc_curchan = ic->ic_curchan; 2386 rt2661_select_band(sc, sc->sc_curchan); 2387 rt2661_select_antenna(sc); 2388 rt2661_set_chan(sc, sc->sc_curchan); 2389 2390 /* update Rx filter */ 2391 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2392 2393 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2394 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2395 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2396 RT2661_DROP_ACKCTS; 2397 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 2398 ic->ic_opmode != IEEE80211_M_MBSS) 2399 tmp |= RT2661_DROP_TODS; 2400 if (!(ifp->if_flags & IFF_PROMISC)) 2401 tmp |= RT2661_DROP_NOT_TO_ME; 2402 } 2403 2404 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2405 2406 /* clear STA registers */ 2407 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta)); 2408 2409 /* initialize ASIC */ 2410 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2411 2412 /* clear any pending interrupt */ 2413 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2414 2415 /* enable interrupts */ 2416 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2417 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2418 2419 /* kick Rx */ 2420 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2421 2422 ifq_clr_oactive(&ifp->if_snd); 2423 ifp->if_flags |= IFF_RUNNING; 2424 2425 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog_callout, sc); 2426 #undef N 2427 } 2428 2429 static void 2430 rt2661_init(void *priv) 2431 { 2432 struct rt2661_softc *sc = priv; 2433 struct ifnet *ifp = sc->sc_ifp; 2434 struct ieee80211com *ic = ifp->if_l2com; 2435 2436 rt2661_init_locked(sc); 2437 2438 if (ifp->if_flags & IFF_RUNNING) 2439 ieee80211_start_all(ic); /* start all vap's */ 2440 } 2441 2442 void 2443 rt2661_stop_locked(struct rt2661_softc *sc) 2444 { 2445 struct ifnet *ifp = sc->sc_ifp; 2446 uint32_t tmp; 2447 volatile int *flags = &sc->sc_flags; 2448 2449 while (*flags & RAL_INPUT_RUNNING) 2450 zsleep(sc, &wlan_global_serializer, 0, "ralrunning", hz/10); 2451 2452 callout_stop(&sc->watchdog_ch); 2453 sc->sc_tx_timer = 0; 2454 2455 if (ifp->if_flags & IFF_RUNNING) { 2456 ifp->if_flags &= ~IFF_RUNNING; 2457 ifq_clr_oactive(&ifp->if_snd); 2458 2459 /* abort Tx (for all 5 Tx rings) */ 2460 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2461 2462 /* disable Rx (value remains after reset!) */ 2463 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2464 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2465 2466 /* reset ASIC */ 2467 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2468 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2469 2470 /* disable interrupts */ 2471 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); 2472 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2473 2474 /* clear any pending interrupt */ 2475 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2476 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2477 2478 /* reset Tx and Rx rings */ 2479 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2480 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2481 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2482 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2483 rt2661_reset_tx_ring(sc, &sc->mgtq); 2484 rt2661_reset_rx_ring(sc, &sc->rxq); 2485 } 2486 } 2487 2488 void 2489 rt2661_stop(void *priv) 2490 { 2491 struct rt2661_softc *sc = priv; 2492 2493 rt2661_stop_locked(sc); 2494 } 2495 2496 static int 2497 rt2661_load_microcode(struct rt2661_softc *sc) 2498 { 2499 struct ifnet *ifp = sc->sc_ifp; 2500 const struct firmware *fp; 2501 const char *imagename; 2502 int ntries, error; 2503 2504 switch (sc->sc_id) { 2505 case 0x0301: imagename = "rt2561sfw"; break; 2506 case 0x0302: imagename = "rt2561fw"; break; 2507 case 0x0401: imagename = "rt2661fw"; break; 2508 default: 2509 if_printf(ifp, "%s: unexpected pci device id 0x%x, " 2510 "don't know how to retrieve firmware\n", 2511 __func__, sc->sc_id); 2512 return EINVAL; 2513 } 2514 2515 wlan_assert_serialized(); 2516 wlan_serialize_exit(); 2517 fp = firmware_get(imagename); 2518 wlan_serialize_enter(); 2519 2520 if (fp == NULL) { 2521 if_printf(ifp, "%s: unable to retrieve firmware image %s\n", 2522 __func__, imagename); 2523 return EINVAL; 2524 } 2525 2526 /* 2527 * Load 8051 microcode into NIC. 2528 */ 2529 /* reset 8051 */ 2530 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2531 2532 /* cancel any pending Host to MCU command */ 2533 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2534 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2535 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2536 2537 /* write 8051's microcode */ 2538 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2539 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, fp->data, fp->datasize); 2540 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2541 2542 /* kick 8051's ass */ 2543 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2544 2545 /* wait for 8051 to initialize */ 2546 for (ntries = 0; ntries < 500; ntries++) { 2547 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2548 break; 2549 DELAY(100); 2550 } 2551 if (ntries == 500) { 2552 if_printf(ifp, "%s: timeout waiting for MCU to initialize\n", 2553 __func__); 2554 error = EIO; 2555 } else 2556 error = 0; 2557 2558 firmware_put(fp, FIRMWARE_UNLOAD); 2559 return error; 2560 } 2561 2562 #ifdef notyet 2563 /* 2564 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2565 * false CCA count. This function is called periodically (every seconds) when 2566 * in the RUN state. Values taken from the reference driver. 2567 */ 2568 static void 2569 rt2661_rx_tune(struct rt2661_softc *sc) 2570 { 2571 uint8_t bbp17; 2572 uint16_t cca; 2573 int lo, hi, dbm; 2574 2575 /* 2576 * Tuning range depends on operating band and on the presence of an 2577 * external low-noise amplifier. 2578 */ 2579 lo = 0x20; 2580 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2581 lo += 0x08; 2582 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2583 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2584 lo += 0x10; 2585 hi = lo + 0x20; 2586 2587 /* retrieve false CCA count since last call (clear on read) */ 2588 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2589 2590 if (dbm >= -35) { 2591 bbp17 = 0x60; 2592 } else if (dbm >= -58) { 2593 bbp17 = hi; 2594 } else if (dbm >= -66) { 2595 bbp17 = lo + 0x10; 2596 } else if (dbm >= -74) { 2597 bbp17 = lo + 0x08; 2598 } else { 2599 /* RSSI < -74dBm, tune using false CCA count */ 2600 2601 bbp17 = sc->bbp17; /* current value */ 2602 2603 hi -= 2 * (-74 - dbm); 2604 if (hi < lo) 2605 hi = lo; 2606 2607 if (bbp17 > hi) { 2608 bbp17 = hi; 2609 2610 } else if (cca > 512) { 2611 if (++bbp17 > hi) 2612 bbp17 = hi; 2613 } else if (cca < 100) { 2614 if (--bbp17 < lo) 2615 bbp17 = lo; 2616 } 2617 } 2618 2619 if (bbp17 != sc->bbp17) { 2620 rt2661_bbp_write(sc, 17, bbp17); 2621 sc->bbp17 = bbp17; 2622 } 2623 } 2624 2625 /* 2626 * Enter/Leave radar detection mode. 2627 * This is for 802.11h additional regulatory domains. 2628 */ 2629 static void 2630 rt2661_radar_start(struct rt2661_softc *sc) 2631 { 2632 uint32_t tmp; 2633 2634 /* disable Rx */ 2635 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2636 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2637 2638 rt2661_bbp_write(sc, 82, 0x20); 2639 rt2661_bbp_write(sc, 83, 0x00); 2640 rt2661_bbp_write(sc, 84, 0x40); 2641 2642 /* save current BBP registers values */ 2643 sc->bbp18 = rt2661_bbp_read(sc, 18); 2644 sc->bbp21 = rt2661_bbp_read(sc, 21); 2645 sc->bbp22 = rt2661_bbp_read(sc, 22); 2646 sc->bbp16 = rt2661_bbp_read(sc, 16); 2647 sc->bbp17 = rt2661_bbp_read(sc, 17); 2648 sc->bbp64 = rt2661_bbp_read(sc, 64); 2649 2650 rt2661_bbp_write(sc, 18, 0xff); 2651 rt2661_bbp_write(sc, 21, 0x3f); 2652 rt2661_bbp_write(sc, 22, 0x3f); 2653 rt2661_bbp_write(sc, 16, 0xbd); 2654 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2655 rt2661_bbp_write(sc, 64, 0x21); 2656 2657 /* restore Rx filter */ 2658 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2659 } 2660 2661 static int 2662 rt2661_radar_stop(struct rt2661_softc *sc) 2663 { 2664 uint8_t bbp66; 2665 2666 /* read radar detection result */ 2667 bbp66 = rt2661_bbp_read(sc, 66); 2668 2669 /* restore BBP registers values */ 2670 rt2661_bbp_write(sc, 16, sc->bbp16); 2671 rt2661_bbp_write(sc, 17, sc->bbp17); 2672 rt2661_bbp_write(sc, 18, sc->bbp18); 2673 rt2661_bbp_write(sc, 21, sc->bbp21); 2674 rt2661_bbp_write(sc, 22, sc->bbp22); 2675 rt2661_bbp_write(sc, 64, sc->bbp64); 2676 2677 return bbp66 == 1; 2678 } 2679 #endif 2680 2681 static int 2682 rt2661_prepare_beacon(struct rt2661_softc *sc, struct ieee80211vap *vap) 2683 { 2684 struct ieee80211com *ic = vap->iv_ic; 2685 struct ieee80211_beacon_offsets bo; 2686 struct rt2661_tx_desc desc; 2687 struct mbuf *m0; 2688 int rate; 2689 2690 m0 = ieee80211_beacon_alloc(vap->iv_bss, &bo); 2691 if (m0 == NULL) { 2692 device_printf(sc->sc_dev, "could not allocate beacon frame\n"); 2693 return ENOBUFS; 2694 } 2695 2696 /* send beacons at the lowest available rate */ 2697 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 12 : 2; 2698 2699 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2700 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2701 2702 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2703 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2704 2705 /* copy beacon header and payload into NIC memory */ 2706 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2707 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2708 2709 m_freem(m0); 2710 2711 return 0; 2712 } 2713 2714 /* 2715 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2716 * and HostAP operating modes. 2717 */ 2718 static void 2719 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2720 { 2721 struct ifnet *ifp = sc->sc_ifp; 2722 struct ieee80211com *ic = ifp->if_l2com; 2723 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2724 uint32_t tmp; 2725 2726 if (vap->iv_opmode != IEEE80211_M_STA) { 2727 /* 2728 * Change default 16ms TBTT adjustment to 8ms. 2729 * Must be done before enabling beacon generation. 2730 */ 2731 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2732 } 2733 2734 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2735 2736 /* set beacon interval (in 1/16ms unit) */ 2737 tmp |= vap->iv_bss->ni_intval * 16; 2738 2739 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2740 if (vap->iv_opmode == IEEE80211_M_STA) 2741 tmp |= RT2661_TSF_MODE(1); 2742 else 2743 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2744 2745 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2746 } 2747 2748 static void 2749 rt2661_enable_tsf(struct rt2661_softc *sc) 2750 { 2751 RAL_WRITE(sc, RT2661_TXRX_CSR9, 2752 (RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000) 2753 | RT2661_TSF_TICKING | RT2661_TSF_MODE(2)); 2754 } 2755 2756 /* 2757 * Retrieve the "Received Signal Strength Indicator" from the raw values 2758 * contained in Rx descriptors. The computation depends on which band the 2759 * frame was received. Correction values taken from the reference driver. 2760 */ 2761 static int 2762 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 2763 { 2764 int lna, agc, rssi; 2765 2766 lna = (raw >> 5) & 0x3; 2767 agc = raw & 0x1f; 2768 2769 if (lna == 0) { 2770 /* 2771 * No mapping available. 2772 * 2773 * NB: Since RSSI is relative to noise floor, -1 is 2774 * adequate for caller to know error happened. 2775 */ 2776 return -1; 2777 } 2778 2779 rssi = (2 * agc) - RT2661_NOISE_FLOOR; 2780 2781 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 2782 rssi += sc->rssi_2ghz_corr; 2783 2784 if (lna == 1) 2785 rssi -= 64; 2786 else if (lna == 2) 2787 rssi -= 74; 2788 else if (lna == 3) 2789 rssi -= 90; 2790 } else { 2791 rssi += sc->rssi_5ghz_corr; 2792 2793 if (lna == 1) 2794 rssi -= 64; 2795 else if (lna == 2) 2796 rssi -= 86; 2797 else if (lna == 3) 2798 rssi -= 100; 2799 } 2800 return rssi; 2801 } 2802 2803 static void 2804 rt2661_scan_start(struct ieee80211com *ic) 2805 { 2806 struct ifnet *ifp = ic->ic_ifp; 2807 struct rt2661_softc *sc = ifp->if_softc; 2808 uint32_t tmp; 2809 2810 /* abort TSF synchronization */ 2811 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 2812 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff); 2813 rt2661_set_bssid(sc, ifp->if_broadcastaddr); 2814 } 2815 2816 static void 2817 rt2661_scan_end(struct ieee80211com *ic) 2818 { 2819 struct ifnet *ifp = ic->ic_ifp; 2820 struct rt2661_softc *sc = ifp->if_softc; 2821 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2822 2823 rt2661_enable_tsf_sync(sc); 2824 /* XXX keep local copy */ 2825 rt2661_set_bssid(sc, vap->iv_bss->ni_bssid); 2826 } 2827 2828 static void 2829 rt2661_set_channel(struct ieee80211com *ic) 2830 { 2831 struct ifnet *ifp = ic->ic_ifp; 2832 struct rt2661_softc *sc = ifp->if_softc; 2833 2834 rt2661_set_chan(sc, ic->ic_curchan); 2835 } 2836