1 /* 2 * Copyright (c) 2006 3 * Damien Bergamini <damien.bergamini@free.fr> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: src/sys/dev/ral/rt2661reg.h,v 1.1 2006/03/05 20:36:56 damien Exp $ 18 * $DragonFly: src/sys/dev/netif/ral/rt2661reg.h,v 1.11 2008/01/17 13:33:11 sephe Exp $ 19 */ 20 21 #define RT2661_NOISE_FLOOR -95 22 23 #define RT2661_TX_RING_COUNT 32 24 #define RT2661_MGT_RING_COUNT 32 25 #define RT2661_RX_RING_COUNT 64 26 27 #define RT2661_CIPHER_NONE 0 28 #define RT2661_CIPHER_WEP40 1 29 #define RT2661_CIPHER_WEP104 2 30 #define RT2661_CIPHER_TKIP 3 31 #define RT2661_CIPHER_AES 4 32 33 #define RT2661_TX_DESC_SIZE (sizeof (struct rt2661_tx_desc)) 34 #define RT2661_TX_DESC_WSIZE (RT2661_TX_DESC_SIZE / 4) 35 #define RT2661_RX_DESC_SIZE (sizeof (struct rt2661_rx_desc)) 36 #define RT2661_RX_DESC_WSIZE (RT2661_RX_DESC_SIZE / 4) 37 38 #define RT2661_MAX_SCATTER 5 39 40 /* 41 * Control and status registers. 42 */ 43 #define RT2661_HOST_CMD_CSR 0x0008 44 #define RT2661_MCU_CNTL_CSR 0x000c 45 #define RT2661_SOFT_RESET_CSR 0x0010 46 #define RT2661_MCU_INT_SOURCE_CSR 0x0014 47 #define RT2661_MCU_INT_MASK_CSR 0x0018 48 #define RT2661_PCI_USEC_CSR 0x001c 49 #define RT2661_GLOBAL_KEY_BASE 0x1000 50 #define RT2661_PAIRWISE_KEY_BASE 0x1200 51 #define RT2661_TARGET_ADDR_BASE 0x1a00 52 #define RT2661_H2M_MAILBOX_CSR 0x2100 53 #define RT2661_M2H_CMD_DONE_CSR 0x2104 54 #define RT2661_HW_BEACON_BASE0 0x2c00 55 #define RT2661_MAC_CSR0 0x3000 56 #define RT2661_MAC_CSR1 0x3004 57 #define RT2661_MAC_CSR2 0x3008 58 #define RT2661_MAC_CSR3 0x300c 59 #define RT2661_MAC_CSR4 0x3010 60 #define RT2661_MAC_CSR5 0x3014 61 #define RT2661_MAC_CSR6 0x3018 62 #define RT2661_MAC_CSR7 0x301c 63 #define RT2661_MAC_CSR8 0x3020 64 #define RT2661_MAC_CSR9 0x3024 65 #define RT2661_MAC_CSR10 0x3028 66 #define RT2661_MAC_CSR11 0x302c 67 #define RT2661_MAC_CSR12 0x3030 68 #define RT2661_MAC_CSR13 0x3034 69 #define RT2661_MAC_CSR14 0x3038 70 #define RT2661_MAC_CSR15 0x303c 71 #define RT2661_TXRX_CSR0 0x3040 72 #define RT2661_TXRX_CSR1 0x3044 73 #define RT2661_TXRX_CSR2 0x3048 74 #define RT2661_TXRX_CSR3 0x304c 75 #define RT2661_TXRX_CSR4 0x3050 76 #define RT2661_TXRX_CSR5 0x3054 77 #define RT2661_TXRX_CSR6 0x3058 78 #define RT2661_TXRX_CSR7 0x305c 79 #define RT2661_TXRX_CSR8 0x3060 80 #define RT2661_TXRX_CSR9 0x3064 81 #define RT2661_TXRX_CSR10 0x3068 82 #define RT2661_TXRX_CSR11 0x306c 83 #define RT2661_TXRX_CSR12 0x3070 84 #define RT2661_TXRX_CSR13 0x3074 85 #define RT2661_TXRX_CSR14 0x3078 86 #define RT2661_TXRX_CSR15 0x307c 87 #define RT2661_PHY_CSR0 0x3080 88 #define RT2661_PHY_CSR1 0x3084 89 #define RT2661_PHY_CSR2 0x3088 90 #define RT2661_PHY_CSR3 0x308c 91 #define RT2661_PHY_CSR4 0x3090 92 #define RT2661_PHY_CSR5 0x3094 93 #define RT2661_PHY_CSR6 0x3098 94 #define RT2661_PHY_CSR7 0x309c 95 #define RT2661_SEC_CSR0 0x30a0 96 #define RT2661_SEC_CSR1 0x30a4 97 #define RT2661_SEC_CSR2 0x30a8 98 #define RT2661_SEC_CSR3 0x30ac 99 #define RT2661_SEC_CSR4 0x30b0 100 #define RT2661_SEC_CSR5 0x30b4 101 #define RT2661_STA_CSR0 0x30c0 102 #define RT2661_STA_CSR1 0x30c4 103 #define RT2661_STA_CSR2 0x30c8 104 #define RT2661_STA_CSR3 0x30cc 105 #define RT2661_STA_CSR4 0x30d0 106 #define RT2661_AC0_BASE_CSR 0x3400 107 #define RT2661_AC1_BASE_CSR 0x3404 108 #define RT2661_AC2_BASE_CSR 0x3408 109 #define RT2661_AC3_BASE_CSR 0x340c 110 #define RT2661_MGT_BASE_CSR 0x3410 111 #define RT2661_TX_RING_CSR0 0x3418 112 #define RT2661_TX_RING_CSR1 0x341c 113 #define RT2661_AIFSN_CSR 0x3420 114 #define RT2661_CWMIN_CSR 0x3424 115 #define RT2661_CWMAX_CSR 0x3428 116 #define RT2661_TX_DMA_DST_CSR 0x342c 117 #define RT2661_TX_CNTL_CSR 0x3430 118 #define RT2661_LOAD_TX_RING_CSR 0x3434 119 #define RT2661_RX_BASE_CSR 0x3450 120 #define RT2661_RX_RING_CSR 0x3454 121 #define RT2661_RX_CNTL_CSR 0x3458 122 #define RT2661_PCI_CFG_CSR 0x3460 123 #define RT2661_INT_SOURCE_CSR 0x3468 124 #define RT2661_INT_MASK_CSR 0x346c 125 #define RT2661_E2PROM_CSR 0x3470 126 #define RT2661_AC_TXOP_CSR0 0x3474 127 #define RT2661_AC_TXOP_CSR1 0x3478 128 #define RT2661_TEST_MODE_CSR 0x3484 129 #define RT2661_IO_CNTL_CSR 0x3498 130 #define RT2661_MCU_CODE_BASE 0x4000 131 132 133 /* possible flags for register HOST_CMD_CSR */ 134 #define RT2661_KICK_CMD (1 << 7) 135 /* Host to MCU (8051) command identifiers */ 136 #define RT2661_MCU_CMD_SLEEP 0x30 137 #define RT2661_MCU_CMD_WAKEUP 0x31 138 #define RT2661_MCU_SET_LED 0x50 139 #define RT2661_MCU_SET_RSSI_LED 0x52 140 141 /* possible flags for register MCU_CNTL_CSR */ 142 #define RT2661_MCU_SEL (1 << 0) 143 #define RT2661_MCU_RESET (1 << 1) 144 #define RT2661_MCU_READY (1 << 2) 145 146 /* possible flags for register MCU_INT_SOURCE_CSR */ 147 #define RT2661_MCU_CMD_DONE 0xff 148 #define RT2661_MCU_WAKEUP (1 << 8) 149 #define RT2661_MCU_BEACON_EXPIRE (1 << 9) 150 151 /* possible flags for register H2M_MAILBOX_CSR */ 152 #define RT2661_H2M_BUSY (1 << 24) 153 #define RT2661_TOKEN_NO_INTR 0xff 154 155 /* possible flags for register MAC_CSR5 */ 156 #define RT2661_ONE_BSSID 3 157 158 /* possible flags for register TXRX_CSR0 */ 159 /* Tx filter flags are in the low 16 bits */ 160 #define RT2661_AUTO_TX_SEQ (1 << 15) 161 /* Rx filter flags are in the high 16 bits */ 162 #define RT2661_DISABLE_RX (1 << 16) 163 #define RT2661_DROP_CRC_ERROR (1 << 17) 164 #define RT2661_DROP_PHY_ERROR (1 << 18) 165 #define RT2661_DROP_CTL (1 << 19) 166 #define RT2661_DROP_NOT_TO_ME (1 << 20) 167 #define RT2661_DROP_TODS (1 << 21) 168 #define RT2661_DROP_VER_ERROR (1 << 22) 169 #define RT2661_DROP_MULTICAST (1 << 23) 170 #define RT2661_DROP_BROADCAST (1 << 24) 171 #define RT2661_DROP_ACKCTS (1 << 25) 172 173 /* possible flags for register TXRX_CSR4 */ 174 #define RT2661_SHORT_PREAMBLE (1 << 18) 175 #define RT2661_MRR_ENABLED (1 << 19) 176 #define RT2661_MRR_CCK_FALLBACK (1 << 22) 177 #define RT2661_LRETRY_LIMIT(n) (((n) & 0xf) << 24) 178 #define RT2661_SRETRY_LIMIT(n) (((n) & 0xf) << 28) 179 180 /* possible flags for register TXRX_CSR9 */ 181 #define RT2661_TSF_TICKING (1 << 16) 182 #define RT2661_TSF_MODE(x) (((x) & 0x3) << 17) 183 /* TBTT stands for Target Beacon Transmission Time */ 184 #define RT2661_ENABLE_TBTT (1 << 19) 185 #define RT2661_GENERATE_BEACON (1 << 20) 186 187 /* possible flags for register PHY_CSR0 */ 188 #define RT2661_PA_PE_2GHZ (1 << 16) 189 #define RT2661_PA_PE_5GHZ (1 << 17) 190 191 /* possible flags for register PHY_CSR3 */ 192 #define RT2661_BBP_READ (1 << 15) 193 #define RT2661_BBP_BUSY (1 << 16) 194 195 /* possible flags for register PHY_CSR4 */ 196 #define RT2661_RF_21BIT (21 << 24) 197 #define RT2661_RF_BUSY (1 << 31) 198 199 /* possible values for register STA_CSR4 */ 200 #define RT2661_TX_STAT_VALID (1 << 0) 201 #define RT2661_TX_RESULT(v) (((v) >> 1) & 0x7) 202 #define RT2661_TX_RETRYCNT(v) (((v) >> 4) & 0xf) 203 #define RT2661_TX_QID(v) (((v) >> 8) & 0xf) 204 #define RT2661_TX_SUCCESS 0 205 #define RT2661_TX_RETRY_FAIL 6 206 207 /* possible flags for register TX_CNTL_CSR */ 208 #define RT2661_KICK_MGT (1 << 4) 209 210 /* possible flags for register INT_SOURCE_CSR */ 211 #define RT2661_TX_DONE (1 << 0) 212 #define RT2661_RX_DONE (1 << 1) 213 #define RT2661_TX0_DMA_DONE (1 << 16) 214 #define RT2661_TX1_DMA_DONE (1 << 17) 215 #define RT2661_TX2_DMA_DONE (1 << 18) 216 #define RT2661_TX3_DMA_DONE (1 << 19) 217 #define RT2661_MGT_DONE (1 << 20) 218 219 /* possible flags for register E2PROM_CSR */ 220 #define RT2661_C (1 << 1) 221 #define RT2661_S (1 << 2) 222 #define RT2661_D (1 << 3) 223 #define RT2661_Q (1 << 4) 224 #define RT2661_93C46 (1 << 5) 225 226 /* Tx descriptor */ 227 struct rt2661_tx_desc { 228 uint32_t flags; 229 #define RT2661_TX_BUSY (1 << 0) 230 #define RT2661_TX_VALID (1 << 1) 231 #define RT2661_TX_MORE_FRAG (1 << 2) 232 #define RT2661_TX_NEED_ACK (1 << 3) 233 #define RT2661_TX_TIMESTAMP (1 << 4) 234 #define RT2661_TX_OFDM (1 << 5) 235 #define RT2661_TX_IFS (1 << 6) 236 #define RT2661_TX_LONG_RETRY (1 << 7) 237 #define RT2661_TX_HWMIC (1 << 8) 238 #define RT2661_TX_PAIRWISE_KEY (1 << 9) 239 #define RT2661_TX_BURST (1 << 28) 240 241 uint16_t wme; 242 #define RT2661_QID(v) (v) 243 #define RT2661_AIFSN(v) ((v) << 4) 244 #define RT2661_LOGCWMIN(v) ((v) << 8) 245 #define RT2661_LOGCWMAX(v) ((v) << 12) 246 247 uint16_t xflags; 248 #define RT2661_TX_HWSEQ (1 << 12) 249 250 uint8_t plcp_signal; 251 uint8_t plcp_service; 252 #define RT2661_PLCP_LENGEXT 0x80 253 254 uint8_t plcp_length_lo; 255 uint8_t plcp_length_hi; 256 257 uint8_t iv[4]; 258 uint8_t eiv[4]; 259 260 uint8_t offset; 261 uint8_t qid; 262 #define RT2661_QID_MGT 13 263 264 uint8_t txpower; 265 #define RT2661_DEFAULT_TXPOWER 0 266 267 uint8_t reserved1; 268 269 uint32_t addr[RT2661_MAX_SCATTER]; 270 uint16_t len[RT2661_MAX_SCATTER]; 271 272 uint16_t reserved2; 273 } __packed; 274 275 /* Rx descriptor */ 276 struct rt2661_rx_desc { 277 uint32_t flags; 278 #define RT2661_RX_BUSY (1 << 0) 279 #define RT2661_RX_DROP (1 << 1) 280 #define RT2661_RX_CRC_ERROR (1 << 6) 281 #define RT2661_RX_OFDM (1 << 7) 282 #define RT2661_RX_CIPHER_MASK 0x00000300 283 #define RT2661_RX_KEYIX(f) (((f) >> 10) & 0x3f) 284 #define RT2661_RX_CIPHER(f) (((f) >> 29) & 0x7) 285 286 uint8_t rate; 287 uint8_t rssi; 288 uint8_t reserved1; 289 uint8_t offset; 290 uint8_t iv[4]; 291 uint8_t eiv[4]; 292 uint32_t reserved2; 293 uint32_t physaddr; 294 uint32_t reserved3[10]; 295 } __packed; 296 297 #define RAL_RF1 0 298 #define RAL_RF2 2 299 #define RAL_RF3 1 300 #define RAL_RF4 3 301 302 /* dual-band RF */ 303 #define RT2661_RF_5225 1 304 #define RT2661_RF_5325 2 305 /* single-band RF */ 306 #define RT2661_RF_2527 3 307 #define RT2661_RF_2529 4 308 309 #define RT2661_BBP_2661D 0x2661d 310 311 #define RT2661_RX_DESC_BACK 4 312 313 #define RT2661_SMART_MODE (1 << 0) 314 315 #define RT2661_BBPR94_DEFAULT 6 316 317 #define RT2661_SHIFT_D 3 318 #define RT2661_SHIFT_Q 4 319 320 #define RT2661_EEPROM_MAC01 0x02 321 #define RT2661_EEPROM_MAC23 0x03 322 #define RT2661_EEPROM_MAC45 0x04 323 #define RT2661_EEPROM_ANTENNA 0x10 324 #define RT2661_EEPROM_CONFIG2 0x11 325 #define RT2661_EEPROM_BBP_BASE 0x13 326 #define RT2661_EEPROM_TXPOWER_2GHZ 0x23 327 #define RT2661_EEPROM_2GHZ_TSSI1 0x2a 328 #define RT2661_EEPROM_2GHZ_TSSI2 0x2b 329 #define RT2661_EEPROM_2GHZ_TSSI3 0x2c 330 #define RT2661_EEPROM_2GHZ_TSSI4 0x2d 331 #define RT2661_EEPROM_2GHZ_TSSI5 0x2e 332 #define RT2661_EEPROM_FREQ_OFFSET 0x2f 333 #define RT2661_EEPROM_LED_OFFSET 0x30 334 #define RT2661_EEPROM_TXPOWER_5GHZ 0x31 335 #define RT2661_EEPROM_RSSI_2GHZ_OFFSET 0x4d 336 #define RT2661_EEPROM_RSSI_5GHZ_OFFSET 0x4e 337 338 #define RT2661_EE_LED_RDYG 0x01 339 #define RT2661_EE_LED_RDYA 0x02 340 #define RT2661_EE_LED_ACT 0x04 341 #define RT2661_EE_LED_GPIO0 0x08 342 #define RT2661_EE_LED_GPIO1 0x10 343 #define RT2661_EE_LED_GPIO2 0x20 344 #define RT2661_EE_LED_GPIO3 0x40 345 #define RT2661_EE_LED_GPIO4 0x80 346 #define RT2661_EE_LED_MODE_SHIFT 8 347 #define RT2661_EE_LED_MODE_MASK 0x1f 348 349 #define RT2661_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 350 351 #define RT2661_MCU_LED_RF (1 << 5) 352 #define RT2661_MCU_LED_LINKG (1 << 6) 353 #define RT2661_MCU_LED_LINKA (1 << 7) 354 #define RT2661_MCU_LED_GPIO0 (1 << 8) 355 #define RT2661_MCU_LED_GPIO1 (1 << 9) 356 #define RT2661_MCU_LED_GPIO2 (1 << 10) 357 #define RT2661_MCU_LED_GPIO3 (1 << 11) 358 #define RT2661_MCU_LED_GPIO4 (1 << 12) 359 #define RT2661_MCU_LED_ACT (1 << 13) 360 #define RT2661_MCU_LED_RDYG (1 << 14) 361 #define RT2661_MCU_LED_RDYA (1 << 15) 362 363 #define RT2661_MCU_LED_DEFAULT \ 364 (RT2661_MCU_LED_GPIO0 | RT2661_MCU_LED_GPIO1 | RT2661_MCU_LED_GPIO2 | \ 365 RT2661_MCU_LED_GPIO3 | RT2661_MCU_LED_GPIO4 | RT2661_MCU_LED_ACT | \ 366 RT2661_MCU_LED_RDYG | RT2661_MCU_LED_RDYA) 367 368 #define RT2661_TXPOWER_DEFAULT 5 369 #define RT2661_TXPOWER_MAX 36 370 371 /* 372 * control and status registers access macros 373 */ 374 #define RAL_READ(sc, reg) \ 375 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 376 377 #define RAL_READ_REGION_4(sc, offset, datap, count) \ 378 bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 379 (datap), (count)) 380 381 #define RAL_WRITE(sc, reg, val) \ 382 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 383 384 #define RAL_WRITE_REGION_1(sc, offset, datap, count) \ 385 bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \ 386 (datap), (count)) 387 388 /* 389 * EEPROM access macro 390 */ 391 #define RT2661_EEPROM_CTL(sc, val) do { \ 392 RAL_WRITE((sc), RT2661_E2PROM_CSR, (val)); \ 393 DELAY(RT2661_EEPROM_DELAY); \ 394 } while (/* CONSTCOND */0) 395 396 /* 397 * Default values for MAC registers; values taken from the reference driver. 398 */ 399 #define RT2661_DEF_MAC \ 400 { RT2661_TXRX_CSR0, 0x0000b032 }, \ 401 { RT2661_TXRX_CSR1, 0x9eb39eb3 }, \ 402 { RT2661_TXRX_CSR2, 0x8a8b8c8d }, \ 403 { RT2661_TXRX_CSR3, 0x00858687 }, \ 404 { RT2661_TXRX_CSR7, 0x2e31353b }, \ 405 { RT2661_TXRX_CSR8, 0x2a2a2a2c }, \ 406 { RT2661_TXRX_CSR15, 0x0000000f }, \ 407 { RT2661_MAC_CSR6, 0x00000fff }, \ 408 { RT2661_MAC_CSR8, 0x016c030a }, \ 409 { RT2661_MAC_CSR10, 0x00000718 }, \ 410 { RT2661_MAC_CSR12, 0x00000004 }, \ 411 { RT2661_MAC_CSR13, 0x0000e000 }, \ 412 { RT2661_SEC_CSR0, 0x00000000 }, \ 413 { RT2661_SEC_CSR1, 0x00000000 }, \ 414 { RT2661_SEC_CSR2, 0x00000000 }, \ 415 { RT2661_SEC_CSR3, 0x00000000 }, \ 416 { RT2661_SEC_CSR4, 0x00000000 }, \ 417 { RT2661_SEC_CSR5, 0x00000000 }, \ 418 { RT2661_PHY_CSR1, 0x000023b0 }, \ 419 { RT2661_PHY_CSR5, 0x060a100c }, \ 420 { RT2661_PHY_CSR6, 0x00080606 }, \ 421 { RT2661_PHY_CSR7, 0x00000a08 }, \ 422 { RT2661_PCI_CFG_CSR, 0x3cca4808 }, \ 423 { RT2661_AIFSN_CSR, 0x00002273 }, \ 424 { RT2661_CWMIN_CSR, 0x00002344 }, \ 425 { RT2661_CWMAX_CSR, 0x000034aa }, \ 426 { RT2661_TEST_MODE_CSR, 0x00000200 }, \ 427 { RT2661_M2H_CMD_DONE_CSR, 0xffffffff } 428 429 /* 430 * Default values for BBP registers; values taken from the reference driver. 431 */ 432 #define RT2661_DEF_BBP \ 433 { 3, 0x00 }, \ 434 { 15, 0x30 }, \ 435 { 17, 0x20 }, \ 436 { 21, 0xc8 }, \ 437 { 22, 0x38 }, \ 438 { 23, 0x06 }, \ 439 { 24, 0xfe }, \ 440 { 25, 0x0a }, \ 441 { 26, 0x0d }, \ 442 { 34, 0x12 }, \ 443 { 37, 0x07 }, \ 444 { 39, 0xf8 }, \ 445 { 41, 0x60 }, \ 446 { 53, 0x10 }, \ 447 { 54, 0x18 }, \ 448 { 60, 0x10 }, \ 449 { 61, 0x04 }, \ 450 { 62, 0x04 }, \ 451 { 75, 0xfe }, \ 452 { 86, 0xfe }, \ 453 { 88, 0xfe }, \ 454 { 90, 0x0f }, \ 455 { 99, 0x00 }, \ 456 { 102, 0x16 }, \ 457 { 107, 0x04 } 458 459 /* 460 * Default settings for RF registers; values taken from the reference driver. 461 */ 462 #define RT2661_RF5225_1 \ 463 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \ 464 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \ 465 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \ 466 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \ 467 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \ 468 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \ 469 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \ 470 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \ 471 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \ 472 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \ 473 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \ 474 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \ 475 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \ 476 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \ 477 \ 478 { 36, 0x00b33, 0x01266, 0x26014, 0x30288 }, \ 479 { 40, 0x00b33, 0x01268, 0x26014, 0x30280 }, \ 480 { 44, 0x00b33, 0x01269, 0x26014, 0x30282 }, \ 481 { 48, 0x00b33, 0x0126a, 0x26014, 0x30284 }, \ 482 { 52, 0x00b33, 0x0126b, 0x26014, 0x30286 }, \ 483 { 56, 0x00b33, 0x0126c, 0x26014, 0x30288 }, \ 484 { 60, 0x00b33, 0x0126e, 0x26014, 0x30280 }, \ 485 { 64, 0x00b33, 0x0126f, 0x26014, 0x30282 }, \ 486 \ 487 { 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 }, \ 488 { 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 }, \ 489 { 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 }, \ 490 { 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 }, \ 491 { 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 }, \ 492 { 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 }, \ 493 { 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 }, \ 494 { 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 }, \ 495 { 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 }, \ 496 { 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 }, \ 497 { 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 }, \ 498 \ 499 { 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 }, \ 500 { 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 }, \ 501 { 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 }, \ 502 { 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 }, \ 503 { 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 } 504 505 #define RT2661_RF5225_2 \ 506 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \ 507 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \ 508 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \ 509 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \ 510 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \ 511 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \ 512 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \ 513 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \ 514 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \ 515 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \ 516 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \ 517 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \ 518 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \ 519 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \ 520 \ 521 { 36, 0x00b35, 0x11206, 0x26014, 0x30280 }, \ 522 { 40, 0x00b34, 0x111a0, 0x26014, 0x30280 }, \ 523 { 44, 0x00b34, 0x111a1, 0x26014, 0x30286 }, \ 524 { 48, 0x00b34, 0x111a3, 0x26014, 0x30282 }, \ 525 { 52, 0x00b34, 0x111a4, 0x26014, 0x30288 }, \ 526 { 56, 0x00b34, 0x111a6, 0x26014, 0x30284 }, \ 527 { 60, 0x00b34, 0x111a8, 0x26014, 0x30280 }, \ 528 { 64, 0x00b34, 0x111a9, 0x26014, 0x30286 }, \ 529 \ 530 { 100, 0x00b35, 0x11226, 0x2e014, 0x30280 }, \ 531 { 104, 0x00b35, 0x11228, 0x2e014, 0x30280 }, \ 532 { 108, 0x00b35, 0x1122a, 0x2e014, 0x30280 }, \ 533 { 112, 0x00b35, 0x1122c, 0x2e014, 0x30280 }, \ 534 { 116, 0x00b35, 0x1122e, 0x2e014, 0x30280 }, \ 535 { 120, 0x00b34, 0x111c0, 0x2e014, 0x30280 }, \ 536 { 124, 0x00b34, 0x111c1, 0x2e014, 0x30286 }, \ 537 { 128, 0x00b34, 0x111c3, 0x2e014, 0x30282 }, \ 538 { 132, 0x00b34, 0x111c4, 0x2e014, 0x30288 }, \ 539 { 136, 0x00b34, 0x111c6, 0x2e014, 0x30284 }, \ 540 { 140, 0x00b34, 0x111c8, 0x2e014, 0x30280 }, \ 541 \ 542 { 149, 0x00b34, 0x111cb, 0x2e014, 0x30286 }, \ 543 { 153, 0x00b34, 0x111cd, 0x2e014, 0x30282 }, \ 544 { 157, 0x00b35, 0x11242, 0x2e014, 0x30285 }, \ 545 { 161, 0x00b35, 0x11244, 0x2e014, 0x30285 }, \ 546 { 165, 0x00b35, 0x11246, 0x2e014, 0x30285 } 547