1 /* 2 * Copyright (c) 2006 3 * Damien Bergamini <damien.bergamini@free.fr> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: src/sys/dev/ral/rt2661reg.h,v 1.1 2006/03/05 20:36:56 damien Exp $ 18 * $DragonFly: src/sys/dev/netif/ral/rt2661reg.h,v 1.1 2006/05/20 09:13:09 sephe Exp $ 19 */ 20 21 #define RT2661_TX_RING_COUNT 32 22 #define RT2661_MGT_RING_COUNT 32 23 #define RT2661_RX_RING_COUNT 64 24 25 #define RT2661_TX_DESC_SIZE (sizeof (struct rt2661_tx_desc)) 26 #define RT2661_TX_DESC_WSIZE (RT2661_TX_DESC_SIZE / 4) 27 #define RT2661_RX_DESC_SIZE (sizeof (struct rt2661_rx_desc)) 28 #define RT2661_RX_DESC_WSIZE (RT2661_RX_DESC_SIZE / 4) 29 30 #define RT2661_MAX_SCATTER 5 31 32 /* 33 * Control and status registers. 34 */ 35 #define RT2661_HOST_CMD_CSR 0x0008 36 #define RT2661_MCU_CNTL_CSR 0x000c 37 #define RT2661_SOFT_RESET_CSR 0x0010 38 #define RT2661_MCU_INT_SOURCE_CSR 0x0014 39 #define RT2661_MCU_INT_MASK_CSR 0x0018 40 #define RT2661_PCI_USEC_CSR 0x001c 41 #define RT2661_H2M_MAILBOX_CSR 0x2100 42 #define RT2661_M2H_CMD_DONE_CSR 0x2104 43 #define RT2661_HW_BEACON_BASE0 0x2c00 44 #define RT2661_MAC_CSR0 0x3000 45 #define RT2661_MAC_CSR1 0x3004 46 #define RT2661_MAC_CSR2 0x3008 47 #define RT2661_MAC_CSR3 0x300c 48 #define RT2661_MAC_CSR4 0x3010 49 #define RT2661_MAC_CSR5 0x3014 50 #define RT2661_MAC_CSR6 0x3018 51 #define RT2661_MAC_CSR7 0x301c 52 #define RT2661_MAC_CSR8 0x3020 53 #define RT2661_MAC_CSR9 0x3024 54 #define RT2661_MAC_CSR10 0x3028 55 #define RT2661_MAC_CSR11 0x302c 56 #define RT2661_MAC_CSR12 0x3030 57 #define RT2661_MAC_CSR13 0x3034 58 #define RT2661_MAC_CSR14 0x3038 59 #define RT2661_MAC_CSR15 0x303c 60 #define RT2661_TXRX_CSR0 0x3040 61 #define RT2661_TXRX_CSR1 0x3044 62 #define RT2661_TXRX_CSR2 0x3048 63 #define RT2661_TXRX_CSR3 0x304c 64 #define RT2661_TXRX_CSR4 0x3050 65 #define RT2661_TXRX_CSR5 0x3054 66 #define RT2661_TXRX_CSR6 0x3058 67 #define RT2661_TXRX_CSR7 0x305c 68 #define RT2661_TXRX_CSR8 0x3060 69 #define RT2661_TXRX_CSR9 0x3064 70 #define RT2661_TXRX_CSR10 0x3068 71 #define RT2661_TXRX_CSR11 0x306c 72 #define RT2661_TXRX_CSR12 0x3070 73 #define RT2661_TXRX_CSR13 0x3074 74 #define RT2661_TXRX_CSR14 0x3078 75 #define RT2661_TXRX_CSR15 0x307c 76 #define RT2661_PHY_CSR0 0x3080 77 #define RT2661_PHY_CSR1 0x3084 78 #define RT2661_PHY_CSR2 0x3088 79 #define RT2661_PHY_CSR3 0x308c 80 #define RT2661_PHY_CSR4 0x3090 81 #define RT2661_PHY_CSR5 0x3094 82 #define RT2661_PHY_CSR6 0x3098 83 #define RT2661_PHY_CSR7 0x309c 84 #define RT2661_SEC_CSR0 0x30a0 85 #define RT2661_SEC_CSR1 0x30a4 86 #define RT2661_SEC_CSR2 0x30a8 87 #define RT2661_SEC_CSR3 0x30ac 88 #define RT2661_SEC_CSR4 0x30b0 89 #define RT2661_SEC_CSR5 0x30b4 90 #define RT2661_STA_CSR0 0x30c0 91 #define RT2661_STA_CSR1 0x30c4 92 #define RT2661_STA_CSR2 0x30c8 93 #define RT2661_STA_CSR3 0x30cc 94 #define RT2661_STA_CSR4 0x30d0 95 #define RT2661_AC0_BASE_CSR 0x3400 96 #define RT2661_AC1_BASE_CSR 0x3404 97 #define RT2661_AC2_BASE_CSR 0x3408 98 #define RT2661_AC3_BASE_CSR 0x340c 99 #define RT2661_MGT_BASE_CSR 0x3410 100 #define RT2661_TX_RING_CSR0 0x3418 101 #define RT2661_TX_RING_CSR1 0x341c 102 #define RT2661_AIFSN_CSR 0x3420 103 #define RT2661_CWMIN_CSR 0x3424 104 #define RT2661_CWMAX_CSR 0x3428 105 #define RT2661_TX_DMA_DST_CSR 0x342c 106 #define RT2661_TX_CNTL_CSR 0x3430 107 #define RT2661_LOAD_TX_RING_CSR 0x3434 108 #define RT2661_RX_BASE_CSR 0x3450 109 #define RT2661_RX_RING_CSR 0x3454 110 #define RT2661_RX_CNTL_CSR 0x3458 111 #define RT2661_PCI_CFG_CSR 0x3460 112 #define RT2661_INT_SOURCE_CSR 0x3468 113 #define RT2661_INT_MASK_CSR 0x346c 114 #define RT2661_E2PROM_CSR 0x3470 115 #define RT2661_AC_TXOP_CSR0 0x3474 116 #define RT2661_AC_TXOP_CSR1 0x3478 117 #define RT2661_TEST_MODE_CSR 0x3484 118 #define RT2661_IO_CNTL_CSR 0x3498 119 #define RT2661_MCU_CODE_BASE 0x4000 120 121 122 /* possible flags for register HOST_CMD_CSR */ 123 #define RT2661_KICK_CMD (1 << 7) 124 /* Host to MCU (8051) command identifiers */ 125 #define RT2661_MCU_CMD_SLEEP 0x30 126 #define RT2661_MCU_CMD_WAKEUP 0x31 127 #define RT2661_MCU_SET_LED 0x50 128 #define RT2661_MCU_SET_RSSI_LED 0x52 129 130 /* possible flags for register MCU_CNTL_CSR */ 131 #define RT2661_MCU_SEL (1 << 0) 132 #define RT2661_MCU_RESET (1 << 1) 133 #define RT2661_MCU_READY (1 << 2) 134 135 /* possible flags for register MCU_INT_SOURCE_CSR */ 136 #define RT2661_MCU_CMD_DONE 0xff 137 #define RT2661_MCU_WAKEUP (1 << 8) 138 #define RT2661_MCU_BEACON_EXPIRE (1 << 9) 139 140 /* possible flags for register H2M_MAILBOX_CSR */ 141 #define RT2661_H2M_BUSY (1 << 24) 142 #define RT2661_TOKEN_NO_INTR 0xff 143 144 /* possible flags for register MAC_CSR5 */ 145 #define RT2661_ONE_BSSID 3 146 147 /* possible flags for register TXRX_CSR0 */ 148 /* Tx filter flags are in the low 16 bits */ 149 #define RT2661_AUTO_TX_SEQ (1 << 15) 150 /* Rx filter flags are in the high 16 bits */ 151 #define RT2661_DISABLE_RX (1 << 16) 152 #define RT2661_DROP_CRC_ERROR (1 << 17) 153 #define RT2661_DROP_PHY_ERROR (1 << 18) 154 #define RT2661_DROP_CTL (1 << 19) 155 #define RT2661_DROP_NOT_TO_ME (1 << 20) 156 #define RT2661_DROP_TODS (1 << 21) 157 #define RT2661_DROP_VER_ERROR (1 << 22) 158 #define RT2661_DROP_MULTICAST (1 << 23) 159 #define RT2661_DROP_BROADCAST (1 << 24) 160 #define RT2661_DROP_ACKCTS (1 << 25) 161 162 /* possible flags for register TXRX_CSR4 */ 163 #define RT2661_SHORT_PREAMBLE (1 << 19) 164 #define RT2661_MRR_ENABLED (1 << 20) 165 #define RT2661_MRR_CCK_FALLBACK (1 << 23) 166 167 /* possible flags for register TXRX_CSR9 */ 168 #define RT2661_TSF_TICKING (1 << 16) 169 #define RT2661_TSF_MODE(x) (((x) & 0x3) << 17) 170 /* TBTT stands for Target Beacon Transmission Time */ 171 #define RT2661_ENABLE_TBTT (1 << 19) 172 #define RT2661_GENERATE_BEACON (1 << 20) 173 174 /* possible flags for register PHY_CSR0 */ 175 #define RT2661_PA_PE_2GHZ (1 << 16) 176 #define RT2661_PA_PE_5GHZ (1 << 17) 177 178 /* possible flags for register PHY_CSR3 */ 179 #define RT2661_BBP_READ (1 << 15) 180 #define RT2661_BBP_BUSY (1 << 16) 181 182 /* possible flags for register PHY_CSR4 */ 183 #define RT2661_RF_21BIT (21 << 24) 184 #define RT2661_RF_BUSY (1 << 31) 185 186 /* possible values for register STA_CSR4 */ 187 #define RT2661_TX_STAT_VALID (1 << 0) 188 #define RT2661_TX_RESULT(v) (((v) >> 1) & 0x7) 189 #define RT2661_TX_RETRYCNT(v) (((v) >> 4) & 0xf) 190 #define RT2661_TX_QID(v) (((v) >> 8) & 0xf) 191 #define RT2661_TX_SUCCESS 0 192 #define RT2661_TX_RETRY_FAIL 6 193 194 /* possible flags for register TX_CNTL_CSR */ 195 #define RT2661_KICK_MGT (1 << 4) 196 197 /* possible flags for register INT_SOURCE_CSR */ 198 #define RT2661_TX_DONE (1 << 0) 199 #define RT2661_RX_DONE (1 << 1) 200 #define RT2661_TX0_DMA_DONE (1 << 16) 201 #define RT2661_TX1_DMA_DONE (1 << 17) 202 #define RT2661_TX2_DMA_DONE (1 << 18) 203 #define RT2661_TX3_DMA_DONE (1 << 19) 204 #define RT2661_MGT_DONE (1 << 20) 205 206 /* possible flags for register E2PROM_CSR */ 207 #define RT2661_C (1 << 1) 208 #define RT2661_S (1 << 2) 209 #define RT2661_D (1 << 3) 210 #define RT2661_Q (1 << 4) 211 #define RT2661_93C46 (1 << 5) 212 213 /* Tx descriptor */ 214 struct rt2661_tx_desc { 215 uint32_t flags; 216 #define RT2661_TX_BUSY (1 << 0) 217 #define RT2661_TX_VALID (1 << 1) 218 #define RT2661_TX_MORE_FRAG (1 << 2) 219 #define RT2661_TX_NEED_ACK (1 << 3) 220 #define RT2661_TX_TIMESTAMP (1 << 4) 221 #define RT2661_TX_OFDM (1 << 5) 222 #define RT2661_TX_IFS (1 << 6) 223 #define RT2661_TX_LONG_RETRY (1 << 7) 224 #define RT2661_TX_BURST (1 << 28) 225 226 uint16_t wme; 227 #define RT2661_QID(v) (v) 228 #define RT2661_AIFSN(v) ((v) << 4) 229 #define RT2661_LOGCWMIN(v) ((v) << 8) 230 #define RT2661_LOGCWMAX(v) ((v) << 12) 231 232 uint16_t xflags; 233 #define RT2661_TX_HWSEQ (1 << 12) 234 235 uint8_t plcp_signal; 236 uint8_t plcp_service; 237 #define RT2661_PLCP_LENGEXT 0x80 238 239 uint8_t plcp_length_lo; 240 uint8_t plcp_length_hi; 241 242 uint32_t iv; 243 uint32_t eiv; 244 245 uint8_t offset; 246 uint8_t qid; 247 #define RT2661_QID_MGT 13 248 249 uint8_t txpower; 250 #define RT2661_DEFAULT_TXPOWER 0 251 252 uint8_t reserved1; 253 254 uint32_t addr[RT2661_MAX_SCATTER]; 255 uint16_t len[RT2661_MAX_SCATTER]; 256 257 uint16_t reserved2; 258 } __packed; 259 260 /* Rx descriptor */ 261 struct rt2661_rx_desc { 262 uint32_t flags; 263 #define RT2661_RX_BUSY (1 << 0) 264 #define RT2661_RX_DROP (1 << 1) 265 #define RT2661_RX_CRC_ERROR (1 << 6) 266 #define RT2661_RX_OFDM (1 << 7) 267 #define RT2661_RX_PHY_ERROR (1 << 8) 268 #define RT2661_RX_CIPHER_MASK 0x00000600 269 270 uint8_t rate; 271 uint8_t rssi; 272 uint8_t reserved1; 273 uint8_t offset; 274 uint32_t iv; 275 uint32_t eiv; 276 uint32_t reserved2; 277 uint32_t physaddr; 278 uint32_t reserved3[10]; 279 } __packed; 280 281 #define RAL_RF1 0 282 #define RAL_RF2 2 283 #define RAL_RF3 1 284 #define RAL_RF4 3 285 286 /* dual-band RF */ 287 #define RT2661_RF_5225 1 288 #define RT2661_RF_5325 2 289 /* single-band RF */ 290 #define RT2661_RF_2527 3 291 #define RT2661_RF_2529 4 292 293 #define RT2661_RX_DESC_BACK 4 294 295 #define RT2661_SMART_MODE (1 << 0) 296 297 #define RT2661_BBPR94_DEFAULT 6 298 299 #define RT2661_SHIFT_D 3 300 #define RT2661_SHIFT_Q 4 301 302 #define RT2661_EEPROM_MAC01 0x02 303 #define RT2661_EEPROM_MAC23 0x03 304 #define RT2661_EEPROM_MAC45 0x04 305 #define RT2661_EEPROM_ANTENNA 0x10 306 #define RT2661_EEPROM_CONFIG2 0x11 307 #define RT2661_EEPROM_BBP_BASE 0x13 308 #define RT2661_EEPROM_TXPOWER 0x23 309 #define RT2661_EEPROM_FREQ_OFFSET 0x2f 310 #define RT2661_EEPROM_RSSI_2GHZ_OFFSET 0x4d 311 #define RT2661_EEPROM_RSSI_5GHZ_OFFSET 0x4e 312 313 #define RT2661_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 314 315 /* 316 * control and status registers access macros 317 */ 318 #define RAL_READ(sc, reg) \ 319 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 320 321 #define RAL_READ_REGION_4(sc, offset, datap, count) \ 322 bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 323 (datap), (count)) 324 325 #define RAL_WRITE(sc, reg, val) \ 326 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 327 328 #define RAL_WRITE_REGION_1(sc, offset, datap, count) \ 329 bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \ 330 (datap), (count)) 331 332 /* 333 * EEPROM access macro 334 */ 335 #define RT2661_EEPROM_CTL(sc, val) do { \ 336 RAL_WRITE((sc), RT2661_E2PROM_CSR, (val)); \ 337 DELAY(RT2661_EEPROM_DELAY); \ 338 } while (/* CONSTCOND */0) 339 340 /* 341 * Default values for MAC registers; values taken from the reference driver. 342 */ 343 #define RT2661_DEF_MAC \ 344 { RT2661_TXRX_CSR0, 0x0000b032 }, \ 345 { RT2661_TXRX_CSR1, 0x9eb39eb3 }, \ 346 { RT2661_TXRX_CSR2, 0x8a8b8c8d }, \ 347 { RT2661_TXRX_CSR3, 0x00858687 }, \ 348 { RT2661_TXRX_CSR7, 0x2e31353b }, \ 349 { RT2661_TXRX_CSR8, 0x2a2a2a2c }, \ 350 { RT2661_TXRX_CSR15, 0x0000000f }, \ 351 { RT2661_MAC_CSR6, 0x00000fff }, \ 352 { RT2661_MAC_CSR8, 0x016c030a }, \ 353 { RT2661_MAC_CSR10, 0x00000718 }, \ 354 { RT2661_MAC_CSR12, 0x00000004 }, \ 355 { RT2661_MAC_CSR13, 0x0000e000 }, \ 356 { RT2661_SEC_CSR0, 0x00000000 }, \ 357 { RT2661_SEC_CSR1, 0x00000000 }, \ 358 { RT2661_SEC_CSR5, 0x00000000 }, \ 359 { RT2661_PHY_CSR1, 0x000023b0 }, \ 360 { RT2661_PHY_CSR5, 0x060a100c }, \ 361 { RT2661_PHY_CSR6, 0x00080606 }, \ 362 { RT2661_PHY_CSR7, 0x00000a08 }, \ 363 { RT2661_PCI_CFG_CSR, 0x3cca4808 }, \ 364 { RT2661_AIFSN_CSR, 0x00002273 }, \ 365 { RT2661_CWMIN_CSR, 0x00002344 }, \ 366 { RT2661_CWMAX_CSR, 0x000034aa }, \ 367 { RT2661_TEST_MODE_CSR, 0x00000200 }, \ 368 { RT2661_M2H_CMD_DONE_CSR, 0xffffffff } 369 370 /* 371 * Default values for BBP registers; values taken from the reference driver. 372 */ 373 #define RT2661_DEF_BBP \ 374 { 3, 0x00 }, \ 375 { 15, 0x30 }, \ 376 { 17, 0x20 }, \ 377 { 21, 0xc8 }, \ 378 { 22, 0x38 }, \ 379 { 23, 0x06 }, \ 380 { 24, 0xfe }, \ 381 { 25, 0x0a }, \ 382 { 26, 0x0d }, \ 383 { 34, 0x12 }, \ 384 { 37, 0x07 }, \ 385 { 39, 0xf8 }, \ 386 { 41, 0x60 }, \ 387 { 53, 0x10 }, \ 388 { 54, 0x18 }, \ 389 { 60, 0x10 }, \ 390 { 61, 0x04 }, \ 391 { 62, 0x04 }, \ 392 { 75, 0xfe }, \ 393 { 86, 0xfe }, \ 394 { 88, 0xfe }, \ 395 { 90, 0x0f }, \ 396 { 99, 0x00 }, \ 397 { 102, 0x16 }, \ 398 { 107, 0x04 } 399 400 /* 401 * Default settings for RF registers; values taken from the reference driver. 402 */ 403 #define RT2661_RF5225_1 \ 404 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \ 405 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \ 406 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \ 407 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \ 408 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \ 409 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \ 410 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \ 411 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \ 412 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \ 413 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \ 414 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \ 415 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \ 416 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \ 417 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \ 418 \ 419 { 36, 0x00b33, 0x01266, 0x26014, 0x30288 }, \ 420 { 40, 0x00b33, 0x01268, 0x26014, 0x30280 }, \ 421 { 44, 0x00b33, 0x01269, 0x26014, 0x30282 }, \ 422 { 48, 0x00b33, 0x0126a, 0x26014, 0x30284 }, \ 423 { 52, 0x00b33, 0x0126b, 0x26014, 0x30286 }, \ 424 { 56, 0x00b33, 0x0126c, 0x26014, 0x30288 }, \ 425 { 60, 0x00b33, 0x0126e, 0x26014, 0x30280 }, \ 426 { 64, 0x00b33, 0x0126f, 0x26014, 0x30282 }, \ 427 \ 428 { 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 }, \ 429 { 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 }, \ 430 { 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 }, \ 431 { 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 }, \ 432 { 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 }, \ 433 { 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 }, \ 434 { 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 }, \ 435 { 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 }, \ 436 { 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 }, \ 437 { 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 }, \ 438 { 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 }, \ 439 \ 440 { 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 }, \ 441 { 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 }, \ 442 { 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 }, \ 443 { 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 }, \ 444 { 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 } 445 446 #define RT2661_RF5225_2 \ 447 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \ 448 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \ 449 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \ 450 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \ 451 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \ 452 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \ 453 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \ 454 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \ 455 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \ 456 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \ 457 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \ 458 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \ 459 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \ 460 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \ 461 \ 462 { 36, 0x00b35, 0x11206, 0x26014, 0x30280 }, \ 463 { 40, 0x00b34, 0x111a0, 0x26014, 0x30280 }, \ 464 { 44, 0x00b34, 0x111a1, 0x26014, 0x30286 }, \ 465 { 48, 0x00b34, 0x111a3, 0x26014, 0x30282 }, \ 466 { 52, 0x00b34, 0x111a4, 0x26014, 0x30288 }, \ 467 { 56, 0x00b34, 0x111a6, 0x26014, 0x30284 }, \ 468 { 60, 0x00b34, 0x111a8, 0x26014, 0x30280 }, \ 469 { 64, 0x00b34, 0x111a9, 0x26014, 0x30286 }, \ 470 \ 471 { 100, 0x00b35, 0x11226, 0x2e014, 0x30280 }, \ 472 { 104, 0x00b35, 0x11228, 0x2e014, 0x30280 }, \ 473 { 108, 0x00b35, 0x1122a, 0x2e014, 0x30280 }, \ 474 { 112, 0x00b35, 0x1122c, 0x2e014, 0x30280 }, \ 475 { 116, 0x00b35, 0x1122e, 0x2e014, 0x30280 }, \ 476 { 120, 0x00b34, 0x111c0, 0x2e014, 0x30280 }, \ 477 { 124, 0x00b34, 0x111c1, 0x2e014, 0x30286 }, \ 478 { 128, 0x00b34, 0x111c3, 0x2e014, 0x30282 }, \ 479 { 132, 0x00b34, 0x111c4, 0x2e014, 0x30288 }, \ 480 { 136, 0x00b34, 0x111c6, 0x2e014, 0x30284 }, \ 481 { 140, 0x00b34, 0x111c8, 0x2e014, 0x30280 }, \ 482 \ 483 { 149, 0x00b34, 0x111cb, 0x2e014, 0x30286 }, \ 484 { 153, 0x00b34, 0x111cd, 0x2e014, 0x30282 }, \ 485 { 157, 0x00b35, 0x11242, 0x2e014, 0x30285 }, \ 486 { 161, 0x00b35, 0x11244, 0x2e014, 0x30285 }, \ 487 { 165, 0x00b35, 0x11246, 0x2e014, 0x30285 } 488