1 /*- 2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $OpenBSD: rt2860.c,v 1.65 2010/10/23 14:24:54 damien Exp $ 18 */ 19 20 #include <sys/cdefs.h> 21 __FBSDID("$FreeBSD$"); 22 23 /*- 24 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28 #include <sys/param.h> 29 #include <sys/sysctl.h> 30 #include <sys/sockio.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 #include <sys/endian.h> 41 #include <sys/firmware.h> 42 43 #if defined(__DragonFly__) 44 /* empty */ 45 #else 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 #endif 49 #include <sys/rman.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_var.h> 54 #include <net/if_arp.h> 55 #include <net/ethernet.h> 56 #include <net/if_dl.h> 57 #include <net/if_media.h> 58 #include <net/if_types.h> 59 60 #include <netproto/802_11/ieee80211_var.h> 61 #include <netproto/802_11/ieee80211_radiotap.h> 62 #include <netproto/802_11/ieee80211_regdomain.h> 63 #include <netproto/802_11/ieee80211_ratectl.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/in_var.h> 68 #include <netinet/ip.h> 69 #include <netinet/if_ether.h> 70 71 #include <dev/netif/ral/rt2860reg.h> 72 #include <dev/netif/ral/rt2860var.h> 73 74 #define RAL_DEBUG 75 #ifdef RAL_DEBUG 76 #define DPRINTF(x) do { if (sc->sc_debug > 0) kprintf x; } while (0) 77 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) kprintf x; } while (0) 78 #else 79 #define DPRINTF(x) 80 #define DPRINTFN(n, x) 81 #endif 82 83 static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *, 84 const char [IFNAMSIZ], int, enum ieee80211_opmode, 85 int, const uint8_t [IEEE80211_ADDR_LEN], 86 const uint8_t [IEEE80211_ADDR_LEN]); 87 static void rt2860_vap_delete(struct ieee80211vap *); 88 static void rt2860_dma_map_addr(void *, bus_dma_segment_t *, int, int); 89 static int rt2860_alloc_tx_ring(struct rt2860_softc *, 90 struct rt2860_tx_ring *); 91 static void rt2860_reset_tx_ring(struct rt2860_softc *, 92 struct rt2860_tx_ring *); 93 static void rt2860_free_tx_ring(struct rt2860_softc *, 94 struct rt2860_tx_ring *); 95 static int rt2860_alloc_tx_pool(struct rt2860_softc *); 96 static void rt2860_free_tx_pool(struct rt2860_softc *); 97 static int rt2860_alloc_rx_ring(struct rt2860_softc *, 98 struct rt2860_rx_ring *); 99 static void rt2860_reset_rx_ring(struct rt2860_softc *, 100 struct rt2860_rx_ring *); 101 static void rt2860_free_rx_ring(struct rt2860_softc *, 102 struct rt2860_rx_ring *); 103 static void rt2860_updatestats(struct rt2860_softc *); 104 static void rt2860_newassoc(struct ieee80211_node *, int); 105 static void rt2860_node_free(struct ieee80211_node *); 106 #ifdef IEEE80211_HT 107 static int rt2860_ampdu_rx_start(struct ieee80211com *, 108 struct ieee80211_node *, uint8_t); 109 static void rt2860_ampdu_rx_stop(struct ieee80211com *, 110 struct ieee80211_node *, uint8_t); 111 #endif 112 static int rt2860_newstate(struct ieee80211vap *, enum ieee80211_state, 113 int); 114 static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 115 static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 116 static void rt2860_intr_coherent(struct rt2860_softc *); 117 static void rt2860_drain_stats_fifo(struct rt2860_softc *); 118 static void rt2860_tx_intr(struct rt2860_softc *, int); 119 static void rt2860_rx_intr(struct rt2860_softc *); 120 static void rt2860_tbtt_intr(struct rt2860_softc *); 121 static void rt2860_gp_intr(struct rt2860_softc *); 122 static int rt2860_tx(struct rt2860_softc *, struct mbuf *, 123 struct ieee80211_node *); 124 static int rt2860_raw_xmit(struct ieee80211_node *, struct mbuf *, 125 const struct ieee80211_bpf_params *); 126 static int rt2860_tx_raw(struct rt2860_softc *, struct mbuf *, 127 struct ieee80211_node *, 128 const struct ieee80211_bpf_params *params); 129 static int rt2860_transmit(struct ieee80211com *, struct mbuf *); 130 static void rt2860_start(struct rt2860_softc *); 131 static void rt2860_watchdog(void *); 132 static void rt2860_parent(struct ieee80211com *); 133 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 134 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 135 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 136 static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 137 static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 138 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 139 static void rt2860_enable_mrr(struct rt2860_softc *); 140 static void rt2860_set_txpreamble(struct rt2860_softc *); 141 static void rt2860_set_basicrates(struct rt2860_softc *, 142 const struct ieee80211_rateset *); 143 static void rt2860_scan_start(struct ieee80211com *); 144 static void rt2860_scan_end(struct ieee80211com *); 145 static void rt2860_set_channel(struct ieee80211com *); 146 static void rt2860_select_chan_group(struct rt2860_softc *, int); 147 static void rt2860_set_chan(struct rt2860_softc *, u_int); 148 static void rt3090_set_chan(struct rt2860_softc *, u_int); 149 static void rt5390_set_chan(struct rt2860_softc *, u_int); 150 static int rt3090_rf_init(struct rt2860_softc *); 151 static void rt5390_rf_init(struct rt2860_softc *); 152 static void rt3090_rf_wakeup(struct rt2860_softc *); 153 static void rt5390_rf_wakeup(struct rt2860_softc *); 154 static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 155 uint8_t *); 156 static void rt3090_rf_setup(struct rt2860_softc *); 157 static void rt2860_set_leds(struct rt2860_softc *, uint16_t); 158 static void rt2860_set_gp_timer(struct rt2860_softc *, int); 159 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 160 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 161 static void rt2860_update_promisc(struct ieee80211com *); 162 static void rt2860_updateslot(struct ieee80211com *); 163 static void rt2860_updateprot(struct rt2860_softc *); 164 static int rt2860_updateedca(struct ieee80211com *); 165 #ifdef HW_CRYPTO 166 static int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 167 struct ieee80211_key *); 168 static void rt2860_delete_key(struct ieee80211com *, 169 struct ieee80211_node *, struct ieee80211_key *); 170 #endif 171 static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 172 static const char *rt2860_get_rf(uint16_t); 173 static int rt2860_read_eeprom(struct rt2860_softc *, 174 uint8_t macaddr[IEEE80211_ADDR_LEN]); 175 static int rt2860_bbp_init(struct rt2860_softc *); 176 static void rt5390_bbp_init(struct rt2860_softc *); 177 static int rt2860_txrx_enable(struct rt2860_softc *); 178 static void rt2860_init(void *); 179 static void rt2860_init_locked(struct rt2860_softc *); 180 static void rt2860_stop(void *); 181 static void rt2860_stop_locked(struct rt2860_softc *); 182 static int rt2860_load_microcode(struct rt2860_softc *); 183 #ifdef NOT_YET 184 static void rt2860_calib(struct rt2860_softc *); 185 #endif 186 static void rt3090_set_rx_antenna(struct rt2860_softc *, int); 187 static void rt2860_switch_chan(struct rt2860_softc *, 188 struct ieee80211_channel *); 189 static int rt2860_setup_beacon(struct rt2860_softc *, 190 struct ieee80211vap *); 191 static void rt2860_enable_tsf_sync(struct rt2860_softc *); 192 193 static const struct { 194 uint32_t reg; 195 uint32_t val; 196 } rt2860_def_mac[] = { 197 RT2860_DEF_MAC 198 }; 199 200 static const struct { 201 uint8_t reg; 202 uint8_t val; 203 } rt2860_def_bbp[] = { 204 RT2860_DEF_BBP 205 }, rt5390_def_bbp[] = { 206 RT5390_DEF_BBP 207 }; 208 209 static const struct rfprog { 210 uint8_t chan; 211 uint32_t r1, r2, r3, r4; 212 } rt2860_rf2850[] = { 213 RT2860_RF2850 214 }; 215 216 struct { 217 uint8_t n, r, k; 218 } rt3090_freqs[] = { 219 RT3070_RF3052 220 }; 221 222 static const struct { 223 uint8_t reg; 224 uint8_t val; 225 } rt3090_def_rf[] = { 226 RT3070_DEF_RF 227 }, rt5390_def_rf[] = { 228 RT5390_DEF_RF 229 }, rt5392_def_rf[] = { 230 RT5392_DEF_RF 231 }; 232 233 int 234 rt2860_attach(device_t dev, int id) 235 { 236 struct rt2860_softc *sc = device_get_softc(dev); 237 struct ieee80211com *ic = &sc->sc_ic; 238 uint32_t tmp; 239 uint8_t bands[IEEE80211_MODE_BYTES]; 240 int error, ntries, qid; 241 242 sc->sc_dev = dev; 243 sc->sc_debug = 0; 244 245 #if defined(__DragonFly__) 246 lockinit(&sc->sc_mtx, device_get_nameunit(dev), 0, LK_CANRECURSE); 247 #else 248 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 249 MTX_DEF | MTX_RECURSE); 250 #endif 251 252 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 253 mbufq_init(&sc->sc_snd, ifqmaxlen); 254 255 /* wait for NIC to initialize */ 256 for (ntries = 0; ntries < 100; ntries++) { 257 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 258 if (tmp != 0 && tmp != 0xffffffff) 259 break; 260 DELAY(10); 261 } 262 if (ntries == 100) { 263 device_printf(sc->sc_dev, 264 "timeout waiting for NIC to initialize\n"); 265 error = EIO; 266 goto fail1; 267 } 268 sc->mac_ver = tmp >> 16; 269 sc->mac_rev = tmp & 0xffff; 270 271 if (sc->mac_ver != 0x2860 && 272 (id == 0x0681 || id == 0x0781 || id == 0x1059)) 273 sc->sc_flags |= RT2860_ADVANCED_PS; 274 275 /* retrieve RF rev. no and various other things from EEPROM */ 276 rt2860_read_eeprom(sc, ic->ic_macaddr); 277 #if defined(__DragonFly__) 278 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), " 279 "RF %s (MIMO %dT%dR), address %s\n", 280 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev), 281 sc->ntxchains, sc->nrxchains, ether_sprintf(ic->ic_macaddr)); 282 #else 283 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), " 284 "RF %s (MIMO %dT%dR), address %6D\n", 285 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev), 286 sc->ntxchains, sc->nrxchains, ic->ic_macaddr, ":"); 287 #endif 288 289 /* 290 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 291 */ 292 for (qid = 0; qid < 6; qid++) { 293 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 294 device_printf(sc->sc_dev, 295 "could not allocate Tx ring %d\n", qid); 296 goto fail2; 297 } 298 } 299 300 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 301 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 302 goto fail2; 303 } 304 305 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 306 device_printf(sc->sc_dev, "could not allocate Tx pool\n"); 307 goto fail3; 308 } 309 310 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 311 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 312 WME_AC_VO : 5; 313 314 ic->ic_softc = sc; 315 ic->ic_name = device_get_nameunit(dev); 316 ic->ic_opmode = IEEE80211_M_STA; 317 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 318 319 /* set device capabilities */ 320 ic->ic_caps = 321 IEEE80211_C_STA /* station mode */ 322 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 323 | IEEE80211_C_HOSTAP /* hostap mode */ 324 | IEEE80211_C_MONITOR /* monitor mode */ 325 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 326 | IEEE80211_C_WDS /* 4-address traffic works */ 327 | IEEE80211_C_MBSS /* mesh point link mode */ 328 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 329 | IEEE80211_C_SHSLOT /* short slot time supported */ 330 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 331 #if 0 332 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 333 #endif 334 | IEEE80211_C_WME /* 802.11e */ 335 ; 336 337 memset(bands, 0, sizeof(bands)); 338 setbit(bands, IEEE80211_MODE_11B); 339 setbit(bands, IEEE80211_MODE_11G); 340 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) 341 setbit(bands, IEEE80211_MODE_11A); 342 ieee80211_init_channels(ic, NULL, bands); 343 344 ieee80211_ifattach(ic); 345 346 ic->ic_wme.wme_update = rt2860_updateedca; 347 ic->ic_scan_start = rt2860_scan_start; 348 ic->ic_scan_end = rt2860_scan_end; 349 ic->ic_set_channel = rt2860_set_channel; 350 ic->ic_updateslot = rt2860_updateslot; 351 ic->ic_update_promisc = rt2860_update_promisc; 352 ic->ic_raw_xmit = rt2860_raw_xmit; 353 sc->sc_node_free = ic->ic_node_free; 354 ic->ic_node_free = rt2860_node_free; 355 ic->ic_newassoc = rt2860_newassoc; 356 ic->ic_transmit = rt2860_transmit; 357 ic->ic_parent = rt2860_parent; 358 ic->ic_vap_create = rt2860_vap_create; 359 ic->ic_vap_delete = rt2860_vap_delete; 360 361 ieee80211_radiotap_attach(ic, 362 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 363 RT2860_TX_RADIOTAP_PRESENT, 364 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 365 RT2860_RX_RADIOTAP_PRESENT); 366 367 #ifdef RAL_DEBUG 368 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 369 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 370 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 371 #endif 372 if (bootverbose) 373 ieee80211_announce(ic); 374 375 return 0; 376 377 fail3: rt2860_free_rx_ring(sc, &sc->rxq); 378 fail2: while (--qid >= 0) 379 rt2860_free_tx_ring(sc, &sc->txq[qid]); 380 #if defined(__DragonFly__) 381 fail1: lockuninit(&sc->sc_mtx); 382 #else 383 fail1: mtx_destroy(&sc->sc_mtx); 384 #endif 385 return error; 386 } 387 388 int 389 rt2860_detach(void *xsc) 390 { 391 struct rt2860_softc *sc = xsc; 392 struct ieee80211com *ic = &sc->sc_ic; 393 int qid; 394 395 RAL_LOCK(sc); 396 rt2860_stop_locked(sc); 397 RAL_UNLOCK(sc); 398 399 ieee80211_ifdetach(ic); 400 mbufq_drain(&sc->sc_snd); 401 for (qid = 0; qid < 6; qid++) 402 rt2860_free_tx_ring(sc, &sc->txq[qid]); 403 rt2860_free_rx_ring(sc, &sc->rxq); 404 rt2860_free_tx_pool(sc); 405 406 #if defined(__DragonFly__) 407 lockuninit(&sc->sc_mtx); 408 #else 409 mtx_destroy(&sc->sc_mtx); 410 #endif 411 412 return 0; 413 } 414 415 void 416 rt2860_shutdown(void *xsc) 417 { 418 struct rt2860_softc *sc = xsc; 419 420 rt2860_stop(sc); 421 } 422 423 void 424 rt2860_suspend(void *xsc) 425 { 426 struct rt2860_softc *sc = xsc; 427 428 rt2860_stop(sc); 429 } 430 431 void 432 rt2860_resume(void *xsc) 433 { 434 struct rt2860_softc *sc = xsc; 435 436 if (sc->sc_ic.ic_nrunning > 0) 437 rt2860_init(sc); 438 } 439 440 static struct ieee80211vap * 441 rt2860_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 442 enum ieee80211_opmode opmode, int flags, 443 const uint8_t bssid[IEEE80211_ADDR_LEN], 444 const uint8_t mac[IEEE80211_ADDR_LEN]) 445 { 446 struct rt2860_softc *sc = ic->ic_softc; 447 struct rt2860_vap *rvp; 448 struct ieee80211vap *vap; 449 450 switch (opmode) { 451 case IEEE80211_M_STA: 452 case IEEE80211_M_IBSS: 453 case IEEE80211_M_AHDEMO: 454 case IEEE80211_M_MONITOR: 455 case IEEE80211_M_HOSTAP: 456 case IEEE80211_M_MBSS: 457 /* XXXRP: TBD */ 458 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 459 device_printf(sc->sc_dev, "only 1 vap supported\n"); 460 return NULL; 461 } 462 if (opmode == IEEE80211_M_STA) 463 flags |= IEEE80211_CLONE_NOBEACONS; 464 break; 465 case IEEE80211_M_WDS: 466 if (TAILQ_EMPTY(&ic->ic_vaps) || 467 ic->ic_opmode != IEEE80211_M_HOSTAP) { 468 device_printf(sc->sc_dev, 469 "wds only supported in ap mode\n"); 470 return NULL; 471 } 472 /* 473 * Silently remove any request for a unique 474 * bssid; WDS vap's always share the local 475 * mac address. 476 */ 477 flags &= ~IEEE80211_CLONE_BSSID; 478 break; 479 default: 480 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 481 return NULL; 482 } 483 rvp = kmalloc(sizeof(struct rt2860_vap), M_80211_VAP, M_WAITOK | M_ZERO); 484 vap = &rvp->ral_vap; 485 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 486 487 /* override state transition machine */ 488 rvp->ral_newstate = vap->iv_newstate; 489 vap->iv_newstate = rt2860_newstate; 490 #if 0 491 vap->iv_update_beacon = rt2860_beacon_update; 492 #endif 493 494 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 495 vap->iv_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 496 497 ieee80211_ratectl_init(vap); 498 /* complete setup */ 499 ieee80211_vap_attach(vap, ieee80211_media_change, 500 ieee80211_media_status, mac); 501 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 502 ic->ic_opmode = opmode; 503 return vap; 504 } 505 506 static void 507 rt2860_vap_delete(struct ieee80211vap *vap) 508 { 509 struct rt2860_vap *rvp = RT2860_VAP(vap); 510 511 ieee80211_ratectl_deinit(vap); 512 ieee80211_vap_detach(vap); 513 kfree(rvp, M_80211_VAP); 514 } 515 516 static void 517 rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 518 { 519 if (error != 0) 520 return; 521 522 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 523 524 *(bus_addr_t *)arg = segs[0].ds_addr; 525 } 526 527 528 static int 529 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 530 { 531 int size, error; 532 533 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 534 535 #if defined(__DragonFly__) 536 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 537 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 538 size, 1, size, 0, &ring->desc_dmat); 539 #else 540 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 541 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 542 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 543 #endif 544 if (error != 0) { 545 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 546 goto fail; 547 } 548 549 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->txd, 550 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 551 if (error != 0) { 552 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 553 goto fail; 554 } 555 556 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->txd, 557 size, rt2860_dma_map_addr, &ring->paddr, 0); 558 if (error != 0) { 559 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 560 goto fail; 561 } 562 563 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 564 565 return 0; 566 567 fail: rt2860_free_tx_ring(sc, ring); 568 return error; 569 } 570 571 void 572 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 573 { 574 struct rt2860_tx_data *data; 575 int i; 576 577 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 578 if ((data = ring->data[i]) == NULL) 579 continue; /* nothing mapped in this slot */ 580 581 if (data->m != NULL) { 582 bus_dmamap_sync(sc->txwi_dmat, data->map, 583 BUS_DMASYNC_POSTWRITE); 584 bus_dmamap_unload(sc->txwi_dmat, data->map); 585 m_freem(data->m); 586 data->m = NULL; 587 } 588 if (data->ni != NULL) { 589 ieee80211_free_node(data->ni); 590 data->ni = NULL; 591 } 592 593 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 594 ring->data[i] = NULL; 595 } 596 597 ring->queued = 0; 598 ring->cur = ring->next = 0; 599 } 600 601 void 602 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 603 { 604 struct rt2860_tx_data *data; 605 int i; 606 607 if (ring->txd != NULL) { 608 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 609 BUS_DMASYNC_POSTWRITE); 610 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 611 bus_dmamem_free(ring->desc_dmat, ring->txd, ring->desc_map); 612 } 613 if (ring->desc_dmat != NULL) 614 bus_dma_tag_destroy(ring->desc_dmat); 615 616 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 617 if ((data = ring->data[i]) == NULL) 618 continue; /* nothing mapped in this slot */ 619 620 if (data->m != NULL) { 621 bus_dmamap_sync(sc->txwi_dmat, data->map, 622 BUS_DMASYNC_POSTWRITE); 623 bus_dmamap_unload(sc->txwi_dmat, data->map); 624 m_freem(data->m); 625 } 626 if (data->ni != NULL) 627 ieee80211_free_node(data->ni); 628 629 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 630 } 631 } 632 633 /* 634 * Allocate a pool of TX Wireless Information blocks. 635 */ 636 int 637 rt2860_alloc_tx_pool(struct rt2860_softc *sc) 638 { 639 caddr_t vaddr; 640 bus_addr_t paddr; 641 int i, size, error; 642 643 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 644 645 /* init data_pool early in case of failure.. */ 646 SLIST_INIT(&sc->data_pool); 647 648 #if defined(__DragonFly__) 649 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 650 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 651 size, 1, size, 0, &sc->txwi_dmat); 652 #else 653 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 654 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 655 size, 1, size, 0, NULL, NULL, &sc->txwi_dmat); 656 #endif 657 if (error != 0) { 658 device_printf(sc->sc_dev, "could not create txwi DMA tag\n"); 659 goto fail; 660 } 661 662 error = bus_dmamem_alloc(sc->txwi_dmat, (void **)&sc->txwi_vaddr, 663 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->txwi_map); 664 if (error != 0) { 665 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 666 goto fail; 667 } 668 669 error = bus_dmamap_load(sc->txwi_dmat, sc->txwi_map, 670 sc->txwi_vaddr, size, rt2860_dma_map_addr, &paddr, 0); 671 if (error != 0) { 672 device_printf(sc->sc_dev, "could not load txwi DMA map\n"); 673 goto fail; 674 } 675 676 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 677 678 vaddr = sc->txwi_vaddr; 679 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 680 struct rt2860_tx_data *data = &sc->data[i]; 681 682 error = bus_dmamap_create(sc->txwi_dmat, 0, &data->map); 683 if (error != 0) { 684 device_printf(sc->sc_dev, "could not create DMA map\n"); 685 goto fail; 686 } 687 data->txwi = (struct rt2860_txwi *)vaddr; 688 data->paddr = paddr; 689 vaddr += RT2860_TXWI_DMASZ; 690 paddr += RT2860_TXWI_DMASZ; 691 692 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 693 } 694 695 return 0; 696 697 fail: rt2860_free_tx_pool(sc); 698 return error; 699 } 700 701 void 702 rt2860_free_tx_pool(struct rt2860_softc *sc) 703 { 704 if (sc->txwi_vaddr != NULL) { 705 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, 706 BUS_DMASYNC_POSTWRITE); 707 bus_dmamap_unload(sc->txwi_dmat, sc->txwi_map); 708 bus_dmamem_free(sc->txwi_dmat, sc->txwi_vaddr, sc->txwi_map); 709 } 710 if (sc->txwi_dmat != NULL) 711 bus_dma_tag_destroy(sc->txwi_dmat); 712 713 while (!SLIST_EMPTY(&sc->data_pool)) { 714 struct rt2860_tx_data *data; 715 data = SLIST_FIRST(&sc->data_pool); 716 bus_dmamap_destroy(sc->txwi_dmat, data->map); 717 SLIST_REMOVE_HEAD(&sc->data_pool, next); 718 } 719 } 720 721 int 722 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 723 { 724 bus_addr_t physaddr; 725 int i, size, error; 726 727 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 728 729 #if defined(__DragonFly__) 730 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 731 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 732 size, 1, size, 0, &ring->desc_dmat); 733 #else 734 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 735 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 736 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 737 #endif 738 if (error != 0) { 739 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 740 goto fail; 741 } 742 743 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->rxd, 744 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 745 if (error != 0) { 746 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 747 goto fail; 748 } 749 750 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->rxd, 751 size, rt2860_dma_map_addr, &ring->paddr, 0); 752 if (error != 0) { 753 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 754 goto fail; 755 } 756 757 #if defined(__DragonFly__) 758 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 759 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 760 1, MCLBYTES, 0, &ring->data_dmat); 761 #else 762 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 763 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 764 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 765 #endif 766 if (error != 0) { 767 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 768 goto fail; 769 } 770 771 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 772 struct rt2860_rx_data *data = &ring->data[i]; 773 struct rt2860_rxd *rxd = &ring->rxd[i]; 774 775 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 776 if (error != 0) { 777 device_printf(sc->sc_dev, "could not create DMA map\n"); 778 goto fail; 779 } 780 781 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 782 if (data->m == NULL) { 783 device_printf(sc->sc_dev, 784 "could not allocate rx mbuf\n"); 785 error = ENOMEM; 786 goto fail; 787 } 788 789 error = bus_dmamap_load(ring->data_dmat, data->map, 790 mtod(data->m, void *), MCLBYTES, rt2860_dma_map_addr, 791 &physaddr, 0); 792 if (error != 0) { 793 device_printf(sc->sc_dev, 794 "could not load rx buf DMA map"); 795 goto fail; 796 } 797 798 rxd->sdp0 = htole32(physaddr); 799 rxd->sdl0 = htole16(MCLBYTES); 800 } 801 802 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 803 804 return 0; 805 806 fail: rt2860_free_rx_ring(sc, ring); 807 return error; 808 } 809 810 void 811 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 812 { 813 int i; 814 815 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 816 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 817 818 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 819 820 ring->cur = 0; 821 } 822 823 void 824 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 825 { 826 int i; 827 828 if (ring->rxd != NULL) { 829 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 830 BUS_DMASYNC_POSTWRITE); 831 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 832 bus_dmamem_free(ring->desc_dmat, ring->rxd, ring->desc_map); 833 } 834 if (ring->desc_dmat != NULL) 835 bus_dma_tag_destroy(ring->desc_dmat); 836 837 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 838 struct rt2860_rx_data *data = &ring->data[i]; 839 840 if (data->m != NULL) { 841 bus_dmamap_sync(ring->data_dmat, data->map, 842 BUS_DMASYNC_POSTREAD); 843 bus_dmamap_unload(ring->data_dmat, data->map); 844 m_freem(data->m); 845 } 846 if (data->map != NULL) 847 bus_dmamap_destroy(ring->data_dmat, data->map); 848 } 849 if (ring->data_dmat != NULL) 850 bus_dma_tag_destroy(ring->data_dmat); 851 } 852 853 static void 854 rt2860_updatestats(struct rt2860_softc *sc) 855 { 856 struct ieee80211com *ic = &sc->sc_ic; 857 858 /* 859 * In IBSS or HostAP modes (when the hardware sends beacons), the 860 * MAC can run into a livelock and start sending CTS-to-self frames 861 * like crazy if protection is enabled. Fortunately, we can detect 862 * when such a situation occurs and reset the MAC. 863 */ 864 if (ic->ic_curmode != IEEE80211_M_STA) { 865 /* check if we're in a livelock situation.. */ 866 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 867 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 868 /* ..and reset MAC/BBP for a while.. */ 869 DPRINTF(("CTS-to-self livelock detected\n")); 870 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 871 RAL_BARRIER_WRITE(sc); 872 DELAY(1); 873 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 874 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 875 } 876 } 877 } 878 879 static void 880 rt2860_newassoc(struct ieee80211_node *ni, int isnew) 881 { 882 struct ieee80211com *ic = ni->ni_ic; 883 struct rt2860_softc *sc = ic->ic_softc; 884 uint8_t wcid; 885 886 wcid = IEEE80211_AID(ni->ni_associd); 887 if (isnew && ni->ni_associd != 0) { 888 sc->wcid2ni[wcid] = ni; 889 890 /* init WCID table entry */ 891 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 892 ni->ni_macaddr, IEEE80211_ADDR_LEN); 893 } 894 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 895 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 896 } 897 898 static void 899 rt2860_node_free(struct ieee80211_node *ni) 900 { 901 struct ieee80211com *ic = ni->ni_ic; 902 struct rt2860_softc *sc = ic->ic_softc; 903 uint8_t wcid; 904 905 if (ni->ni_associd != 0) { 906 wcid = IEEE80211_AID(ni->ni_associd); 907 908 /* clear Rx WCID search table entry */ 909 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2); 910 } 911 sc->sc_node_free(ni); 912 } 913 914 #ifdef IEEE80211_HT 915 static int 916 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 917 uint8_t tid) 918 { 919 struct rt2860_softc *sc = ic->ic_softc; 920 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 921 uint32_t tmp; 922 923 /* update BA session mask */ 924 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 925 tmp |= (1 << tid) << 16; 926 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 927 return 0; 928 } 929 930 static void 931 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 932 uint8_t tid) 933 { 934 struct rt2860_softc *sc = ic->ic_softc; 935 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 936 uint32_t tmp; 937 938 /* update BA session mask */ 939 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 940 tmp &= ~((1 << tid) << 16); 941 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 942 } 943 #endif 944 945 int 946 rt2860_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 947 { 948 struct rt2860_vap *rvp = RT2860_VAP(vap); 949 struct ieee80211com *ic = vap->iv_ic; 950 struct rt2860_softc *sc = ic->ic_softc; 951 uint32_t tmp; 952 int error; 953 954 if (vap->iv_state == IEEE80211_S_RUN) { 955 /* turn link LED off */ 956 rt2860_set_leds(sc, RT2860_LED_RADIO); 957 } 958 959 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 960 /* abort TSF synchronization */ 961 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 962 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 963 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 964 RT2860_TBTT_TIMER_EN)); 965 } 966 967 rt2860_set_gp_timer(sc, 0); 968 969 error = rvp->ral_newstate(vap, nstate, arg); 970 if (error != 0) 971 return (error); 972 973 if (nstate == IEEE80211_S_RUN) { 974 struct ieee80211_node *ni = vap->iv_bss; 975 976 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 977 rt2860_enable_mrr(sc); 978 rt2860_set_txpreamble(sc); 979 rt2860_set_basicrates(sc, &ni->ni_rates); 980 rt2860_set_bssid(sc, ni->ni_bssid); 981 } 982 983 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 984 vap->iv_opmode == IEEE80211_M_IBSS || 985 vap->iv_opmode == IEEE80211_M_MBSS) { 986 error = rt2860_setup_beacon(sc, vap); 987 if (error != 0) 988 return error; 989 } 990 991 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 992 rt2860_enable_tsf_sync(sc); 993 rt2860_set_gp_timer(sc, 500); 994 } 995 996 /* turn link LED on */ 997 rt2860_set_leds(sc, RT2860_LED_RADIO | 998 (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ? 999 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 1000 } 1001 return error; 1002 } 1003 1004 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 1005 static uint16_t 1006 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 1007 { 1008 uint32_t tmp; 1009 uint16_t reg; 1010 int ntries; 1011 1012 addr *= 2; 1013 /*- 1014 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1015 * DATA0: F E D C 1016 * DATA1: B A 9 8 1017 * DATA2: 7 6 5 4 1018 * DATA3: 3 2 1 0 1019 */ 1020 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 1021 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1022 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1023 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 1024 for (ntries = 0; ntries < 500; ntries++) { 1025 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 1026 if (!(tmp & RT3070_EFSROM_KICK)) 1027 break; 1028 DELAY(2); 1029 } 1030 if (ntries == 500) 1031 return 0xffff; 1032 1033 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 1034 return 0xffff; /* address not found */ 1035 1036 /* determine to which 32-bit register our 16-bit word belongs */ 1037 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1038 tmp = RAL_READ(sc, reg); 1039 1040 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 1041 } 1042 1043 /* 1044 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 1045 * 93C66 or 93C86). 1046 */ 1047 static uint16_t 1048 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1049 { 1050 uint32_t tmp; 1051 uint16_t val; 1052 int n; 1053 1054 /* clock C once before the first command */ 1055 RT2860_EEPROM_CTL(sc, 0); 1056 1057 RT2860_EEPROM_CTL(sc, RT2860_S); 1058 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1059 RT2860_EEPROM_CTL(sc, RT2860_S); 1060 1061 /* write start bit (1) */ 1062 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1063 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1064 1065 /* write READ opcode (10) */ 1066 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1067 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1068 RT2860_EEPROM_CTL(sc, RT2860_S); 1069 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1070 1071 /* write address (A5-A0 or A7-A0) */ 1072 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1073 for (; n >= 0; n--) { 1074 RT2860_EEPROM_CTL(sc, RT2860_S | 1075 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1076 RT2860_EEPROM_CTL(sc, RT2860_S | 1077 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1078 } 1079 1080 RT2860_EEPROM_CTL(sc, RT2860_S); 1081 1082 /* read data Q15-Q0 */ 1083 val = 0; 1084 for (n = 15; n >= 0; n--) { 1085 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1086 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1087 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1088 RT2860_EEPROM_CTL(sc, RT2860_S); 1089 } 1090 1091 RT2860_EEPROM_CTL(sc, 0); 1092 1093 /* clear Chip Select and clock C */ 1094 RT2860_EEPROM_CTL(sc, RT2860_S); 1095 RT2860_EEPROM_CTL(sc, 0); 1096 RT2860_EEPROM_CTL(sc, RT2860_C); 1097 1098 return val; 1099 } 1100 1101 static __inline uint16_t 1102 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1103 { 1104 /* either eFUSE ROM or EEPROM */ 1105 return sc->sc_srom_read(sc, addr); 1106 } 1107 1108 static void 1109 rt2860_intr_coherent(struct rt2860_softc *sc) 1110 { 1111 uint32_t tmp; 1112 1113 /* DMA finds data coherent event when checking the DDONE bit */ 1114 1115 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1116 1117 /* restart DMA engine */ 1118 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1119 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1120 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1121 1122 (void)rt2860_txrx_enable(sc); 1123 } 1124 1125 static void 1126 rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1127 { 1128 struct ieee80211_node *ni; 1129 uint32_t stat; 1130 int retrycnt; 1131 uint8_t wcid, mcs, pid; 1132 1133 /* drain Tx status FIFO (maxsize = 16) */ 1134 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1135 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1136 1137 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1138 ni = sc->wcid2ni[wcid]; 1139 1140 /* if no ACK was requested, no feedback is available */ 1141 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff || ni == NULL) 1142 continue; 1143 1144 /* update per-STA AMRR stats */ 1145 if (stat & RT2860_TXQ_OK) { 1146 /* 1147 * Check if there were retries, ie if the Tx success 1148 * rate is different from the requested rate. Note 1149 * that it works only because we do not allow rate 1150 * fallback from OFDM to CCK. 1151 */ 1152 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1153 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1154 if (mcs + 1 != pid) 1155 retrycnt = 1; 1156 else 1157 retrycnt = 0; 1158 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 1159 IEEE80211_RATECTL_TX_SUCCESS, &retrycnt, NULL); 1160 } else { 1161 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 1162 IEEE80211_RATECTL_TX_FAILURE, &retrycnt, NULL); 1163 if_inc_counter(ni->ni_vap->iv_ifp, 1164 IFCOUNTER_OERRORS, 1); 1165 } 1166 } 1167 } 1168 1169 static void 1170 rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1171 { 1172 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1173 uint32_t hw; 1174 1175 rt2860_drain_stats_fifo(sc); 1176 1177 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1178 while (ring->next != hw) { 1179 struct rt2860_tx_data *data = ring->data[ring->next]; 1180 1181 if (data != NULL) { 1182 bus_dmamap_sync(sc->txwi_dmat, data->map, 1183 BUS_DMASYNC_POSTWRITE); 1184 bus_dmamap_unload(sc->txwi_dmat, data->map); 1185 if (data->m->m_flags & M_TXCB) { 1186 ieee80211_process_callback(data->ni, data->m, 1187 0); 1188 } 1189 ieee80211_tx_complete(data->ni, data->m, 0); 1190 data->ni = NULL; 1191 data->m = NULL; 1192 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1193 ring->data[ring->next] = NULL; 1194 } 1195 ring->queued--; 1196 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1197 } 1198 1199 sc->sc_tx_timer = 0; 1200 if (ring->queued < RT2860_TX_RING_COUNT) 1201 sc->qfullmsk &= ~(1 << qid); 1202 rt2860_start(sc); 1203 } 1204 1205 /* 1206 * Return the Rx chain with the highest RSSI for a given frame. 1207 */ 1208 static __inline uint8_t 1209 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1210 { 1211 uint8_t rxchain = 0; 1212 1213 if (sc->nrxchains > 1) { 1214 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1215 rxchain = 1; 1216 if (sc->nrxchains > 2) 1217 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1218 rxchain = 2; 1219 } 1220 return rxchain; 1221 } 1222 1223 static void 1224 rt2860_rx_intr(struct rt2860_softc *sc) 1225 { 1226 struct rt2860_rx_radiotap_header *tap; 1227 struct ieee80211com *ic = &sc->sc_ic; 1228 struct ieee80211_frame *wh; 1229 struct ieee80211_node *ni; 1230 struct mbuf *m, *m1; 1231 bus_addr_t physaddr; 1232 uint32_t hw; 1233 uint16_t phy; 1234 uint8_t ant; 1235 int8_t rssi, nf; 1236 int error; 1237 1238 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1239 while (sc->rxq.cur != hw) { 1240 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1241 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1242 struct rt2860_rxwi *rxwi; 1243 1244 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1245 BUS_DMASYNC_POSTREAD); 1246 1247 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1248 DPRINTF(("RXD DDONE bit not set!\n")); 1249 break; /* should not happen */ 1250 } 1251 1252 if (__predict_false(rxd->flags & 1253 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1254 #if defined(__DragonFly__) 1255 /* not implemented */ 1256 #else 1257 counter_u64_add(ic->ic_ierrors, 1); 1258 #endif 1259 goto skip; 1260 } 1261 1262 #ifdef HW_CRYPTO 1263 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1264 /* report MIC failures to net80211 for TKIP */ 1265 ic->ic_stats.is_rx_locmicfail++; 1266 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1267 #if defined(__DragonFly__) 1268 /* not implemented */ 1269 #else 1270 counter_u64_add(ic->ic_ierrors, 1); 1271 #endif 1272 goto skip; 1273 } 1274 #endif 1275 1276 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1277 if (__predict_false(m1 == NULL)) { 1278 #if defined(__DragonFly__) 1279 /* not implemented */ 1280 #else 1281 counter_u64_add(ic->ic_ierrors, 1); 1282 #endif 1283 goto skip; 1284 } 1285 1286 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1287 BUS_DMASYNC_POSTREAD); 1288 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1289 1290 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1291 mtod(m1, void *), MCLBYTES, rt2860_dma_map_addr, 1292 &physaddr, 0); 1293 if (__predict_false(error != 0)) { 1294 m_freem(m1); 1295 1296 /* try to reload the old mbuf */ 1297 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1298 mtod(data->m, void *), MCLBYTES, 1299 rt2860_dma_map_addr, &physaddr, 0); 1300 if (__predict_false(error != 0)) { 1301 panic("%s: could not load old rx mbuf", 1302 device_get_name(sc->sc_dev)); 1303 } 1304 /* physical address may have changed */ 1305 rxd->sdp0 = htole32(physaddr); 1306 #if defined(__DragonFly__) 1307 /* not implemented */ 1308 #else 1309 counter_u64_add(ic->ic_ierrors, 1); 1310 #endif 1311 goto skip; 1312 } 1313 1314 /* 1315 * New mbuf successfully loaded, update Rx ring and continue 1316 * processing. 1317 */ 1318 m = data->m; 1319 data->m = m1; 1320 rxd->sdp0 = htole32(physaddr); 1321 1322 rxwi = mtod(m, struct rt2860_rxwi *); 1323 1324 /* finalize mbuf */ 1325 m->m_data = (caddr_t)(rxwi + 1); 1326 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff; 1327 1328 wh = mtod(m, struct ieee80211_frame *); 1329 #ifdef HW_CRYPTO 1330 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1331 /* frame is decrypted by hardware */ 1332 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1333 } 1334 #endif 1335 1336 /* HW may insert 2 padding bytes after 802.11 header */ 1337 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1338 u_int hdrlen = ieee80211_hdrsize(wh); 1339 bcopy(wh, (caddr_t)wh + 2, hdrlen); 1340 m->m_data += 2; 1341 wh = mtod(m, struct ieee80211_frame *); 1342 } 1343 1344 ant = rt2860_maxrssi_chain(sc, rxwi); 1345 rssi = rt2860_rssi2dbm(sc, rxwi->rssi[ant], ant); 1346 nf = RT2860_NOISE_FLOOR; 1347 1348 if (ieee80211_radiotap_active(ic)) { 1349 tap = &sc->sc_rxtap; 1350 tap->wr_flags = 0; 1351 tap->wr_antenna = ant; 1352 tap->wr_antsignal = nf + rssi; 1353 tap->wr_antnoise = nf; 1354 /* in case it can't be found below */ 1355 tap->wr_rate = 2; 1356 phy = le16toh(rxwi->phy); 1357 switch (phy & RT2860_PHY_MODE) { 1358 case RT2860_PHY_CCK: 1359 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1360 case 0: tap->wr_rate = 2; break; 1361 case 1: tap->wr_rate = 4; break; 1362 case 2: tap->wr_rate = 11; break; 1363 case 3: tap->wr_rate = 22; break; 1364 } 1365 if (phy & RT2860_PHY_SHPRE) 1366 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1367 break; 1368 case RT2860_PHY_OFDM: 1369 switch (phy & RT2860_PHY_MCS) { 1370 case 0: tap->wr_rate = 12; break; 1371 case 1: tap->wr_rate = 18; break; 1372 case 2: tap->wr_rate = 24; break; 1373 case 3: tap->wr_rate = 36; break; 1374 case 4: tap->wr_rate = 48; break; 1375 case 5: tap->wr_rate = 72; break; 1376 case 6: tap->wr_rate = 96; break; 1377 case 7: tap->wr_rate = 108; break; 1378 } 1379 break; 1380 } 1381 } 1382 1383 RAL_UNLOCK(sc); 1384 wh = mtod(m, struct ieee80211_frame *); 1385 1386 /* send the frame to the 802.11 layer */ 1387 ni = ieee80211_find_rxnode(ic, 1388 (struct ieee80211_frame_min *)wh); 1389 if (ni != NULL) { 1390 (void)ieee80211_input(ni, m, rssi - nf, nf); 1391 ieee80211_free_node(ni); 1392 } else 1393 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 1394 1395 RAL_LOCK(sc); 1396 1397 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1398 1399 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1400 BUS_DMASYNC_PREWRITE); 1401 1402 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1403 } 1404 1405 /* tell HW what we have processed */ 1406 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1407 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1408 } 1409 1410 static void 1411 rt2860_tbtt_intr(struct rt2860_softc *sc) 1412 { 1413 #if 0 1414 struct ieee80211com *ic = &sc->sc_ic; 1415 1416 #ifndef IEEE80211_STA_ONLY 1417 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1418 /* one less beacon until next DTIM */ 1419 if (ic->ic_dtim_count == 0) 1420 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1421 else 1422 ic->ic_dtim_count--; 1423 1424 /* update dynamic parts of beacon */ 1425 rt2860_setup_beacon(sc); 1426 1427 /* flush buffered multicast frames */ 1428 if (ic->ic_dtim_count == 0) 1429 ieee80211_notify_dtim(ic); 1430 } 1431 #endif 1432 /* check if protection mode has changed */ 1433 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1434 rt2860_updateprot(sc); 1435 sc->sc_ic_flags = ic->ic_flags; 1436 } 1437 #endif 1438 } 1439 1440 static void 1441 rt2860_gp_intr(struct rt2860_softc *sc) 1442 { 1443 struct ieee80211com *ic = &sc->sc_ic; 1444 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1445 1446 DPRINTFN(2, ("GP timeout state=%d\n", vap->iv_state)); 1447 1448 if (vap->iv_state == IEEE80211_S_RUN) 1449 rt2860_updatestats(sc); 1450 } 1451 1452 void 1453 rt2860_intr(void *arg) 1454 { 1455 struct rt2860_softc *sc = arg; 1456 uint32_t r; 1457 1458 RAL_LOCK(sc); 1459 1460 r = RAL_READ(sc, RT2860_INT_STATUS); 1461 if (__predict_false(r == 0xffffffff)) { 1462 RAL_UNLOCK(sc); 1463 return; /* device likely went away */ 1464 } 1465 if (r == 0) { 1466 RAL_UNLOCK(sc); 1467 return; /* not for us */ 1468 } 1469 1470 /* acknowledge interrupts */ 1471 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1472 1473 if (r & RT2860_TX_RX_COHERENT) 1474 rt2860_intr_coherent(sc); 1475 1476 if (r & RT2860_MAC_INT_2) /* TX status */ 1477 rt2860_drain_stats_fifo(sc); 1478 1479 if (r & RT2860_TX_DONE_INT5) 1480 rt2860_tx_intr(sc, 5); 1481 1482 if (r & RT2860_RX_DONE_INT) 1483 rt2860_rx_intr(sc); 1484 1485 if (r & RT2860_TX_DONE_INT4) 1486 rt2860_tx_intr(sc, 4); 1487 1488 if (r & RT2860_TX_DONE_INT3) 1489 rt2860_tx_intr(sc, 3); 1490 1491 if (r & RT2860_TX_DONE_INT2) 1492 rt2860_tx_intr(sc, 2); 1493 1494 if (r & RT2860_TX_DONE_INT1) 1495 rt2860_tx_intr(sc, 1); 1496 1497 if (r & RT2860_TX_DONE_INT0) 1498 rt2860_tx_intr(sc, 0); 1499 1500 if (r & RT2860_MAC_INT_0) /* TBTT */ 1501 rt2860_tbtt_intr(sc); 1502 1503 if (r & RT2860_MAC_INT_3) { /* Auto wakeup */ 1504 /* TBD wakeup */; 1505 } 1506 1507 if (r & RT2860_MAC_INT_4) /* GP timer */ 1508 rt2860_gp_intr(sc); 1509 1510 RAL_UNLOCK(sc); 1511 } 1512 1513 static int 1514 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1515 { 1516 struct ieee80211com *ic = &sc->sc_ic; 1517 struct ieee80211vap *vap = ni->ni_vap; 1518 struct rt2860_tx_ring *ring; 1519 struct rt2860_tx_data *data; 1520 struct rt2860_txd *txd; 1521 struct rt2860_txwi *txwi; 1522 struct ieee80211_frame *wh; 1523 const struct ieee80211_txparam *tp; 1524 struct ieee80211_key *k; 1525 struct mbuf *m1; 1526 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1527 bus_dma_segment_t *seg; 1528 u_int hdrlen; 1529 uint16_t qos, dur; 1530 uint8_t type, qsel, mcs, pid, tid, qid; 1531 int i, nsegs, ntxds, pad, rate, ridx, error; 1532 1533 #if defined(__DragonFly__) 1534 ntxds = 0; /* quiet gcc5 */ 1535 #endif 1536 /* the data pool contains at least one element, pick the first */ 1537 data = SLIST_FIRST(&sc->data_pool); 1538 1539 wh = mtod(m, struct ieee80211_frame *); 1540 1541 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1542 k = ieee80211_crypto_encap(ni, m); 1543 if (k == NULL) { 1544 m_freem(m); 1545 return ENOBUFS; 1546 } 1547 1548 /* packet header may have moved, reset our local pointer */ 1549 wh = mtod(m, struct ieee80211_frame *); 1550 } 1551 1552 hdrlen = ieee80211_anyhdrsize(wh); 1553 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1554 1555 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1556 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1557 rate = tp->mcastrate; 1558 } else if (m->m_flags & M_EAPOL) { 1559 rate = tp->mgmtrate; 1560 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1561 rate = tp->ucastrate; 1562 } else { 1563 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1564 rate = ni->ni_txrate; 1565 } 1566 rate &= IEEE80211_RATE_VAL; 1567 1568 qid = M_WME_GETAC(m); 1569 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1570 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 1571 tid = qos & IEEE80211_QOS_TID; 1572 } else { 1573 qos = 0; 1574 tid = 0; 1575 } 1576 ring = &sc->txq[qid]; 1577 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, rate); 1578 1579 /* get MCS code from rate index */ 1580 mcs = rt2860_rates[ridx].mcs; 1581 1582 /* setup TX Wireless Information */ 1583 txwi = data->txwi; 1584 txwi->flags = 0; 1585 /* let HW generate seq numbers for non-QoS frames */ 1586 txwi->xflags = qos ? 0 : RT2860_TX_NSEQ; 1587 if (type == IEEE80211_FC0_TYPE_DATA) 1588 txwi->wcid = IEEE80211_AID(ni->ni_associd); 1589 else 1590 txwi->wcid = 0xff; 1591 txwi->len = htole16(m->m_pkthdr.len); 1592 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1593 txwi->phy = htole16(RT2860_PHY_CCK); 1594 if (ridx != RT2860_RIDX_CCK1 && 1595 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1596 mcs |= RT2860_PHY_SHPRE; 1597 } else 1598 txwi->phy = htole16(RT2860_PHY_OFDM); 1599 txwi->phy |= htole16(mcs); 1600 1601 /* 1602 * We store the MCS code into the driver-private PacketID field. 1603 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1604 * that we know at which initial rate the frame was transmitted. 1605 * We add 1 to the MCS code because setting the PacketID field to 1606 * 0 means that we don't want feedback in TX_STAT_FIFO. 1607 */ 1608 pid = (mcs + 1) & 0xf; 1609 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1610 1611 /* check if RTS/CTS or CTS-to-self protection is required */ 1612 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1613 (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold || 1614 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1615 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1616 txwi->txop = RT2860_TX_TXOP_HT; 1617 else 1618 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1619 1620 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1621 (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 1622 IEEE80211_QOS_ACKPOLICY_NOACK)) { 1623 txwi->xflags |= RT2860_TX_ACK; 1624 1625 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1626 dur = rt2860_rates[ridx].sp_ack_dur; 1627 else 1628 dur = rt2860_rates[ridx].lp_ack_dur; 1629 *(uint16_t *)wh->i_dur = htole16(dur); 1630 } 1631 /* ask MAC to insert timestamp into probe responses */ 1632 if ((wh->i_fc[0] & 1633 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1634 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1635 /* NOTE: beacons do not pass through tx_data() */ 1636 txwi->flags |= RT2860_TX_TS; 1637 1638 if (ieee80211_radiotap_active_vap(vap)) { 1639 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1640 1641 tap->wt_flags = 0; 1642 tap->wt_rate = rate; 1643 if (mcs & RT2860_PHY_SHPRE) 1644 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1645 1646 ieee80211_radiotap_tx(vap, m); 1647 } 1648 1649 pad = (hdrlen + 3) & ~3; 1650 1651 /* copy and trim 802.11 header */ 1652 memcpy(txwi + 1, wh, hdrlen); 1653 m_adj(m, hdrlen); 1654 1655 #if defined(__DragonFly__) 1656 error = bus_dmamap_load_mbuf_segment(sc->txwi_dmat, data->map, m, 1657 segs, 1, &nsegs, BUS_DMA_NOWAIT); 1658 #else 1659 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1660 &nsegs, 0); 1661 #endif 1662 if (__predict_false(error != 0 && error != EFBIG)) { 1663 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1664 error); 1665 m_freem(m); 1666 return error; 1667 } 1668 if (__predict_true(error == 0)) { 1669 /* determine how many TXDs are required */ 1670 ntxds = 1 + (nsegs / 2); 1671 1672 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1673 /* not enough free TXDs, force mbuf defrag */ 1674 bus_dmamap_unload(sc->txwi_dmat, data->map); 1675 error = EFBIG; 1676 } 1677 } 1678 if (__predict_false(error != 0)) { 1679 m1 = m_defrag(m, M_NOWAIT); 1680 if (m1 == NULL) { 1681 device_printf(sc->sc_dev, 1682 "could not defragment mbuf\n"); 1683 m_freem(m); 1684 return ENOBUFS; 1685 } 1686 m = m1; 1687 1688 #if defined(__DragonFly__) 1689 error = bus_dmamap_load_mbuf_segment(sc->txwi_dmat, data->map, 1690 m, segs, 1, &nsegs, BUS_DMA_NOWAIT); 1691 #else 1692 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1693 segs, &nsegs, 0); 1694 #endif 1695 if (__predict_false(error != 0)) { 1696 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1697 error); 1698 m_freem(m); 1699 return error; 1700 } 1701 1702 /* determine how many TXDs are now required */ 1703 ntxds = 1 + (nsegs / 2); 1704 1705 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1706 /* this is a hopeless case, drop the mbuf! */ 1707 bus_dmamap_unload(sc->txwi_dmat, data->map); 1708 m_freem(m); 1709 return ENOBUFS; 1710 } 1711 } 1712 1713 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1714 1715 /* first segment is TXWI + 802.11 header */ 1716 txd = &ring->txd[ring->cur]; 1717 txd->sdp0 = htole32(data->paddr); 1718 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1719 txd->flags = qsel; 1720 1721 /* setup payload segments */ 1722 seg = &segs[0]; 1723 for (i = nsegs; i >= 2; i -= 2) { 1724 txd->sdp1 = htole32(seg->ds_addr); 1725 txd->sdl1 = htole16(seg->ds_len); 1726 seg++; 1727 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1728 /* grab a new Tx descriptor */ 1729 txd = &ring->txd[ring->cur]; 1730 txd->sdp0 = htole32(seg->ds_addr); 1731 txd->sdl0 = htole16(seg->ds_len); 1732 txd->flags = qsel; 1733 seg++; 1734 } 1735 /* finalize last segment */ 1736 if (i > 0) { 1737 txd->sdp1 = htole32(seg->ds_addr); 1738 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1739 } else { 1740 txd->sdl0 |= htole16(RT2860_TX_LS0); 1741 txd->sdl1 = 0; 1742 } 1743 1744 /* remove from the free pool and link it into the SW Tx slot */ 1745 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1746 data->m = m; 1747 data->ni = ni; 1748 ring->data[ring->cur] = data; 1749 1750 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1751 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1752 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1753 1754 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1755 qid, txwi->wcid, nsegs, ridx)); 1756 1757 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1758 ring->queued += ntxds; 1759 if (ring->queued >= RT2860_TX_RING_COUNT) 1760 sc->qfullmsk |= 1 << qid; 1761 1762 /* kick Tx */ 1763 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1764 1765 return 0; 1766 } 1767 1768 static int 1769 rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1770 const struct ieee80211_bpf_params *params) 1771 { 1772 struct ieee80211com *ic = ni->ni_ic; 1773 struct rt2860_softc *sc = ic->ic_softc; 1774 int error; 1775 1776 RAL_LOCK(sc); 1777 1778 /* prevent management frames from being sent if we're not ready */ 1779 if (!(sc->sc_flags & RT2860_RUNNING)) { 1780 RAL_UNLOCK(sc); 1781 m_freem(m); 1782 return ENETDOWN; 1783 } 1784 if (params == NULL) { 1785 /* 1786 * Legacy path; interpret frame contents to decide 1787 * precisely how to send the frame. 1788 */ 1789 error = rt2860_tx(sc, m, ni); 1790 } else { 1791 /* 1792 * Caller supplied explicit parameters to use in 1793 * sending the frame. 1794 */ 1795 error = rt2860_tx_raw(sc, m, ni, params); 1796 } 1797 sc->sc_tx_timer = 5; 1798 RAL_UNLOCK(sc); 1799 return error; 1800 } 1801 1802 static int 1803 rt2860_tx_raw(struct rt2860_softc *sc, struct mbuf *m, 1804 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 1805 { 1806 struct ieee80211com *ic = &sc->sc_ic; 1807 struct ieee80211vap *vap = ni->ni_vap; 1808 struct rt2860_tx_ring *ring; 1809 struct rt2860_tx_data *data; 1810 struct rt2860_txd *txd; 1811 struct rt2860_txwi *txwi; 1812 struct ieee80211_frame *wh; 1813 struct mbuf *m1; 1814 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1815 bus_dma_segment_t *seg; 1816 u_int hdrlen; 1817 uint16_t dur; 1818 uint8_t type, qsel, mcs, pid, tid, qid; 1819 int i, nsegs, ntxds, pad, rate, ridx, error; 1820 1821 #if defined(__DragonFly__) 1822 ntxds = 0; /* quiet gcc5 */ 1823 #endif 1824 /* the data pool contains at least one element, pick the first */ 1825 data = SLIST_FIRST(&sc->data_pool); 1826 1827 wh = mtod(m, struct ieee80211_frame *); 1828 hdrlen = ieee80211_hdrsize(wh); 1829 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1830 1831 /* Choose a TX rate index. */ 1832 rate = params->ibp_rate0; 1833 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 1834 rate & IEEE80211_RATE_VAL); 1835 if (ridx == (uint8_t)-1) { 1836 /* XXX fall back to mcast/mgmt rate? */ 1837 m_freem(m); 1838 return EINVAL; 1839 } 1840 1841 qid = params->ibp_pri & 3; 1842 tid = 0; 1843 ring = &sc->txq[qid]; 1844 1845 /* get MCS code from rate index */ 1846 mcs = rt2860_rates[ridx].mcs; 1847 1848 /* setup TX Wireless Information */ 1849 txwi = data->txwi; 1850 txwi->flags = 0; 1851 /* let HW generate seq numbers for non-QoS frames */ 1852 txwi->xflags = params->ibp_pri & 3 ? 0 : RT2860_TX_NSEQ; 1853 txwi->wcid = 0xff; 1854 txwi->len = htole16(m->m_pkthdr.len); 1855 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1856 txwi->phy = htole16(RT2860_PHY_CCK); 1857 if (ridx != RT2860_RIDX_CCK1 && 1858 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1859 mcs |= RT2860_PHY_SHPRE; 1860 } else 1861 txwi->phy = htole16(RT2860_PHY_OFDM); 1862 txwi->phy |= htole16(mcs); 1863 1864 /* 1865 * We store the MCS code into the driver-private PacketID field. 1866 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1867 * that we know at which initial rate the frame was transmitted. 1868 * We add 1 to the MCS code because setting the PacketID field to 1869 * 0 means that we don't want feedback in TX_STAT_FIFO. 1870 */ 1871 pid = (mcs + 1) & 0xf; 1872 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1873 1874 /* check if RTS/CTS or CTS-to-self protection is required */ 1875 if (params->ibp_flags & IEEE80211_BPF_RTS || 1876 params->ibp_flags & IEEE80211_BPF_CTS) 1877 txwi->txop = RT2860_TX_TXOP_HT; 1878 else 1879 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1880 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 1881 txwi->xflags |= RT2860_TX_ACK; 1882 1883 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1884 dur = rt2860_rates[ridx].sp_ack_dur; 1885 else 1886 dur = rt2860_rates[ridx].lp_ack_dur; 1887 *(uint16_t *)wh->i_dur = htole16(dur); 1888 } 1889 /* ask MAC to insert timestamp into probe responses */ 1890 if ((wh->i_fc[0] & 1891 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1892 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1893 /* NOTE: beacons do not pass through tx_data() */ 1894 txwi->flags |= RT2860_TX_TS; 1895 1896 if (ieee80211_radiotap_active_vap(vap)) { 1897 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1898 1899 tap->wt_flags = 0; 1900 tap->wt_rate = rate; 1901 if (mcs & RT2860_PHY_SHPRE) 1902 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1903 1904 ieee80211_radiotap_tx(vap, m); 1905 } 1906 1907 pad = (hdrlen + 3) & ~3; 1908 1909 /* copy and trim 802.11 header */ 1910 memcpy(txwi + 1, wh, hdrlen); 1911 m_adj(m, hdrlen); 1912 1913 #if defined(__DragonFly__) 1914 error = bus_dmamap_load_mbuf_segment(sc->txwi_dmat, data->map, m, 1915 segs, 1, &nsegs, BUS_DMA_NOWAIT); 1916 #else 1917 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1918 &nsegs, 0); 1919 #endif 1920 if (__predict_false(error != 0 && error != EFBIG)) { 1921 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1922 error); 1923 m_freem(m); 1924 return error; 1925 } 1926 if (__predict_true(error == 0)) { 1927 /* determine how many TXDs are required */ 1928 ntxds = 1 + (nsegs / 2); 1929 1930 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1931 /* not enough free TXDs, force mbuf defrag */ 1932 bus_dmamap_unload(sc->txwi_dmat, data->map); 1933 error = EFBIG; 1934 } 1935 } 1936 if (__predict_false(error != 0)) { 1937 m1 = m_defrag(m, M_NOWAIT); 1938 if (m1 == NULL) { 1939 device_printf(sc->sc_dev, 1940 "could not defragment mbuf\n"); 1941 m_freem(m); 1942 return ENOBUFS; 1943 } 1944 m = m1; 1945 1946 #if defined(__DragonFly__) 1947 error = bus_dmamap_load_mbuf_segment(sc->txwi_dmat, data->map, 1948 m, segs, 1, &nsegs, BUS_DMA_NOWAIT); 1949 #else 1950 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1951 segs, &nsegs, 0); 1952 #endif 1953 if (__predict_false(error != 0)) { 1954 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1955 error); 1956 m_freem(m); 1957 return error; 1958 } 1959 1960 /* determine how many TXDs are now required */ 1961 ntxds = 1 + (nsegs / 2); 1962 1963 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1964 /* this is a hopeless case, drop the mbuf! */ 1965 bus_dmamap_unload(sc->txwi_dmat, data->map); 1966 m_freem(m); 1967 return ENOBUFS; 1968 } 1969 } 1970 1971 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1972 1973 /* first segment is TXWI + 802.11 header */ 1974 txd = &ring->txd[ring->cur]; 1975 txd->sdp0 = htole32(data->paddr); 1976 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1977 txd->flags = qsel; 1978 1979 /* setup payload segments */ 1980 seg = &segs[0]; 1981 for (i = nsegs; i >= 2; i -= 2) { 1982 txd->sdp1 = htole32(seg->ds_addr); 1983 txd->sdl1 = htole16(seg->ds_len); 1984 seg++; 1985 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1986 /* grab a new Tx descriptor */ 1987 txd = &ring->txd[ring->cur]; 1988 txd->sdp0 = htole32(seg->ds_addr); 1989 txd->sdl0 = htole16(seg->ds_len); 1990 txd->flags = qsel; 1991 seg++; 1992 } 1993 /* finalize last segment */ 1994 if (i > 0) { 1995 txd->sdp1 = htole32(seg->ds_addr); 1996 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1997 } else { 1998 txd->sdl0 |= htole16(RT2860_TX_LS0); 1999 txd->sdl1 = 0; 2000 } 2001 2002 /* remove from the free pool and link it into the SW Tx slot */ 2003 SLIST_REMOVE_HEAD(&sc->data_pool, next); 2004 data->m = m; 2005 data->ni = ni; 2006 ring->data[ring->cur] = data; 2007 2008 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 2009 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 2010 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 2011 2012 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 2013 qid, txwi->wcid, nsegs, ridx)); 2014 2015 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 2016 ring->queued += ntxds; 2017 if (ring->queued >= RT2860_TX_RING_COUNT) 2018 sc->qfullmsk |= 1 << qid; 2019 2020 /* kick Tx */ 2021 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 2022 2023 return 0; 2024 } 2025 2026 static int 2027 rt2860_transmit(struct ieee80211com *ic, struct mbuf *m) 2028 { 2029 struct rt2860_softc *sc = ic->ic_softc; 2030 int error; 2031 2032 RAL_LOCK(sc); 2033 if ((sc->sc_flags & RT2860_RUNNING) == 0) { 2034 RAL_UNLOCK(sc); 2035 return (ENXIO); 2036 } 2037 error = mbufq_enqueue(&sc->sc_snd, m); 2038 if (error) { 2039 RAL_UNLOCK(sc); 2040 return (error); 2041 } 2042 rt2860_start(sc); 2043 RAL_UNLOCK(sc); 2044 2045 return (0); 2046 } 2047 2048 static void 2049 rt2860_start(struct rt2860_softc *sc) 2050 { 2051 struct ieee80211_node *ni; 2052 struct mbuf *m; 2053 2054 RAL_LOCK_ASSERT(sc); 2055 2056 if ((sc->sc_flags & RT2860_RUNNING) == 0) 2057 return; 2058 2059 while (!SLIST_EMPTY(&sc->data_pool) && sc->qfullmsk == 0 && 2060 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 2061 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2062 if (rt2860_tx(sc, m, ni) != 0) { 2063 if_inc_counter(ni->ni_vap->iv_ifp, 2064 IFCOUNTER_OERRORS, 1); 2065 ieee80211_free_node(ni); 2066 continue; 2067 } 2068 sc->sc_tx_timer = 5; 2069 } 2070 } 2071 2072 static void 2073 rt2860_watchdog(void *arg) 2074 { 2075 struct rt2860_softc *sc = arg; 2076 2077 RAL_LOCK_ASSERT(sc); 2078 2079 KASSERT(sc->sc_flags & RT2860_RUNNING, ("not running")); 2080 2081 if (sc->sc_invalid) /* card ejected */ 2082 return; 2083 2084 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 2085 device_printf(sc->sc_dev, "device timeout\n"); 2086 rt2860_stop_locked(sc); 2087 rt2860_init_locked(sc); 2088 #if defined(__DragonFly__) 2089 /* not implemented */ 2090 #else 2091 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2092 #endif 2093 return; 2094 } 2095 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 2096 } 2097 2098 static void 2099 rt2860_parent(struct ieee80211com *ic) 2100 { 2101 struct rt2860_softc *sc = ic->ic_softc; 2102 int startall = 0; 2103 2104 RAL_LOCK(sc); 2105 if (ic->ic_nrunning> 0) { 2106 if (!(sc->sc_flags & RT2860_RUNNING)) { 2107 rt2860_init_locked(sc); 2108 startall = 1; 2109 } else 2110 rt2860_update_promisc(ic); 2111 } else if (sc->sc_flags & RT2860_RUNNING) 2112 rt2860_stop_locked(sc); 2113 RAL_UNLOCK(sc); 2114 if (startall) 2115 ieee80211_start_all(ic); 2116 } 2117 2118 /* 2119 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 2120 * We access the BBP through the 8051 microcontroller unit which means that 2121 * the microcode must be loaded first. 2122 */ 2123 void 2124 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2125 { 2126 int ntries; 2127 2128 for (ntries = 0; ntries < 100; ntries++) { 2129 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2130 break; 2131 DELAY(1); 2132 } 2133 if (ntries == 100) { 2134 device_printf(sc->sc_dev, 2135 "could not write to BBP through MCU\n"); 2136 return; 2137 } 2138 2139 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2140 RT2860_BBP_CSR_KICK | reg << 8 | val); 2141 RAL_BARRIER_WRITE(sc); 2142 2143 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2144 DELAY(1000); 2145 } 2146 2147 uint8_t 2148 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 2149 { 2150 uint32_t val; 2151 int ntries; 2152 2153 for (ntries = 0; ntries < 100; ntries++) { 2154 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2155 break; 2156 DELAY(1); 2157 } 2158 if (ntries == 100) { 2159 device_printf(sc->sc_dev, 2160 "could not read from BBP through MCU\n"); 2161 return 0; 2162 } 2163 2164 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2165 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 2166 RAL_BARRIER_WRITE(sc); 2167 2168 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2169 DELAY(1000); 2170 2171 for (ntries = 0; ntries < 100; ntries++) { 2172 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 2173 if (!(val & RT2860_BBP_CSR_KICK)) 2174 return val & 0xff; 2175 DELAY(1); 2176 } 2177 device_printf(sc->sc_dev, "could not read from BBP through MCU\n"); 2178 2179 return 0; 2180 } 2181 2182 /* 2183 * Write to one of the 4 programmable 24-bit RF registers. 2184 */ 2185 static void 2186 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 2187 { 2188 uint32_t tmp; 2189 int ntries; 2190 2191 for (ntries = 0; ntries < 100; ntries++) { 2192 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 2193 break; 2194 DELAY(1); 2195 } 2196 if (ntries == 100) { 2197 device_printf(sc->sc_dev, "could not write to RF\n"); 2198 return; 2199 } 2200 2201 /* RF registers are 24-bit on the RT2860 */ 2202 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 2203 (val & 0x3fffff) << 2 | (reg & 3); 2204 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 2205 } 2206 2207 static uint8_t 2208 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 2209 { 2210 uint32_t tmp; 2211 int ntries; 2212 2213 for (ntries = 0; ntries < 100; ntries++) { 2214 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2215 break; 2216 DELAY(1); 2217 } 2218 if (ntries == 100) { 2219 device_printf(sc->sc_dev, "could not read RF register\n"); 2220 return 0xff; 2221 } 2222 tmp = RT3070_RF_KICK | reg << 8; 2223 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2224 2225 for (ntries = 0; ntries < 100; ntries++) { 2226 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2227 if (!(tmp & RT3070_RF_KICK)) 2228 break; 2229 DELAY(1); 2230 } 2231 if (ntries == 100) { 2232 device_printf(sc->sc_dev, "could not read RF register\n"); 2233 return 0xff; 2234 } 2235 return tmp & 0xff; 2236 } 2237 2238 void 2239 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2240 { 2241 uint32_t tmp; 2242 int ntries; 2243 2244 for (ntries = 0; ntries < 10; ntries++) { 2245 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2246 break; 2247 DELAY(10); 2248 } 2249 if (ntries == 10) { 2250 device_printf(sc->sc_dev, "could not write to RF\n"); 2251 return; 2252 } 2253 2254 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2255 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2256 } 2257 2258 /* 2259 * Send a command to the 8051 microcontroller unit. 2260 */ 2261 int 2262 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2263 { 2264 int slot, ntries; 2265 uint32_t tmp; 2266 uint8_t cid; 2267 2268 for (ntries = 0; ntries < 100; ntries++) { 2269 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2270 break; 2271 DELAY(2); 2272 } 2273 if (ntries == 100) 2274 return EIO; 2275 2276 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2277 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2278 RAL_BARRIER_WRITE(sc); 2279 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2280 2281 if (!wait) 2282 return 0; 2283 /* wait for the command to complete */ 2284 for (ntries = 0; ntries < 200; ntries++) { 2285 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2286 /* find the command slot */ 2287 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2288 if ((tmp & 0xff) == cid) 2289 break; 2290 if (slot < 4) 2291 break; 2292 DELAY(100); 2293 } 2294 if (ntries == 200) { 2295 /* clear command and status */ 2296 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2297 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2298 return ETIMEDOUT; 2299 } 2300 /* get command status (1 means success) */ 2301 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2302 tmp = (tmp >> (slot * 8)) & 0xff; 2303 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2304 cmd, slot, tmp)); 2305 /* clear command and status */ 2306 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2307 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2308 return (tmp == 1) ? 0 : EIO; 2309 } 2310 2311 static void 2312 rt2860_enable_mrr(struct rt2860_softc *sc) 2313 { 2314 #define CCK(mcs) (mcs) 2315 #define OFDM(mcs) (1 << 3 | (mcs)) 2316 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2317 OFDM(6) << 28 | /* 54->48 */ 2318 OFDM(5) << 24 | /* 48->36 */ 2319 OFDM(4) << 20 | /* 36->24 */ 2320 OFDM(3) << 16 | /* 24->18 */ 2321 OFDM(2) << 12 | /* 18->12 */ 2322 OFDM(1) << 8 | /* 12-> 9 */ 2323 OFDM(0) << 4 | /* 9-> 6 */ 2324 OFDM(0)); /* 6-> 6 */ 2325 2326 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2327 CCK(2) << 12 | /* 11->5.5 */ 2328 CCK(1) << 8 | /* 5.5-> 2 */ 2329 CCK(0) << 4 | /* 2-> 1 */ 2330 CCK(0)); /* 1-> 1 */ 2331 #undef OFDM 2332 #undef CCK 2333 } 2334 2335 static void 2336 rt2860_set_txpreamble(struct rt2860_softc *sc) 2337 { 2338 struct ieee80211com *ic = &sc->sc_ic; 2339 uint32_t tmp; 2340 2341 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2342 tmp &= ~RT2860_CCK_SHORT_EN; 2343 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2344 tmp |= RT2860_CCK_SHORT_EN; 2345 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2346 } 2347 2348 void 2349 rt2860_set_basicrates(struct rt2860_softc *sc, 2350 const struct ieee80211_rateset *rs) 2351 { 2352 struct ieee80211com *ic = &sc->sc_ic; 2353 uint32_t mask = 0; 2354 uint8_t rate; 2355 int i; 2356 2357 for (i = 0; i < rs->rs_nrates; i++) { 2358 rate = rs->rs_rates[i]; 2359 2360 if (!(rate & IEEE80211_RATE_BASIC)) 2361 continue; 2362 2363 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt, 2364 IEEE80211_RV(rate)); 2365 } 2366 2367 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, mask); 2368 } 2369 2370 static void 2371 rt2860_scan_start(struct ieee80211com *ic) 2372 { 2373 struct rt2860_softc *sc = ic->ic_softc; 2374 uint32_t tmp; 2375 2376 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 2377 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 2378 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 2379 RT2860_TBTT_TIMER_EN)); 2380 rt2860_set_gp_timer(sc, 0); 2381 } 2382 2383 static void 2384 rt2860_scan_end(struct ieee80211com *ic) 2385 { 2386 struct rt2860_softc *sc = ic->ic_softc; 2387 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2388 2389 if (vap->iv_state == IEEE80211_S_RUN) { 2390 rt2860_enable_tsf_sync(sc); 2391 rt2860_set_gp_timer(sc, 500); 2392 } 2393 } 2394 2395 static void 2396 rt2860_set_channel(struct ieee80211com *ic) 2397 { 2398 struct rt2860_softc *sc = ic->ic_softc; 2399 2400 RAL_LOCK(sc); 2401 rt2860_switch_chan(sc, ic->ic_curchan); 2402 RAL_UNLOCK(sc); 2403 } 2404 2405 static void 2406 rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2407 { 2408 uint32_t tmp; 2409 uint8_t agc; 2410 2411 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2412 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2413 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2414 rt2860_mcu_bbp_write(sc, 86, 0x00); 2415 2416 if (group == 0) { 2417 if (sc->ext_2ghz_lna) { 2418 rt2860_mcu_bbp_write(sc, 82, 0x62); 2419 rt2860_mcu_bbp_write(sc, 75, 0x46); 2420 } else { 2421 rt2860_mcu_bbp_write(sc, 82, 0x84); 2422 rt2860_mcu_bbp_write(sc, 75, 0x50); 2423 } 2424 } else { 2425 if (sc->ext_5ghz_lna) { 2426 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2427 rt2860_mcu_bbp_write(sc, 75, 0x46); 2428 } else { 2429 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2430 rt2860_mcu_bbp_write(sc, 75, 0x50); 2431 } 2432 } 2433 2434 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2435 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2436 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2437 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2438 2439 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2440 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2441 if (sc->nrxchains > 1) 2442 tmp |= RT2860_LNA_PE1_EN; 2443 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2444 tmp |= RT3593_LNA_PE2_EN; 2445 if (group == 0) { /* 2GHz */ 2446 tmp |= RT2860_PA_PE_G0_EN; 2447 if (sc->ntxchains > 1) 2448 tmp |= RT2860_PA_PE_G1_EN; 2449 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2450 tmp |= RT3593_PA_PE_G2_EN; 2451 } else { /* 5GHz */ 2452 tmp |= RT2860_PA_PE_A0_EN; 2453 if (sc->ntxchains > 1) 2454 tmp |= RT2860_PA_PE_A1_EN; 2455 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2456 tmp |= RT3593_PA_PE_A2_EN; 2457 } 2458 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2459 2460 if (sc->mac_ver == 0x3593) { 2461 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2462 if (sc->sc_flags & RT2860_PCIE) { 2463 tmp &= ~0x01010000; 2464 if (group == 0) 2465 tmp |= 0x00010000; 2466 } else { 2467 tmp &= ~0x00008080; 2468 if (group == 0) 2469 tmp |= 0x00000080; 2470 } 2471 tmp = (tmp & ~0x00001000) | 0x00000010; 2472 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2473 } 2474 2475 /* set initial AGC value */ 2476 if (group == 0) { /* 2GHz band */ 2477 if (sc->mac_ver >= 0x3071) 2478 agc = 0x1c + sc->lna[0] * 2; 2479 else 2480 agc = 0x2e + sc->lna[0]; 2481 } else { /* 5GHz band */ 2482 agc = 0x32 + (sc->lna[group] * 5) / 3; 2483 } 2484 rt2860_mcu_bbp_write(sc, 66, agc); 2485 2486 DELAY(1000); 2487 } 2488 2489 static void 2490 rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2491 { 2492 const struct rfprog *rfprog = rt2860_rf2850; 2493 uint32_t r2, r3, r4; 2494 int8_t txpow1, txpow2; 2495 u_int i; 2496 2497 /* find the settings for this channel (we know it exists) */ 2498 for (i = 0; rfprog[i].chan != chan; i++); 2499 2500 r2 = rfprog[i].r2; 2501 if (sc->ntxchains == 1) 2502 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2503 if (sc->nrxchains == 1) 2504 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2505 else if (sc->nrxchains == 2) 2506 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2507 2508 /* use Tx power values from EEPROM */ 2509 txpow1 = sc->txpow1[i]; 2510 txpow2 = sc->txpow2[i]; 2511 if (chan > 14) { 2512 if (txpow1 >= 0) 2513 txpow1 = txpow1 << 1 | 1; 2514 else 2515 txpow1 = (7 + txpow1) << 1; 2516 if (txpow2 >= 0) 2517 txpow2 = txpow2 << 1 | 1; 2518 else 2519 txpow2 = (7 + txpow2) << 1; 2520 } 2521 r3 = rfprog[i].r3 | txpow1 << 7; 2522 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2523 2524 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2525 rt2860_rf_write(sc, RT2860_RF2, r2); 2526 rt2860_rf_write(sc, RT2860_RF3, r3); 2527 rt2860_rf_write(sc, RT2860_RF4, r4); 2528 2529 DELAY(200); 2530 2531 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2532 rt2860_rf_write(sc, RT2860_RF2, r2); 2533 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2534 rt2860_rf_write(sc, RT2860_RF4, r4); 2535 2536 DELAY(200); 2537 2538 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2539 rt2860_rf_write(sc, RT2860_RF2, r2); 2540 rt2860_rf_write(sc, RT2860_RF3, r3); 2541 rt2860_rf_write(sc, RT2860_RF4, r4); 2542 } 2543 2544 static void 2545 rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2546 { 2547 int8_t txpow1, txpow2; 2548 uint8_t rf; 2549 int i; 2550 2551 /* RT3090 is 2GHz only */ 2552 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2553 2554 /* find the settings for this channel (we know it exists) */ 2555 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2556 2557 /* use Tx power values from EEPROM */ 2558 txpow1 = sc->txpow1[i]; 2559 txpow2 = sc->txpow2[i]; 2560 2561 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2562 rf = rt3090_rf_read(sc, 3); 2563 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2564 rt3090_rf_write(sc, 3, rf); 2565 rf = rt3090_rf_read(sc, 6); 2566 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2567 rt3090_rf_write(sc, 6, rf); 2568 2569 /* set Tx0 power */ 2570 rf = rt3090_rf_read(sc, 12); 2571 rf = (rf & ~0x1f) | txpow1; 2572 rt3090_rf_write(sc, 12, rf); 2573 2574 /* set Tx1 power */ 2575 rf = rt3090_rf_read(sc, 13); 2576 rf = (rf & ~0x1f) | txpow2; 2577 rt3090_rf_write(sc, 13, rf); 2578 2579 rf = rt3090_rf_read(sc, 1); 2580 rf &= ~0xfc; 2581 if (sc->ntxchains == 1) 2582 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2583 else if (sc->ntxchains == 2) 2584 rf |= RT3070_TX2_PD; 2585 if (sc->nrxchains == 1) 2586 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2587 else if (sc->nrxchains == 2) 2588 rf |= RT3070_RX2_PD; 2589 rt3090_rf_write(sc, 1, rf); 2590 2591 /* set RF offset */ 2592 rf = rt3090_rf_read(sc, 23); 2593 rf = (rf & ~0x7f) | sc->freq; 2594 rt3090_rf_write(sc, 23, rf); 2595 2596 /* program RF filter */ 2597 rf = rt3090_rf_read(sc, 24); /* Tx */ 2598 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2599 rt3090_rf_write(sc, 24, rf); 2600 rf = rt3090_rf_read(sc, 31); /* Rx */ 2601 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2602 rt3090_rf_write(sc, 31, rf); 2603 2604 /* enable RF tuning */ 2605 rf = rt3090_rf_read(sc, 7); 2606 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2607 } 2608 2609 static void 2610 rt5390_set_chan(struct rt2860_softc *sc, u_int chan) 2611 { 2612 uint8_t h20mhz, rf, tmp; 2613 int8_t txpow1, txpow2; 2614 int i; 2615 2616 /* RT5390 is 2GHz only */ 2617 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2618 2619 /* find the settings for this channel (we know it exists) */ 2620 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2621 2622 /* use Tx power values from EEPROM */ 2623 txpow1 = sc->txpow1[i]; 2624 txpow2 = sc->txpow2[i]; 2625 2626 rt3090_rf_write(sc, 8, rt3090_freqs[i].n); 2627 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f); 2628 rf = rt3090_rf_read(sc, 11); 2629 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03); 2630 rt3090_rf_write(sc, 11, rf); 2631 2632 rf = rt3090_rf_read(sc, 49); 2633 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 2634 /* the valid range of the RF R49 is 0x00~0x27 */ 2635 if ((rf & 0x3f) > 0x27) 2636 rf = (rf & ~0x3f) | 0x27; 2637 rt3090_rf_write(sc, 49, rf); 2638 if (sc->mac_ver == 0x5392) { 2639 rf = rt3090_rf_read(sc, 50); 2640 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 2641 /* the valid range of the RF R50 is 0x00~0x27 */ 2642 if ((rf & 0x3f) > 0x27) 2643 rf = (rf & ~0x3f) | 0x27; 2644 rt3090_rf_write(sc, 50, rf); 2645 } 2646 2647 rf = rt3090_rf_read(sc, 1); 2648 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 2649 if (sc->mac_ver == 0x5392) 2650 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2651 rt3090_rf_write(sc, 1, rf); 2652 2653 rf = rt3090_rf_read(sc, 2); 2654 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2655 DELAY(1000); 2656 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2657 2658 rf = rt3090_rf_read(sc, 17); 2659 tmp = rf; 2660 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 2661 rf = MIN(rf, 0x5f); 2662 if (tmp != rf) 2663 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0); 2664 2665 if (sc->mac_ver == 0x5390) { 2666 if (chan <= 4) 2667 rf = 0x73; 2668 else if (chan >= 5 && chan <= 6) 2669 rf = 0x63; 2670 else if (chan >= 7 && chan <= 10) 2671 rf = 0x53; 2672 else 2673 rf = 43; 2674 rt3090_rf_write(sc, 55, rf); 2675 2676 if (chan == 1) 2677 rf = 0x0c; 2678 else if (chan == 2) 2679 rf = 0x0b; 2680 else if (chan == 3) 2681 rf = 0x0a; 2682 else if (chan >= 4 && chan <= 6) 2683 rf = 0x09; 2684 else if (chan >= 7 && chan <= 12) 2685 rf = 0x08; 2686 else if (chan == 13) 2687 rf = 0x07; 2688 else 2689 rf = 0x06; 2690 rt3090_rf_write(sc, 59, rf); 2691 } 2692 2693 /* Tx/Rx h20M */ 2694 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 2695 rf = rt3090_rf_read(sc, 30); 2696 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 2697 rt3090_rf_write(sc, 30, rf); 2698 2699 /* Rx BB filter VCM */ 2700 rf = rt3090_rf_read(sc, 30); 2701 rf = (rf & ~0x18) | 0x10; 2702 rt3090_rf_write(sc, 30, rf); 2703 2704 /* Initiate VCO calibration. */ 2705 rf = rt3090_rf_read(sc, 3); 2706 rf |= RT3593_VCOCAL; 2707 rt3090_rf_write(sc, 3, rf); 2708 } 2709 2710 static int 2711 rt3090_rf_init(struct rt2860_softc *sc) 2712 { 2713 uint32_t tmp; 2714 uint8_t rf, bbp; 2715 int i; 2716 2717 rf = rt3090_rf_read(sc, 30); 2718 /* toggle RF R30 bit 7 */ 2719 rt3090_rf_write(sc, 30, rf | 0x80); 2720 DELAY(1000); 2721 rt3090_rf_write(sc, 30, rf & ~0x80); 2722 2723 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2724 tmp &= ~0x1f000000; 2725 if (sc->patch_dac && sc->mac_rev < 0x0211) 2726 tmp |= 0x0d000000; /* 1.35V */ 2727 else 2728 tmp |= 0x01000000; /* 1.2V */ 2729 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2730 2731 /* patch LNA_PE_G1 */ 2732 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2733 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2734 2735 /* initialize RF registers to default value */ 2736 for (i = 0; i < nitems(rt3090_def_rf); i++) { 2737 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2738 rt3090_def_rf[i].val); 2739 } 2740 2741 /* select 20MHz bandwidth */ 2742 rt3090_rf_write(sc, 31, 0x14); 2743 2744 rf = rt3090_rf_read(sc, 6); 2745 rt3090_rf_write(sc, 6, rf | 0x40); 2746 2747 if (sc->mac_ver != 0x3593) { 2748 /* calibrate filter for 20MHz bandwidth */ 2749 sc->rf24_20mhz = 0x1f; /* default value */ 2750 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2751 2752 /* select 40MHz bandwidth */ 2753 bbp = rt2860_mcu_bbp_read(sc, 4); 2754 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2755 rf = rt3090_rf_read(sc, 31); 2756 rt3090_rf_write(sc, 31, rf | 0x20); 2757 2758 /* calibrate filter for 40MHz bandwidth */ 2759 sc->rf24_40mhz = 0x2f; /* default value */ 2760 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2761 2762 /* go back to 20MHz bandwidth */ 2763 bbp = rt2860_mcu_bbp_read(sc, 4); 2764 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2765 } 2766 if (sc->mac_rev < 0x0211) 2767 rt3090_rf_write(sc, 27, 0x03); 2768 2769 tmp = RAL_READ(sc, RT3070_OPT_14); 2770 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2771 2772 if (sc->rf_rev == RT3070_RF_3020) 2773 rt3090_set_rx_antenna(sc, 0); 2774 2775 bbp = rt2860_mcu_bbp_read(sc, 138); 2776 if (sc->mac_ver == 0x3593) { 2777 if (sc->ntxchains == 1) 2778 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2779 else if (sc->ntxchains == 2) 2780 bbp |= 0x40; /* turn off DAC2 */ 2781 if (sc->nrxchains == 1) 2782 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2783 else if (sc->nrxchains == 2) 2784 bbp &= ~0x04; /* turn off ADC2 */ 2785 } else { 2786 if (sc->ntxchains == 1) 2787 bbp |= 0x20; /* turn off DAC1 */ 2788 if (sc->nrxchains == 1) 2789 bbp &= ~0x02; /* turn off ADC1 */ 2790 } 2791 rt2860_mcu_bbp_write(sc, 138, bbp); 2792 2793 rf = rt3090_rf_read(sc, 1); 2794 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2795 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2796 rt3090_rf_write(sc, 1, rf); 2797 2798 rf = rt3090_rf_read(sc, 15); 2799 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2800 2801 rf = rt3090_rf_read(sc, 17); 2802 rf &= ~RT3070_TX_LO1; 2803 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2804 rf |= 0x20; /* fix for long range Rx issue */ 2805 if (sc->txmixgain_2ghz >= 2) 2806 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2807 rt3090_rf_write(sc, 17, rf); 2808 2809 rf = rt3090_rf_read(sc, 20); 2810 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2811 2812 rf = rt3090_rf_read(sc, 21); 2813 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2814 2815 return (0); 2816 } 2817 2818 static void 2819 rt5390_rf_init(struct rt2860_softc *sc) 2820 { 2821 uint8_t rf, bbp; 2822 int i; 2823 2824 rf = rt3090_rf_read(sc, 2); 2825 /* Toggle RF R2 bit 7. */ 2826 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2827 DELAY(1000); 2828 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2829 2830 /* Initialize RF registers to default value. */ 2831 if (sc->mac_ver == 0x5392) { 2832 for (i = 0; i < nitems(rt5392_def_rf); i++) { 2833 rt3090_rf_write(sc, rt5392_def_rf[i].reg, 2834 rt5392_def_rf[i].val); 2835 } 2836 } else { 2837 for (i = 0; i < nitems(rt5390_def_rf); i++) { 2838 rt3090_rf_write(sc, rt5390_def_rf[i].reg, 2839 rt5390_def_rf[i].val); 2840 } 2841 } 2842 2843 sc->rf24_20mhz = 0x1f; 2844 sc->rf24_40mhz = 0x2f; 2845 2846 if (sc->mac_rev < 0x0211) 2847 rt3090_rf_write(sc, 27, 0x03); 2848 2849 /* Set led open drain enable. */ 2850 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1); 2851 2852 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2853 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2854 2855 if (sc->mac_ver == 0x5390) 2856 rt3090_set_rx_antenna(sc, 0); 2857 2858 /* Patch RSSI inaccurate issue. */ 2859 rt2860_mcu_bbp_write(sc, 79, 0x13); 2860 rt2860_mcu_bbp_write(sc, 80, 0x05); 2861 rt2860_mcu_bbp_write(sc, 81, 0x33); 2862 2863 /* Enable DC filter. */ 2864 if (sc->mac_rev >= 0x0211) 2865 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2866 2867 bbp = rt2860_mcu_bbp_read(sc, 138); 2868 if (sc->ntxchains == 1) 2869 bbp |= 0x20; /* Turn off DAC1. */ 2870 if (sc->nrxchains == 1) 2871 bbp &= ~0x02; /* Turn off ADC1. */ 2872 rt2860_mcu_bbp_write(sc, 138, bbp); 2873 2874 /* Enable RX LO1 and LO2. */ 2875 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1); 2876 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2); 2877 2878 /* Avoid data lost and CRC error. */ 2879 rt2860_mcu_bbp_write(sc, 4, 2880 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL); 2881 2882 rf = rt3090_rf_read(sc, 30); 2883 rf = (rf & ~0x18) | 0x10; 2884 rt3090_rf_write(sc, 30, rf); 2885 } 2886 2887 static void 2888 rt3090_rf_wakeup(struct rt2860_softc *sc) 2889 { 2890 uint32_t tmp; 2891 uint8_t rf; 2892 2893 if (sc->mac_ver == 0x3593) { 2894 /* enable VCO */ 2895 rf = rt3090_rf_read(sc, 1); 2896 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2897 2898 /* initiate VCO calibration */ 2899 rf = rt3090_rf_read(sc, 3); 2900 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2901 2902 /* enable VCO bias current control */ 2903 rf = rt3090_rf_read(sc, 6); 2904 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2905 2906 /* initiate res calibration */ 2907 rf = rt3090_rf_read(sc, 2); 2908 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2909 2910 /* set reference current control to 0.33 mA */ 2911 rf = rt3090_rf_read(sc, 22); 2912 rf &= ~RT3593_CP_IC_MASK; 2913 rf |= 1 << RT3593_CP_IC_SHIFT; 2914 rt3090_rf_write(sc, 22, rf); 2915 2916 /* enable RX CTB */ 2917 rf = rt3090_rf_read(sc, 46); 2918 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2919 2920 rf = rt3090_rf_read(sc, 20); 2921 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2922 rt3090_rf_write(sc, 20, rf); 2923 } else { 2924 /* enable RF block */ 2925 rf = rt3090_rf_read(sc, 1); 2926 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2927 2928 /* enable VCO bias current control */ 2929 rf = rt3090_rf_read(sc, 7); 2930 rt3090_rf_write(sc, 7, rf | 0x30); 2931 2932 rf = rt3090_rf_read(sc, 9); 2933 rt3090_rf_write(sc, 9, rf | 0x0e); 2934 2935 /* enable RX CTB */ 2936 rf = rt3090_rf_read(sc, 21); 2937 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2938 2939 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2940 rf = rt3090_rf_read(sc, 27); 2941 rf &= ~0x77; 2942 if (sc->mac_rev < 0x0211) 2943 rf |= 0x03; 2944 rt3090_rf_write(sc, 27, rf); 2945 } 2946 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2947 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2948 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2949 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2950 } 2951 } 2952 2953 static void 2954 rt5390_rf_wakeup(struct rt2860_softc *sc) 2955 { 2956 uint32_t tmp; 2957 uint8_t rf; 2958 2959 rf = rt3090_rf_read(sc, 1); 2960 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | 2961 RT3070_TX0_PD; 2962 if (sc->mac_ver == 0x5392) 2963 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2964 rt3090_rf_write(sc, 1, rf); 2965 2966 rf = rt3090_rf_read(sc, 6); 2967 rf |= RT3593_VCO_IC | RT3593_VCOCAL; 2968 if (sc->mac_ver == 0x5390) 2969 rf &= ~RT3593_VCO_IC; 2970 rt3090_rf_write(sc, 6, rf); 2971 2972 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL); 2973 2974 rf = rt3090_rf_read(sc, 22); 2975 rf = (rf & ~0xe0) | 0x20; 2976 rt3090_rf_write(sc, 22, rf); 2977 2978 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB); 2979 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77); 2980 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL); 2981 2982 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2983 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2984 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2985 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2986 } 2987 } 2988 2989 static int 2990 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2991 uint8_t *val) 2992 { 2993 uint8_t rf22, rf24; 2994 uint8_t bbp55_pb, bbp55_sb, delta; 2995 int ntries; 2996 2997 /* program filter */ 2998 rf24 = rt3090_rf_read(sc, 24); 2999 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 3000 rt3090_rf_write(sc, 24, rf24); 3001 3002 /* enable baseband loopback mode */ 3003 rf22 = rt3090_rf_read(sc, 22); 3004 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 3005 3006 /* set power and frequency of passband test tone */ 3007 rt2860_mcu_bbp_write(sc, 24, 0x00); 3008 for (ntries = 0; ntries < 100; ntries++) { 3009 /* transmit test tone */ 3010 rt2860_mcu_bbp_write(sc, 25, 0x90); 3011 DELAY(1000); 3012 /* read received power */ 3013 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 3014 if (bbp55_pb != 0) 3015 break; 3016 } 3017 if (ntries == 100) 3018 return (ETIMEDOUT); 3019 3020 /* set power and frequency of stopband test tone */ 3021 rt2860_mcu_bbp_write(sc, 24, 0x06); 3022 for (ntries = 0; ntries < 100; ntries++) { 3023 /* transmit test tone */ 3024 rt2860_mcu_bbp_write(sc, 25, 0x90); 3025 DELAY(1000); 3026 /* read received power */ 3027 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 3028 3029 delta = bbp55_pb - bbp55_sb; 3030 if (delta > target) 3031 break; 3032 3033 /* reprogram filter */ 3034 rf24++; 3035 rt3090_rf_write(sc, 24, rf24); 3036 } 3037 if (ntries < 100) { 3038 if (rf24 != init) 3039 rf24--; /* backtrack */ 3040 *val = rf24; 3041 rt3090_rf_write(sc, 24, rf24); 3042 } 3043 3044 /* restore initial state */ 3045 rt2860_mcu_bbp_write(sc, 24, 0x00); 3046 3047 /* disable baseband loopback mode */ 3048 rf22 = rt3090_rf_read(sc, 22); 3049 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 3050 3051 return (0); 3052 } 3053 3054 static void 3055 rt3090_rf_setup(struct rt2860_softc *sc) 3056 { 3057 uint8_t bbp; 3058 int i; 3059 3060 if (sc->mac_rev >= 0x0211) { 3061 /* enable DC filter */ 3062 rt2860_mcu_bbp_write(sc, 103, 0xc0); 3063 3064 /* improve power consumption */ 3065 bbp = rt2860_mcu_bbp_read(sc, 31); 3066 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 3067 } 3068 3069 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 3070 if (sc->mac_rev < 0x0211) { 3071 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 3072 sc->patch_dac ? 0x2c : 0x0f); 3073 } else 3074 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 3075 3076 /* initialize RF registers from ROM */ 3077 if (sc->mac_ver < 0x5390) { 3078 for (i = 0; i < 10; i++) { 3079 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 3080 continue; 3081 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 3082 } 3083 } 3084 } 3085 3086 static void 3087 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 3088 { 3089 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3090 which | (sc->leds & 0x7f), 0); 3091 } 3092 3093 /* 3094 * Hardware has a general-purpose programmable timer interrupt that can 3095 * periodically raise MAC_INT_4. 3096 */ 3097 static void 3098 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 3099 { 3100 uint32_t tmp; 3101 3102 /* disable GP timer before reprogramming it */ 3103 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3104 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 3105 3106 if (ms == 0) 3107 return; 3108 3109 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 3110 ms *= 16; /* Unit: 64us */ 3111 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 3112 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 3113 3114 /* enable GP timer */ 3115 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3116 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 3117 } 3118 3119 static void 3120 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 3121 { 3122 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 3123 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3124 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 3125 bssid[4] | bssid[5] << 8); 3126 } 3127 3128 static void 3129 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 3130 { 3131 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 3132 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3133 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 3134 addr[4] | addr[5] << 8 | 0xff << 16); 3135 } 3136 3137 static void 3138 rt2860_updateslot(struct ieee80211com *ic) 3139 { 3140 struct rt2860_softc *sc = ic->ic_softc; 3141 uint32_t tmp; 3142 3143 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 3144 tmp &= ~0xff; 3145 tmp |= IEEE80211_GET_SLOTTIME(ic); 3146 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3147 } 3148 3149 static void 3150 rt2860_updateprot(struct rt2860_softc *sc) 3151 { 3152 struct ieee80211com *ic = &sc->sc_ic; 3153 uint32_t tmp; 3154 3155 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3156 /* setup protection frame rate (MCS code) */ 3157 tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 3158 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 3159 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3160 3161 /* CCK frames don't require protection */ 3162 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 3163 3164 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3165 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3166 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3167 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3168 tmp |= RT2860_PROT_CTRL_CTS; 3169 } 3170 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 3171 } 3172 3173 static void 3174 rt2860_update_promisc(struct ieee80211com *ic) 3175 { 3176 struct rt2860_softc *sc = ic->ic_softc; 3177 uint32_t tmp; 3178 3179 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG); 3180 tmp &= ~RT2860_DROP_NOT_MYBSS; 3181 if (ic->ic_promisc == 0) 3182 tmp |= RT2860_DROP_NOT_MYBSS; 3183 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3184 } 3185 3186 static int 3187 rt2860_updateedca(struct ieee80211com *ic) 3188 { 3189 struct rt2860_softc *sc = ic->ic_softc; 3190 const struct wmeParams *wmep; 3191 int aci; 3192 3193 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 3194 3195 /* update MAC TX configuration registers */ 3196 for (aci = 0; aci < WME_NUM_AC; aci++) { 3197 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 3198 wmep[aci].wmep_logcwmax << 16 | 3199 wmep[aci].wmep_logcwmin << 12 | 3200 wmep[aci].wmep_aifsn << 8 | 3201 wmep[aci].wmep_txopLimit); 3202 } 3203 3204 /* update SCH/DMA registers too */ 3205 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 3206 wmep[WME_AC_VO].wmep_aifsn << 12 | 3207 wmep[WME_AC_VI].wmep_aifsn << 8 | 3208 wmep[WME_AC_BK].wmep_aifsn << 4 | 3209 wmep[WME_AC_BE].wmep_aifsn); 3210 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 3211 wmep[WME_AC_VO].wmep_logcwmin << 12 | 3212 wmep[WME_AC_VI].wmep_logcwmin << 8 | 3213 wmep[WME_AC_BK].wmep_logcwmin << 4 | 3214 wmep[WME_AC_BE].wmep_logcwmin); 3215 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 3216 wmep[WME_AC_VO].wmep_logcwmax << 12 | 3217 wmep[WME_AC_VI].wmep_logcwmax << 8 | 3218 wmep[WME_AC_BK].wmep_logcwmax << 4 | 3219 wmep[WME_AC_BE].wmep_logcwmax); 3220 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 3221 wmep[WME_AC_BK].wmep_txopLimit << 16 | 3222 wmep[WME_AC_BE].wmep_txopLimit); 3223 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 3224 wmep[WME_AC_VO].wmep_txopLimit << 16 | 3225 wmep[WME_AC_VI].wmep_txopLimit); 3226 3227 return 0; 3228 } 3229 3230 #ifdef HW_CRYPTO 3231 static int 3232 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3233 struct ieee80211_key *k) 3234 { 3235 struct rt2860_softc *sc = ic->ic_softc; 3236 bus_size_t base; 3237 uint32_t attr; 3238 uint8_t mode, wcid, iv[8]; 3239 3240 /* defer setting of WEP keys until interface is brought up */ 3241 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 3242 (IFF_UP | IFF_RUNNING)) 3243 return 0; 3244 3245 /* map net80211 cipher to RT2860 security mode */ 3246 switch (k->k_cipher) { 3247 case IEEE80211_CIPHER_WEP40: 3248 mode = RT2860_MODE_WEP40; 3249 break; 3250 case IEEE80211_CIPHER_WEP104: 3251 mode = RT2860_MODE_WEP104; 3252 break; 3253 case IEEE80211_CIPHER_TKIP: 3254 mode = RT2860_MODE_TKIP; 3255 break; 3256 case IEEE80211_CIPHER_CCMP: 3257 mode = RT2860_MODE_AES_CCMP; 3258 break; 3259 default: 3260 return EINVAL; 3261 } 3262 3263 if (k->k_flags & IEEE80211_KEY_GROUP) { 3264 wcid = 0; /* NB: update WCID0 for group keys */ 3265 base = RT2860_SKEY(0, k->k_id); 3266 } else { 3267 wcid = ((struct rt2860_node *)ni)->wcid; 3268 base = RT2860_PKEY(wcid); 3269 } 3270 3271 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3272 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 3273 #ifndef IEEE80211_STA_ONLY 3274 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3275 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 3276 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 3277 } else 3278 #endif 3279 { 3280 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 3281 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 3282 } 3283 } else 3284 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 3285 3286 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 3287 (k->k_flags & IEEE80211_KEY_TX)) { 3288 /* set initial packet number in IV+EIV */ 3289 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 3290 k->k_cipher == IEEE80211_CIPHER_WEP104) { 3291 uint32_t val = arc4random(); 3292 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 3293 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 3294 val += 0x000100; 3295 iv[0] = val; 3296 iv[1] = val >> 8; 3297 iv[2] = val >> 16; 3298 iv[3] = k->k_id << 6; 3299 iv[4] = iv[5] = iv[6] = iv[7] = 0; 3300 } else { 3301 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3302 iv[0] = k->k_tsc >> 8; 3303 iv[1] = (iv[0] | 0x20) & 0x7f; 3304 iv[2] = k->k_tsc; 3305 } else /* CCMP */ { 3306 iv[0] = k->k_tsc; 3307 iv[1] = k->k_tsc >> 8; 3308 iv[2] = 0; 3309 } 3310 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3311 iv[4] = k->k_tsc >> 16; 3312 iv[5] = k->k_tsc >> 24; 3313 iv[6] = k->k_tsc >> 32; 3314 iv[7] = k->k_tsc >> 40; 3315 } 3316 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3317 } 3318 3319 if (k->k_flags & IEEE80211_KEY_GROUP) { 3320 /* install group key */ 3321 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3322 attr &= ~(0xf << (k->k_id * 4)); 3323 attr |= mode << (k->k_id * 4); 3324 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3325 } else { 3326 /* install pairwise key */ 3327 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3328 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3329 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3330 } 3331 return 0; 3332 } 3333 3334 static void 3335 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3336 struct ieee80211_key *k) 3337 { 3338 struct rt2860_softc *sc = ic->ic_softc; 3339 uint32_t attr; 3340 uint8_t wcid; 3341 3342 if (k->k_flags & IEEE80211_KEY_GROUP) { 3343 /* remove group key */ 3344 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3345 attr &= ~(0xf << (k->k_id * 4)); 3346 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3347 3348 } else { 3349 /* remove pairwise key */ 3350 wcid = ((struct rt2860_node *)ni)->wcid; 3351 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3352 attr &= ~0xf; 3353 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3354 } 3355 } 3356 #endif 3357 3358 static int8_t 3359 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3360 { 3361 struct ieee80211com *ic = &sc->sc_ic; 3362 struct ieee80211_channel *c = ic->ic_curchan; 3363 int delta; 3364 3365 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3366 u_int chan = ieee80211_chan2ieee(ic, c); 3367 delta = sc->rssi_5ghz[rxchain]; 3368 3369 /* determine channel group */ 3370 if (chan <= 64) 3371 delta -= sc->lna[1]; 3372 else if (chan <= 128) 3373 delta -= sc->lna[2]; 3374 else 3375 delta -= sc->lna[3]; 3376 } else 3377 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3378 3379 return -12 - delta - rssi; 3380 } 3381 3382 /* 3383 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3384 * Used to adjust per-rate Tx power registers. 3385 */ 3386 static __inline uint32_t 3387 b4inc(uint32_t b32, int8_t delta) 3388 { 3389 int8_t i, b4; 3390 3391 for (i = 0; i < 8; i++) { 3392 b4 = b32 & 0xf; 3393 b4 += delta; 3394 if (b4 < 0) 3395 b4 = 0; 3396 else if (b4 > 0xf) 3397 b4 = 0xf; 3398 b32 = b32 >> 4 | b4 << 28; 3399 } 3400 return b32; 3401 } 3402 3403 static const char * 3404 rt2860_get_rf(uint16_t rev) 3405 { 3406 switch (rev) { 3407 case RT2860_RF_2820: return "RT2820"; 3408 case RT2860_RF_2850: return "RT2850"; 3409 case RT2860_RF_2720: return "RT2720"; 3410 case RT2860_RF_2750: return "RT2750"; 3411 case RT3070_RF_3020: return "RT3020"; 3412 case RT3070_RF_2020: return "RT2020"; 3413 case RT3070_RF_3021: return "RT3021"; 3414 case RT3070_RF_3022: return "RT3022"; 3415 case RT3070_RF_3052: return "RT3052"; 3416 case RT3070_RF_3320: return "RT3320"; 3417 case RT3070_RF_3053: return "RT3053"; 3418 case RT5390_RF_5360: return "RT5360"; 3419 case RT5390_RF_5390: return "RT5390"; 3420 default: return "unknown"; 3421 } 3422 } 3423 3424 static int 3425 rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 3426 { 3427 int8_t delta_2ghz, delta_5ghz; 3428 uint32_t tmp; 3429 uint16_t val; 3430 int ridx, ant, i; 3431 3432 /* check whether the ROM is eFUSE ROM or EEPROM */ 3433 sc->sc_srom_read = rt2860_eeprom_read_2; 3434 if (sc->mac_ver >= 0x3071) { 3435 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3436 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3437 if (tmp & RT3070_SEL_EFUSE) 3438 sc->sc_srom_read = rt3090_efuse_read_2; 3439 } 3440 3441 #ifdef RAL_DEBUG 3442 /* read EEPROM version */ 3443 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3444 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val >> 8, val & 0xff)); 3445 #endif 3446 3447 /* read MAC address */ 3448 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3449 macaddr[0] = val & 0xff; 3450 macaddr[1] = val >> 8; 3451 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3452 macaddr[2] = val & 0xff; 3453 macaddr[3] = val >> 8; 3454 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3455 macaddr[4] = val & 0xff; 3456 macaddr[5] = val >> 8; 3457 3458 #ifdef RAL_DEBUG 3459 /* read country code */ 3460 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3461 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3462 #endif 3463 3464 /* read vendor BBP settings */ 3465 for (i = 0; i < 8; i++) { 3466 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3467 sc->bbp[i].val = val & 0xff; 3468 sc->bbp[i].reg = val >> 8; 3469 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3470 } 3471 if (sc->mac_ver >= 0x3071) { 3472 /* read vendor RF settings */ 3473 for (i = 0; i < 10; i++) { 3474 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3475 sc->rf[i].val = val & 0xff; 3476 sc->rf[i].reg = val >> 8; 3477 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3478 sc->rf[i].val)); 3479 } 3480 } 3481 3482 /* read RF frequency offset from EEPROM */ 3483 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3484 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3485 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3486 if ((val >> 8) != 0xff) { 3487 /* read LEDs operating mode */ 3488 sc->leds = val >> 8; 3489 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3490 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3491 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3492 } else { 3493 /* broken EEPROM, use default settings */ 3494 sc->leds = 0x01; 3495 sc->led[0] = 0x5555; 3496 sc->led[1] = 0x2221; 3497 sc->led[2] = 0xa9f8; 3498 } 3499 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3500 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3501 3502 /* read RF information */ 3503 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3504 if (sc->mac_ver >= 0x5390) 3505 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID); 3506 else 3507 sc->rf_rev = (val >> 8) & 0xf; 3508 sc->ntxchains = (val >> 4) & 0xf; 3509 sc->nrxchains = val & 0xf; 3510 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3511 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3512 3513 /* check if RF supports automatic Tx access gain control */ 3514 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3515 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3516 /* check if driver should patch the DAC issue */ 3517 if ((val >> 8) != 0xff) 3518 sc->patch_dac = (val >> 15) & 1; 3519 if ((val & 0xff) != 0xff) { 3520 sc->ext_5ghz_lna = (val >> 3) & 1; 3521 sc->ext_2ghz_lna = (val >> 2) & 1; 3522 /* check if RF supports automatic Tx access gain control */ 3523 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */ 3524 /* check if we have a hardware radio switch */ 3525 sc->rfswitch = val & 1; 3526 } 3527 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3528 /* read PCIe power save level */ 3529 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3530 if ((val & 0xff) != 0xff) { 3531 sc->pslevel = val & 0x3; 3532 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3533 if ((val & 0xff80) != 0x9280) 3534 sc->pslevel = MIN(sc->pslevel, 1); 3535 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3536 } 3537 } 3538 3539 /* read power settings for 2GHz channels */ 3540 for (i = 0; i < 14; i += 2) { 3541 val = rt2860_srom_read(sc, 3542 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3543 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3544 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3545 3546 if (sc->mac_ver != 0x5390) { 3547 val = rt2860_srom_read(sc, 3548 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3549 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3550 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3551 } 3552 } 3553 /* fix broken Tx power entries */ 3554 for (i = 0; i < 14; i++) { 3555 if (sc->txpow1[i] < 0 || 3556 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31)) 3557 sc->txpow1[i] = 5; 3558 if (sc->mac_ver != 0x5390) { 3559 if (sc->txpow2[i] < 0 || 3560 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31)) 3561 sc->txpow2[i] = 5; 3562 } 3563 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3564 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3565 } 3566 /* read power settings for 5GHz channels */ 3567 for (i = 0; i < 40; i += 2) { 3568 val = rt2860_srom_read(sc, 3569 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3570 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3571 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3572 3573 val = rt2860_srom_read(sc, 3574 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3575 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3576 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3577 } 3578 /* fix broken Tx power entries */ 3579 for (i = 0; i < 40; i++) { 3580 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3581 sc->txpow1[14 + i] = 5; 3582 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3583 sc->txpow2[14 + i] = 5; 3584 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3585 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3586 sc->txpow2[14 + i])); 3587 } 3588 3589 /* read Tx power compensation for each Tx rate */ 3590 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3591 delta_2ghz = delta_5ghz = 0; 3592 if ((val & 0xff) != 0xff && (val & 0x80)) { 3593 delta_2ghz = val & 0xf; 3594 if (!(val & 0x40)) /* negative number */ 3595 delta_2ghz = -delta_2ghz; 3596 } 3597 val >>= 8; 3598 if ((val & 0xff) != 0xff && (val & 0x80)) { 3599 delta_5ghz = val & 0xf; 3600 if (!(val & 0x40)) /* negative number */ 3601 delta_5ghz = -delta_5ghz; 3602 } 3603 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3604 delta_2ghz, delta_5ghz)); 3605 3606 for (ridx = 0; ridx < 5; ridx++) { 3607 uint32_t reg; 3608 3609 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3610 reg = val; 3611 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3612 reg |= (uint32_t)val << 16; 3613 3614 sc->txpow20mhz[ridx] = reg; 3615 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3616 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3617 3618 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3619 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3620 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3621 } 3622 3623 /* read factory-calibrated samples for temperature compensation */ 3624 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3625 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3626 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3627 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3628 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3629 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3630 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3631 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3632 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3633 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3634 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3635 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3636 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3637 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3638 sc->step_2ghz = val >> 8; 3639 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3640 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3641 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3642 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3643 sc->tssi_2ghz[8], sc->step_2ghz)); 3644 /* check that ref value is correct, otherwise disable calibration */ 3645 if (sc->tssi_2ghz[4] == 0xff) 3646 sc->calib_2ghz = 0; 3647 3648 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3649 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3650 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3651 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3652 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3653 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3654 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3655 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3656 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3657 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3658 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3659 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3660 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3661 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3662 sc->step_5ghz = val >> 8; 3663 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3664 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3665 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3666 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3667 sc->tssi_5ghz[8], sc->step_5ghz)); 3668 /* check that ref value is correct, otherwise disable calibration */ 3669 if (sc->tssi_5ghz[4] == 0xff) 3670 sc->calib_5ghz = 0; 3671 3672 /* read RSSI offsets and LNA gains from EEPROM */ 3673 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3674 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3675 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3676 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3677 if (sc->mac_ver >= 0x3071) { 3678 /* 3679 * On RT3090 chips (limited to 2 Rx chains), this ROM 3680 * field contains the Tx mixer gain for the 2GHz band. 3681 */ 3682 if ((val & 0xff) != 0xff) 3683 sc->txmixgain_2ghz = val & 0x7; 3684 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3685 } else 3686 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3687 sc->lna[2] = val >> 8; /* channel group 2 */ 3688 3689 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3690 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3691 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3692 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3693 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3694 sc->lna[3] = val >> 8; /* channel group 3 */ 3695 3696 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3697 if (sc->mac_ver >= 0x3071) 3698 sc->lna[0] = RT3090_DEF_LNA; 3699 else /* channel group 0 */ 3700 sc->lna[0] = val & 0xff; 3701 sc->lna[1] = val >> 8; /* channel group 1 */ 3702 3703 /* fix broken 5GHz LNA entries */ 3704 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3705 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3706 sc->lna[2] = sc->lna[1]; 3707 } 3708 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3709 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3710 sc->lna[3] = sc->lna[1]; 3711 } 3712 3713 /* fix broken RSSI offset entries */ 3714 for (ant = 0; ant < 3; ant++) { 3715 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3716 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3717 ant + 1, sc->rssi_2ghz[ant])); 3718 sc->rssi_2ghz[ant] = 0; 3719 } 3720 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3721 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3722 ant + 1, sc->rssi_5ghz[ant])); 3723 sc->rssi_5ghz[ant] = 0; 3724 } 3725 } 3726 3727 return 0; 3728 } 3729 3730 static int 3731 rt2860_bbp_init(struct rt2860_softc *sc) 3732 { 3733 int i, ntries; 3734 3735 /* wait for BBP to wake up */ 3736 for (ntries = 0; ntries < 20; ntries++) { 3737 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3738 if (bbp0 != 0 && bbp0 != 0xff) 3739 break; 3740 } 3741 if (ntries == 20) { 3742 device_printf(sc->sc_dev, 3743 "timeout waiting for BBP to wake up\n"); 3744 return (ETIMEDOUT); 3745 } 3746 3747 /* initialize BBP registers to default values */ 3748 if (sc->mac_ver >= 0x5390) 3749 rt5390_bbp_init(sc); 3750 else { 3751 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3752 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3753 rt2860_def_bbp[i].val); 3754 } 3755 } 3756 3757 /* fix BBP84 for RT2860E */ 3758 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3759 rt2860_mcu_bbp_write(sc, 84, 0x19); 3760 3761 if (sc->mac_ver >= 0x3071) { 3762 rt2860_mcu_bbp_write(sc, 79, 0x13); 3763 rt2860_mcu_bbp_write(sc, 80, 0x05); 3764 rt2860_mcu_bbp_write(sc, 81, 0x33); 3765 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3766 rt2860_mcu_bbp_write(sc, 69, 0x16); 3767 rt2860_mcu_bbp_write(sc, 73, 0x12); 3768 } 3769 3770 return 0; 3771 } 3772 3773 static void 3774 rt5390_bbp_init(struct rt2860_softc *sc) 3775 { 3776 uint8_t bbp; 3777 int i; 3778 3779 /* Apply maximum likelihood detection for 2 stream case. */ 3780 if (sc->nrxchains > 1) { 3781 bbp = rt2860_mcu_bbp_read(sc, 105); 3782 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD); 3783 } 3784 3785 /* Avoid data lost and CRC error. */ 3786 bbp = rt2860_mcu_bbp_read(sc, 4); 3787 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3788 3789 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3790 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg, 3791 rt5390_def_bbp[i].val); 3792 } 3793 3794 if (sc->mac_ver == 0x5392) { 3795 rt2860_mcu_bbp_write(sc, 84, 0x9a); 3796 rt2860_mcu_bbp_write(sc, 95, 0x9a); 3797 rt2860_mcu_bbp_write(sc, 98, 0x12); 3798 rt2860_mcu_bbp_write(sc, 106, 0x05); 3799 rt2860_mcu_bbp_write(sc, 134, 0xd0); 3800 rt2860_mcu_bbp_write(sc, 135, 0xf6); 3801 } 3802 3803 bbp = rt2860_mcu_bbp_read(sc, 152); 3804 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80); 3805 3806 /* Disable hardware antenna diversity. */ 3807 if (sc->mac_ver == 0x5390) 3808 rt2860_mcu_bbp_write(sc, 154, 0); 3809 } 3810 3811 static int 3812 rt2860_txrx_enable(struct rt2860_softc *sc) 3813 { 3814 struct ieee80211com *ic = &sc->sc_ic; 3815 uint32_t tmp; 3816 int ntries; 3817 3818 /* enable Tx/Rx DMA engine */ 3819 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3820 RAL_BARRIER_READ_WRITE(sc); 3821 for (ntries = 0; ntries < 200; ntries++) { 3822 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3823 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3824 break; 3825 DELAY(1000); 3826 } 3827 if (ntries == 200) { 3828 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3829 return ETIMEDOUT; 3830 } 3831 3832 DELAY(50); 3833 3834 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3835 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3836 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3837 3838 /* set Rx filter */ 3839 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3840 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3841 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3842 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3843 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3844 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3845 if (ic->ic_opmode == IEEE80211_M_STA) 3846 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3847 } 3848 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3849 3850 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3851 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3852 3853 return 0; 3854 } 3855 3856 static void 3857 rt2860_init(void *arg) 3858 { 3859 struct rt2860_softc *sc = arg; 3860 struct ieee80211com *ic = &sc->sc_ic; 3861 3862 RAL_LOCK(sc); 3863 rt2860_init_locked(sc); 3864 RAL_UNLOCK(sc); 3865 3866 if (sc->sc_flags & RT2860_RUNNING) 3867 ieee80211_start_all(ic); 3868 } 3869 3870 static void 3871 rt2860_init_locked(struct rt2860_softc *sc) 3872 { 3873 struct ieee80211com *ic = &sc->sc_ic; 3874 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3875 uint32_t tmp; 3876 uint8_t bbp1, bbp3; 3877 int i, qid, ridx, ntries, error; 3878 3879 RAL_LOCK_ASSERT(sc); 3880 3881 if (sc->rfswitch) { 3882 /* hardware has a radio switch on GPIO pin 2 */ 3883 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3884 device_printf(sc->sc_dev, 3885 "radio is disabled by hardware switch\n"); 3886 #ifdef notyet 3887 rt2860_stop_locked(sc); 3888 return; 3889 #endif 3890 } 3891 } 3892 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3893 3894 /* disable DMA */ 3895 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3896 tmp &= 0xff0; 3897 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3898 3899 /* PBF hardware reset */ 3900 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3901 RAL_BARRIER_WRITE(sc); 3902 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3903 3904 if ((error = rt2860_load_microcode(sc)) != 0) { 3905 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 3906 rt2860_stop_locked(sc); 3907 return; 3908 } 3909 3910 rt2860_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 3911 3912 /* init Tx power for all Tx rates (from EEPROM) */ 3913 for (ridx = 0; ridx < 5; ridx++) { 3914 if (sc->txpow20mhz[ridx] == 0xffffffff) 3915 continue; 3916 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3917 } 3918 3919 for (ntries = 0; ntries < 100; ntries++) { 3920 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3921 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3922 break; 3923 DELAY(1000); 3924 } 3925 if (ntries == 100) { 3926 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3927 rt2860_stop_locked(sc); 3928 return; 3929 } 3930 tmp &= 0xff0; 3931 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3932 3933 /* reset Rx ring and all 6 Tx rings */ 3934 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3935 3936 /* PBF hardware reset */ 3937 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3938 RAL_BARRIER_WRITE(sc); 3939 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3940 3941 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3942 3943 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3944 RAL_BARRIER_WRITE(sc); 3945 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3946 3947 for (i = 0; i < nitems(rt2860_def_mac); i++) 3948 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3949 if (sc->mac_ver >= 0x5390) 3950 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404); 3951 else if (sc->mac_ver >= 0x3071) { 3952 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3953 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3954 4 << RT2860_DLY_PAPE_EN_SHIFT); 3955 } 3956 3957 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3958 sc->sc_flags |= RT2860_PCIE; 3959 /* PCIe has different clock cycle count than PCI */ 3960 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3961 tmp = (tmp & ~0xff) | 0x7d; 3962 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3963 } 3964 3965 /* wait while MAC is busy */ 3966 for (ntries = 0; ntries < 100; ntries++) { 3967 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3968 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3969 break; 3970 DELAY(1000); 3971 } 3972 if (ntries == 100) { 3973 device_printf(sc->sc_dev, "timeout waiting for MAC\n"); 3974 rt2860_stop_locked(sc); 3975 return; 3976 } 3977 3978 /* clear Host to MCU mailbox */ 3979 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3980 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3981 3982 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3983 DELAY(1000); 3984 3985 if ((error = rt2860_bbp_init(sc)) != 0) { 3986 rt2860_stop_locked(sc); 3987 return; 3988 } 3989 3990 /* clear RX WCID search table */ 3991 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3992 /* clear pairwise key table */ 3993 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3994 /* clear IV/EIV table */ 3995 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3996 /* clear WCID attribute table */ 3997 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3998 /* clear shared key table */ 3999 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 4000 /* clear shared key mode */ 4001 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 4002 4003 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 4004 for (qid = 0; qid < 6; qid++) { 4005 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 4006 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 4007 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 4008 } 4009 4010 /* init Rx ring */ 4011 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 4012 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 4013 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 4014 4015 /* setup maximum buffer sizes */ 4016 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 4017 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 4018 4019 for (ntries = 0; ntries < 100; ntries++) { 4020 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 4021 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4022 break; 4023 DELAY(1000); 4024 } 4025 if (ntries == 100) { 4026 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 4027 rt2860_stop_locked(sc); 4028 return; 4029 } 4030 tmp &= 0xff0; 4031 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 4032 4033 /* disable interrupts mitigation */ 4034 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 4035 4036 /* write vendor-specific BBP values (from EEPROM) */ 4037 for (i = 0; i < 8; i++) { 4038 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 4039 continue; 4040 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 4041 } 4042 4043 /* select Main antenna for 1T1R devices */ 4044 if (sc->rf_rev == RT3070_RF_2020 || 4045 sc->rf_rev == RT3070_RF_3020 || 4046 sc->rf_rev == RT3070_RF_3320 || 4047 sc->mac_ver == 0x5390) 4048 rt3090_set_rx_antenna(sc, 0); 4049 4050 /* send LEDs operating mode to microcontroller */ 4051 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 4052 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 4053 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 4054 4055 if (sc->mac_ver >= 0x5390) 4056 rt5390_rf_init(sc); 4057 else if (sc->mac_ver >= 0x3071) { 4058 if ((error = rt3090_rf_init(sc)) != 0) { 4059 rt2860_stop_locked(sc); 4060 return; 4061 } 4062 } 4063 4064 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 4065 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 4066 4067 if (sc->mac_ver >= 0x5390) 4068 rt5390_rf_wakeup(sc); 4069 else if (sc->mac_ver >= 0x3071) 4070 rt3090_rf_wakeup(sc); 4071 4072 /* disable non-existing Rx chains */ 4073 bbp3 = rt2860_mcu_bbp_read(sc, 3); 4074 bbp3 &= ~(1 << 3 | 1 << 4); 4075 if (sc->nrxchains == 2) 4076 bbp3 |= 1 << 3; 4077 else if (sc->nrxchains == 3) 4078 bbp3 |= 1 << 4; 4079 rt2860_mcu_bbp_write(sc, 3, bbp3); 4080 4081 /* disable non-existing Tx chains */ 4082 bbp1 = rt2860_mcu_bbp_read(sc, 1); 4083 if (sc->ntxchains == 1) 4084 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 4085 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 4086 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 4087 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 4088 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 4089 rt2860_mcu_bbp_write(sc, 1, bbp1); 4090 4091 if (sc->mac_ver >= 0x3071) 4092 rt3090_rf_setup(sc); 4093 4094 /* select default channel */ 4095 rt2860_switch_chan(sc, ic->ic_curchan); 4096 4097 /* reset RF from MCU */ 4098 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 4099 4100 /* set RTS threshold */ 4101 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 4102 tmp &= ~0xffff00; 4103 tmp |= IEEE80211_RTS_DEFAULT << 8; 4104 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 4105 4106 /* setup initial protection mode */ 4107 rt2860_updateprot(sc); 4108 4109 /* turn radio LED on */ 4110 rt2860_set_leds(sc, RT2860_LED_RADIO); 4111 4112 /* enable Tx/Rx DMA engine */ 4113 if ((error = rt2860_txrx_enable(sc)) != 0) { 4114 rt2860_stop_locked(sc); 4115 return; 4116 } 4117 4118 /* clear pending interrupts */ 4119 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 4120 /* enable interrupts */ 4121 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 4122 4123 if (sc->sc_flags & RT2860_ADVANCED_PS) 4124 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 4125 4126 sc->sc_flags |= RT2860_RUNNING; 4127 4128 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 4129 } 4130 4131 static void 4132 rt2860_stop(void *arg) 4133 { 4134 struct rt2860_softc *sc = arg; 4135 4136 RAL_LOCK(sc); 4137 rt2860_stop_locked(sc); 4138 RAL_UNLOCK(sc); 4139 } 4140 4141 static void 4142 rt2860_stop_locked(struct rt2860_softc *sc) 4143 { 4144 uint32_t tmp; 4145 int qid; 4146 4147 if (sc->sc_flags & RT2860_RUNNING) 4148 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 4149 4150 callout_stop(&sc->watchdog_ch); 4151 sc->sc_tx_timer = 0; 4152 sc->sc_flags &= ~RT2860_RUNNING; 4153 4154 /* disable interrupts */ 4155 RAL_WRITE(sc, RT2860_INT_MASK, 0); 4156 4157 /* disable GP timer */ 4158 rt2860_set_gp_timer(sc, 0); 4159 4160 /* disable Rx */ 4161 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 4162 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4163 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 4164 4165 /* reset adapter */ 4166 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4167 RAL_BARRIER_WRITE(sc); 4168 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 4169 4170 /* reset Tx and Rx rings (and reclaim TXWIs) */ 4171 sc->qfullmsk = 0; 4172 for (qid = 0; qid < 6; qid++) 4173 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 4174 rt2860_reset_rx_ring(sc, &sc->rxq); 4175 } 4176 4177 int 4178 rt2860_load_microcode(struct rt2860_softc *sc) 4179 { 4180 const struct firmware *fp; 4181 int ntries, error; 4182 4183 RAL_LOCK_ASSERT(sc); 4184 4185 RAL_UNLOCK(sc); 4186 fp = firmware_get("rt2860fw"); 4187 RAL_LOCK(sc); 4188 if (fp == NULL) { 4189 device_printf(sc->sc_dev, 4190 "unable to receive rt2860fw firmware image\n"); 4191 return EINVAL; 4192 } 4193 4194 /* set "host program ram write selection" bit */ 4195 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 4196 /* write microcode image */ 4197 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, fp->data, fp->datasize); 4198 /* kick microcontroller unit */ 4199 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 4200 RAL_BARRIER_WRITE(sc); 4201 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 4202 4203 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 4204 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 4205 4206 /* wait until microcontroller is ready */ 4207 RAL_BARRIER_READ_WRITE(sc); 4208 for (ntries = 0; ntries < 1000; ntries++) { 4209 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 4210 break; 4211 DELAY(1000); 4212 } 4213 if (ntries == 1000) { 4214 device_printf(sc->sc_dev, 4215 "timeout waiting for MCU to initialize\n"); 4216 error = ETIMEDOUT; 4217 } else 4218 error = 0; 4219 4220 firmware_put(fp, FIRMWARE_UNLOAD); 4221 return error; 4222 } 4223 4224 /* 4225 * This function is called periodically to adjust Tx power based on 4226 * temperature variation. 4227 */ 4228 #ifdef NOT_YET 4229 static void 4230 rt2860_calib(struct rt2860_softc *sc) 4231 { 4232 struct ieee80211com *ic = &sc->sc_ic; 4233 const uint8_t *tssi; 4234 uint8_t step, bbp49; 4235 int8_t ridx, d; 4236 4237 /* read current temperature */ 4238 bbp49 = rt2860_mcu_bbp_read(sc, 49); 4239 4240 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 4241 tssi = &sc->tssi_2ghz[4]; 4242 step = sc->step_2ghz; 4243 } else { 4244 tssi = &sc->tssi_5ghz[4]; 4245 step = sc->step_5ghz; 4246 } 4247 4248 if (bbp49 < tssi[0]) { /* lower than reference */ 4249 /* use higher Tx power than default */ 4250 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 4251 } else if (bbp49 > tssi[0]) { /* greater than reference */ 4252 /* use lower Tx power than default */ 4253 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 4254 } else { 4255 /* use default Tx power */ 4256 d = 0; 4257 } 4258 d *= step; 4259 4260 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 4261 4262 /* write adjusted Tx power values for each Tx rate */ 4263 for (ridx = 0; ridx < 5; ridx++) { 4264 if (sc->txpow20mhz[ridx] == 0xffffffff) 4265 continue; 4266 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 4267 b4inc(sc->txpow20mhz[ridx], d)); 4268 } 4269 } 4270 #endif 4271 4272 static void 4273 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 4274 { 4275 uint32_t tmp; 4276 4277 if (aux) { 4278 if (sc->mac_ver == 0x5390) { 4279 rt2860_mcu_bbp_write(sc, 152, 4280 rt2860_mcu_bbp_read(sc, 152) & ~0x80); 4281 } else { 4282 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4283 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C); 4284 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4285 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 4286 } 4287 } else { 4288 if (sc->mac_ver == 0x5390) { 4289 rt2860_mcu_bbp_write(sc, 152, 4290 rt2860_mcu_bbp_read(sc, 152) | 0x80); 4291 } else { 4292 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4293 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C); 4294 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4295 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 4296 } 4297 } 4298 } 4299 4300 static void 4301 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 4302 { 4303 struct ieee80211com *ic = &sc->sc_ic; 4304 u_int chan, group; 4305 4306 chan = ieee80211_chan2ieee(ic, c); 4307 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 4308 return; 4309 4310 if (sc->mac_ver >= 0x5390) 4311 rt5390_set_chan(sc, chan); 4312 else if (sc->mac_ver >= 0x3071) 4313 rt3090_set_chan(sc, chan); 4314 else 4315 rt2860_set_chan(sc, chan); 4316 4317 /* determine channel group */ 4318 if (chan <= 14) 4319 group = 0; 4320 else if (chan <= 64) 4321 group = 1; 4322 else if (chan <= 128) 4323 group = 2; 4324 else 4325 group = 3; 4326 4327 /* XXX necessary only when group has changed! */ 4328 if (sc->mac_ver < 0x5390) 4329 rt2860_select_chan_group(sc, group); 4330 4331 DELAY(1000); 4332 } 4333 4334 static int 4335 rt2860_setup_beacon(struct rt2860_softc *sc, struct ieee80211vap *vap) 4336 { 4337 struct ieee80211com *ic = vap->iv_ic; 4338 struct rt2860_txwi txwi; 4339 struct mbuf *m; 4340 int ridx; 4341 4342 if ((m = ieee80211_beacon_alloc(vap->iv_bss)) == NULL) 4343 return ENOBUFS; 4344 4345 memset(&txwi, 0, sizeof txwi); 4346 txwi.wcid = 0xff; 4347 txwi.len = htole16(m->m_pkthdr.len); 4348 /* send beacons at the lowest available rate */ 4349 ridx = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 4350 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4351 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4352 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4353 txwi.phy |= htole16(RT2860_PHY_OFDM); 4354 txwi.txop = RT2860_TX_TXOP_HT; 4355 txwi.flags = RT2860_TX_TS; 4356 txwi.xflags = RT2860_TX_NSEQ; 4357 4358 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4359 (uint8_t *)&txwi, sizeof txwi); 4360 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4361 mtod(m, uint8_t *), m->m_pkthdr.len); 4362 4363 m_freem(m); 4364 4365 return 0; 4366 } 4367 4368 static void 4369 rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4370 { 4371 struct ieee80211com *ic = &sc->sc_ic; 4372 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4373 uint32_t tmp; 4374 4375 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4376 4377 tmp &= ~0x1fffff; 4378 tmp |= vap->iv_bss->ni_intval * 16; 4379 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4380 if (vap->iv_opmode == IEEE80211_M_STA) { 4381 /* 4382 * Local TSF is always updated with remote TSF on beacon 4383 * reception. 4384 */ 4385 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4386 } 4387 else if (vap->iv_opmode == IEEE80211_M_IBSS || 4388 vap->iv_opmode == IEEE80211_M_MBSS) { 4389 tmp |= RT2860_BCN_TX_EN; 4390 /* 4391 * Local TSF is updated with remote TSF on beacon reception 4392 * only if the remote TSF is greater than local TSF. 4393 */ 4394 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4395 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) { 4396 tmp |= RT2860_BCN_TX_EN; 4397 /* SYNC with nobody */ 4398 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4399 } 4400 4401 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4402 } 4403