1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $ 36 */ 37 38 /* 39 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 40 * 41 * Written by Bill Paul <wpaul@windriver.com> 42 * Senior Networking Software Engineer 43 * Wind River Systems 44 */ 45 46 /* 47 * This driver is designed to support RealTek's next generation of 48 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 49 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 50 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 51 * 52 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 53 * with the older 8139 family, however it also supports a special 54 * C+ mode of operation that provides several new performance enhancing 55 * features. These include: 56 * 57 * o Descriptor based DMA mechanism. Each descriptor represents 58 * a single packet fragment. Data buffers may be aligned on 59 * any byte boundary. 60 * 61 * o 64-bit DMA 62 * 63 * o TCP/IP checksum offload for both RX and TX 64 * 65 * o High and normal priority transmit DMA rings 66 * 67 * o VLAN tag insertion and extraction 68 * 69 * o TCP large send (segmentation offload) 70 * 71 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 72 * programming API is fairly straightforward. The RX filtering, EEPROM 73 * access and PHY access is the same as it is on the older 8139 series 74 * chips. 75 * 76 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 77 * same programming API and feature set as the 8139C+ with the following 78 * differences and additions: 79 * 80 * o 1000Mbps mode 81 * 82 * o Jumbo frames 83 * 84 * o GMII and TBI ports/registers for interfacing with copper 85 * or fiber PHYs 86 * 87 * o RX and TX DMA rings can have up to 1024 descriptors 88 * (the 8139C+ allows a maximum of 64) 89 * 90 * o Slight differences in register layout from the 8139C+ 91 * 92 * The TX start and timer interrupt registers are at different locations 93 * on the 8169 than they are on the 8139C+. Also, the status word in the 94 * RX descriptor has a slightly different bit layout. The 8169 does not 95 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 96 * copper gigE PHY. 97 * 98 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 99 * (the 'S' stands for 'single-chip'). These devices have the same 100 * programming API as the older 8169, but also have some vendor-specific 101 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 102 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 103 * 104 * This driver takes advantage of the RX and TX checksum offload and 105 * VLAN tag insertion/extraction features. It also implements TX 106 * interrupt moderation using the timer interrupt registers, which 107 * significantly reduces TX interrupt load. There is also support 108 * for jumbo frames, however the 8169/8169S/8110S can not transmit 109 * jumbo frames larger than 7440, so the max MTU possible with this 110 * driver is 7422 bytes. 111 */ 112 113 #define _IP_VHL 114 115 #include "opt_ifpoll.h" 116 117 #include <sys/param.h> 118 #include <sys/bus.h> 119 #include <sys/endian.h> 120 #include <sys/kernel.h> 121 #include <sys/in_cksum.h> 122 #include <sys/interrupt.h> 123 #include <sys/malloc.h> 124 #include <sys/mbuf.h> 125 #include <sys/rman.h> 126 #include <sys/serialize.h> 127 #include <sys/socket.h> 128 #include <sys/sockio.h> 129 #include <sys/sysctl.h> 130 131 #include <net/bpf.h> 132 #include <net/ethernet.h> 133 #include <net/if.h> 134 #include <net/ifq_var.h> 135 #include <net/if_arp.h> 136 #include <net/if_dl.h> 137 #include <net/if_media.h> 138 #include <net/if_poll.h> 139 #include <net/if_types.h> 140 #include <net/vlan/if_vlan_var.h> 141 #include <net/vlan/if_vlan_ether.h> 142 143 #include <netinet/ip.h> 144 145 #include <dev/netif/mii_layer/mii.h> 146 #include <dev/netif/mii_layer/miivar.h> 147 148 #include "pcidevs.h" 149 #include <bus/pci/pcireg.h> 150 #include <bus/pci/pcivar.h> 151 152 /* "device miibus" required. See GENERIC if you get errors here. */ 153 #include "miibus_if.h" 154 155 #include <dev/netif/re/if_rereg.h> 156 #include <dev/netif/re/if_revar.h> 157 158 /* 159 * Various supported device vendors/types and their names. 160 */ 161 static const struct re_type { 162 uint16_t re_vid; 163 uint16_t re_did; 164 const char *re_name; 165 } re_devs[] = { 166 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, 167 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 168 169 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, 170 "RealTek 8139C+ 10/100BaseTX" }, 171 172 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, 173 "RealTek 810x PCIe 10/100baseTX" }, 174 175 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, 176 "RealTek 8111/8168 PCIe Gigabit Ethernet" }, 177 178 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, 179 "RealTek 8110/8169 Gigabit Ethernet" }, 180 181 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, 182 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 183 184 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, 185 "Corega CG-LAPCIGT Gigabit Ethernet" }, 186 187 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, 188 "Linksys EG1032 Gigabit Ethernet" }, 189 190 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, 191 "US Robotics 997902 Gigabit Ethernet" }, 192 193 { PCI_VENDOR_TTTECH, PCI_PRODUCT_TTTECH_MC322, 194 "TTTech MC322 Gigabit Ethernet" }, 195 196 { 0, 0, NULL } 197 }; 198 199 static const struct re_hwrev re_hwrevs[] = { 200 { RE_HWREV_8139CPLUS, ETHERMTU, 201 RE_C_HWCSUM | RE_C_8139CP | RE_C_FASTE }, 202 203 { RE_HWREV_8169, ETHERMTU, 204 RE_C_HWCSUM | RE_C_8169 }, 205 206 { RE_HWREV_8110S, RE_MTU_6K, 207 RE_C_HWCSUM | RE_C_8169 }, 208 209 { RE_HWREV_8169S, RE_MTU_6K, 210 RE_C_HWCSUM | RE_C_8169 }, 211 212 { RE_HWREV_8169SB, RE_MTU_6K, 213 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 214 215 { RE_HWREV_8169SC, RE_MTU_6K, 216 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 217 218 { RE_HWREV_8168B1, RE_MTU_6K, 219 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT }, 220 221 { RE_HWREV_8168B2, RE_MTU_6K, 222 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD }, 223 224 { RE_HWREV_8168C, RE_MTU_6K, 225 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 226 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 227 228 { RE_HWREV_8168CP, RE_MTU_6K, 229 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 230 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 231 232 { RE_HWREV_8168D, RE_MTU_9K, 233 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 234 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX | RE_C_PHYPMCH }, 235 236 { RE_HWREV_8168DP, RE_MTU_9K, 237 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 238 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 239 240 { RE_HWREV_8168E, RE_MTU_9K, 241 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 242 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX | RE_C_PHYPMCH }, 243 244 { RE_HWREV_8168F, RE_MTU_9K, 245 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 246 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 247 248 { RE_HWREV_8111F, RE_MTU_9K, 249 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 250 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 251 252 { RE_HWREV_8411, ETHERMTU, 253 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 254 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 255 256 { RE_HWREV_8168G, ETHERMTU, 257 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 258 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 259 260 { RE_HWREV_8168EP, ETHERMTU, 261 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 262 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 263 264 { RE_HWREV_8168GU, ETHERMTU, 265 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 266 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 267 268 { RE_HWREV_8168H, ETHERMTU, 269 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 270 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 271 272 { RE_HWREV_8411B, ETHERMTU, 273 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 274 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 275 276 { RE_HWREV_8100E, ETHERMTU, 277 RE_C_HWCSUM | RE_C_FASTE }, 278 279 { RE_HWREV_8101E, ETHERMTU, 280 RE_C_HWCSUM | RE_C_FASTE }, 281 282 { RE_HWREV_8102E, ETHERMTU, 283 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX | 284 RE_C_FASTE }, 285 286 { RE_HWREV_8102EL, ETHERMTU, 287 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX | 288 RE_C_FASTE }, 289 290 { RE_HWREV_8105E, ETHERMTU, 291 RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | RE_C_AUTOPAD | 292 RE_C_STOP_RXTX | RE_C_FASTE | RE_C_PHYPMCH }, 293 294 { RE_HWREV_8401E, ETHERMTU, 295 RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | RE_C_AUTOPAD | 296 RE_C_STOP_RXTX | RE_C_FASTE | RE_C_PHYPMCH }, 297 298 { RE_HWREV_8402, ETHERMTU, 299 RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | RE_C_AUTOPAD | 300 RE_C_STOP_RXTX | RE_C_FASTE | RE_C_PHYPMCH }, 301 302 { RE_HWREV_8106E, ETHERMTU, 303 RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | RE_C_AUTOPAD | 304 RE_C_STOP_RXTX | RE_C_FASTE | RE_C_PHYPMCH }, 305 306 { RE_HWREV_NULL, 0, 0 } 307 }; 308 309 static int re_probe(device_t); 310 static int re_attach(device_t); 311 static int re_detach(device_t); 312 static int re_suspend(device_t); 313 static int re_resume(device_t); 314 static void re_shutdown(device_t); 315 316 static int re_allocmem(device_t); 317 static void re_freemem(device_t); 318 static void re_freebufmem(struct re_softc *, int, int); 319 static int re_encap(struct re_softc *, struct mbuf **, int *); 320 static int re_newbuf_std(struct re_softc *, int, int); 321 static int re_newbuf_jumbo(struct re_softc *, int, int); 322 static void re_setup_rxdesc(struct re_softc *, int); 323 static int re_rx_list_init(struct re_softc *); 324 static int re_tx_list_init(struct re_softc *); 325 static int re_rxeof(struct re_softc *); 326 static int re_txeof(struct re_softc *); 327 static int re_tx_collect(struct re_softc *); 328 static void re_intr(void *); 329 static void re_tick(void *); 330 static void re_tick_serialized(void *); 331 static void re_disable_aspm(device_t); 332 333 static void re_start(struct ifnet *, struct ifaltq_subque *); 334 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 335 static void re_init(void *); 336 static void re_stop(struct re_softc *); 337 static void re_watchdog(struct ifnet *); 338 static int re_ifmedia_upd(struct ifnet *); 339 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 340 341 static void re_eeprom_putbyte(struct re_softc *, int); 342 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *); 343 static void re_read_eeprom(struct re_softc *, caddr_t, int, int); 344 static void re_get_eewidth(struct re_softc *); 345 346 static int re_gmii_readreg(device_t, int, int); 347 static int re_gmii_writereg(device_t, int, int, int); 348 349 static int re_miibus_readreg(device_t, int, int); 350 static int re_miibus_writereg(device_t, int, int, int); 351 static void re_miibus_statchg(device_t); 352 353 static void re_setmulti(struct re_softc *); 354 static void re_reset(struct re_softc *, int); 355 static void re_get_eaddr(struct re_softc *, uint8_t *); 356 357 static void re_setup_hw_im(struct re_softc *); 358 static void re_setup_sim_im(struct re_softc *); 359 static void re_disable_hw_im(struct re_softc *); 360 static void re_disable_sim_im(struct re_softc *); 361 static void re_config_imtype(struct re_softc *, int); 362 static void re_setup_intr(struct re_softc *, int, int); 363 364 static int re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *); 365 static int re_sysctl_rxtime(SYSCTL_HANDLER_ARGS); 366 static int re_sysctl_txtime(SYSCTL_HANDLER_ARGS); 367 static int re_sysctl_simtime(SYSCTL_HANDLER_ARGS); 368 static int re_sysctl_imtype(SYSCTL_HANDLER_ARGS); 369 370 static int re_jpool_alloc(struct re_softc *); 371 static void re_jpool_free(struct re_softc *); 372 static struct re_jbuf *re_jbuf_alloc(struct re_softc *); 373 static void re_jbuf_free(void *); 374 static void re_jbuf_ref(void *); 375 376 #ifdef RE_DIAG 377 static int re_diag(struct re_softc *); 378 #endif 379 380 #ifdef IFPOLL_ENABLE 381 static void re_npoll(struct ifnet *, struct ifpoll_info *); 382 static void re_npoll_compat(struct ifnet *, void *, int); 383 #endif 384 385 static device_method_t re_methods[] = { 386 /* Device interface */ 387 DEVMETHOD(device_probe, re_probe), 388 DEVMETHOD(device_attach, re_attach), 389 DEVMETHOD(device_detach, re_detach), 390 DEVMETHOD(device_suspend, re_suspend), 391 DEVMETHOD(device_resume, re_resume), 392 DEVMETHOD(device_shutdown, re_shutdown), 393 394 /* bus interface */ 395 DEVMETHOD(bus_print_child, bus_generic_print_child), 396 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 397 398 /* MII interface */ 399 DEVMETHOD(miibus_readreg, re_miibus_readreg), 400 DEVMETHOD(miibus_writereg, re_miibus_writereg), 401 DEVMETHOD(miibus_statchg, re_miibus_statchg), 402 403 DEVMETHOD_END 404 }; 405 406 static driver_t re_driver = { 407 "re", 408 re_methods, 409 sizeof(struct re_softc) 410 }; 411 412 static devclass_t re_devclass; 413 414 DECLARE_DUMMY_MODULE(if_re); 415 MODULE_DEPEND(if_re, miibus, 1, 1, 1); 416 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, NULL, NULL); 417 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, NULL, NULL); 418 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, NULL, NULL); 419 420 static int re_rx_desc_count = RE_RX_DESC_CNT_DEF; 421 static int re_tx_desc_count = RE_TX_DESC_CNT_DEF; 422 static int re_msi_enable = 0; 423 424 TUNABLE_INT("hw.re.rx_desc_count", &re_rx_desc_count); 425 TUNABLE_INT("hw.re.tx_desc_count", &re_tx_desc_count); 426 TUNABLE_INT("hw.re.msi.enable", &re_msi_enable); 427 428 #define EE_SET(x) \ 429 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x)) 430 431 #define EE_CLR(x) \ 432 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x)) 433 434 static __inline void 435 re_free_rxchain(struct re_softc *sc) 436 { 437 if (sc->re_head != NULL) { 438 m_freem(sc->re_head); 439 sc->re_head = sc->re_tail = NULL; 440 } 441 } 442 443 /* 444 * Send a read command and address to the EEPROM, check for ACK. 445 */ 446 static void 447 re_eeprom_putbyte(struct re_softc *sc, int addr) 448 { 449 int d, i; 450 451 d = addr | (RE_9346_READ << sc->re_eewidth); 452 453 /* 454 * Feed in each bit and strobe the clock. 455 */ 456 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) { 457 if (d & i) 458 EE_SET(RE_EE_DATAIN); 459 else 460 EE_CLR(RE_EE_DATAIN); 461 DELAY(100); 462 EE_SET(RE_EE_CLK); 463 DELAY(150); 464 EE_CLR(RE_EE_CLK); 465 DELAY(100); 466 } 467 } 468 469 /* 470 * Read a word of data stored in the EEPROM at address 'addr.' 471 */ 472 static void 473 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest) 474 { 475 int i; 476 uint16_t word = 0; 477 478 /* 479 * Send address of word we want to read. 480 */ 481 re_eeprom_putbyte(sc, addr); 482 483 /* 484 * Start reading bits from EEPROM. 485 */ 486 for (i = 0x8000; i != 0; i >>= 1) { 487 EE_SET(RE_EE_CLK); 488 DELAY(100); 489 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT) 490 word |= i; 491 EE_CLR(RE_EE_CLK); 492 DELAY(100); 493 } 494 495 *dest = word; 496 } 497 498 /* 499 * Read a sequence of words from the EEPROM. 500 */ 501 static void 502 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt) 503 { 504 int i; 505 uint16_t word = 0, *ptr; 506 507 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 508 DELAY(100); 509 510 for (i = 0; i < cnt; i++) { 511 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL); 512 re_eeprom_getword(sc, off + i, &word); 513 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL); 514 ptr = (uint16_t *)(dest + (i * 2)); 515 *ptr = word; 516 } 517 518 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 519 } 520 521 static void 522 re_get_eewidth(struct re_softc *sc) 523 { 524 uint16_t re_did = 0; 525 526 sc->re_eewidth = 6; 527 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 528 if (re_did != 0x8129) 529 sc->re_eewidth = 8; 530 } 531 532 static int 533 re_gmii_readreg(device_t dev, int phy, int reg) 534 { 535 struct re_softc *sc = device_get_softc(dev); 536 u_int32_t rval; 537 int i; 538 539 if (phy != 1) 540 return(0); 541 542 /* Let the rgephy driver read the GMEDIASTAT register */ 543 544 if (reg == RE_GMEDIASTAT) 545 return(CSR_READ_1(sc, RE_GMEDIASTAT)); 546 547 CSR_WRITE_4(sc, RE_PHYAR, reg << 16); 548 549 for (i = 0; i < RE_PHY_TIMEOUT; i++) { 550 rval = CSR_READ_4(sc, RE_PHYAR); 551 if (rval & RE_PHYAR_BUSY) 552 break; 553 DELAY(25); 554 } 555 556 if (i == RE_PHY_TIMEOUT) { 557 device_printf(dev, "PHY read failed\n"); 558 return(0); 559 } 560 561 /* 562 * Controller requires a 20us delay to process next MDIO request. 563 */ 564 DELAY(20); 565 566 return(rval & RE_PHYAR_PHYDATA); 567 } 568 569 static int 570 re_gmii_writereg(device_t dev, int phy, int reg, int data) 571 { 572 struct re_softc *sc = device_get_softc(dev); 573 uint32_t rval; 574 int i; 575 576 CSR_WRITE_4(sc, RE_PHYAR, 577 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY); 578 579 for (i = 0; i < RE_PHY_TIMEOUT; i++) { 580 rval = CSR_READ_4(sc, RE_PHYAR); 581 if ((rval & RE_PHYAR_BUSY) == 0) 582 break; 583 DELAY(25); 584 } 585 586 if (i == RE_PHY_TIMEOUT) { 587 device_printf(dev, "PHY write failed\n"); 588 return(0); 589 } 590 591 /* 592 * Controller requires a 20us delay to process next MDIO request. 593 */ 594 DELAY(20); 595 596 return(0); 597 } 598 599 static int 600 re_miibus_readreg(device_t dev, int phy, int reg) 601 { 602 struct re_softc *sc = device_get_softc(dev); 603 uint16_t rval = 0; 604 uint16_t re8139_reg = 0; 605 606 if (!RE_IS_8139CP(sc)) { 607 rval = re_gmii_readreg(dev, phy, reg); 608 return(rval); 609 } 610 611 /* Pretend the internal PHY is only at address 0 */ 612 if (phy) 613 return(0); 614 615 switch(reg) { 616 case MII_BMCR: 617 re8139_reg = RE_BMCR; 618 break; 619 case MII_BMSR: 620 re8139_reg = RE_BMSR; 621 break; 622 case MII_ANAR: 623 re8139_reg = RE_ANAR; 624 break; 625 case MII_ANER: 626 re8139_reg = RE_ANER; 627 break; 628 case MII_ANLPAR: 629 re8139_reg = RE_LPAR; 630 break; 631 case MII_PHYIDR1: 632 case MII_PHYIDR2: 633 return(0); 634 /* 635 * Allow the rlphy driver to read the media status 636 * register. If we have a link partner which does not 637 * support NWAY, this is the register which will tell 638 * us the results of parallel detection. 639 */ 640 case RE_MEDIASTAT: 641 return(CSR_READ_1(sc, RE_MEDIASTAT)); 642 default: 643 device_printf(dev, "bad phy register\n"); 644 return(0); 645 } 646 rval = CSR_READ_2(sc, re8139_reg); 647 if (re8139_reg == RE_BMCR) { 648 /* 8139C+ has different bit layout. */ 649 rval &= ~(BMCR_LOOP | BMCR_ISO); 650 } 651 return(rval); 652 } 653 654 static int 655 re_miibus_writereg(device_t dev, int phy, int reg, int data) 656 { 657 struct re_softc *sc= device_get_softc(dev); 658 u_int16_t re8139_reg = 0; 659 660 if (!RE_IS_8139CP(sc)) 661 return(re_gmii_writereg(dev, phy, reg, data)); 662 663 /* Pretend the internal PHY is only at address 0 */ 664 if (phy) 665 return(0); 666 667 switch(reg) { 668 case MII_BMCR: 669 re8139_reg = RE_BMCR; 670 /* 8139C+ has different bit layout. */ 671 data &= ~(BMCR_LOOP | BMCR_ISO); 672 break; 673 case MII_BMSR: 674 re8139_reg = RE_BMSR; 675 break; 676 case MII_ANAR: 677 re8139_reg = RE_ANAR; 678 break; 679 case MII_ANER: 680 re8139_reg = RE_ANER; 681 break; 682 case MII_ANLPAR: 683 re8139_reg = RE_LPAR; 684 break; 685 case MII_PHYIDR1: 686 case MII_PHYIDR2: 687 return(0); 688 default: 689 device_printf(dev, "bad phy register\n"); 690 return(0); 691 } 692 CSR_WRITE_2(sc, re8139_reg, data); 693 return(0); 694 } 695 696 static void 697 re_miibus_statchg(device_t dev) 698 { 699 } 700 701 /* 702 * Program the 64-bit multicast hash filter. 703 */ 704 static void 705 re_setmulti(struct re_softc *sc) 706 { 707 struct ifnet *ifp = &sc->arpcom.ac_if; 708 int h = 0; 709 uint32_t hashes[2] = { 0, 0 }; 710 struct ifmultiaddr *ifma; 711 uint32_t rxfilt; 712 int mcnt = 0; 713 714 rxfilt = CSR_READ_4(sc, RE_RXCFG); 715 716 /* Set the individual bit to receive frames for this host only. */ 717 rxfilt |= RE_RXCFG_RX_INDIV; 718 /* Set capture broadcast bit to capture broadcast frames. */ 719 rxfilt |= RE_RXCFG_RX_BROAD; 720 721 rxfilt &= ~(RE_RXCFG_RX_ALLPHYS | RE_RXCFG_RX_MULTI); 722 if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) { 723 rxfilt |= RE_RXCFG_RX_MULTI; 724 725 /* If we want promiscuous mode, set the allframes bit. */ 726 if (ifp->if_flags & IFF_PROMISC) 727 rxfilt |= RE_RXCFG_RX_ALLPHYS; 728 729 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 730 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF); 731 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF); 732 return; 733 } 734 735 /* first, zot all the existing hash bits */ 736 CSR_WRITE_4(sc, RE_MAR0, 0); 737 CSR_WRITE_4(sc, RE_MAR4, 0); 738 739 /* now program new ones */ 740 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 741 if (ifma->ifma_addr->sa_family != AF_LINK) 742 continue; 743 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 744 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 745 if (h < 32) 746 hashes[0] |= (1 << h); 747 else 748 hashes[1] |= (1 << (h - 32)); 749 mcnt++; 750 } 751 752 if (mcnt) 753 rxfilt |= RE_RXCFG_RX_MULTI; 754 else 755 rxfilt &= ~RE_RXCFG_RX_MULTI; 756 757 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 758 759 /* 760 * For some unfathomable reason, RealTek decided to reverse 761 * the order of the multicast hash registers in the PCI Express 762 * parts. This means we have to write the hash pattern in reverse 763 * order for those devices. 764 */ 765 if (sc->re_caps & RE_C_PCIE) { 766 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[1])); 767 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[0])); 768 } else { 769 CSR_WRITE_4(sc, RE_MAR0, hashes[0]); 770 CSR_WRITE_4(sc, RE_MAR4, hashes[1]); 771 } 772 } 773 774 static void 775 re_reset(struct re_softc *sc, int running) 776 { 777 int i; 778 779 if ((sc->re_caps & RE_C_STOP_RXTX) && running) { 780 CSR_WRITE_1(sc, RE_COMMAND, 781 RE_CMD_STOPREQ | RE_CMD_TX_ENB | RE_CMD_RX_ENB); 782 DELAY(100); 783 } 784 785 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET); 786 787 for (i = 0; i < RE_TIMEOUT; i++) { 788 DELAY(10); 789 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0) 790 break; 791 } 792 if (i == RE_TIMEOUT) 793 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 794 } 795 796 #ifdef RE_DIAG 797 /* 798 * The following routine is designed to test for a defect on some 799 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 800 * lines connected to the bus, however for a 32-bit only card, they 801 * should be pulled high. The result of this defect is that the 802 * NIC will not work right if you plug it into a 64-bit slot: DMA 803 * operations will be done with 64-bit transfers, which will fail 804 * because the 64-bit data lines aren't connected. 805 * 806 * There's no way to work around this (short of talking a soldering 807 * iron to the board), however we can detect it. The method we use 808 * here is to put the NIC into digital loopback mode, set the receiver 809 * to promiscuous mode, and then try to send a frame. We then compare 810 * the frame data we sent to what was received. If the data matches, 811 * then the NIC is working correctly, otherwise we know the user has 812 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 813 * slot. In the latter case, there's no way the NIC can work correctly, 814 * so we print out a message on the console and abort the device attach. 815 */ 816 817 static int 818 re_diag(struct re_softc *sc) 819 { 820 struct ifnet *ifp = &sc->arpcom.ac_if; 821 struct mbuf *m0; 822 struct ether_header *eh; 823 struct re_desc *cur_rx; 824 uint16_t status; 825 int total_len, i, error = 0, phyaddr; 826 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 827 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 828 char ethstr[2][ETHER_ADDRSTRLEN + 1]; 829 830 /* Allocate a single mbuf */ 831 832 MGETHDR(m0, M_NOWAIT, MT_DATA); 833 if (m0 == NULL) 834 return(ENOBUFS); 835 836 /* 837 * Initialize the NIC in test mode. This sets the chip up 838 * so that it can send and receive frames, but performs the 839 * following special functions: 840 * - Puts receiver in promiscuous mode 841 * - Enables digital loopback mode 842 * - Leaves interrupts turned off 843 */ 844 845 ifp->if_flags |= IFF_PROMISC; 846 sc->re_flags |= RE_F_TESTMODE; 847 re_init(sc); 848 sc->re_flags |= RE_F_LINKED; 849 if (!RE_IS_8139CP(sc)) 850 phyaddr = 1; 851 else 852 phyaddr = 0; 853 854 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET); 855 for (i = 0; i < RE_TIMEOUT; i++) { 856 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR); 857 if (!(status & BMCR_RESET)) 858 break; 859 } 860 861 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP); 862 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG); 863 864 DELAY(100000); 865 866 /* Put some data in the mbuf */ 867 868 eh = mtod(m0, struct ether_header *); 869 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN); 870 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN); 871 eh->ether_type = htons(ETHERTYPE_IP); 872 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 873 874 /* 875 * Queue the packet, start transmission. 876 * Note: ifq_handoff() ultimately calls re_start() for us. 877 */ 878 879 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 880 error = ifq_handoff(ifp, m0, NULL); 881 if (error) { 882 m0 = NULL; 883 goto done; 884 } 885 m0 = NULL; 886 887 /* Wait for it to propagate through the chip */ 888 889 DELAY(100000); 890 for (i = 0; i < RE_TIMEOUT; i++) { 891 status = CSR_READ_2(sc, RE_ISR); 892 CSR_WRITE_2(sc, RE_ISR, status); 893 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) == 894 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) 895 break; 896 DELAY(10); 897 } 898 899 if (i == RE_TIMEOUT) { 900 if_printf(ifp, "diagnostic failed to receive packet " 901 "in loopback mode\n"); 902 error = EIO; 903 goto done; 904 } 905 906 /* 907 * The packet should have been dumped into the first 908 * entry in the RX DMA ring. Grab it from there. 909 */ 910 911 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, sc->re_ldata.re_rx_dmamap[0], 912 BUS_DMASYNC_POSTREAD); 913 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 914 sc->re_ldata.re_rx_dmamap[0]); 915 916 m0 = sc->re_ldata.re_rx_mbuf[0]; 917 sc->re_ldata.re_rx_mbuf[0] = NULL; 918 eh = mtod(m0, struct ether_header *); 919 920 cur_rx = &sc->re_ldata.re_rx_list[0]; 921 total_len = RE_RXBYTES(cur_rx); 922 923 if (total_len != ETHER_MIN_LEN) { 924 if_printf(ifp, "diagnostic failed, received short packet\n"); 925 error = EIO; 926 goto done; 927 } 928 929 /* Test that the received packet data matches what we sent. */ 930 931 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) || 932 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) || 933 be16toh(eh->ether_type) != ETHERTYPE_IP) { 934 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 935 if_printf(ifp, "expected TX data: %s/%s/0x%x\n", 936 kether_ntoa(dst, ethstr[0]), kether_ntoa(src, ethstr[1]), ETHERTYPE_IP); 937 if_printf(ifp, "received RX data: %s/%s/0x%x\n", 938 kether_ntoa(eh->ether_dhost, ethstr[0]), 939 kether_ntoa(eh->ether_shost, ethstr[1]), 940 ntohs(eh->ether_type)); 941 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 942 "into a 64-bit PCI slot.\n"); 943 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 944 "for proper operation.\n"); 945 if_printf(ifp, "Read the re(4) man page for more details.\n"); 946 error = EIO; 947 } 948 949 done: 950 /* Turn interface off, release resources */ 951 952 sc->re_flags &= ~(RE_F_LINKED | RE_F_TESTMODE); 953 ifp->if_flags &= ~IFF_PROMISC; 954 re_stop(sc); 955 if (m0 != NULL) 956 m_freem(m0); 957 958 return (error); 959 } 960 #endif /* RE_DIAG */ 961 962 /* 963 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 964 * IDs against our list and return a device name if we find a match. 965 */ 966 static int 967 re_probe(device_t dev) 968 { 969 const struct re_type *t; 970 const struct re_hwrev *hw_rev; 971 struct re_softc *sc; 972 int rid; 973 uint32_t hwrev, macmode, txcfg; 974 uint16_t vendor, product; 975 976 vendor = pci_get_vendor(dev); 977 product = pci_get_device(dev); 978 979 /* 980 * Only attach to rev.3 of the Linksys EG1032 adapter. 981 * Rev.2 is supported by sk(4). 982 */ 983 if (vendor == PCI_VENDOR_LINKSYS && 984 product == PCI_PRODUCT_LINKSYS_EG1032 && 985 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3) 986 return ENXIO; 987 988 if (vendor == PCI_VENDOR_REALTEK && 989 product == PCI_PRODUCT_REALTEK_RT8139 && 990 pci_get_revid(dev) != PCI_REVID_REALTEK_RT8139CP) { 991 /* Poor 8139 */ 992 return ENXIO; 993 } 994 995 for (t = re_devs; t->re_name != NULL; t++) { 996 if (product == t->re_did && vendor == t->re_vid) 997 break; 998 } 999 1000 /* 1001 * Check if we found a RealTek device. 1002 */ 1003 if (t->re_name == NULL) 1004 return ENXIO; 1005 1006 /* 1007 * Temporarily map the I/O space so we can read the chip ID register. 1008 */ 1009 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO); 1010 rid = RE_PCI_LOIO; 1011 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1012 RF_ACTIVE); 1013 if (sc->re_res == NULL) { 1014 device_printf(dev, "couldn't map ports/memory\n"); 1015 kfree(sc, M_TEMP); 1016 return ENXIO; 1017 } 1018 1019 sc->re_btag = rman_get_bustag(sc->re_res); 1020 sc->re_bhandle = rman_get_bushandle(sc->re_res); 1021 1022 txcfg = CSR_READ_4(sc, RE_TXCFG); 1023 hwrev = txcfg & RE_TXCFG_HWREV; 1024 macmode = txcfg & RE_TXCFG_MACMODE; 1025 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res); 1026 kfree(sc, M_TEMP); 1027 1028 /* 1029 * and continue matching for the specific chip... 1030 */ 1031 for (hw_rev = re_hwrevs; hw_rev->re_hwrev != RE_HWREV_NULL; hw_rev++) { 1032 if (hw_rev->re_hwrev == hwrev) { 1033 sc = device_get_softc(dev); 1034 1035 sc->re_hwrev = hw_rev->re_hwrev; 1036 sc->re_caps = hw_rev->re_caps; 1037 sc->re_maxmtu = hw_rev->re_maxmtu; 1038 1039 /* 1040 * Apply chip property fixup 1041 */ 1042 switch (sc->re_hwrev) { 1043 case RE_HWREV_8168GU: 1044 if (vendor == PCI_VENDOR_REALTEK && 1045 product == PCI_PRODUCT_REALTEK_RT8101E) { 1046 /* 8106EUS */ 1047 sc->re_caps = RE_C_HWCSUM | RE_C_MAC2 | 1048 RE_C_PHYPMGT | RE_C_AUTOPAD | 1049 RE_C_STOP_RXTX | RE_C_FASTE; 1050 sc->re_maxmtu = ETHERMTU; 1051 device_printf(dev, "8106EUS fixup\n"); 1052 } else { 1053 /* 8168GU */ 1054 goto ee_eaddr1; 1055 } 1056 break; 1057 1058 case RE_HWREV_8168E: 1059 if (vendor == PCI_VENDOR_REALTEK && 1060 product == PCI_PRODUCT_REALTEK_RT8101E) { 1061 /* 8105E */ 1062 sc->re_caps = RE_C_HWCSUM | RE_C_MAC2 | 1063 RE_C_PHYPMGT | RE_C_AUTOPAD | 1064 RE_C_STOP_RXTX | RE_C_FASTE | 1065 RE_C_PHYPMCH; 1066 sc->re_maxmtu = ETHERMTU; 1067 device_printf(dev, "8105E fixup\n"); 1068 goto ee_eaddr0; 1069 } 1070 /* 8168E */ 1071 break; 1072 1073 case RE_HWREV_8101E: 1074 case RE_HWREV_8102E: 1075 case RE_HWREV_8102EL: 1076 case RE_HWREV_8401E: 1077 case RE_HWREV_8105E: 1078 case RE_HWREV_8106E: 1079 ee_eaddr0: 1080 sc->re_caps |= RE_C_EE_EADDR; 1081 sc->re_ee_eaddr = RE_EE_EADDR0; 1082 break; 1083 1084 case RE_HWREV_8168F: 1085 case RE_HWREV_8111F: 1086 case RE_HWREV_8168G: 1087 if (macmode == 0 || 1088 macmode == 0x100000) { 1089 sc->re_caps |= RE_C_EE_EADDR; 1090 sc->re_ee_eaddr = RE_EE_EADDR1; 1091 } 1092 break; 1093 1094 case RE_HWREV_8411: 1095 case RE_HWREV_8168EP: 1096 case RE_HWREV_8168H: 1097 case RE_HWREV_8411B: 1098 ee_eaddr1: 1099 sc->re_caps |= RE_C_EE_EADDR; 1100 sc->re_ee_eaddr = RE_EE_EADDR1; 1101 break; 1102 } 1103 if (pci_is_pcie(dev)) 1104 sc->re_caps |= RE_C_PCIE; 1105 1106 device_set_desc(dev, t->re_name); 1107 return 0; 1108 } 1109 } 1110 device_printf(dev, "unknown hwrev 0x%08x, macmode 0x%08x\n", 1111 hwrev, macmode); 1112 1113 return ENXIO; 1114 } 1115 1116 static int 1117 re_allocmem(device_t dev) 1118 { 1119 struct re_softc *sc = device_get_softc(dev); 1120 bus_dmamem_t dmem; 1121 int error, i; 1122 1123 /* 1124 * Allocate list data 1125 */ 1126 sc->re_ldata.re_tx_mbuf = 1127 kmalloc(sc->re_tx_desc_cnt * sizeof(struct mbuf *), 1128 M_DEVBUF, M_ZERO | M_WAITOK); 1129 1130 sc->re_ldata.re_rx_mbuf = 1131 kmalloc(sc->re_rx_desc_cnt * sizeof(struct mbuf *), 1132 M_DEVBUF, M_ZERO | M_WAITOK); 1133 1134 sc->re_ldata.re_rx_paddr = 1135 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_addr_t), 1136 M_DEVBUF, M_ZERO | M_WAITOK); 1137 1138 sc->re_ldata.re_tx_dmamap = 1139 kmalloc(sc->re_tx_desc_cnt * sizeof(bus_dmamap_t), 1140 M_DEVBUF, M_ZERO | M_WAITOK); 1141 1142 sc->re_ldata.re_rx_dmamap = 1143 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_dmamap_t), 1144 M_DEVBUF, M_ZERO | M_WAITOK); 1145 1146 /* 1147 * Allocate the parent bus DMA tag appropriate for PCI. 1148 */ 1149 error = bus_dma_tag_create(NULL, /* parent */ 1150 1, 0, /* alignment, boundary */ 1151 BUS_SPACE_MAXADDR, /* lowaddr */ 1152 BUS_SPACE_MAXADDR, /* highaddr */ 1153 NULL, NULL, /* filter, filterarg */ 1154 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 1155 0, /* nsegments */ 1156 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1157 0, /* flags */ 1158 &sc->re_parent_tag); 1159 if (error) { 1160 device_printf(dev, "could not allocate parent dma tag\n"); 1161 return error; 1162 } 1163 1164 /* Allocate TX descriptor list. */ 1165 error = bus_dmamem_coherent(sc->re_parent_tag, 1166 RE_RING_ALIGN, 0, 1167 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1168 RE_TX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO, 1169 &dmem); 1170 if (error) { 1171 device_printf(dev, "could not allocate TX ring\n"); 1172 return error; 1173 } 1174 sc->re_ldata.re_tx_list_tag = dmem.dmem_tag; 1175 sc->re_ldata.re_tx_list_map = dmem.dmem_map; 1176 sc->re_ldata.re_tx_list = dmem.dmem_addr; 1177 sc->re_ldata.re_tx_list_addr = dmem.dmem_busaddr; 1178 1179 /* Allocate RX descriptor list. */ 1180 error = bus_dmamem_coherent(sc->re_parent_tag, 1181 RE_RING_ALIGN, 0, 1182 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1183 RE_RX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO, 1184 &dmem); 1185 if (error) { 1186 device_printf(dev, "could not allocate RX ring\n"); 1187 return error; 1188 } 1189 sc->re_ldata.re_rx_list_tag = dmem.dmem_tag; 1190 sc->re_ldata.re_rx_list_map = dmem.dmem_map; 1191 sc->re_ldata.re_rx_list = dmem.dmem_addr; 1192 sc->re_ldata.re_rx_list_addr = dmem.dmem_busaddr; 1193 1194 /* Allocate maps for TX mbufs. */ 1195 error = bus_dma_tag_create(sc->re_parent_tag, 1196 1, 0, 1197 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1198 NULL, NULL, 1199 RE_FRAMELEN_MAX, RE_MAXSEGS, MCLBYTES, 1200 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1201 &sc->re_ldata.re_tx_mtag); 1202 if (error) { 1203 device_printf(dev, "could not allocate TX buf dma tag\n"); 1204 return(error); 1205 } 1206 1207 /* Create DMA maps for TX buffers */ 1208 for (i = 0; i < sc->re_tx_desc_cnt; i++) { 1209 error = bus_dmamap_create(sc->re_ldata.re_tx_mtag, 1210 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1211 &sc->re_ldata.re_tx_dmamap[i]); 1212 if (error) { 1213 device_printf(dev, "can't create DMA map for TX buf\n"); 1214 re_freebufmem(sc, i, 0); 1215 return(error); 1216 } 1217 } 1218 1219 /* Allocate maps for RX mbufs. */ 1220 error = bus_dma_tag_create(sc->re_parent_tag, 1221 RE_RXBUF_ALIGN, 0, 1222 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1223 NULL, NULL, 1224 MCLBYTES, 1, MCLBYTES, 1225 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED, 1226 &sc->re_ldata.re_rx_mtag); 1227 if (error) { 1228 device_printf(dev, "could not allocate RX buf dma tag\n"); 1229 return(error); 1230 } 1231 1232 /* Create spare DMA map for RX */ 1233 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, BUS_DMA_WAITOK, 1234 &sc->re_ldata.re_rx_spare); 1235 if (error) { 1236 device_printf(dev, "can't create spare DMA map for RX\n"); 1237 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag); 1238 sc->re_ldata.re_rx_mtag = NULL; 1239 return error; 1240 } 1241 1242 /* Create DMA maps for RX buffers */ 1243 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 1244 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, 1245 BUS_DMA_WAITOK, &sc->re_ldata.re_rx_dmamap[i]); 1246 if (error) { 1247 device_printf(dev, "can't create DMA map for RX buf\n"); 1248 re_freebufmem(sc, sc->re_tx_desc_cnt, i); 1249 return(error); 1250 } 1251 } 1252 1253 /* Create jumbo buffer pool for RX if required */ 1254 if (sc->re_caps & RE_C_CONTIGRX) { 1255 error = re_jpool_alloc(sc); 1256 if (error) { 1257 re_jpool_free(sc); 1258 /* Disable jumbo frame support */ 1259 sc->re_maxmtu = ETHERMTU; 1260 } 1261 } 1262 return(0); 1263 } 1264 1265 static void 1266 re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt) 1267 { 1268 int i; 1269 1270 /* Destroy all the RX and TX buffer maps */ 1271 if (sc->re_ldata.re_tx_mtag) { 1272 for (i = 0; i < tx_cnt; i++) { 1273 bus_dmamap_destroy(sc->re_ldata.re_tx_mtag, 1274 sc->re_ldata.re_tx_dmamap[i]); 1275 } 1276 bus_dma_tag_destroy(sc->re_ldata.re_tx_mtag); 1277 sc->re_ldata.re_tx_mtag = NULL; 1278 } 1279 1280 if (sc->re_ldata.re_rx_mtag) { 1281 for (i = 0; i < rx_cnt; i++) { 1282 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag, 1283 sc->re_ldata.re_rx_dmamap[i]); 1284 } 1285 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag, 1286 sc->re_ldata.re_rx_spare); 1287 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag); 1288 sc->re_ldata.re_rx_mtag = NULL; 1289 } 1290 } 1291 1292 static void 1293 re_freemem(device_t dev) 1294 { 1295 struct re_softc *sc = device_get_softc(dev); 1296 1297 /* Unload and free the RX DMA ring memory and map */ 1298 if (sc->re_ldata.re_rx_list_tag) { 1299 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag, 1300 sc->re_ldata.re_rx_list_map); 1301 bus_dmamem_free(sc->re_ldata.re_rx_list_tag, 1302 sc->re_ldata.re_rx_list, 1303 sc->re_ldata.re_rx_list_map); 1304 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1305 } 1306 1307 /* Unload and free the TX DMA ring memory and map */ 1308 if (sc->re_ldata.re_tx_list_tag) { 1309 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag, 1310 sc->re_ldata.re_tx_list_map); 1311 bus_dmamem_free(sc->re_ldata.re_tx_list_tag, 1312 sc->re_ldata.re_tx_list, 1313 sc->re_ldata.re_tx_list_map); 1314 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1315 } 1316 1317 /* Free RX/TX buf DMA stuffs */ 1318 re_freebufmem(sc, sc->re_tx_desc_cnt, sc->re_rx_desc_cnt); 1319 1320 /* Unload and free the stats buffer and map */ 1321 if (sc->re_ldata.re_stag) { 1322 bus_dmamap_unload(sc->re_ldata.re_stag, sc->re_ldata.re_smap); 1323 bus_dmamem_free(sc->re_ldata.re_stag, 1324 sc->re_ldata.re_stats, 1325 sc->re_ldata.re_smap); 1326 bus_dma_tag_destroy(sc->re_ldata.re_stag); 1327 } 1328 1329 if (sc->re_caps & RE_C_CONTIGRX) 1330 re_jpool_free(sc); 1331 1332 if (sc->re_parent_tag) 1333 bus_dma_tag_destroy(sc->re_parent_tag); 1334 1335 if (sc->re_ldata.re_tx_mbuf != NULL) 1336 kfree(sc->re_ldata.re_tx_mbuf, M_DEVBUF); 1337 if (sc->re_ldata.re_rx_mbuf != NULL) 1338 kfree(sc->re_ldata.re_rx_mbuf, M_DEVBUF); 1339 if (sc->re_ldata.re_rx_paddr != NULL) 1340 kfree(sc->re_ldata.re_rx_paddr, M_DEVBUF); 1341 if (sc->re_ldata.re_tx_dmamap != NULL) 1342 kfree(sc->re_ldata.re_tx_dmamap, M_DEVBUF); 1343 if (sc->re_ldata.re_rx_dmamap != NULL) 1344 kfree(sc->re_ldata.re_rx_dmamap, M_DEVBUF); 1345 } 1346 1347 /* 1348 * Attach the interface. Allocate softc structures, do ifmedia 1349 * setup and ethernet/BPF attach. 1350 */ 1351 static int 1352 re_attach(device_t dev) 1353 { 1354 struct re_softc *sc = device_get_softc(dev); 1355 struct mii_probe_args mii_args; 1356 struct ifnet *ifp; 1357 struct sysctl_ctx_list *ctx; 1358 struct sysctl_oid *tree; 1359 uint8_t eaddr[ETHER_ADDR_LEN], cfg; 1360 int error = 0, qlen, msi_enable, cfg5_reg; 1361 u_int irq_flags; 1362 1363 callout_init_mp(&sc->re_timer); 1364 sc->re_dev = dev; 1365 1366 if (RE_IS_8139CP(sc)) { 1367 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_8139CP; 1368 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_8139CP; 1369 } else { 1370 sc->re_rx_desc_cnt = re_rx_desc_count; 1371 if (sc->re_rx_desc_cnt > RE_RX_DESC_CNT_MAX) 1372 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_MAX; 1373 1374 sc->re_tx_desc_cnt = re_tx_desc_count; 1375 if (sc->re_tx_desc_cnt > RE_TX_DESC_CNT_MAX) 1376 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_MAX; 1377 } 1378 1379 qlen = RE_IFQ_MAXLEN; 1380 if (sc->re_tx_desc_cnt > qlen) 1381 qlen = sc->re_tx_desc_cnt; 1382 1383 sc->re_rxbuf_size = MCLBYTES; 1384 sc->re_newbuf = re_newbuf_std; 1385 1386 sc->re_tx_time = 5; /* 125us */ 1387 sc->re_rx_time = 2; /* 50us */ 1388 if (sc->re_caps & RE_C_PCIE) 1389 sc->re_sim_time = 75; /* 75us */ 1390 else 1391 sc->re_sim_time = 125; /* 125us */ 1392 if (!RE_IS_8139CP(sc)) { 1393 /* simulated interrupt moderation */ 1394 sc->re_imtype = RE_IMTYPE_SIM; 1395 } else { 1396 sc->re_imtype = RE_IMTYPE_NONE; 1397 } 1398 re_config_imtype(sc, sc->re_imtype); 1399 1400 ctx = device_get_sysctl_ctx(dev); 1401 tree = device_get_sysctl_tree(dev); 1402 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1403 "rx_desc_count", CTLFLAG_RD, &sc->re_rx_desc_cnt, 1404 0, "RX desc count"); 1405 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1406 "tx_desc_count", CTLFLAG_RD, &sc->re_tx_desc_cnt, 1407 0, "TX desc count"); 1408 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "sim_time", 1409 CTLTYPE_INT | CTLFLAG_RW, 1410 sc, 0, re_sysctl_simtime, "I", 1411 "Simulated interrupt moderation time (usec)."); 1412 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "imtype", 1413 CTLTYPE_INT | CTLFLAG_RW, 1414 sc, 0, re_sysctl_imtype, "I", 1415 "Interrupt moderation type -- " 1416 "0:disable, 1:simulated, " 1417 "2:hardware(if supported)"); 1418 if (sc->re_caps & RE_C_HWIM) { 1419 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 1420 OID_AUTO, "hw_rxtime", 1421 CTLTYPE_INT | CTLFLAG_RW, 1422 sc, 0, re_sysctl_rxtime, "I", 1423 "Hardware interrupt moderation time " 1424 "(unit: 25usec)."); 1425 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 1426 OID_AUTO, "hw_txtime", 1427 CTLTYPE_INT | CTLFLAG_RW, 1428 sc, 0, re_sysctl_txtime, "I", 1429 "Hardware interrupt moderation time " 1430 "(unit: 25usec)."); 1431 } 1432 1433 #ifndef BURN_BRIDGES 1434 /* 1435 * Handle power management nonsense. 1436 */ 1437 1438 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1439 uint32_t membase, irq; 1440 1441 /* Save important PCI config data. */ 1442 membase = pci_read_config(dev, RE_PCI_LOMEM, 4); 1443 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1444 1445 /* Reset the power state. */ 1446 device_printf(dev, "chip is in D%d power mode " 1447 "-- setting to D0\n", pci_get_powerstate(dev)); 1448 1449 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1450 1451 /* Restore PCI config data. */ 1452 pci_write_config(dev, RE_PCI_LOMEM, membase, 4); 1453 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1454 } 1455 #endif 1456 /* 1457 * Map control/status registers. 1458 */ 1459 pci_enable_busmaster(dev); 1460 1461 if (pci_is_pcie(dev)) { 1462 sc->re_res_rid = PCIR_BAR(2); 1463 sc->re_res_type = SYS_RES_MEMORY; 1464 } else { 1465 sc->re_res_rid = PCIR_BAR(0); 1466 sc->re_res_type = SYS_RES_IOPORT; 1467 } 1468 sc->re_res = bus_alloc_resource_any(dev, sc->re_res_type, 1469 &sc->re_res_rid, RF_ACTIVE); 1470 if (sc->re_res == NULL) { 1471 device_printf(dev, "couldn't map IO\n"); 1472 error = ENXIO; 1473 goto fail; 1474 } 1475 1476 sc->re_btag = rman_get_bustag(sc->re_res); 1477 sc->re_bhandle = rman_get_bushandle(sc->re_res); 1478 1479 /* 1480 * Allocate interrupt 1481 */ 1482 if (pci_is_pcie(dev)) 1483 msi_enable = re_msi_enable; 1484 else 1485 msi_enable = 0; 1486 sc->re_irq_type = pci_alloc_1intr(dev, msi_enable, 1487 &sc->re_irq_rid, &irq_flags); 1488 1489 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->re_irq_rid, 1490 irq_flags); 1491 if (sc->re_irq == NULL) { 1492 device_printf(dev, "couldn't map interrupt\n"); 1493 error = ENXIO; 1494 goto fail; 1495 } 1496 1497 /* Disable ASPM */ 1498 re_disable_aspm(dev); 1499 1500 /* Reset the adapter. */ 1501 re_reset(sc, 0); 1502 1503 if (RE_IS_8139CP(sc)) { 1504 sc->re_bus_speed = 33; /* XXX */ 1505 } else if (sc->re_caps & RE_C_PCIE) { 1506 sc->re_bus_speed = 125; 1507 } else { 1508 uint8_t cfg2; 1509 1510 cfg2 = CSR_READ_1(sc, RE_CFG2); 1511 switch (cfg2 & RE_CFG2_PCICLK_MASK) { 1512 case RE_CFG2_PCICLK_33MHZ: 1513 sc->re_bus_speed = 33; 1514 break; 1515 case RE_CFG2_PCICLK_66MHZ: 1516 sc->re_bus_speed = 66; 1517 break; 1518 default: 1519 device_printf(dev, "unknown bus speed, assume 33MHz\n"); 1520 sc->re_bus_speed = 33; 1521 break; 1522 } 1523 if (cfg2 & RE_CFG2_PCI64) 1524 sc->re_caps |= RE_C_PCI64; 1525 } 1526 device_printf(dev, "Hardware rev. 0x%08x; PCI%s %dMHz\n", 1527 sc->re_hwrev, 1528 (sc->re_caps & RE_C_PCIE) ? 1529 "-E" : ((sc->re_caps & RE_C_PCI64) ? "64" : "32"), 1530 sc->re_bus_speed); 1531 1532 /* 1533 * Enable PME. 1534 */ 1535 if (RE_IS_8139CP(sc)) 1536 cfg5_reg = RE_CFG5_8139CP; 1537 else 1538 cfg5_reg = RE_CFG5; 1539 CSR_WRITE_1(sc, RE_EECMD, RE_EE_MODE); 1540 cfg = CSR_READ_1(sc, RE_CFG1); 1541 cfg |= RE_CFG1_PME; 1542 CSR_WRITE_1(sc, RE_CFG1, cfg); 1543 cfg = CSR_READ_1(sc, cfg5_reg); 1544 cfg &= RE_CFG5_PME_STS; 1545 CSR_WRITE_1(sc, cfg5_reg, cfg); 1546 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 1547 1548 re_get_eaddr(sc, eaddr); 1549 1550 if (!RE_IS_8139CP(sc)) { 1551 /* Set RX length mask */ 1552 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 1553 sc->re_txstart = RE_GTXSTART; 1554 } else { 1555 /* Set RX length mask */ 1556 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 1557 sc->re_txstart = RE_TXSTART; 1558 } 1559 1560 /* Allocate DMA stuffs */ 1561 error = re_allocmem(dev); 1562 if (error) 1563 goto fail; 1564 1565 /* 1566 * Apply some magic PCI settings from Realtek ... 1567 */ 1568 if (RE_IS_8169(sc)) { 1569 CSR_WRITE_1(sc, 0x82, 1); 1570 pci_write_config(dev, PCIR_CACHELNSZ, 0x8, 1); 1571 } 1572 pci_write_config(dev, PCIR_LATTIMER, 0x40, 1); 1573 1574 if (sc->re_caps & RE_C_MAC2) { 1575 /* 1576 * Following part is extracted from Realtek BSD driver v176. 1577 * However, this does _not_ make much/any sense: 1578 * 8168C's PCI Express device control is located at 0x78, 1579 * so the reading from 0x79 (higher part of 0x78) and setting 1580 * the 4~6bits intend to enlarge the "max read request size" 1581 * (we will do it). The content of the rest part of this 1582 * register is not meaningful to other PCI registers, so 1583 * writing the value to 0x54 could be completely wrong. 1584 * 0x80 is the lower part of PCI Express device status, non- 1585 * reserved bits are RW1C, writing 0 to them will not have 1586 * any effect at all. 1587 */ 1588 #ifdef foo 1589 uint8_t val; 1590 1591 val = pci_read_config(dev, 0x79, 1); 1592 val = (val & ~0x70) | 0x50; 1593 pci_write_config(dev, 0x54, val, 1); 1594 pci_write_config(dev, 0x80, 0, 1); 1595 #endif 1596 } 1597 1598 /* 1599 * Apply some PHY fixup from Realtek ... 1600 */ 1601 if (sc->re_caps & RE_C_PHYPMCH) { 1602 CSR_WRITE_1(sc, RE_PMCH, CSR_READ_1(sc, RE_PMCH) | 0x80); 1603 if (sc->re_hwrev == RE_HWREV_8401E) 1604 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1605 } 1606 if (sc->re_caps & RE_C_PHYPMGT) { 1607 /* Power up PHY */ 1608 re_miibus_writereg(dev, 1, 0x1f, 0); 1609 re_miibus_writereg(dev, 1, 0xe, 0); 1610 } 1611 1612 /* Do MII setup */ 1613 mii_probe_args_init(&mii_args, re_ifmedia_upd, re_ifmedia_sts); 1614 mii_args.mii_probemask = 1 << 0; 1615 if (!RE_IS_8139CP(sc)) 1616 mii_args.mii_probemask = 1 << 1; 1617 if (mii_probe(dev, &sc->re_miibus, &mii_args)) { 1618 device_printf(dev, "MII without any phy!\n"); 1619 error = ENXIO; 1620 goto fail; 1621 } 1622 1623 ifp = &sc->arpcom.ac_if; 1624 ifp->if_softc = sc; 1625 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1626 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1627 ifp->if_ioctl = re_ioctl; 1628 ifp->if_start = re_start; 1629 #ifdef IFPOLL_ENABLE 1630 ifp->if_npoll = re_npoll; 1631 #endif 1632 ifp->if_watchdog = re_watchdog; 1633 ifp->if_init = re_init; 1634 if (!RE_IS_8139CP(sc)) /* XXX */ 1635 ifp->if_baudrate = 1000000000; 1636 else 1637 ifp->if_baudrate = 100000000; 1638 ifp->if_nmbclusters = sc->re_rx_desc_cnt; 1639 ifq_set_maxlen(&ifp->if_snd, qlen); 1640 ifq_set_ready(&ifp->if_snd); 1641 1642 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1643 if (sc->re_caps & RE_C_HWCSUM) 1644 ifp->if_capabilities |= IFCAP_HWCSUM; 1645 1646 ifp->if_capenable = ifp->if_capabilities; 1647 if (ifp->if_capabilities & IFCAP_HWCSUM) { 1648 /* 1649 * RTL8168/8111C generates wrong IP checksummed frame if the 1650 * packet has IP options so disable TX IP checksum offloading. 1651 */ 1652 if (sc->re_hwrev == RE_HWREV_8168CP || 1653 sc->re_hwrev == RE_HWREV_8168C) 1654 sc->re_hwassist = CSUM_TCP | CSUM_UDP; 1655 else 1656 sc->re_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1657 } 1658 ifp->if_hwassist = sc->re_hwassist; 1659 1660 /* 1661 * Call MI attach routine. 1662 */ 1663 ether_ifattach(ifp, eaddr, NULL); 1664 1665 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->re_irq)); 1666 1667 #ifdef IFPOLL_ENABLE 1668 ifpoll_compat_setup(&sc->re_npoll, ctx, (struct sysctl_oid *)tree, 1669 device_get_unit(dev), ifp->if_serializer); 1670 #endif 1671 1672 #ifdef RE_DIAG 1673 /* 1674 * Perform hardware diagnostic on the original RTL8169. 1675 * Some 32-bit cards were incorrectly wired and would 1676 * malfunction if plugged into a 64-bit slot. 1677 */ 1678 if (sc->re_hwrev == RE_HWREV_8169) { 1679 lwkt_serialize_enter(ifp->if_serializer); 1680 error = re_diag(sc); 1681 lwkt_serialize_exit(ifp->if_serializer); 1682 1683 if (error) { 1684 device_printf(dev, "hardware diagnostic failure\n"); 1685 ether_ifdetach(ifp); 1686 goto fail; 1687 } 1688 } 1689 #endif /* RE_DIAG */ 1690 1691 /* Hook interrupt last to avoid having to lock softc */ 1692 error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc, 1693 &sc->re_intrhand, ifp->if_serializer); 1694 1695 if (error) { 1696 device_printf(dev, "couldn't set up irq\n"); 1697 ether_ifdetach(ifp); 1698 goto fail; 1699 } 1700 1701 fail: 1702 if (error) 1703 re_detach(dev); 1704 1705 return (error); 1706 } 1707 1708 /* 1709 * Shutdown hardware and free up resources. This can be called any 1710 * time after the mutex has been initialized. It is called in both 1711 * the error case in attach and the normal detach case so it needs 1712 * to be careful about only freeing resources that have actually been 1713 * allocated. 1714 */ 1715 static int 1716 re_detach(device_t dev) 1717 { 1718 struct re_softc *sc = device_get_softc(dev); 1719 struct ifnet *ifp = &sc->arpcom.ac_if; 1720 1721 /* These should only be active if attach succeeded */ 1722 if (device_is_attached(dev)) { 1723 lwkt_serialize_enter(ifp->if_serializer); 1724 re_stop(sc); 1725 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand); 1726 lwkt_serialize_exit(ifp->if_serializer); 1727 1728 ether_ifdetach(ifp); 1729 } 1730 if (sc->re_miibus) 1731 device_delete_child(dev, sc->re_miibus); 1732 bus_generic_detach(dev); 1733 1734 if (sc->re_irq) 1735 bus_release_resource(dev, SYS_RES_IRQ, sc->re_irq_rid, 1736 sc->re_irq); 1737 1738 if (sc->re_irq_type == PCI_INTR_TYPE_MSI) 1739 pci_release_msi(dev); 1740 1741 if (sc->re_res) { 1742 bus_release_resource(dev, sc->re_res_type, sc->re_res_rid, 1743 sc->re_res); 1744 } 1745 1746 /* Free DMA stuffs */ 1747 re_freemem(dev); 1748 1749 return(0); 1750 } 1751 1752 static void 1753 re_setup_rxdesc(struct re_softc *sc, int idx) 1754 { 1755 bus_addr_t paddr; 1756 uint32_t cmdstat; 1757 struct re_desc *d; 1758 1759 paddr = sc->re_ldata.re_rx_paddr[idx]; 1760 d = &sc->re_ldata.re_rx_list[idx]; 1761 1762 d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr)); 1763 d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr)); 1764 1765 cmdstat = sc->re_rxbuf_size | RE_RDESC_CMD_OWN; 1766 if (idx == (sc->re_rx_desc_cnt - 1)) 1767 cmdstat |= RE_RDESC_CMD_EOR; 1768 d->re_cmdstat = htole32(cmdstat); 1769 } 1770 1771 static int 1772 re_newbuf_std(struct re_softc *sc, int idx, int init) 1773 { 1774 bus_dma_segment_t seg; 1775 bus_dmamap_t map; 1776 struct mbuf *m; 1777 int error, nsegs; 1778 1779 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR); 1780 if (m == NULL) { 1781 error = ENOBUFS; 1782 1783 if (init) { 1784 if_printf(&sc->arpcom.ac_if, "m_getcl failed\n"); 1785 return error; 1786 } else { 1787 goto back; 1788 } 1789 } 1790 m->m_len = m->m_pkthdr.len = MCLBYTES; 1791 1792 /* 1793 * NOTE: 1794 * re(4) chips need address of the receive buffer to be 8-byte 1795 * aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1796 */ 1797 1798 error = bus_dmamap_load_mbuf_segment(sc->re_ldata.re_rx_mtag, 1799 sc->re_ldata.re_rx_spare, m, 1800 &seg, 1, &nsegs, BUS_DMA_NOWAIT); 1801 if (error) { 1802 m_freem(m); 1803 if (init) { 1804 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 1805 return error; 1806 } else { 1807 goto back; 1808 } 1809 } 1810 1811 if (!init) { 1812 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, 1813 sc->re_ldata.re_rx_dmamap[idx], 1814 BUS_DMASYNC_POSTREAD); 1815 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 1816 sc->re_ldata.re_rx_dmamap[idx]); 1817 } 1818 sc->re_ldata.re_rx_mbuf[idx] = m; 1819 sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr; 1820 1821 map = sc->re_ldata.re_rx_dmamap[idx]; 1822 sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare; 1823 sc->re_ldata.re_rx_spare = map; 1824 back: 1825 re_setup_rxdesc(sc, idx); 1826 return error; 1827 } 1828 1829 static int 1830 re_newbuf_jumbo(struct re_softc *sc, int idx, int init) 1831 { 1832 struct mbuf *m; 1833 struct re_jbuf *jbuf; 1834 int error = 0; 1835 1836 MGETHDR(m, init ? M_WAITOK : M_NOWAIT, MT_DATA); 1837 if (m == NULL) { 1838 error = ENOBUFS; 1839 if (init) { 1840 if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n"); 1841 return error; 1842 } else { 1843 goto back; 1844 } 1845 } 1846 1847 jbuf = re_jbuf_alloc(sc); 1848 if (jbuf == NULL) { 1849 m_freem(m); 1850 1851 error = ENOBUFS; 1852 if (init) { 1853 if_printf(&sc->arpcom.ac_if, "jpool is empty\n"); 1854 return error; 1855 } else { 1856 goto back; 1857 } 1858 } 1859 1860 m->m_ext.ext_arg = jbuf; 1861 m->m_ext.ext_buf = jbuf->re_buf; 1862 m->m_ext.ext_free = re_jbuf_free; 1863 m->m_ext.ext_ref = re_jbuf_ref; 1864 m->m_ext.ext_size = sc->re_rxbuf_size; 1865 1866 m->m_data = m->m_ext.ext_buf; 1867 m->m_flags |= M_EXT; 1868 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1869 1870 /* 1871 * NOTE: 1872 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer 1873 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1874 */ 1875 1876 sc->re_ldata.re_rx_mbuf[idx] = m; 1877 sc->re_ldata.re_rx_paddr[idx] = jbuf->re_paddr; 1878 back: 1879 re_setup_rxdesc(sc, idx); 1880 return error; 1881 } 1882 1883 static int 1884 re_tx_list_init(struct re_softc *sc) 1885 { 1886 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 1887 1888 sc->re_ldata.re_tx_prodidx = 0; 1889 sc->re_ldata.re_tx_considx = 0; 1890 sc->re_ldata.re_tx_free = sc->re_tx_desc_cnt; 1891 1892 return(0); 1893 } 1894 1895 static int 1896 re_rx_list_init(struct re_softc *sc) 1897 { 1898 int i, error; 1899 1900 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc)); 1901 1902 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 1903 error = sc->re_newbuf(sc, i, 1); 1904 if (error) 1905 return(error); 1906 } 1907 1908 sc->re_ldata.re_rx_prodidx = 0; 1909 sc->re_head = sc->re_tail = NULL; 1910 1911 return(0); 1912 } 1913 1914 #define RE_IP4_PACKET 0x1 1915 #define RE_TCP_PACKET 0x2 1916 #define RE_UDP_PACKET 0x4 1917 1918 static __inline uint8_t 1919 re_packet_type(struct re_softc *sc, uint32_t rxstat, uint32_t rxctrl) 1920 { 1921 uint8_t packet_type = 0; 1922 1923 if (sc->re_caps & RE_C_MAC2) { 1924 if (rxctrl & RE_RDESC_CTL_PROTOIP4) 1925 packet_type |= RE_IP4_PACKET; 1926 } else { 1927 if (rxstat & RE_RDESC_STAT_PROTOID) 1928 packet_type |= RE_IP4_PACKET; 1929 } 1930 if (RE_TCPPKT(rxstat)) 1931 packet_type |= RE_TCP_PACKET; 1932 else if (RE_UDPPKT(rxstat)) 1933 packet_type |= RE_UDP_PACKET; 1934 return packet_type; 1935 } 1936 1937 /* 1938 * RX handler for C+ and 8169. For the gigE chips, we support 1939 * the reception of jumbo frames that have been fragmented 1940 * across multiple 2K mbuf cluster buffers. 1941 */ 1942 static int 1943 re_rxeof(struct re_softc *sc) 1944 { 1945 struct ifnet *ifp = &sc->arpcom.ac_if; 1946 struct mbuf *m; 1947 struct re_desc *cur_rx; 1948 uint32_t rxstat, rxctrl; 1949 int i, total_len, rx = 0; 1950 1951 for (i = sc->re_ldata.re_rx_prodidx; 1952 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_RXDESC_INC(sc, i)) { 1953 cur_rx = &sc->re_ldata.re_rx_list[i]; 1954 m = sc->re_ldata.re_rx_mbuf[i]; 1955 total_len = RE_RXBYTES(cur_rx); 1956 rxstat = le32toh(cur_rx->re_cmdstat); 1957 rxctrl = le32toh(cur_rx->re_control); 1958 1959 rx = 1; 1960 1961 #ifdef INVARIANTS 1962 if (sc->re_flags & RE_F_USE_JPOOL) 1963 KKASSERT(rxstat & RE_RDESC_STAT_EOF); 1964 #endif 1965 1966 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1967 if (sc->re_flags & RE_F_DROP_RXFRAG) { 1968 re_setup_rxdesc(sc, i); 1969 continue; 1970 } 1971 1972 if (sc->re_newbuf(sc, i, 0)) { 1973 /* Drop upcoming fragments */ 1974 sc->re_flags |= RE_F_DROP_RXFRAG; 1975 continue; 1976 } 1977 1978 m->m_len = MCLBYTES; 1979 if (sc->re_head == NULL) { 1980 sc->re_head = sc->re_tail = m; 1981 } else { 1982 sc->re_tail->m_next = m; 1983 sc->re_tail = m; 1984 } 1985 continue; 1986 } else if (sc->re_flags & RE_F_DROP_RXFRAG) { 1987 /* 1988 * Last fragment of a multi-fragment packet. 1989 * 1990 * Since error already happened, this fragment 1991 * must be dropped as well as the fragment chain. 1992 */ 1993 re_setup_rxdesc(sc, i); 1994 re_free_rxchain(sc); 1995 sc->re_flags &= ~RE_F_DROP_RXFRAG; 1996 continue; 1997 } 1998 1999 /* 2000 * NOTE: for the 8139C+, the frame length field 2001 * is always 12 bits in size, but for the gigE chips, 2002 * it is 13 bits (since the max RX frame length is 16K). 2003 * Unfortunately, all 32 bits in the status word 2004 * were already used, so to make room for the extra 2005 * length bit, RealTek took out the 'frame alignment 2006 * error' bit and shifted the other status bits 2007 * over one slot. The OWN, EOR, FS and LS bits are 2008 * still in the same places. We have already extracted 2009 * the frame length and checked the OWN bit, so rather 2010 * than using an alternate bit mapping, we shift the 2011 * status bits one space to the right so we can evaluate 2012 * them using the 8169 status as though it was in the 2013 * same format as that of the 8139C+. 2014 */ 2015 if (!RE_IS_8139CP(sc)) 2016 rxstat >>= 1; 2017 2018 if (rxstat & RE_RDESC_STAT_RXERRSUM) { 2019 IFNET_STAT_INC(ifp, ierrors, 1); 2020 /* 2021 * If this is part of a multi-fragment packet, 2022 * discard all the pieces. 2023 */ 2024 re_free_rxchain(sc); 2025 re_setup_rxdesc(sc, i); 2026 continue; 2027 } 2028 2029 /* 2030 * If allocating a replacement mbuf fails, 2031 * reload the current one. 2032 */ 2033 2034 if (sc->re_newbuf(sc, i, 0)) { 2035 IFNET_STAT_INC(ifp, ierrors, 1); 2036 continue; 2037 } 2038 2039 if (sc->re_head != NULL) { 2040 m->m_len = total_len % MCLBYTES; 2041 /* 2042 * Special case: if there's 4 bytes or less 2043 * in this buffer, the mbuf can be discarded: 2044 * the last 4 bytes is the CRC, which we don't 2045 * care about anyway. 2046 */ 2047 if (m->m_len <= ETHER_CRC_LEN) { 2048 sc->re_tail->m_len -= 2049 (ETHER_CRC_LEN - m->m_len); 2050 m_freem(m); 2051 } else { 2052 m->m_len -= ETHER_CRC_LEN; 2053 sc->re_tail->m_next = m; 2054 } 2055 m = sc->re_head; 2056 sc->re_head = sc->re_tail = NULL; 2057 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2058 } else { 2059 m->m_pkthdr.len = m->m_len = 2060 (total_len - ETHER_CRC_LEN); 2061 } 2062 2063 IFNET_STAT_INC(ifp, ipackets, 1); 2064 m->m_pkthdr.rcvif = ifp; 2065 2066 /* Do RX checksumming if enabled */ 2067 2068 if (ifp->if_capenable & IFCAP_RXCSUM) { 2069 uint8_t packet_type; 2070 2071 packet_type = re_packet_type(sc, rxstat, rxctrl); 2072 2073 /* Check IP header checksum */ 2074 if (packet_type & RE_IP4_PACKET) { 2075 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2076 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0) 2077 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2078 } 2079 2080 /* Check TCP/UDP checksum */ 2081 if (((packet_type & RE_TCP_PACKET) && 2082 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) || 2083 ((packet_type & RE_UDP_PACKET) && 2084 (rxstat & RE_RDESC_STAT_UDPSUMBAD) == 0)) { 2085 m->m_pkthdr.csum_flags |= 2086 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 2087 CSUM_FRAG_NOT_CHECKED; 2088 m->m_pkthdr.csum_data = 0xffff; 2089 } 2090 } 2091 2092 if (rxctrl & RE_RDESC_CTL_HASTAG) { 2093 m->m_flags |= M_VLANTAG; 2094 m->m_pkthdr.ether_vlantag = 2095 be16toh((rxctrl & RE_RDESC_CTL_TAGDATA)); 2096 } 2097 ifp->if_input(ifp, m, NULL, -1); 2098 } 2099 2100 sc->re_ldata.re_rx_prodidx = i; 2101 2102 return rx; 2103 } 2104 2105 #undef RE_IP4_PACKET 2106 #undef RE_TCP_PACKET 2107 #undef RE_UDP_PACKET 2108 2109 static int 2110 re_tx_collect(struct re_softc *sc) 2111 { 2112 struct ifnet *ifp = &sc->arpcom.ac_if; 2113 uint32_t txstat; 2114 int idx, tx = 0; 2115 2116 for (idx = sc->re_ldata.re_tx_considx; 2117 sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt; 2118 RE_TXDESC_INC(sc, idx)) { 2119 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat); 2120 if (txstat & RE_TDESC_CMD_OWN) 2121 break; 2122 2123 tx = 1; 2124 2125 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0; 2126 2127 /* 2128 * We only stash mbufs in the last descriptor 2129 * in a fragment chain, which also happens to 2130 * be the only place where the TX status bits 2131 * are valid. 2132 */ 2133 if (txstat & RE_TDESC_CMD_EOF) { 2134 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, 2135 sc->re_ldata.re_tx_dmamap[idx]); 2136 m_freem(sc->re_ldata.re_tx_mbuf[idx]); 2137 sc->re_ldata.re_tx_mbuf[idx] = NULL; 2138 if (txstat & (RE_TDESC_STAT_EXCESSCOL| 2139 RE_TDESC_STAT_COLCNT)) 2140 IFNET_STAT_INC(ifp, collisions, 1); 2141 if (txstat & RE_TDESC_STAT_TXERRSUM) 2142 IFNET_STAT_INC(ifp, oerrors, 1); 2143 else 2144 IFNET_STAT_INC(ifp, opackets, 1); 2145 } 2146 sc->re_ldata.re_tx_free++; 2147 } 2148 sc->re_ldata.re_tx_considx = idx; 2149 2150 return tx; 2151 } 2152 2153 static int 2154 re_txeof(struct re_softc *sc) 2155 { 2156 struct ifnet *ifp = &sc->arpcom.ac_if; 2157 int tx; 2158 2159 tx = re_tx_collect(sc); 2160 2161 /* There is enough free TX descs */ 2162 if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE) 2163 ifq_clr_oactive(&ifp->if_snd); 2164 2165 /* 2166 * Some chips will ignore a second TX request issued while an 2167 * existing transmission is in progress. If the transmitter goes 2168 * idle but there are still packets waiting to be sent, we need 2169 * to restart the channel here to flush them out. This only seems 2170 * to be required with the PCIe devices. 2171 */ 2172 if (sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt) 2173 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2174 else 2175 ifp->if_timer = 0; 2176 2177 return tx; 2178 } 2179 2180 static void 2181 re_tick(void *xsc) 2182 { 2183 struct re_softc *sc = xsc; 2184 2185 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 2186 re_tick_serialized(xsc); 2187 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 2188 } 2189 2190 static void 2191 re_tick_serialized(void *xsc) 2192 { 2193 struct re_softc *sc = xsc; 2194 struct ifnet *ifp = &sc->arpcom.ac_if; 2195 struct mii_data *mii; 2196 2197 ASSERT_SERIALIZED(ifp->if_serializer); 2198 2199 mii = device_get_softc(sc->re_miibus); 2200 mii_tick(mii); 2201 if (sc->re_flags & RE_F_LINKED) { 2202 if (!(mii->mii_media_status & IFM_ACTIVE)) 2203 sc->re_flags &= ~RE_F_LINKED; 2204 } else { 2205 if (mii->mii_media_status & IFM_ACTIVE && 2206 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2207 sc->re_flags |= RE_F_LINKED; 2208 if (!ifq_is_empty(&ifp->if_snd)) 2209 if_devstart(ifp); 2210 } 2211 } 2212 2213 callout_reset(&sc->re_timer, hz, re_tick, sc); 2214 } 2215 2216 #ifdef IFPOLL_ENABLE 2217 2218 static void 2219 re_npoll_compat(struct ifnet *ifp, void *arg __unused, int count) 2220 { 2221 struct re_softc *sc = ifp->if_softc; 2222 2223 ASSERT_SERIALIZED(ifp->if_serializer); 2224 2225 if (sc->re_npoll.ifpc_stcount-- == 0) { 2226 uint16_t status; 2227 2228 sc->re_npoll.ifpc_stcount = sc->re_npoll.ifpc_stfrac; 2229 2230 status = CSR_READ_2(sc, RE_ISR); 2231 if (status == 0xffff) 2232 return; 2233 if (status) 2234 CSR_WRITE_2(sc, RE_ISR, status); 2235 2236 /* 2237 * XXX check behaviour on receiver stalls. 2238 */ 2239 2240 if (status & RE_ISR_SYSTEM_ERR) 2241 re_init(sc); 2242 } 2243 2244 sc->rxcycles = count; 2245 re_rxeof(sc); 2246 re_txeof(sc); 2247 2248 if (!ifq_is_empty(&ifp->if_snd)) 2249 if_devstart(ifp); 2250 } 2251 2252 static void 2253 re_npoll(struct ifnet *ifp, struct ifpoll_info *info) 2254 { 2255 struct re_softc *sc = ifp->if_softc; 2256 2257 ASSERT_SERIALIZED(ifp->if_serializer); 2258 2259 if (info != NULL) { 2260 int cpuid = sc->re_npoll.ifpc_cpuid; 2261 2262 info->ifpi_rx[cpuid].poll_func = re_npoll_compat; 2263 info->ifpi_rx[cpuid].arg = NULL; 2264 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 2265 2266 if (ifp->if_flags & IFF_RUNNING) 2267 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 2268 ifq_set_cpuid(&ifp->if_snd, cpuid); 2269 } else { 2270 if (ifp->if_flags & IFF_RUNNING) 2271 re_setup_intr(sc, 1, sc->re_imtype); 2272 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->re_irq)); 2273 } 2274 } 2275 #endif /* IFPOLL_ENABLE */ 2276 2277 static void 2278 re_intr(void *arg) 2279 { 2280 struct re_softc *sc = arg; 2281 struct ifnet *ifp = &sc->arpcom.ac_if; 2282 uint16_t status; 2283 int rx, tx; 2284 2285 ASSERT_SERIALIZED(ifp->if_serializer); 2286 2287 if ((sc->re_flags & RE_F_SUSPENDED) || 2288 (ifp->if_flags & IFF_RUNNING) == 0) 2289 return; 2290 2291 rx = tx = 0; 2292 2293 status = CSR_READ_2(sc, RE_ISR); 2294 /* If the card has gone away the read returns 0xffff. */ 2295 if (status == 0xffff) 2296 goto reload; 2297 if (status) 2298 CSR_WRITE_2(sc, RE_ISR, status); 2299 2300 if ((status & sc->re_intrs) == 0) 2301 goto reload; 2302 2303 if (status & (sc->re_rx_ack | RE_ISR_RX_ERR)) 2304 rx |= re_rxeof(sc); 2305 2306 if (status & (sc->re_tx_ack | RE_ISR_TX_ERR)) 2307 tx |= re_txeof(sc); 2308 2309 if (status & RE_ISR_SYSTEM_ERR) 2310 re_init(sc); 2311 2312 if (status & RE_ISR_LINKCHG) { 2313 callout_stop(&sc->re_timer); 2314 re_tick_serialized(sc); 2315 } 2316 2317 reload: 2318 if (sc->re_imtype == RE_IMTYPE_SIM) { 2319 if ((sc->re_flags & RE_F_TIMER_INTR)) { 2320 if ((tx | rx) == 0) { 2321 /* 2322 * Nothing needs to be processed, fallback 2323 * to use TX/RX interrupts. 2324 */ 2325 re_setup_intr(sc, 1, RE_IMTYPE_NONE); 2326 2327 /* 2328 * Recollect, mainly to avoid the possible 2329 * race introduced by changing interrupt 2330 * masks. 2331 */ 2332 re_rxeof(sc); 2333 tx = re_txeof(sc); 2334 } else { 2335 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */ 2336 } 2337 } else if (tx | rx) { 2338 /* 2339 * Assume that using simulated interrupt moderation 2340 * (hardware timer based) could reduce the interript 2341 * rate. 2342 */ 2343 re_setup_intr(sc, 1, RE_IMTYPE_SIM); 2344 } 2345 } 2346 2347 if (tx && !ifq_is_empty(&ifp->if_snd)) 2348 if_devstart(ifp); 2349 } 2350 2351 static int 2352 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0) 2353 { 2354 struct mbuf *m = *m_head; 2355 bus_dma_segment_t segs[RE_MAXSEGS]; 2356 bus_dmamap_t map; 2357 int error, maxsegs, idx, i, nsegs; 2358 struct re_desc *d, *tx_ring; 2359 uint32_t cmd_csum, ctl_csum, vlantag; 2360 2361 KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE, 2362 ("not enough free TX desc")); 2363 2364 map = sc->re_ldata.re_tx_dmamap[*idx0]; 2365 2366 /* 2367 * Set up checksum offload. Note: checksum offload bits must 2368 * appear in all descriptors of a multi-descriptor transmit 2369 * attempt. (This is according to testing done with an 8169 2370 * chip. I'm not sure if this is a requirement or a bug.) 2371 */ 2372 cmd_csum = ctl_csum = 0; 2373 if (m->m_pkthdr.csum_flags & CSUM_IP) { 2374 cmd_csum |= RE_TDESC_CMD_IPCSUM; 2375 ctl_csum |= RE_TDESC_CTL_IPCSUM; 2376 } 2377 if (m->m_pkthdr.csum_flags & CSUM_TCP) { 2378 cmd_csum |= RE_TDESC_CMD_TCPCSUM; 2379 ctl_csum |= RE_TDESC_CTL_TCPCSUM; 2380 } 2381 if (m->m_pkthdr.csum_flags & CSUM_UDP) { 2382 cmd_csum |= RE_TDESC_CMD_UDPCSUM; 2383 ctl_csum |= RE_TDESC_CTL_UDPCSUM; 2384 } 2385 2386 /* For MAC2 chips, csum flags are set on re_control */ 2387 if (sc->re_caps & RE_C_MAC2) 2388 cmd_csum = 0; 2389 else 2390 ctl_csum = 0; 2391 2392 if ((sc->re_caps & RE_C_AUTOPAD) == 0) { 2393 /* 2394 * With some of the RealTek chips, using the checksum offload 2395 * support in conjunction with the autopadding feature results 2396 * in the transmission of corrupt frames. For example, if we 2397 * need to send a really small IP fragment that's less than 60 2398 * bytes in size, and IP header checksumming is enabled, the 2399 * resulting ethernet frame that appears on the wire will 2400 * have garbled payload. To work around this, if TX checksum 2401 * offload is enabled, we always manually pad short frames out 2402 * to the minimum ethernet frame size. 2403 * 2404 * Note: this appears unnecessary for TCP, and doing it for TCP 2405 * with PCIe adapters seems to result in bad checksums. 2406 */ 2407 if ((m->m_pkthdr.csum_flags & 2408 (CSUM_DELAY_IP | CSUM_DELAY_DATA)) && 2409 (m->m_pkthdr.csum_flags & CSUM_TCP) == 0 && 2410 m->m_pkthdr.len < RE_MIN_FRAMELEN) { 2411 error = m_devpad(m, RE_MIN_FRAMELEN); 2412 if (error) 2413 goto back; 2414 } 2415 } 2416 2417 vlantag = 0; 2418 if (m->m_flags & M_VLANTAG) { 2419 vlantag = htobe16(m->m_pkthdr.ether_vlantag) | 2420 RE_TDESC_CTL_INSTAG; 2421 } 2422 2423 maxsegs = sc->re_ldata.re_tx_free; 2424 if (maxsegs > RE_MAXSEGS) 2425 maxsegs = RE_MAXSEGS; 2426 2427 error = bus_dmamap_load_mbuf_defrag(sc->re_ldata.re_tx_mtag, map, 2428 m_head, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 2429 if (error) 2430 goto back; 2431 2432 m = *m_head; 2433 bus_dmamap_sync(sc->re_ldata.re_tx_mtag, map, BUS_DMASYNC_PREWRITE); 2434 2435 /* 2436 * Map the segment array into descriptors. We also keep track 2437 * of the end of the ring and set the end-of-ring bits as needed, 2438 * and we set the ownership bits in all except the very first 2439 * descriptor, whose ownership bits will be turned on later. 2440 */ 2441 tx_ring = sc->re_ldata.re_tx_list; 2442 idx = *idx0; 2443 i = 0; 2444 for (;;) { 2445 uint32_t cmdstat; 2446 2447 d = &tx_ring[idx]; 2448 2449 cmdstat = segs[i].ds_len; 2450 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr)); 2451 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr)); 2452 if (i == 0) 2453 cmdstat |= RE_TDESC_CMD_SOF; 2454 else 2455 cmdstat |= RE_TDESC_CMD_OWN; 2456 if (idx == (sc->re_tx_desc_cnt - 1)) 2457 cmdstat |= RE_TDESC_CMD_EOR; 2458 d->re_cmdstat = htole32(cmdstat | cmd_csum); 2459 d->re_control = htole32(ctl_csum | vlantag); 2460 2461 i++; 2462 if (i == nsegs) 2463 break; 2464 RE_TXDESC_INC(sc, idx); 2465 } 2466 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF); 2467 2468 /* Transfer ownership of packet to the chip. */ 2469 d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN); 2470 if (*idx0 != idx) 2471 tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN); 2472 2473 /* 2474 * Insure that the map for this transmission 2475 * is placed at the array index of the last descriptor 2476 * in this chain. 2477 */ 2478 sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx]; 2479 sc->re_ldata.re_tx_dmamap[idx] = map; 2480 2481 sc->re_ldata.re_tx_mbuf[idx] = m; 2482 sc->re_ldata.re_tx_free -= nsegs; 2483 2484 RE_TXDESC_INC(sc, idx); 2485 *idx0 = idx; 2486 back: 2487 if (error) { 2488 m_freem(*m_head); 2489 *m_head = NULL; 2490 } 2491 return error; 2492 } 2493 2494 /* 2495 * Main transmit routine for C+ and gigE NICs. 2496 */ 2497 2498 static void 2499 re_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 2500 { 2501 struct re_softc *sc = ifp->if_softc; 2502 struct mbuf *m_head; 2503 int idx, need_trans, oactive, error; 2504 2505 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 2506 ASSERT_SERIALIZED(ifp->if_serializer); 2507 2508 if ((sc->re_flags & RE_F_LINKED) == 0) { 2509 ifq_purge(&ifp->if_snd); 2510 return; 2511 } 2512 2513 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 2514 return; 2515 2516 idx = sc->re_ldata.re_tx_prodidx; 2517 2518 need_trans = 0; 2519 oactive = 0; 2520 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) { 2521 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) { 2522 if (!oactive) { 2523 if (re_tx_collect(sc)) { 2524 oactive = 1; 2525 continue; 2526 } 2527 } 2528 ifq_set_oactive(&ifp->if_snd); 2529 break; 2530 } 2531 2532 m_head = ifq_dequeue(&ifp->if_snd); 2533 if (m_head == NULL) 2534 break; 2535 2536 error = re_encap(sc, &m_head, &idx); 2537 if (error) { 2538 /* m_head is freed by re_encap(), if we reach here */ 2539 IFNET_STAT_INC(ifp, oerrors, 1); 2540 2541 if (error == EFBIG && !oactive) { 2542 if (re_tx_collect(sc)) { 2543 oactive = 1; 2544 continue; 2545 } 2546 } 2547 ifq_set_oactive(&ifp->if_snd); 2548 break; 2549 } 2550 2551 oactive = 0; 2552 need_trans = 1; 2553 2554 /* 2555 * If there's a BPF listener, bounce a copy of this frame 2556 * to him. 2557 */ 2558 ETHER_BPF_MTAP(ifp, m_head); 2559 } 2560 2561 /* 2562 * If sc->re_ldata.re_tx_mbuf[idx] is not NULL it is possible 2563 * for OACTIVE to not be properly set when we also do not 2564 * have sufficient free tx descriptors, leaving packet in 2565 * ifp->if_snd. This can cause if_start_dispatch() to loop 2566 * infinitely so make sure OACTIVE is set properly. 2567 */ 2568 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) { 2569 if (!ifq_is_oactive(&ifp->if_snd)) { 2570 #if 0 2571 if_printf(ifp, "Debug: OACTIVE was not set when " 2572 "re_tx_free was below minimum!\n"); 2573 #endif 2574 ifq_set_oactive(&ifp->if_snd); 2575 } 2576 } 2577 if (!need_trans) 2578 return; 2579 2580 sc->re_ldata.re_tx_prodidx = idx; 2581 2582 /* 2583 * RealTek put the TX poll request register in a different 2584 * location on the 8169 gigE chip. I don't know why. 2585 */ 2586 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2587 2588 /* 2589 * Set a timeout in case the chip goes out to lunch. 2590 */ 2591 ifp->if_timer = 5; 2592 } 2593 2594 static void 2595 re_init(void *xsc) 2596 { 2597 struct re_softc *sc = xsc; 2598 struct ifnet *ifp = &sc->arpcom.ac_if; 2599 struct mii_data *mii; 2600 int error, framelen; 2601 2602 ASSERT_SERIALIZED(ifp->if_serializer); 2603 2604 mii = device_get_softc(sc->re_miibus); 2605 2606 /* 2607 * Cancel pending I/O and free all RX/TX buffers. 2608 */ 2609 re_stop(sc); 2610 2611 if (sc->re_caps & RE_C_CONTIGRX) { 2612 if (ifp->if_mtu > ETHERMTU) { 2613 KKASSERT(sc->re_ldata.re_jbuf != NULL); 2614 sc->re_flags |= RE_F_USE_JPOOL; 2615 sc->re_rxbuf_size = RE_FRAMELEN_MAX; 2616 sc->re_newbuf = re_newbuf_jumbo; 2617 } else { 2618 sc->re_flags &= ~RE_F_USE_JPOOL; 2619 sc->re_rxbuf_size = MCLBYTES; 2620 sc->re_newbuf = re_newbuf_std; 2621 } 2622 } 2623 2624 /* 2625 * Adjust max read request size according to MTU; mainly to 2626 * improve TX performance for common case (ETHERMTU) on GigE 2627 * NICs. However, this could _not_ be done on 10/100 only 2628 * NICs; their DMA engines will malfunction using non-default 2629 * max read request size. 2630 */ 2631 if ((sc->re_caps & (RE_C_PCIE | RE_C_FASTE)) == RE_C_PCIE) { 2632 if (ifp->if_mtu > ETHERMTU) { 2633 /* 2634 * 512 seems to be the only value that works 2635 * reliably with jumbo frame 2636 */ 2637 pcie_set_max_readrq(sc->re_dev, 2638 PCIEM_DEVCTL_MAX_READRQ_512); 2639 } else { 2640 pcie_set_max_readrq(sc->re_dev, 2641 PCIEM_DEVCTL_MAX_READRQ_4096); 2642 } 2643 } 2644 2645 /* 2646 * Enable C+ RX and TX mode, as well as VLAN stripping and 2647 * RX checksum offload. We must configure the C+ register 2648 * before all others. 2649 */ 2650 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB | 2651 RE_CPLUSCMD_PCI_MRW | 2652 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 2653 RE_CPLUSCMD_VLANSTRIP : 0) | 2654 (ifp->if_capenable & IFCAP_RXCSUM ? 2655 RE_CPLUSCMD_RXCSUM_ENB : 0)); 2656 2657 /* 2658 * Init our MAC address. Even though the chipset 2659 * documentation doesn't mention it, we need to enter "Config 2660 * register write enable" mode to modify the ID registers. 2661 */ 2662 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG); 2663 CSR_WRITE_4(sc, RE_IDR0, 2664 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0]))); 2665 CSR_WRITE_2(sc, RE_IDR4, 2666 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4]))); 2667 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 2668 2669 /* 2670 * For C+ mode, initialize the RX descriptors and mbufs. 2671 */ 2672 error = re_rx_list_init(sc); 2673 if (error) { 2674 re_stop(sc); 2675 return; 2676 } 2677 error = re_tx_list_init(sc); 2678 if (error) { 2679 re_stop(sc); 2680 return; 2681 } 2682 2683 /* 2684 * Load the addresses of the RX and TX lists into the chip. 2685 */ 2686 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI, 2687 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr)); 2688 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO, 2689 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr)); 2690 2691 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI, 2692 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr)); 2693 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO, 2694 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr)); 2695 2696 /* 2697 * Enable transmit and receive. 2698 */ 2699 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2700 2701 /* 2702 * Set the initial TX and RX configuration. 2703 */ 2704 if (sc->re_flags & RE_F_TESTMODE) { 2705 if (!RE_IS_8139CP(sc)) 2706 CSR_WRITE_4(sc, RE_TXCFG, 2707 RE_TXCFG_CONFIG | RE_LOOPTEST_ON); 2708 else 2709 CSR_WRITE_4(sc, RE_TXCFG, 2710 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS); 2711 } else 2712 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG); 2713 2714 framelen = RE_FRAMELEN(ifp->if_mtu); 2715 if (framelen < MCLBYTES) 2716 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(MCLBYTES, 128)); 2717 else 2718 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128)); 2719 2720 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG); 2721 2722 /* 2723 * Program the multicast filter, if necessary. 2724 */ 2725 re_setmulti(sc); 2726 2727 #ifdef IFPOLL_ENABLE 2728 /* 2729 * Disable interrupts if we are polling. 2730 */ 2731 if (ifp->if_flags & IFF_NPOLLING) 2732 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 2733 else /* otherwise ... */ 2734 #endif /* IFPOLL_ENABLE */ 2735 /* 2736 * Enable interrupts. 2737 */ 2738 if (sc->re_flags & RE_F_TESTMODE) 2739 CSR_WRITE_2(sc, RE_IMR, 0); 2740 else 2741 re_setup_intr(sc, 1, sc->re_imtype); 2742 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs); 2743 2744 /* Start RX/TX process. */ 2745 CSR_WRITE_4(sc, RE_MISSEDPKT, 0); 2746 2747 #ifdef notdef 2748 /* Enable receiver and transmitter. */ 2749 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2750 #endif 2751 2752 /* 2753 * For 8169 gigE NICs, set the max allowed RX packet 2754 * size so we can receive jumbo frames. 2755 */ 2756 if (!RE_IS_8139CP(sc)) { 2757 if (sc->re_caps & RE_C_CONTIGRX) 2758 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, sc->re_rxbuf_size); 2759 else 2760 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383); 2761 } 2762 2763 if (sc->re_flags & RE_F_TESTMODE) 2764 return; 2765 2766 mii_mediachg(mii); 2767 2768 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX); 2769 2770 ifp->if_flags |= IFF_RUNNING; 2771 ifq_clr_oactive(&ifp->if_snd); 2772 2773 callout_reset(&sc->re_timer, hz, re_tick, sc); 2774 } 2775 2776 /* 2777 * Set media options. 2778 */ 2779 static int 2780 re_ifmedia_upd(struct ifnet *ifp) 2781 { 2782 struct re_softc *sc = ifp->if_softc; 2783 struct mii_data *mii; 2784 2785 ASSERT_SERIALIZED(ifp->if_serializer); 2786 2787 mii = device_get_softc(sc->re_miibus); 2788 mii_mediachg(mii); 2789 2790 return(0); 2791 } 2792 2793 /* 2794 * Report current media status. 2795 */ 2796 static void 2797 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2798 { 2799 struct re_softc *sc = ifp->if_softc; 2800 struct mii_data *mii; 2801 2802 ASSERT_SERIALIZED(ifp->if_serializer); 2803 2804 mii = device_get_softc(sc->re_miibus); 2805 2806 mii_pollstat(mii); 2807 ifmr->ifm_active = mii->mii_media_active; 2808 ifmr->ifm_status = mii->mii_media_status; 2809 } 2810 2811 static int 2812 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2813 { 2814 struct re_softc *sc = ifp->if_softc; 2815 struct ifreq *ifr = (struct ifreq *) data; 2816 struct mii_data *mii; 2817 int error = 0, mask; 2818 2819 ASSERT_SERIALIZED(ifp->if_serializer); 2820 2821 switch(command) { 2822 case SIOCSIFMTU: 2823 if (ifr->ifr_mtu > sc->re_maxmtu) { 2824 error = EINVAL; 2825 } else if (ifp->if_mtu != ifr->ifr_mtu) { 2826 ifp->if_mtu = ifr->ifr_mtu; 2827 if (ifp->if_flags & IFF_RUNNING) 2828 ifp->if_init(sc); 2829 } 2830 break; 2831 2832 case SIOCSIFFLAGS: 2833 if (ifp->if_flags & IFF_UP) { 2834 if (ifp->if_flags & IFF_RUNNING) { 2835 if ((ifp->if_flags ^ sc->re_if_flags) & 2836 (IFF_PROMISC | IFF_ALLMULTI)) 2837 re_setmulti(sc); 2838 } else { 2839 re_init(sc); 2840 } 2841 } else if (ifp->if_flags & IFF_RUNNING) { 2842 re_stop(sc); 2843 } 2844 sc->re_if_flags = ifp->if_flags; 2845 break; 2846 2847 case SIOCADDMULTI: 2848 case SIOCDELMULTI: 2849 re_setmulti(sc); 2850 break; 2851 2852 case SIOCGIFMEDIA: 2853 case SIOCSIFMEDIA: 2854 mii = device_get_softc(sc->re_miibus); 2855 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2856 break; 2857 2858 case SIOCSIFCAP: 2859 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & 2860 ifp->if_capabilities; 2861 ifp->if_capenable ^= mask; 2862 2863 if (mask & IFCAP_HWCSUM) { 2864 if (ifp->if_capenable & IFCAP_TXCSUM) 2865 ifp->if_hwassist = sc->re_hwassist; 2866 else 2867 ifp->if_hwassist = 0; 2868 } 2869 if (mask && (ifp->if_flags & IFF_RUNNING)) 2870 re_init(sc); 2871 break; 2872 2873 default: 2874 error = ether_ioctl(ifp, command, data); 2875 break; 2876 } 2877 return(error); 2878 } 2879 2880 static void 2881 re_watchdog(struct ifnet *ifp) 2882 { 2883 struct re_softc *sc = ifp->if_softc; 2884 2885 ASSERT_SERIALIZED(ifp->if_serializer); 2886 2887 if_printf(ifp, "watchdog timeout\n"); 2888 2889 IFNET_STAT_INC(ifp, oerrors, 1); 2890 2891 re_txeof(sc); 2892 re_rxeof(sc); 2893 2894 re_init(sc); 2895 2896 if (!ifq_is_empty(&ifp->if_snd)) 2897 if_devstart(ifp); 2898 } 2899 2900 /* 2901 * Stop the adapter and free any mbufs allocated to the 2902 * RX and TX lists. 2903 */ 2904 static void 2905 re_stop(struct re_softc *sc) 2906 { 2907 struct ifnet *ifp = &sc->arpcom.ac_if; 2908 int i; 2909 2910 ASSERT_SERIALIZED(ifp->if_serializer); 2911 2912 /* Reset the adapter. */ 2913 re_reset(sc, ifp->if_flags & IFF_RUNNING); 2914 2915 ifp->if_timer = 0; 2916 callout_stop(&sc->re_timer); 2917 2918 ifp->if_flags &= ~IFF_RUNNING; 2919 ifq_clr_oactive(&ifp->if_snd); 2920 sc->re_flags &= ~(RE_F_TIMER_INTR | RE_F_DROP_RXFRAG | RE_F_LINKED); 2921 2922 CSR_WRITE_1(sc, RE_COMMAND, 0x00); 2923 CSR_WRITE_2(sc, RE_IMR, 0x0000); 2924 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 2925 2926 re_free_rxchain(sc); 2927 2928 /* Free the TX list buffers. */ 2929 for (i = 0; i < sc->re_tx_desc_cnt; i++) { 2930 if (sc->re_ldata.re_tx_mbuf[i] != NULL) { 2931 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, 2932 sc->re_ldata.re_tx_dmamap[i]); 2933 m_freem(sc->re_ldata.re_tx_mbuf[i]); 2934 sc->re_ldata.re_tx_mbuf[i] = NULL; 2935 } 2936 } 2937 2938 /* Free the RX list buffers. */ 2939 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 2940 if (sc->re_ldata.re_rx_mbuf[i] != NULL) { 2941 if ((sc->re_flags & RE_F_USE_JPOOL) == 0) { 2942 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 2943 sc->re_ldata.re_rx_dmamap[i]); 2944 } 2945 m_freem(sc->re_ldata.re_rx_mbuf[i]); 2946 sc->re_ldata.re_rx_mbuf[i] = NULL; 2947 } 2948 } 2949 } 2950 2951 /* 2952 * Device suspend routine. Stop the interface and save some PCI 2953 * settings in case the BIOS doesn't restore them properly on 2954 * resume. 2955 */ 2956 static int 2957 re_suspend(device_t dev) 2958 { 2959 #ifndef BURN_BRIDGES 2960 int i; 2961 #endif 2962 struct re_softc *sc = device_get_softc(dev); 2963 struct ifnet *ifp = &sc->arpcom.ac_if; 2964 2965 lwkt_serialize_enter(ifp->if_serializer); 2966 2967 re_stop(sc); 2968 2969 #ifndef BURN_BRIDGES 2970 for (i = 0; i < 5; i++) 2971 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2972 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2973 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2974 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2975 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2976 #endif 2977 2978 sc->re_flags |= RE_F_SUSPENDED; 2979 2980 lwkt_serialize_exit(ifp->if_serializer); 2981 2982 return (0); 2983 } 2984 2985 /* 2986 * Device resume routine. Restore some PCI settings in case the BIOS 2987 * doesn't, re-enable busmastering, and restart the interface if 2988 * appropriate. 2989 */ 2990 static int 2991 re_resume(device_t dev) 2992 { 2993 struct re_softc *sc = device_get_softc(dev); 2994 struct ifnet *ifp = &sc->arpcom.ac_if; 2995 #ifndef BURN_BRIDGES 2996 int i; 2997 #endif 2998 2999 lwkt_serialize_enter(ifp->if_serializer); 3000 3001 #ifndef BURN_BRIDGES 3002 /* better way to do this? */ 3003 for (i = 0; i < 5; i++) 3004 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3005 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3006 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3007 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3008 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3009 3010 /* reenable busmastering */ 3011 pci_enable_busmaster(dev); 3012 pci_enable_io(dev, SYS_RES_IOPORT); 3013 #endif 3014 3015 /* reinitialize interface if necessary */ 3016 if (ifp->if_flags & IFF_UP) 3017 re_init(sc); 3018 3019 sc->re_flags &= ~RE_F_SUSPENDED; 3020 3021 lwkt_serialize_exit(ifp->if_serializer); 3022 3023 return (0); 3024 } 3025 3026 /* 3027 * Stop all chip I/O so that the kernel's probe routines don't 3028 * get confused by errant DMAs when rebooting. 3029 */ 3030 static void 3031 re_shutdown(device_t dev) 3032 { 3033 struct re_softc *sc = device_get_softc(dev); 3034 struct ifnet *ifp = &sc->arpcom.ac_if; 3035 3036 lwkt_serialize_enter(ifp->if_serializer); 3037 re_stop(sc); 3038 lwkt_serialize_exit(ifp->if_serializer); 3039 } 3040 3041 static int 3042 re_sysctl_rxtime(SYSCTL_HANDLER_ARGS) 3043 { 3044 struct re_softc *sc = arg1; 3045 3046 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_rx_time); 3047 } 3048 3049 static int 3050 re_sysctl_txtime(SYSCTL_HANDLER_ARGS) 3051 { 3052 struct re_softc *sc = arg1; 3053 3054 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_tx_time); 3055 } 3056 3057 static int 3058 re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *hwtime) 3059 { 3060 struct re_softc *sc = arg1; 3061 struct ifnet *ifp = &sc->arpcom.ac_if; 3062 int error, v; 3063 3064 lwkt_serialize_enter(ifp->if_serializer); 3065 3066 v = *hwtime; 3067 error = sysctl_handle_int(oidp, &v, 0, req); 3068 if (error || req->newptr == NULL) 3069 goto back; 3070 3071 if (v <= 0) { 3072 error = EINVAL; 3073 goto back; 3074 } 3075 3076 if (v != *hwtime) { 3077 *hwtime = v; 3078 3079 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) == 3080 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_HW) 3081 re_setup_hw_im(sc); 3082 } 3083 back: 3084 lwkt_serialize_exit(ifp->if_serializer); 3085 return error; 3086 } 3087 3088 static int 3089 re_sysctl_simtime(SYSCTL_HANDLER_ARGS) 3090 { 3091 struct re_softc *sc = arg1; 3092 struct ifnet *ifp = &sc->arpcom.ac_if; 3093 int error, v; 3094 3095 lwkt_serialize_enter(ifp->if_serializer); 3096 3097 v = sc->re_sim_time; 3098 error = sysctl_handle_int(oidp, &v, 0, req); 3099 if (error || req->newptr == NULL) 3100 goto back; 3101 3102 if (v <= 0) { 3103 error = EINVAL; 3104 goto back; 3105 } 3106 3107 if (v != sc->re_sim_time) { 3108 sc->re_sim_time = v; 3109 3110 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) == 3111 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_SIM) { 3112 #ifdef foo 3113 int reg; 3114 3115 /* 3116 * Following code causes various strange 3117 * performance problems. Hmm ... 3118 */ 3119 CSR_WRITE_2(sc, RE_IMR, 0); 3120 if (!RE_IS_8139CP(sc)) 3121 reg = RE_TIMERINT_8169; 3122 else 3123 reg = RE_TIMERINT; 3124 CSR_WRITE_4(sc, reg, 0); 3125 CSR_READ_4(sc, reg); /* flush */ 3126 3127 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 3128 re_setup_sim_im(sc); 3129 #else 3130 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 3131 DELAY(10); 3132 re_setup_intr(sc, 1, RE_IMTYPE_SIM); 3133 #endif 3134 } 3135 } 3136 back: 3137 lwkt_serialize_exit(ifp->if_serializer); 3138 return error; 3139 } 3140 3141 static int 3142 re_sysctl_imtype(SYSCTL_HANDLER_ARGS) 3143 { 3144 struct re_softc *sc = arg1; 3145 struct ifnet *ifp = &sc->arpcom.ac_if; 3146 int error, v; 3147 3148 lwkt_serialize_enter(ifp->if_serializer); 3149 3150 v = sc->re_imtype; 3151 error = sysctl_handle_int(oidp, &v, 0, req); 3152 if (error || req->newptr == NULL) 3153 goto back; 3154 3155 if (v != RE_IMTYPE_HW && v != RE_IMTYPE_SIM && v != RE_IMTYPE_NONE) { 3156 error = EINVAL; 3157 goto back; 3158 } 3159 if (v == RE_IMTYPE_HW && (sc->re_caps & RE_C_HWIM) == 0) { 3160 /* Can't do hardware interrupt moderation */ 3161 error = EOPNOTSUPP; 3162 goto back; 3163 } 3164 3165 if (v != sc->re_imtype) { 3166 sc->re_imtype = v; 3167 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) == 3168 IFF_RUNNING) 3169 re_setup_intr(sc, 1, sc->re_imtype); 3170 } 3171 back: 3172 lwkt_serialize_exit(ifp->if_serializer); 3173 return error; 3174 } 3175 3176 static void 3177 re_setup_hw_im(struct re_softc *sc) 3178 { 3179 KKASSERT(sc->re_caps & RE_C_HWIM); 3180 3181 /* 3182 * Interrupt moderation 3183 * 3184 * 0xABCD 3185 * A - unknown (maybe TX related) 3186 * B - TX timer (unit: 25us) 3187 * C - unknown (maybe RX related) 3188 * D - RX timer (unit: 25us) 3189 * 3190 * 3191 * re(4)'s interrupt moderation is actually controlled by 3192 * two variables, like most other NICs (bge, bce etc.) 3193 * o timer 3194 * o number of packets [P] 3195 * 3196 * The logic relationship between these two variables is 3197 * similar to other NICs too: 3198 * if (timer expire || packets > [P]) 3199 * Interrupt is delivered 3200 * 3201 * Currently we only know how to set 'timer', but not 3202 * 'number of packets', which should be ~30, as far as I 3203 * tested (sink ~900Kpps, interrupt rate is 30KHz) 3204 */ 3205 CSR_WRITE_2(sc, RE_IM, 3206 RE_IM_RXTIME(sc->re_rx_time) | 3207 RE_IM_TXTIME(sc->re_tx_time) | 3208 RE_IM_MAGIC); 3209 } 3210 3211 static void 3212 re_disable_hw_im(struct re_softc *sc) 3213 { 3214 if (sc->re_caps & RE_C_HWIM) 3215 CSR_WRITE_2(sc, RE_IM, 0); 3216 } 3217 3218 static void 3219 re_setup_sim_im(struct re_softc *sc) 3220 { 3221 if (!RE_IS_8139CP(sc)) { 3222 uint32_t ticks; 3223 3224 /* 3225 * Datasheet says tick decreases at bus speed, 3226 * but it seems the clock runs a little bit 3227 * faster, so we do some compensation here. 3228 */ 3229 ticks = (sc->re_sim_time * sc->re_bus_speed * 8) / 5; 3230 CSR_WRITE_4(sc, RE_TIMERINT_8169, ticks); 3231 } else { 3232 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); /* XXX */ 3233 } 3234 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */ 3235 sc->re_flags |= RE_F_TIMER_INTR; 3236 } 3237 3238 static void 3239 re_disable_sim_im(struct re_softc *sc) 3240 { 3241 if (!RE_IS_8139CP(sc)) 3242 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0); 3243 else 3244 CSR_WRITE_4(sc, RE_TIMERINT, 0); 3245 sc->re_flags &= ~RE_F_TIMER_INTR; 3246 } 3247 3248 static void 3249 re_config_imtype(struct re_softc *sc, int imtype) 3250 { 3251 switch (imtype) { 3252 case RE_IMTYPE_HW: 3253 KKASSERT(sc->re_caps & RE_C_HWIM); 3254 /* FALL THROUGH */ 3255 case RE_IMTYPE_NONE: 3256 sc->re_intrs = RE_INTRS; 3257 sc->re_rx_ack = RE_ISR_RX_OK | RE_ISR_FIFO_OFLOW | 3258 RE_ISR_RX_OVERRUN; 3259 sc->re_tx_ack = RE_ISR_TX_OK; 3260 break; 3261 3262 case RE_IMTYPE_SIM: 3263 sc->re_intrs = RE_INTRS_TIMER; 3264 sc->re_rx_ack = RE_ISR_TIMEOUT_EXPIRED; 3265 sc->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED; 3266 break; 3267 3268 default: 3269 panic("%s: unknown imtype %d", 3270 sc->arpcom.ac_if.if_xname, imtype); 3271 } 3272 } 3273 3274 static void 3275 re_setup_intr(struct re_softc *sc, int enable_intrs, int imtype) 3276 { 3277 re_config_imtype(sc, imtype); 3278 3279 if (enable_intrs) 3280 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 3281 else 3282 CSR_WRITE_2(sc, RE_IMR, 0); 3283 3284 sc->re_npoll.ifpc_stcount = 0; 3285 3286 switch (imtype) { 3287 case RE_IMTYPE_NONE: 3288 re_disable_sim_im(sc); 3289 re_disable_hw_im(sc); 3290 break; 3291 3292 case RE_IMTYPE_HW: 3293 KKASSERT(sc->re_caps & RE_C_HWIM); 3294 re_disable_sim_im(sc); 3295 re_setup_hw_im(sc); 3296 break; 3297 3298 case RE_IMTYPE_SIM: 3299 re_disable_hw_im(sc); 3300 re_setup_sim_im(sc); 3301 break; 3302 3303 default: 3304 panic("%s: unknown imtype %d", 3305 sc->arpcom.ac_if.if_xname, imtype); 3306 } 3307 } 3308 3309 static void 3310 re_get_eaddr(struct re_softc *sc, uint8_t *eaddr) 3311 { 3312 int i; 3313 3314 if (sc->re_caps & RE_C_EE_EADDR) { 3315 uint16_t re_did; 3316 3317 re_get_eewidth(sc); 3318 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 3319 if (re_did == 0x8128) { 3320 uint16_t as[ETHER_ADDR_LEN / 2]; 3321 3322 /* 3323 * Get station address from the EEPROM. 3324 */ 3325 re_read_eeprom(sc, (caddr_t)as, sc->re_ee_eaddr, 3); 3326 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 3327 as[i] = le16toh(as[i]); 3328 bcopy(as, eaddr, ETHER_ADDR_LEN); 3329 return; 3330 } 3331 } 3332 3333 /* 3334 * Get station address from IDRx. 3335 */ 3336 for (i = 0; i < ETHER_ADDR_LEN; ++i) 3337 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i); 3338 } 3339 3340 static int 3341 re_jpool_alloc(struct re_softc *sc) 3342 { 3343 struct re_list_data *ldata = &sc->re_ldata; 3344 struct re_jbuf *jbuf; 3345 bus_addr_t paddr; 3346 bus_size_t jpool_size; 3347 bus_dmamem_t dmem; 3348 caddr_t buf; 3349 int i, error; 3350 3351 lwkt_serialize_init(&ldata->re_jbuf_serializer); 3352 3353 ldata->re_jbuf = kmalloc(sizeof(struct re_jbuf) * RE_JBUF_COUNT(sc), 3354 M_DEVBUF, M_WAITOK | M_ZERO); 3355 3356 jpool_size = RE_JBUF_COUNT(sc) * RE_JBUF_SIZE; 3357 3358 error = bus_dmamem_coherent(sc->re_parent_tag, 3359 RE_RXBUF_ALIGN, 0, 3360 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3361 jpool_size, BUS_DMA_WAITOK, &dmem); 3362 if (error) { 3363 device_printf(sc->re_dev, "could not allocate jumbo memory\n"); 3364 return error; 3365 } 3366 ldata->re_jpool_tag = dmem.dmem_tag; 3367 ldata->re_jpool_map = dmem.dmem_map; 3368 ldata->re_jpool = dmem.dmem_addr; 3369 paddr = dmem.dmem_busaddr; 3370 3371 /* ..and split it into 9KB chunks */ 3372 SLIST_INIT(&ldata->re_jbuf_free); 3373 3374 buf = ldata->re_jpool; 3375 for (i = 0; i < RE_JBUF_COUNT(sc); i++) { 3376 jbuf = &ldata->re_jbuf[i]; 3377 3378 jbuf->re_sc = sc; 3379 jbuf->re_inuse = 0; 3380 jbuf->re_slot = i; 3381 jbuf->re_buf = buf; 3382 jbuf->re_paddr = paddr; 3383 3384 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link); 3385 3386 buf += RE_JBUF_SIZE; 3387 paddr += RE_JBUF_SIZE; 3388 } 3389 return 0; 3390 } 3391 3392 static void 3393 re_jpool_free(struct re_softc *sc) 3394 { 3395 struct re_list_data *ldata = &sc->re_ldata; 3396 3397 if (ldata->re_jpool_tag != NULL) { 3398 bus_dmamap_unload(ldata->re_jpool_tag, ldata->re_jpool_map); 3399 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool, 3400 ldata->re_jpool_map); 3401 bus_dma_tag_destroy(ldata->re_jpool_tag); 3402 ldata->re_jpool_tag = NULL; 3403 } 3404 3405 if (ldata->re_jbuf != NULL) { 3406 kfree(ldata->re_jbuf, M_DEVBUF); 3407 ldata->re_jbuf = NULL; 3408 } 3409 } 3410 3411 static struct re_jbuf * 3412 re_jbuf_alloc(struct re_softc *sc) 3413 { 3414 struct re_list_data *ldata = &sc->re_ldata; 3415 struct re_jbuf *jbuf; 3416 3417 lwkt_serialize_enter(&ldata->re_jbuf_serializer); 3418 3419 jbuf = SLIST_FIRST(&ldata->re_jbuf_free); 3420 if (jbuf != NULL) { 3421 SLIST_REMOVE_HEAD(&ldata->re_jbuf_free, re_link); 3422 jbuf->re_inuse = 1; 3423 } 3424 3425 lwkt_serialize_exit(&ldata->re_jbuf_serializer); 3426 3427 return jbuf; 3428 } 3429 3430 static void 3431 re_jbuf_free(void *arg) 3432 { 3433 struct re_jbuf *jbuf = arg; 3434 struct re_softc *sc = jbuf->re_sc; 3435 struct re_list_data *ldata = &sc->re_ldata; 3436 3437 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) { 3438 panic("%s: free wrong jumbo buffer", 3439 sc->arpcom.ac_if.if_xname); 3440 } else if (jbuf->re_inuse == 0) { 3441 panic("%s: jumbo buffer already freed", 3442 sc->arpcom.ac_if.if_xname); 3443 } 3444 3445 lwkt_serialize_enter(&ldata->re_jbuf_serializer); 3446 atomic_subtract_int(&jbuf->re_inuse, 1); 3447 if (jbuf->re_inuse == 0) 3448 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link); 3449 lwkt_serialize_exit(&ldata->re_jbuf_serializer); 3450 } 3451 3452 static void 3453 re_jbuf_ref(void *arg) 3454 { 3455 struct re_jbuf *jbuf = arg; 3456 struct re_softc *sc = jbuf->re_sc; 3457 struct re_list_data *ldata = &sc->re_ldata; 3458 3459 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) { 3460 panic("%s: ref wrong jumbo buffer", 3461 sc->arpcom.ac_if.if_xname); 3462 } else if (jbuf->re_inuse == 0) { 3463 panic("%s: jumbo buffer already freed", 3464 sc->arpcom.ac_if.if_xname); 3465 } 3466 atomic_add_int(&jbuf->re_inuse, 1); 3467 } 3468 3469 static void 3470 re_disable_aspm(device_t dev) 3471 { 3472 uint16_t link_cap, link_ctrl; 3473 uint8_t pcie_ptr, reg; 3474 3475 pcie_ptr = pci_get_pciecap_ptr(dev); 3476 if (pcie_ptr == 0) 3477 return; 3478 3479 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2); 3480 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0) 3481 return; 3482 3483 if (bootverbose) 3484 device_printf(dev, "disable ASPM\n"); 3485 3486 reg = pcie_ptr + PCIER_LINKCTRL; 3487 link_ctrl = pci_read_config(dev, reg, 2); 3488 link_ctrl &= ~(PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1); 3489 pci_write_config(dev, reg, link_ctrl, 2); 3490 } 3491