1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $ 36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.61 2008/10/04 10:36:21 sephe Exp $ 37 */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul@windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 51 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7440, so the max MTU possible with this 111 * driver is 7422 bytes. 112 */ 113 114 #define _IP_VHL 115 116 #include "opt_polling.h" 117 118 #include <sys/param.h> 119 #include <sys/bus.h> 120 #include <sys/endian.h> 121 #include <sys/kernel.h> 122 #include <sys/in_cksum.h> 123 #include <sys/interrupt.h> 124 #include <sys/malloc.h> 125 #include <sys/mbuf.h> 126 #include <sys/rman.h> 127 #include <sys/serialize.h> 128 #include <sys/socket.h> 129 #include <sys/sockio.h> 130 #include <sys/sysctl.h> 131 132 #include <net/bpf.h> 133 #include <net/ethernet.h> 134 #include <net/if.h> 135 #include <net/ifq_var.h> 136 #include <net/if_arp.h> 137 #include <net/if_dl.h> 138 #include <net/if_media.h> 139 #include <net/if_types.h> 140 #include <net/vlan/if_vlan_var.h> 141 #include <net/vlan/if_vlan_ether.h> 142 143 #include <netinet/ip.h> 144 145 #include <dev/netif/mii_layer/mii.h> 146 #include <dev/netif/mii_layer/miivar.h> 147 148 #include <bus/pci/pcidevs.h> 149 #include <bus/pci/pcireg.h> 150 #include <bus/pci/pcivar.h> 151 152 /* "device miibus" required. See GENERIC if you get errors here. */ 153 #include "miibus_if.h" 154 155 #include <dev/netif/re/if_rereg.h> 156 #include <dev/netif/re/if_revar.h> 157 158 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 159 #if 0 160 #define RE_DISABLE_HWCSUM 161 #endif 162 163 /* 164 * Various supported device vendors/types and their names. 165 */ 166 static const struct re_type re_devs[] = { 167 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, RE_HWREV_8169S, 168 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 169 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, RE_HWREV_8139CPLUS, 170 "RealTek 8139C+ 10/100BaseTX" }, 171 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, RE_HWREV_8101E, 172 "RealTek 8101E PCIe 10/100baseTX" }, 173 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, RE_HWREV_8102EL, 174 "RealTek 8102EL PCIe 10/100baseTX" }, 175 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN1, 176 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 177 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN2, 178 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 179 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN3, 180 "RealTek 8168B/8111B PCIe Gigabit Ethernet" }, 181 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168C, 182 "RealTek 8168C/8111C PCIe Gigabit Ethernet" }, 183 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169, 184 "RealTek 8169 Gigabit Ethernet" }, 185 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169S, 186 "RealTek 8169S Single-chip Gigabit Ethernet" }, 187 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SB, 188 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" }, 189 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SC, 190 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 191 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, RE_HWREV_8169_8110SC, 192 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 193 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8110S, 194 "RealTek 8110S Single-chip Gigabit Ethernet" }, 195 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, RE_HWREV_8169S, 196 "Corega CG-LAPCIGT Gigabit Ethernet" }, 197 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, RE_HWREV_8169S, 198 "Linksys EG1032 Gigabit Ethernet" }, 199 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, RE_HWREV_8169S, 200 "US Robotics 997902 Gigabit Ethernet" }, 201 { 0, 0, 0, NULL } 202 }; 203 204 static const struct re_hwrev re_hwrevs[] = { 205 { RE_HWREV_8139CPLUS, RE_8139CPLUS, RE_F_HASMPC, 206 ETHERMTU, ETHERMTU }, 207 208 { RE_HWREV_8168_SPIN1, RE_8169, RE_F_PCIE, 209 RE_JUMBO_MTU, RE_JUMBO_MTU }, 210 211 { RE_HWREV_8168_SPIN2, RE_8169, RE_F_PCIE, 212 RE_JUMBO_MTU, RE_JUMBO_MTU }, 213 214 { RE_HWREV_8168_SPIN3, RE_8169, RE_F_PCIE, 215 RE_JUMBO_MTU, RE_JUMBO_MTU }, 216 217 { RE_HWREV_8168C, RE_8169, RE_F_PCIE, 218 RE_JUMBO_MTU, RE_JUMBO_MTU }, 219 220 { RE_HWREV_8169, RE_8169, RE_F_HASMPC, 221 RE_SWCSUM_LIM_8169, RE_JUMBO_MTU }, 222 223 { RE_HWREV_8169S, RE_8169, RE_F_HASMPC, 224 RE_JUMBO_MTU, RE_JUMBO_MTU }, 225 226 { RE_HWREV_8110S, RE_8169, RE_F_HASMPC, 227 RE_JUMBO_MTU, RE_JUMBO_MTU }, 228 229 { RE_HWREV_8169_8110SB, RE_8169, RE_F_HASMPC, 230 RE_JUMBO_MTU, RE_JUMBO_MTU }, 231 232 { RE_HWREV_8169_8110SC, RE_8169, 0, 233 RE_JUMBO_MTU, RE_JUMBO_MTU }, 234 235 { RE_HWREV_8100E, RE_8169, RE_F_HASMPC, 236 ETHERMTU, ETHERMTU }, 237 238 { RE_HWREV_8101E, RE_8169, RE_F_PCIE, 239 ETHERMTU, ETHERMTU }, 240 241 { RE_HWREV_8102EL, RE_8169, RE_F_PCIE, 242 ETHERMTU, ETHERMTU }, 243 244 { 0, 0, 0, 0, 0 } 245 }; 246 247 static int re_probe(device_t); 248 static int re_attach(device_t); 249 static int re_detach(device_t); 250 static int re_suspend(device_t); 251 static int re_resume(device_t); 252 static void re_shutdown(device_t); 253 254 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int); 255 static void re_dma_map_desc(void *, bus_dma_segment_t *, int, 256 bus_size_t, int); 257 static int re_allocmem(device_t); 258 static void re_freemem(device_t); 259 static void re_freebufmem(struct re_softc *, int, int); 260 static int re_encap(struct re_softc *, struct mbuf **, int *); 261 static int re_newbuf(struct re_softc *, int, int); 262 static void re_setup_rxdesc(struct re_softc *, int); 263 static int re_rx_list_init(struct re_softc *); 264 static int re_tx_list_init(struct re_softc *); 265 static void re_rxeof(struct re_softc *); 266 static void re_txeof(struct re_softc *); 267 static void re_intr(void *); 268 static void re_tick(void *); 269 static void re_tick_serialized(void *); 270 271 static void re_start(struct ifnet *); 272 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 273 static void re_init(void *); 274 static void re_stop(struct re_softc *); 275 static void re_watchdog(struct ifnet *); 276 static int re_ifmedia_upd(struct ifnet *); 277 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 278 279 static void re_eeprom_putbyte(struct re_softc *, int); 280 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *); 281 static void re_read_eeprom(struct re_softc *, caddr_t, int, int); 282 static int re_gmii_readreg(device_t, int, int); 283 static int re_gmii_writereg(device_t, int, int, int); 284 285 static int re_miibus_readreg(device_t, int, int); 286 static int re_miibus_writereg(device_t, int, int, int); 287 static void re_miibus_statchg(device_t); 288 289 static void re_setmulti(struct re_softc *); 290 static void re_reset(struct re_softc *); 291 static int re_pad_frame(struct mbuf *); 292 293 #ifdef RE_DIAG 294 static int re_diag(struct re_softc *); 295 #endif 296 297 #ifdef DEVICE_POLLING 298 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 299 #endif 300 301 static int re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS); 302 303 static device_method_t re_methods[] = { 304 /* Device interface */ 305 DEVMETHOD(device_probe, re_probe), 306 DEVMETHOD(device_attach, re_attach), 307 DEVMETHOD(device_detach, re_detach), 308 DEVMETHOD(device_suspend, re_suspend), 309 DEVMETHOD(device_resume, re_resume), 310 DEVMETHOD(device_shutdown, re_shutdown), 311 312 /* bus interface */ 313 DEVMETHOD(bus_print_child, bus_generic_print_child), 314 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 315 316 /* MII interface */ 317 DEVMETHOD(miibus_readreg, re_miibus_readreg), 318 DEVMETHOD(miibus_writereg, re_miibus_writereg), 319 DEVMETHOD(miibus_statchg, re_miibus_statchg), 320 321 { 0, 0 } 322 }; 323 324 static driver_t re_driver = { 325 "re", 326 re_methods, 327 sizeof(struct re_softc) 328 }; 329 330 static devclass_t re_devclass; 331 332 DECLARE_DUMMY_MODULE(if_re); 333 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0); 334 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0); 335 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 336 337 #define EE_SET(x) \ 338 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x)) 339 340 #define EE_CLR(x) \ 341 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x)) 342 343 static __inline void 344 re_free_rxchain(struct re_softc *sc) 345 { 346 if (sc->re_head != NULL) { 347 m_freem(sc->re_head); 348 sc->re_head = sc->re_tail = NULL; 349 } 350 } 351 352 /* 353 * Send a read command and address to the EEPROM, check for ACK. 354 */ 355 static void 356 re_eeprom_putbyte(struct re_softc *sc, int addr) 357 { 358 int d, i; 359 360 d = addr | (RE_9346_READ << sc->re_eewidth); 361 362 /* 363 * Feed in each bit and strobe the clock. 364 */ 365 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) { 366 if (d & i) 367 EE_SET(RE_EE_DATAIN); 368 else 369 EE_CLR(RE_EE_DATAIN); 370 DELAY(100); 371 EE_SET(RE_EE_CLK); 372 DELAY(150); 373 EE_CLR(RE_EE_CLK); 374 DELAY(100); 375 } 376 } 377 378 /* 379 * Read a word of data stored in the EEPROM at address 'addr.' 380 */ 381 static void 382 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest) 383 { 384 int i; 385 uint16_t word = 0; 386 387 /* 388 * Send address of word we want to read. 389 */ 390 re_eeprom_putbyte(sc, addr); 391 392 /* 393 * Start reading bits from EEPROM. 394 */ 395 for (i = 0x8000; i != 0; i >>= 1) { 396 EE_SET(RE_EE_CLK); 397 DELAY(100); 398 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT) 399 word |= i; 400 EE_CLR(RE_EE_CLK); 401 DELAY(100); 402 } 403 404 *dest = word; 405 } 406 407 /* 408 * Read a sequence of words from the EEPROM. 409 */ 410 static void 411 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt) 412 { 413 int i; 414 uint16_t word = 0, *ptr; 415 416 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 417 DELAY(100); 418 419 for (i = 0; i < cnt; i++) { 420 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL); 421 re_eeprom_getword(sc, off + i, &word); 422 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL); 423 ptr = (uint16_t *)(dest + (i * 2)); 424 *ptr = word; 425 } 426 427 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 428 } 429 430 static int 431 re_gmii_readreg(device_t dev, int phy, int reg) 432 { 433 struct re_softc *sc = device_get_softc(dev); 434 u_int32_t rval; 435 int i; 436 437 if (phy != 1) 438 return(0); 439 440 /* Let the rgephy driver read the GMEDIASTAT register */ 441 442 if (reg == RE_GMEDIASTAT) 443 return(CSR_READ_1(sc, RE_GMEDIASTAT)); 444 445 CSR_WRITE_4(sc, RE_PHYAR, reg << 16); 446 DELAY(1000); 447 448 for (i = 0; i < RE_TIMEOUT; i++) { 449 rval = CSR_READ_4(sc, RE_PHYAR); 450 if (rval & RE_PHYAR_BUSY) 451 break; 452 DELAY(100); 453 } 454 455 if (i == RE_TIMEOUT) { 456 device_printf(dev, "PHY read failed\n"); 457 return(0); 458 } 459 460 return(rval & RE_PHYAR_PHYDATA); 461 } 462 463 static int 464 re_gmii_writereg(device_t dev, int phy, int reg, int data) 465 { 466 struct re_softc *sc = device_get_softc(dev); 467 uint32_t rval; 468 int i; 469 470 CSR_WRITE_4(sc, RE_PHYAR, 471 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY); 472 DELAY(1000); 473 474 for (i = 0; i < RE_TIMEOUT; i++) { 475 rval = CSR_READ_4(sc, RE_PHYAR); 476 if ((rval & RE_PHYAR_BUSY) == 0) 477 break; 478 DELAY(100); 479 } 480 481 if (i == RE_TIMEOUT) 482 device_printf(dev, "PHY write failed\n"); 483 484 return(0); 485 } 486 487 static int 488 re_miibus_readreg(device_t dev, int phy, int reg) 489 { 490 struct re_softc *sc = device_get_softc(dev); 491 uint16_t rval = 0; 492 uint16_t re8139_reg = 0; 493 494 if (sc->re_type == RE_8169) { 495 rval = re_gmii_readreg(dev, phy, reg); 496 return(rval); 497 } 498 499 /* Pretend the internal PHY is only at address 0 */ 500 if (phy) 501 return(0); 502 503 switch(reg) { 504 case MII_BMCR: 505 re8139_reg = RE_BMCR; 506 break; 507 case MII_BMSR: 508 re8139_reg = RE_BMSR; 509 break; 510 case MII_ANAR: 511 re8139_reg = RE_ANAR; 512 break; 513 case MII_ANER: 514 re8139_reg = RE_ANER; 515 break; 516 case MII_ANLPAR: 517 re8139_reg = RE_LPAR; 518 break; 519 case MII_PHYIDR1: 520 case MII_PHYIDR2: 521 return(0); 522 /* 523 * Allow the rlphy driver to read the media status 524 * register. If we have a link partner which does not 525 * support NWAY, this is the register which will tell 526 * us the results of parallel detection. 527 */ 528 case RE_MEDIASTAT: 529 return(CSR_READ_1(sc, RE_MEDIASTAT)); 530 default: 531 device_printf(dev, "bad phy register\n"); 532 return(0); 533 } 534 rval = CSR_READ_2(sc, re8139_reg); 535 if (sc->re_type == RE_8139CPLUS && re8139_reg == RE_BMCR) { 536 /* 8139C+ has different bit layout. */ 537 rval &= ~(BMCR_LOOP | BMCR_ISO); 538 } 539 return(rval); 540 } 541 542 static int 543 re_miibus_writereg(device_t dev, int phy, int reg, int data) 544 { 545 struct re_softc *sc= device_get_softc(dev); 546 u_int16_t re8139_reg = 0; 547 548 if (sc->re_type == RE_8169) 549 return(re_gmii_writereg(dev, phy, reg, data)); 550 551 /* Pretend the internal PHY is only at address 0 */ 552 if (phy) 553 return(0); 554 555 switch(reg) { 556 case MII_BMCR: 557 re8139_reg = RE_BMCR; 558 if (sc->re_type == RE_8139CPLUS) { 559 /* 8139C+ has different bit layout. */ 560 data &= ~(BMCR_LOOP | BMCR_ISO); 561 } 562 break; 563 case MII_BMSR: 564 re8139_reg = RE_BMSR; 565 break; 566 case MII_ANAR: 567 re8139_reg = RE_ANAR; 568 break; 569 case MII_ANER: 570 re8139_reg = RE_ANER; 571 break; 572 case MII_ANLPAR: 573 re8139_reg = RE_LPAR; 574 break; 575 case MII_PHYIDR1: 576 case MII_PHYIDR2: 577 return(0); 578 default: 579 device_printf(dev, "bad phy register\n"); 580 return(0); 581 } 582 CSR_WRITE_2(sc, re8139_reg, data); 583 return(0); 584 } 585 586 static void 587 re_miibus_statchg(device_t dev) 588 { 589 } 590 591 /* 592 * Program the 64-bit multicast hash filter. 593 */ 594 static void 595 re_setmulti(struct re_softc *sc) 596 { 597 struct ifnet *ifp = &sc->arpcom.ac_if; 598 int h = 0; 599 uint32_t hashes[2] = { 0, 0 }; 600 struct ifmultiaddr *ifma; 601 uint32_t rxfilt; 602 int mcnt = 0; 603 604 rxfilt = CSR_READ_4(sc, RE_RXCFG); 605 606 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 607 rxfilt |= RE_RXCFG_RX_MULTI; 608 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 609 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF); 610 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF); 611 return; 612 } 613 614 /* first, zot all the existing hash bits */ 615 CSR_WRITE_4(sc, RE_MAR0, 0); 616 CSR_WRITE_4(sc, RE_MAR4, 0); 617 618 /* now program new ones */ 619 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 620 if (ifma->ifma_addr->sa_family != AF_LINK) 621 continue; 622 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 623 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 624 if (h < 32) 625 hashes[0] |= (1 << h); 626 else 627 hashes[1] |= (1 << (h - 32)); 628 mcnt++; 629 } 630 631 if (mcnt) 632 rxfilt |= RE_RXCFG_RX_MULTI; 633 else 634 rxfilt &= ~RE_RXCFG_RX_MULTI; 635 636 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 637 638 /* 639 * For some unfathomable reason, RealTek decided to reverse 640 * the order of the multicast hash registers in the PCI Express 641 * parts. This means we have to write the hash pattern in reverse 642 * order for those devices. 643 */ 644 if (sc->re_flags & RE_F_PCIE) { 645 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[0])); 646 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[1])); 647 } else { 648 CSR_WRITE_4(sc, RE_MAR0, hashes[0]); 649 CSR_WRITE_4(sc, RE_MAR4, hashes[1]); 650 } 651 } 652 653 static void 654 re_reset(struct re_softc *sc) 655 { 656 int i; 657 658 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET); 659 660 for (i = 0; i < RE_TIMEOUT; i++) { 661 DELAY(10); 662 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0) 663 break; 664 } 665 if (i == RE_TIMEOUT) 666 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 667 668 CSR_WRITE_1(sc, 0x82, 1); 669 } 670 671 #ifdef RE_DIAG 672 /* 673 * The following routine is designed to test for a defect on some 674 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 675 * lines connected to the bus, however for a 32-bit only card, they 676 * should be pulled high. The result of this defect is that the 677 * NIC will not work right if you plug it into a 64-bit slot: DMA 678 * operations will be done with 64-bit transfers, which will fail 679 * because the 64-bit data lines aren't connected. 680 * 681 * There's no way to work around this (short of talking a soldering 682 * iron to the board), however we can detect it. The method we use 683 * here is to put the NIC into digital loopback mode, set the receiver 684 * to promiscuous mode, and then try to send a frame. We then compare 685 * the frame data we sent to what was received. If the data matches, 686 * then the NIC is working correctly, otherwise we know the user has 687 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 688 * slot. In the latter case, there's no way the NIC can work correctly, 689 * so we print out a message on the console and abort the device attach. 690 */ 691 692 static int 693 re_diag(struct re_softc *sc) 694 { 695 struct ifnet *ifp = &sc->arpcom.ac_if; 696 struct mbuf *m0; 697 struct ether_header *eh; 698 struct re_desc *cur_rx; 699 uint16_t status; 700 uint32_t rxstat; 701 int total_len, i, error = 0, phyaddr; 702 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 703 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 704 705 /* Allocate a single mbuf */ 706 707 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 708 if (m0 == NULL) 709 return(ENOBUFS); 710 711 /* 712 * Initialize the NIC in test mode. This sets the chip up 713 * so that it can send and receive frames, but performs the 714 * following special functions: 715 * - Puts receiver in promiscuous mode 716 * - Enables digital loopback mode 717 * - Leaves interrupts turned off 718 */ 719 720 ifp->if_flags |= IFF_PROMISC; 721 sc->re_testmode = 1; 722 re_reset(sc); 723 re_init(sc); 724 sc->re_link = 1; 725 if (sc->re_type == RE_8169) 726 phyaddr = 1; 727 else 728 phyaddr = 0; 729 730 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET); 731 for (i = 0; i < RE_TIMEOUT; i++) { 732 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR); 733 if (!(status & BMCR_RESET)) 734 break; 735 } 736 737 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP); 738 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG); 739 740 DELAY(100000); 741 742 /* Put some data in the mbuf */ 743 744 eh = mtod(m0, struct ether_header *); 745 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN); 746 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN); 747 eh->ether_type = htons(ETHERTYPE_IP); 748 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 749 750 /* 751 * Queue the packet, start transmission. 752 * Note: ifq_handoff() ultimately calls re_start() for us. 753 */ 754 755 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 756 error = ifq_handoff(ifp, m0, NULL); 757 if (error) { 758 m0 = NULL; 759 goto done; 760 } 761 m0 = NULL; 762 763 /* Wait for it to propagate through the chip */ 764 765 DELAY(100000); 766 for (i = 0; i < RE_TIMEOUT; i++) { 767 status = CSR_READ_2(sc, RE_ISR); 768 CSR_WRITE_2(sc, RE_ISR, status); 769 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) == 770 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) 771 break; 772 DELAY(10); 773 } 774 775 if (i == RE_TIMEOUT) { 776 if_printf(ifp, "diagnostic failed to receive packet " 777 "in loopback mode\n"); 778 error = EIO; 779 goto done; 780 } 781 782 /* 783 * The packet should have been dumped into the first 784 * entry in the RX DMA ring. Grab it from there. 785 */ 786 787 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 788 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 789 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0], 790 BUS_DMASYNC_POSTWRITE); 791 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]); 792 793 m0 = sc->re_ldata.re_rx_mbuf[0]; 794 sc->re_ldata.re_rx_mbuf[0] = NULL; 795 eh = mtod(m0, struct ether_header *); 796 797 cur_rx = &sc->re_ldata.re_rx_list[0]; 798 total_len = RE_RXBYTES(cur_rx); 799 rxstat = le32toh(cur_rx->re_cmdstat); 800 801 if (total_len != ETHER_MIN_LEN) { 802 if_printf(ifp, "diagnostic failed, received short packet\n"); 803 error = EIO; 804 goto done; 805 } 806 807 /* Test that the received packet data matches what we sent. */ 808 809 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) || 810 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) || 811 be16toh(eh->ether_type) != ETHERTYPE_IP) { 812 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 813 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n", 814 dst, ":", src, ":", ETHERTYPE_IP); 815 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n", 816 eh->ether_dhost, ":", eh->ether_shost, ":", 817 ntohs(eh->ether_type)); 818 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 819 "into a 64-bit PCI slot.\n"); 820 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 821 "for proper operation.\n"); 822 if_printf(ifp, "Read the re(4) man page for more details.\n"); 823 error = EIO; 824 } 825 826 done: 827 /* Turn interface off, release resources */ 828 829 sc->re_testmode = 0; 830 sc->re_link = 0; 831 ifp->if_flags &= ~IFF_PROMISC; 832 re_stop(sc); 833 if (m0 != NULL) 834 m_freem(m0); 835 836 return (error); 837 } 838 #endif /* RE_DIAG */ 839 840 /* 841 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 842 * IDs against our list and return a device name if we find a match. 843 */ 844 static int 845 re_probe(device_t dev) 846 { 847 const struct re_type *t; 848 struct re_softc *sc; 849 int rid; 850 uint32_t hwrev; 851 uint16_t vendor, product; 852 853 vendor = pci_get_vendor(dev); 854 product = pci_get_device(dev); 855 856 /* 857 * Only attach to rev.3 of the Linksys EG1032 adapter. 858 * Rev.2 is supported by sk(4). 859 */ 860 if (vendor == PCI_VENDOR_LINKSYS && 861 product == PCI_PRODUCT_LINKSYS_EG1032 && 862 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3) 863 return ENXIO; 864 865 for (t = re_devs; t->re_name != NULL; t++) { 866 if (product == t->re_did && vendor == t->re_vid) 867 break; 868 } 869 870 /* 871 * Check if we found a RealTek device. 872 */ 873 if (t->re_name == NULL) 874 return(ENXIO); 875 876 /* 877 * Temporarily map the I/O space so we can read the chip ID register. 878 */ 879 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO); 880 rid = RE_PCI_LOIO; 881 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 882 RF_ACTIVE); 883 if (sc->re_res == NULL) { 884 device_printf(dev, "couldn't map ports/memory\n"); 885 kfree(sc, M_TEMP); 886 return(ENXIO); 887 } 888 889 sc->re_btag = rman_get_bustag(sc->re_res); 890 sc->re_bhandle = rman_get_bushandle(sc->re_res); 891 892 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV; 893 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res); 894 kfree(sc, M_TEMP); 895 896 /* 897 * and continue matching for the specific chip... 898 */ 899 for (; t->re_name != NULL; t++) { 900 if (product == t->re_did && vendor == t->re_vid && 901 t->re_basetype == hwrev) { 902 device_set_desc(dev, t->re_name); 903 return(0); 904 } 905 } 906 907 if (bootverbose) 908 kprintf("re: unknown hwrev %#x\n", hwrev); 909 return(ENXIO); 910 } 911 912 static void 913 re_dma_map_desc(void *xarg, bus_dma_segment_t *segs, int nsegs, 914 bus_size_t mapsize, int error) 915 { 916 struct re_dmaload_arg *arg = xarg; 917 int i; 918 919 if (error) 920 return; 921 922 if (nsegs > arg->re_nsegs) { 923 arg->re_nsegs = 0; 924 return; 925 } 926 927 arg->re_nsegs = nsegs; 928 for (i = 0; i < nsegs; ++i) 929 arg->re_segs[i] = segs[i]; 930 } 931 932 /* 933 * Map a single buffer address. 934 */ 935 936 static void 937 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 938 { 939 uint32_t *addr; 940 941 if (error) 942 return; 943 944 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 945 addr = arg; 946 *addr = segs->ds_addr; 947 } 948 949 static int 950 re_allocmem(device_t dev) 951 { 952 struct re_softc *sc = device_get_softc(dev); 953 int error, i; 954 955 /* 956 * Allocate the parent bus DMA tag appropriate for PCI. 957 */ 958 error = bus_dma_tag_create(NULL, /* parent */ 959 1, 0, /* alignment, boundary */ 960 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 961 BUS_SPACE_MAXADDR, /* highaddr */ 962 NULL, NULL, /* filter, filterarg */ 963 MAXBSIZE, RE_MAXSEGS, /* maxsize, nsegments */ 964 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 965 BUS_DMA_ALLOCNOW, /* flags */ 966 &sc->re_parent_tag); 967 if (error) { 968 device_printf(dev, "could not allocate parent dma tag\n"); 969 return error; 970 } 971 972 /* Allocate tag for TX descriptor list. */ 973 error = bus_dma_tag_create(sc->re_parent_tag, 974 RE_RING_ALIGN, 0, 975 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 976 NULL, NULL, 977 RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, 978 BUS_DMA_ALLOCNOW, 979 &sc->re_ldata.re_tx_list_tag); 980 if (error) { 981 device_printf(dev, "could not allocate TX ring dma tag\n"); 982 return(error); 983 } 984 985 /* Allocate DMA'able memory for the TX ring */ 986 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag, 987 (void **)&sc->re_ldata.re_tx_list, 988 BUS_DMA_WAITOK | BUS_DMA_ZERO, 989 &sc->re_ldata.re_tx_list_map); 990 if (error) { 991 device_printf(dev, "could not allocate TX ring\n"); 992 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 993 sc->re_ldata.re_tx_list_tag = NULL; 994 return(error); 995 } 996 997 /* Load the map for the TX ring. */ 998 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag, 999 sc->re_ldata.re_tx_list_map, 1000 sc->re_ldata.re_tx_list, RE_TX_LIST_SZ, 1001 re_dma_map_addr, &sc->re_ldata.re_tx_list_addr, 1002 BUS_DMA_NOWAIT); 1003 if (error) { 1004 device_printf(dev, "could not get address of TX ring\n"); 1005 bus_dmamem_free(sc->re_ldata.re_tx_list_tag, 1006 sc->re_ldata.re_tx_list, 1007 sc->re_ldata.re_tx_list_map); 1008 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1009 sc->re_ldata.re_tx_list_tag = NULL; 1010 return(error); 1011 } 1012 1013 /* Allocate tag for RX descriptor list. */ 1014 error = bus_dma_tag_create(sc->re_parent_tag, 1015 RE_RING_ALIGN, 0, 1016 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1017 NULL, NULL, 1018 RE_RX_LIST_SZ, 1, RE_RX_LIST_SZ, 1019 BUS_DMA_ALLOCNOW, 1020 &sc->re_ldata.re_rx_list_tag); 1021 if (error) { 1022 device_printf(dev, "could not allocate RX ring dma tag\n"); 1023 return(error); 1024 } 1025 1026 /* Allocate DMA'able memory for the RX ring */ 1027 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag, 1028 (void **)&sc->re_ldata.re_rx_list, 1029 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1030 &sc->re_ldata.re_rx_list_map); 1031 if (error) { 1032 device_printf(dev, "could not allocate RX ring\n"); 1033 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1034 sc->re_ldata.re_rx_list_tag = NULL; 1035 return(error); 1036 } 1037 1038 /* Load the map for the RX ring. */ 1039 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag, 1040 sc->re_ldata.re_rx_list_map, 1041 sc->re_ldata.re_rx_list, RE_RX_LIST_SZ, 1042 re_dma_map_addr, &sc->re_ldata.re_rx_list_addr, 1043 BUS_DMA_NOWAIT); 1044 if (error) { 1045 device_printf(dev, "could not get address of RX ring\n"); 1046 bus_dmamem_free(sc->re_ldata.re_rx_list_tag, 1047 sc->re_ldata.re_rx_list, 1048 sc->re_ldata.re_rx_list_map); 1049 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1050 sc->re_ldata.re_rx_list_tag = NULL; 1051 return(error); 1052 } 1053 1054 /* Allocate map for RX/TX mbufs. */ 1055 error = bus_dma_tag_create(sc->re_parent_tag, 1056 ETHER_ALIGN, 0, 1057 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1058 NULL, NULL, 1059 RE_JUMBO_FRAMELEN, RE_MAXSEGS, MCLBYTES, 1060 BUS_DMA_ALLOCNOW, 1061 &sc->re_ldata.re_mtag); 1062 if (error) { 1063 device_printf(dev, "could not allocate buf dma tag\n"); 1064 return(error); 1065 } 1066 1067 /* Create spare DMA map for RX */ 1068 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, 1069 &sc->re_ldata.re_rx_spare); 1070 if (error) { 1071 device_printf(dev, "can't create spare DMA map for RX\n"); 1072 bus_dma_tag_destroy(sc->re_ldata.re_mtag); 1073 sc->re_ldata.re_mtag = NULL; 1074 return error; 1075 } 1076 1077 /* Create DMA maps for TX buffers */ 1078 for (i = 0; i < RE_TX_DESC_CNT; i++) { 1079 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, 1080 &sc->re_ldata.re_tx_dmamap[i]); 1081 if (error) { 1082 device_printf(dev, "can't create DMA map for TX buf\n"); 1083 re_freebufmem(sc, i, 0); 1084 return(error); 1085 } 1086 } 1087 1088 /* Create DMA maps for RX buffers */ 1089 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1090 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, 1091 &sc->re_ldata.re_rx_dmamap[i]); 1092 if (error) { 1093 device_printf(dev, "can't create DMA map for RX buf\n"); 1094 re_freebufmem(sc, RE_TX_DESC_CNT, i); 1095 return(error); 1096 } 1097 } 1098 return(0); 1099 } 1100 1101 static void 1102 re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt) 1103 { 1104 int i; 1105 1106 /* Destroy all the RX and TX buffer maps */ 1107 if (sc->re_ldata.re_mtag) { 1108 for (i = 0; i < tx_cnt; i++) { 1109 bus_dmamap_destroy(sc->re_ldata.re_mtag, 1110 sc->re_ldata.re_tx_dmamap[i]); 1111 } 1112 for (i = 0; i < rx_cnt; i++) { 1113 bus_dmamap_destroy(sc->re_ldata.re_mtag, 1114 sc->re_ldata.re_rx_dmamap[i]); 1115 } 1116 bus_dmamap_destroy(sc->re_ldata.re_mtag, 1117 sc->re_ldata.re_rx_spare); 1118 bus_dma_tag_destroy(sc->re_ldata.re_mtag); 1119 } 1120 } 1121 1122 static void 1123 re_freemem(device_t dev) 1124 { 1125 struct re_softc *sc = device_get_softc(dev); 1126 1127 /* Unload and free the RX DMA ring memory and map */ 1128 if (sc->re_ldata.re_rx_list_tag) { 1129 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag, 1130 sc->re_ldata.re_rx_list_map); 1131 bus_dmamem_free(sc->re_ldata.re_rx_list_tag, 1132 sc->re_ldata.re_rx_list, 1133 sc->re_ldata.re_rx_list_map); 1134 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1135 } 1136 1137 /* Unload and free the TX DMA ring memory and map */ 1138 if (sc->re_ldata.re_tx_list_tag) { 1139 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag, 1140 sc->re_ldata.re_tx_list_map); 1141 bus_dmamem_free(sc->re_ldata.re_tx_list_tag, 1142 sc->re_ldata.re_tx_list, 1143 sc->re_ldata.re_tx_list_map); 1144 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1145 } 1146 1147 /* Free RX/TX buf DMA stuffs */ 1148 re_freebufmem(sc, RE_TX_DESC_CNT, RE_RX_DESC_CNT); 1149 1150 /* Unload and free the stats buffer and map */ 1151 if (sc->re_ldata.re_stag) { 1152 bus_dmamap_unload(sc->re_ldata.re_stag, 1153 sc->re_ldata.re_rx_list_map); 1154 bus_dmamem_free(sc->re_ldata.re_stag, 1155 sc->re_ldata.re_stats, 1156 sc->re_ldata.re_smap); 1157 bus_dma_tag_destroy(sc->re_ldata.re_stag); 1158 } 1159 1160 if (sc->re_parent_tag) 1161 bus_dma_tag_destroy(sc->re_parent_tag); 1162 } 1163 1164 /* 1165 * Attach the interface. Allocate softc structures, do ifmedia 1166 * setup and ethernet/BPF attach. 1167 */ 1168 static int 1169 re_attach(device_t dev) 1170 { 1171 struct re_softc *sc = device_get_softc(dev); 1172 struct ifnet *ifp; 1173 const struct re_hwrev *hw_rev; 1174 uint8_t eaddr[ETHER_ADDR_LEN]; 1175 uint16_t as[ETHER_ADDR_LEN / 2]; 1176 uint16_t re_did = 0; 1177 uint32_t hwrev; 1178 int error = 0, rid, i; 1179 1180 callout_init(&sc->re_timer); 1181 #ifdef RE_DIAG 1182 sc->re_dev = dev; 1183 #endif 1184 1185 RE_ENABLE_TX_MODERATION(sc); 1186 1187 sysctl_ctx_init(&sc->re_sysctl_ctx); 1188 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx, 1189 SYSCTL_STATIC_CHILDREN(_hw), 1190 OID_AUTO, 1191 device_get_nameunit(dev), 1192 CTLFLAG_RD, 0, ""); 1193 if (sc->re_sysctl_tree == NULL) { 1194 device_printf(dev, "can't add sysctl node\n"); 1195 error = ENXIO; 1196 goto fail; 1197 } 1198 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1199 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1200 OID_AUTO, "tx_moderation", 1201 CTLTYPE_INT | CTLFLAG_RW, 1202 sc, 0, re_sysctl_tx_moderation, "I", 1203 "Enable/Disable TX moderation"); 1204 1205 #ifndef BURN_BRIDGES 1206 /* 1207 * Handle power management nonsense. 1208 */ 1209 1210 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1211 uint32_t membase, irq; 1212 1213 /* Save important PCI config data. */ 1214 membase = pci_read_config(dev, RE_PCI_LOMEM, 4); 1215 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1216 1217 /* Reset the power state. */ 1218 device_printf(dev, "chip is in D%d power mode " 1219 "-- setting to D0\n", pci_get_powerstate(dev)); 1220 1221 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1222 1223 /* Restore PCI config data. */ 1224 pci_write_config(dev, RE_PCI_LOMEM, membase, 4); 1225 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1226 } 1227 #endif 1228 /* 1229 * Map control/status registers. 1230 */ 1231 pci_enable_busmaster(dev); 1232 1233 rid = RE_PCI_LOIO; 1234 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1235 RF_ACTIVE); 1236 1237 if (sc->re_res == NULL) { 1238 device_printf(dev, "couldn't map ports\n"); 1239 error = ENXIO; 1240 goto fail; 1241 } 1242 1243 sc->re_btag = rman_get_bustag(sc->re_res); 1244 sc->re_bhandle = rman_get_bushandle(sc->re_res); 1245 1246 /* Allocate interrupt */ 1247 rid = 0; 1248 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1249 RF_SHAREABLE | RF_ACTIVE); 1250 1251 if (sc->re_irq == NULL) { 1252 device_printf(dev, "couldn't map interrupt\n"); 1253 error = ENXIO; 1254 goto fail; 1255 } 1256 1257 /* Reset the adapter. */ 1258 re_reset(sc); 1259 1260 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV; 1261 for (hw_rev = re_hwrevs; hw_rev->re_type != 0; hw_rev++) { 1262 if (hw_rev->re_rev == hwrev) { 1263 sc->re_hwrev = hwrev; 1264 sc->re_type = hw_rev->re_type; 1265 sc->re_flags = hw_rev->re_flags; 1266 sc->re_swcsum_lim = hw_rev->re_swcsum_lim; 1267 sc->re_maxmtu = hw_rev->re_maxmtu; 1268 break; 1269 } 1270 } 1271 device_printf(dev, "hardware rev. 0x%08x\n", hwrev); 1272 1273 sc->re_eewidth = 6; 1274 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1275 if (re_did != 0x8129) 1276 sc->re_eewidth = 8; 1277 1278 /* 1279 * Get station address from the EEPROM. 1280 */ 1281 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3); 1282 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1283 as[i] = le16toh(as[i]); 1284 bcopy(as, eaddr, sizeof(eaddr)); 1285 1286 if (sc->re_type == RE_8169) { 1287 /* Set RX length mask */ 1288 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 1289 sc->re_txstart = RE_GTXSTART; 1290 } else { 1291 /* Set RX length mask */ 1292 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 1293 sc->re_txstart = RE_TXSTART; 1294 } 1295 1296 /* Allocate DMA stuffs */ 1297 error = re_allocmem(dev); 1298 if (error) 1299 goto fail; 1300 1301 /* Do MII setup */ 1302 if (mii_phy_probe(dev, &sc->re_miibus, 1303 re_ifmedia_upd, re_ifmedia_sts)) { 1304 device_printf(dev, "MII without any phy!\n"); 1305 error = ENXIO; 1306 goto fail; 1307 } 1308 1309 ifp = &sc->arpcom.ac_if; 1310 ifp->if_softc = sc; 1311 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1312 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1313 ifp->if_ioctl = re_ioctl; 1314 ifp->if_start = re_start; 1315 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1316 1317 switch (hwrev) { 1318 case RE_HWREV_8168C: 1319 case RE_HWREV_8102EL: 1320 /* 1321 * XXX Hardware checksum does not work yet on 8168C 1322 * and 8102EL. Disble it. 1323 */ 1324 ifp->if_capabilities &= ~IFCAP_HWCSUM; 1325 break; 1326 default: 1327 ifp->if_capabilities |= IFCAP_HWCSUM; 1328 break; 1329 } 1330 #ifdef DEVICE_POLLING 1331 ifp->if_poll = re_poll; 1332 #endif 1333 ifp->if_watchdog = re_watchdog; 1334 ifp->if_init = re_init; 1335 if (sc->re_type == RE_8169) 1336 ifp->if_baudrate = 1000000000; 1337 else 1338 ifp->if_baudrate = 100000000; 1339 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN); 1340 ifq_set_ready(&ifp->if_snd); 1341 1342 #ifdef RE_DISABLE_HWCSUM 1343 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1344 ifp->if_hwassist = 0; 1345 #else 1346 ifp->if_capenable = ifp->if_capabilities; 1347 if (ifp->if_capabilities & IFCAP_HWCSUM) 1348 ifp->if_hwassist = RE_CSUM_FEATURES; 1349 else 1350 ifp->if_hwassist = 0; 1351 #endif /* RE_DISABLE_HWCSUM */ 1352 1353 /* 1354 * Call MI attach routine. 1355 */ 1356 ether_ifattach(ifp, eaddr, NULL); 1357 1358 #ifdef RE_DIAG 1359 /* 1360 * Perform hardware diagnostic on the original RTL8169. 1361 * Some 32-bit cards were incorrectly wired and would 1362 * malfunction if plugged into a 64-bit slot. 1363 */ 1364 if (hwrev == RE_HWREV_8169) { 1365 lwkt_serialize_enter(ifp->if_serializer); 1366 error = re_diag(sc); 1367 lwkt_serialize_exit(ifp->if_serializer); 1368 1369 if (error) { 1370 device_printf(dev, "hardware diagnostic failure\n"); 1371 ether_ifdetach(ifp); 1372 goto fail; 1373 } 1374 } 1375 #endif /* RE_DIAG */ 1376 1377 /* Hook interrupt last to avoid having to lock softc */ 1378 error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc, 1379 &sc->re_intrhand, ifp->if_serializer); 1380 1381 if (error) { 1382 device_printf(dev, "couldn't set up irq\n"); 1383 ether_ifdetach(ifp); 1384 goto fail; 1385 } 1386 1387 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->re_irq)); 1388 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 1389 1390 fail: 1391 if (error) 1392 re_detach(dev); 1393 1394 return (error); 1395 } 1396 1397 /* 1398 * Shutdown hardware and free up resources. This can be called any 1399 * time after the mutex has been initialized. It is called in both 1400 * the error case in attach and the normal detach case so it needs 1401 * to be careful about only freeing resources that have actually been 1402 * allocated. 1403 */ 1404 static int 1405 re_detach(device_t dev) 1406 { 1407 struct re_softc *sc = device_get_softc(dev); 1408 struct ifnet *ifp = &sc->arpcom.ac_if; 1409 1410 /* These should only be active if attach succeeded */ 1411 if (device_is_attached(dev)) { 1412 lwkt_serialize_enter(ifp->if_serializer); 1413 re_stop(sc); 1414 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand); 1415 lwkt_serialize_exit(ifp->if_serializer); 1416 1417 ether_ifdetach(ifp); 1418 } 1419 if (sc->re_miibus) 1420 device_delete_child(dev, sc->re_miibus); 1421 bus_generic_detach(dev); 1422 1423 if (sc->re_sysctl_tree != NULL) 1424 sysctl_ctx_free(&sc->re_sysctl_ctx); 1425 1426 if (sc->re_irq) 1427 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq); 1428 if (sc->re_res) { 1429 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, 1430 sc->re_res); 1431 } 1432 1433 /* Free DMA stuffs */ 1434 re_freemem(dev); 1435 1436 return(0); 1437 } 1438 1439 static void 1440 re_setup_rxdesc(struct re_softc *sc, int idx) 1441 { 1442 bus_addr_t paddr; 1443 uint32_t cmdstat; 1444 struct re_desc *d; 1445 1446 paddr = sc->re_ldata.re_rx_paddr[idx]; 1447 d = &sc->re_ldata.re_rx_list[idx]; 1448 1449 d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr)); 1450 d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr)); 1451 1452 cmdstat = MCLBYTES | RE_RDESC_CMD_OWN; 1453 if (idx == (RE_RX_DESC_CNT - 1)) 1454 cmdstat |= RE_TDESC_CMD_EOR; 1455 d->re_cmdstat = htole32(cmdstat); 1456 } 1457 1458 static int 1459 re_newbuf(struct re_softc *sc, int idx, int init) 1460 { 1461 struct re_dmaload_arg arg; 1462 bus_dma_segment_t seg; 1463 bus_dmamap_t map; 1464 struct mbuf *m; 1465 int error; 1466 1467 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 1468 if (m == NULL) { 1469 error = ENOBUFS; 1470 1471 if (init) { 1472 if_printf(&sc->arpcom.ac_if, "m_getcl failed\n"); 1473 return error; 1474 } else { 1475 goto back; 1476 } 1477 } 1478 m->m_len = m->m_pkthdr.len = MCLBYTES; 1479 1480 /* 1481 * NOTE: 1482 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer 1483 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1484 */ 1485 1486 arg.re_nsegs = 1; 1487 arg.re_segs = &seg; 1488 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, 1489 sc->re_ldata.re_rx_spare, m, 1490 re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1491 if (error || arg.re_nsegs == 0) { 1492 if (!error) { 1493 if_printf(&sc->arpcom.ac_if, "too many segments?!\n"); 1494 bus_dmamap_unload(sc->re_ldata.re_mtag, 1495 sc->re_ldata.re_rx_spare); 1496 error = EFBIG; 1497 } 1498 m_freem(m); 1499 1500 if (init) { 1501 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 1502 return error; 1503 } else { 1504 goto back; 1505 } 1506 } 1507 1508 if (!init) { 1509 bus_dmamap_sync(sc->re_ldata.re_mtag, 1510 sc->re_ldata.re_rx_dmamap[idx], 1511 BUS_DMASYNC_POSTREAD); 1512 bus_dmamap_unload(sc->re_ldata.re_mtag, 1513 sc->re_ldata.re_rx_dmamap[idx]); 1514 } 1515 sc->re_ldata.re_rx_mbuf[idx] = m; 1516 sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr; 1517 1518 map = sc->re_ldata.re_rx_dmamap[idx]; 1519 sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare; 1520 sc->re_ldata.re_rx_spare = map; 1521 back: 1522 re_setup_rxdesc(sc, idx); 1523 return error; 1524 } 1525 1526 static int 1527 re_tx_list_init(struct re_softc *sc) 1528 { 1529 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ); 1530 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *)); 1531 1532 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1533 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE); 1534 sc->re_ldata.re_tx_prodidx = 0; 1535 sc->re_ldata.re_tx_considx = 0; 1536 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT; 1537 1538 return(0); 1539 } 1540 1541 static int 1542 re_rx_list_init(struct re_softc *sc) 1543 { 1544 int i, error; 1545 1546 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ); 1547 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *)); 1548 1549 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1550 error = re_newbuf(sc, i, 1); 1551 if (error) 1552 return(error); 1553 } 1554 1555 /* Flush the RX descriptors */ 1556 1557 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1558 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE); 1559 1560 sc->re_ldata.re_rx_prodidx = 0; 1561 sc->re_head = sc->re_tail = NULL; 1562 1563 return(0); 1564 } 1565 1566 /* 1567 * RX handler for C+ and 8169. For the gigE chips, we support 1568 * the reception of jumbo frames that have been fragmented 1569 * across multiple 2K mbuf cluster buffers. 1570 */ 1571 static void 1572 re_rxeof(struct re_softc *sc) 1573 { 1574 struct ifnet *ifp = &sc->arpcom.ac_if; 1575 struct mbuf *m; 1576 struct re_desc *cur_rx; 1577 uint32_t rxstat, rxvlan; 1578 int i, total_len; 1579 struct mbuf_chain chain[MAXCPU]; 1580 1581 /* Invalidate the descriptor memory */ 1582 1583 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1584 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 1585 1586 ether_input_chain_init(chain); 1587 1588 for (i = sc->re_ldata.re_rx_prodidx; 1589 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_DESC_INC(i)) { 1590 cur_rx = &sc->re_ldata.re_rx_list[i]; 1591 m = sc->re_ldata.re_rx_mbuf[i]; 1592 total_len = RE_RXBYTES(cur_rx); 1593 rxstat = le32toh(cur_rx->re_cmdstat); 1594 rxvlan = le32toh(cur_rx->re_vlanctl); 1595 1596 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1597 if (sc->re_drop_rxfrag) { 1598 re_setup_rxdesc(sc, i); 1599 continue; 1600 } 1601 1602 if (re_newbuf(sc, i, 0)) { 1603 /* Drop upcoming fragments */ 1604 sc->re_drop_rxfrag = 1; 1605 continue; 1606 } 1607 1608 m->m_len = MCLBYTES; 1609 if (sc->re_head == NULL) { 1610 sc->re_head = sc->re_tail = m; 1611 } else { 1612 sc->re_tail->m_next = m; 1613 sc->re_tail = m; 1614 } 1615 continue; 1616 } else if (sc->re_drop_rxfrag) { 1617 /* 1618 * Last fragment of a multi-fragment packet. 1619 * 1620 * Since error already happened, this fragment 1621 * must be dropped as well as the fragment chain. 1622 */ 1623 re_setup_rxdesc(sc, i); 1624 re_free_rxchain(sc); 1625 sc->re_drop_rxfrag = 0; 1626 continue; 1627 } 1628 1629 /* 1630 * NOTE: for the 8139C+, the frame length field 1631 * is always 12 bits in size, but for the gigE chips, 1632 * it is 13 bits (since the max RX frame length is 16K). 1633 * Unfortunately, all 32 bits in the status word 1634 * were already used, so to make room for the extra 1635 * length bit, RealTek took out the 'frame alignment 1636 * error' bit and shifted the other status bits 1637 * over one slot. The OWN, EOR, FS and LS bits are 1638 * still in the same places. We have already extracted 1639 * the frame length and checked the OWN bit, so rather 1640 * than using an alternate bit mapping, we shift the 1641 * status bits one space to the right so we can evaluate 1642 * them using the 8169 status as though it was in the 1643 * same format as that of the 8139C+. 1644 */ 1645 if (sc->re_type == RE_8169) 1646 rxstat >>= 1; 1647 1648 if (rxstat & RE_RDESC_STAT_RXERRSUM) { 1649 ifp->if_ierrors++; 1650 /* 1651 * If this is part of a multi-fragment packet, 1652 * discard all the pieces. 1653 */ 1654 re_free_rxchain(sc); 1655 re_setup_rxdesc(sc, i); 1656 continue; 1657 } 1658 1659 /* 1660 * If allocating a replacement mbuf fails, 1661 * reload the current one. 1662 */ 1663 1664 if (re_newbuf(sc, i, 0)) { 1665 ifp->if_ierrors++; 1666 re_free_rxchain(sc); 1667 continue; 1668 } 1669 1670 if (sc->re_head != NULL) { 1671 m->m_len = total_len % MCLBYTES; 1672 /* 1673 * Special case: if there's 4 bytes or less 1674 * in this buffer, the mbuf can be discarded: 1675 * the last 4 bytes is the CRC, which we don't 1676 * care about anyway. 1677 */ 1678 if (m->m_len <= ETHER_CRC_LEN) { 1679 sc->re_tail->m_len -= 1680 (ETHER_CRC_LEN - m->m_len); 1681 m_freem(m); 1682 } else { 1683 m->m_len -= ETHER_CRC_LEN; 1684 sc->re_tail->m_next = m; 1685 } 1686 m = sc->re_head; 1687 sc->re_head = sc->re_tail = NULL; 1688 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1689 } else { 1690 m->m_pkthdr.len = m->m_len = 1691 (total_len - ETHER_CRC_LEN); 1692 } 1693 1694 ifp->if_ipackets++; 1695 m->m_pkthdr.rcvif = ifp; 1696 1697 /* Do RX checksumming if enabled */ 1698 1699 if (ifp->if_capenable & IFCAP_RXCSUM) { 1700 /* Check IP header checksum */ 1701 if (rxstat & RE_RDESC_STAT_PROTOID) 1702 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1703 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0) 1704 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1705 1706 /* Check TCP/UDP checksum */ 1707 if ((RE_TCPPKT(rxstat) && 1708 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) || 1709 (RE_UDPPKT(rxstat) && 1710 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) { 1711 m->m_pkthdr.csum_flags |= 1712 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 1713 CSUM_FRAG_NOT_CHECKED; 1714 m->m_pkthdr.csum_data = 0xffff; 1715 } 1716 } 1717 1718 if (rxvlan & RE_RDESC_VLANCTL_TAG) { 1719 m->m_flags |= M_VLANTAG; 1720 m->m_pkthdr.ether_vlantag = 1721 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA)); 1722 } 1723 ether_input_chain(ifp, m, chain); 1724 } 1725 1726 ether_input_dispatch(chain); 1727 1728 /* Flush the RX DMA ring */ 1729 1730 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1731 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE); 1732 1733 sc->re_ldata.re_rx_prodidx = i; 1734 } 1735 1736 static void 1737 re_txeof(struct re_softc *sc) 1738 { 1739 struct ifnet *ifp = &sc->arpcom.ac_if; 1740 uint32_t txstat; 1741 int idx; 1742 1743 /* Invalidate the TX descriptor list */ 1744 1745 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1746 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_POSTREAD); 1747 1748 for (idx = sc->re_ldata.re_tx_considx; 1749 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT; RE_DESC_INC(idx)) { 1750 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat); 1751 if (txstat & RE_TDESC_CMD_OWN) 1752 break; 1753 1754 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0; 1755 1756 /* 1757 * We only stash mbufs in the last descriptor 1758 * in a fragment chain, which also happens to 1759 * be the only place where the TX status bits 1760 * are valid. 1761 */ 1762 if (txstat & RE_TDESC_CMD_EOF) { 1763 m_freem(sc->re_ldata.re_tx_mbuf[idx]); 1764 sc->re_ldata.re_tx_mbuf[idx] = NULL; 1765 bus_dmamap_unload(sc->re_ldata.re_mtag, 1766 sc->re_ldata.re_tx_dmamap[idx]); 1767 if (txstat & (RE_TDESC_STAT_EXCESSCOL| 1768 RE_TDESC_STAT_COLCNT)) 1769 ifp->if_collisions++; 1770 if (txstat & RE_TDESC_STAT_TXERRSUM) 1771 ifp->if_oerrors++; 1772 else 1773 ifp->if_opackets++; 1774 } 1775 sc->re_ldata.re_tx_free++; 1776 } 1777 sc->re_ldata.re_tx_considx = idx; 1778 1779 /* There is enough free TX descs */ 1780 if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE) 1781 ifp->if_flags &= ~IFF_OACTIVE; 1782 1783 /* 1784 * Some chips will ignore a second TX request issued while an 1785 * existing transmission is in progress. If the transmitter goes 1786 * idle but there are still packets waiting to be sent, we need 1787 * to restart the channel here to flush them out. This only seems 1788 * to be required with the PCIe devices. 1789 */ 1790 if (sc->re_ldata.re_tx_free < RE_TX_DESC_CNT) 1791 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 1792 else 1793 ifp->if_timer = 0; 1794 1795 /* 1796 * If not all descriptors have been released reaped yet, 1797 * reload the timer so that we will eventually get another 1798 * interrupt that will cause us to re-enter this routine. 1799 * This is done in case the transmitter has gone idle. 1800 */ 1801 if (RE_TX_MODERATION_IS_ENABLED(sc) && 1802 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT) 1803 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 1804 } 1805 1806 static void 1807 re_tick(void *xsc) 1808 { 1809 struct re_softc *sc = xsc; 1810 1811 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1812 re_tick_serialized(xsc); 1813 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1814 } 1815 1816 static void 1817 re_tick_serialized(void *xsc) 1818 { 1819 struct re_softc *sc = xsc; 1820 struct ifnet *ifp = &sc->arpcom.ac_if; 1821 struct mii_data *mii; 1822 1823 ASSERT_SERIALIZED(ifp->if_serializer); 1824 1825 mii = device_get_softc(sc->re_miibus); 1826 mii_tick(mii); 1827 if (sc->re_link) { 1828 if (!(mii->mii_media_status & IFM_ACTIVE)) 1829 sc->re_link = 0; 1830 } else { 1831 if (mii->mii_media_status & IFM_ACTIVE && 1832 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1833 sc->re_link = 1; 1834 if (!ifq_is_empty(&ifp->if_snd)) 1835 if_devstart(ifp); 1836 } 1837 } 1838 1839 callout_reset(&sc->re_timer, hz, re_tick, sc); 1840 } 1841 1842 #ifdef DEVICE_POLLING 1843 1844 static void 1845 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1846 { 1847 struct re_softc *sc = ifp->if_softc; 1848 1849 ASSERT_SERIALIZED(ifp->if_serializer); 1850 1851 switch(cmd) { 1852 case POLL_REGISTER: 1853 /* disable interrupts */ 1854 CSR_WRITE_2(sc, RE_IMR, 0x0000); 1855 break; 1856 case POLL_DEREGISTER: 1857 /* enable interrupts */ 1858 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 1859 break; 1860 default: 1861 sc->rxcycles = count; 1862 re_rxeof(sc); 1863 re_txeof(sc); 1864 1865 if (!ifq_is_empty(&ifp->if_snd)) 1866 if_devstart(ifp); 1867 1868 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1869 uint16_t status; 1870 1871 status = CSR_READ_2(sc, RE_ISR); 1872 if (status == 0xffff) 1873 return; 1874 if (status) 1875 CSR_WRITE_2(sc, RE_ISR, status); 1876 1877 /* 1878 * XXX check behaviour on receiver stalls. 1879 */ 1880 1881 if (status & RE_ISR_SYSTEM_ERR) { 1882 re_reset(sc); 1883 re_init(sc); 1884 } 1885 } 1886 break; 1887 } 1888 } 1889 #endif /* DEVICE_POLLING */ 1890 1891 static void 1892 re_intr(void *arg) 1893 { 1894 struct re_softc *sc = arg; 1895 struct ifnet *ifp = &sc->arpcom.ac_if; 1896 uint16_t status; 1897 1898 ASSERT_SERIALIZED(ifp->if_serializer); 1899 1900 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0) 1901 return; 1902 1903 for (;;) { 1904 status = CSR_READ_2(sc, RE_ISR); 1905 /* If the card has gone away the read returns 0xffff. */ 1906 if (status == 0xffff) 1907 break; 1908 if (status) 1909 CSR_WRITE_2(sc, RE_ISR, status); 1910 1911 if ((status & sc->re_intrs) == 0) 1912 break; 1913 1914 if (status & (RE_ISR_RX_OK | RE_ISR_RX_ERR | RE_ISR_FIFO_OFLOW)) 1915 re_rxeof(sc); 1916 1917 if ((status & sc->re_tx_ack) || 1918 (status & RE_ISR_TX_ERR) || 1919 (status & RE_ISR_TX_DESC_UNAVAIL)) 1920 re_txeof(sc); 1921 1922 if (status & RE_ISR_SYSTEM_ERR) { 1923 re_reset(sc); 1924 re_init(sc); 1925 } 1926 1927 if (status & RE_ISR_LINKCHG) { 1928 callout_stop(&sc->re_timer); 1929 re_tick_serialized(sc); 1930 } 1931 } 1932 1933 if (!ifq_is_empty(&ifp->if_snd)) 1934 if_devstart(ifp); 1935 } 1936 1937 static int 1938 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0) 1939 { 1940 struct ifnet *ifp = &sc->arpcom.ac_if; 1941 struct mbuf *m; 1942 struct re_dmaload_arg arg; 1943 bus_dma_segment_t segs[RE_MAXSEGS]; 1944 bus_dmamap_t map; 1945 int error, maxsegs, idx, i; 1946 struct re_desc *d, *tx_ring; 1947 uint32_t csum_flags; 1948 1949 KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE, 1950 ("not enough free TX desc\n")); 1951 1952 m = *m_head; 1953 map = sc->re_ldata.re_tx_dmamap[*idx0]; 1954 1955 /* 1956 * Set up checksum offload. Note: checksum offload bits must 1957 * appear in all descriptors of a multi-descriptor transmit 1958 * attempt. (This is according to testing done with an 8169 1959 * chip. I'm not sure if this is a requirement or a bug.) 1960 */ 1961 csum_flags = 0; 1962 if (m->m_pkthdr.csum_flags & CSUM_IP) 1963 csum_flags |= RE_TDESC_CMD_IPCSUM; 1964 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1965 csum_flags |= RE_TDESC_CMD_TCPCSUM; 1966 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1967 csum_flags |= RE_TDESC_CMD_UDPCSUM; 1968 1969 if (m->m_pkthdr.len > sc->re_swcsum_lim && 1970 (m->m_pkthdr.csum_flags & (CSUM_DELAY_IP | CSUM_DELAY_DATA))) { 1971 struct ether_header *eh; 1972 struct ip *ip; 1973 u_short offset; 1974 1975 m = m_pullup(m, sizeof(struct ether_header *)); 1976 if (m == NULL) { 1977 *m_head = NULL; 1978 return ENOBUFS; 1979 } 1980 eh = mtod(m, struct ether_header *); 1981 1982 /* XXX */ 1983 if (eh->ether_type == ETHERTYPE_VLAN) 1984 offset = sizeof(struct ether_vlan_header); 1985 else 1986 offset = sizeof(struct ether_header); 1987 1988 m = m_pullup(m, offset + sizeof(struct ip *)); 1989 if (m == NULL) { 1990 *m_head = NULL; 1991 return ENOBUFS; 1992 } 1993 ip = (struct ip *)(mtod(m, uint8_t *) + offset); 1994 1995 if (m->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1996 u_short csum; 1997 1998 offset += IP_VHL_HL(ip->ip_vhl) << 2; 1999 csum = in_cksum_skip(m, ntohs(ip->ip_len), offset); 2000 if (m->m_pkthdr.csum_flags & CSUM_UDP && csum == 0) 2001 csum = 0xffff; 2002 offset += m->m_pkthdr.csum_data; /* checksum offset */ 2003 *(u_short *)(m->m_data + offset) = csum; 2004 2005 m->m_pkthdr.csum_flags &= ~CSUM_DELAY_DATA; 2006 } 2007 if (m->m_pkthdr.csum_flags & CSUM_DELAY_IP) { 2008 ip->ip_sum = 0; 2009 if (ip->ip_vhl == IP_VHL_BORING) { 2010 ip->ip_sum = in_cksum_hdr(ip); 2011 } else { 2012 ip->ip_sum = 2013 in_cksum(m, IP_VHL_HL(ip->ip_vhl) << 2); 2014 } 2015 m->m_pkthdr.csum_flags &= ~CSUM_DELAY_IP; 2016 } 2017 *m_head = m; /* 'm' may be changed by above two m_pullup() */ 2018 } 2019 2020 /* 2021 * With some of the RealTek chips, using the checksum offload 2022 * support in conjunction with the autopadding feature results 2023 * in the transmission of corrupt frames. For example, if we 2024 * need to send a really small IP fragment that's less than 60 2025 * bytes in size, and IP header checksumming is enabled, the 2026 * resulting ethernet frame that appears on the wire will 2027 * have garbled payload. To work around this, if TX checksum 2028 * offload is enabled, we always manually pad short frames out 2029 * to the minimum ethernet frame size. We do this by pretending 2030 * the mbuf chain has too many fragments so the coalescing code 2031 * below can assemble the packet into a single buffer that's 2032 * padded out to the mininum frame size. 2033 * 2034 * Note: this appears unnecessary for TCP, and doing it for TCP 2035 * with PCIe adapters seems to result in bad checksums. 2036 */ 2037 if (csum_flags && !(csum_flags & RE_TDESC_CMD_TCPCSUM) && 2038 m->m_pkthdr.len < RE_MIN_FRAMELEN) { 2039 error = re_pad_frame(m); 2040 if (error) 2041 goto back; 2042 } 2043 2044 maxsegs = sc->re_ldata.re_tx_free; 2045 if (maxsegs > RE_MAXSEGS) 2046 maxsegs = RE_MAXSEGS; 2047 2048 arg.re_nsegs = maxsegs; 2049 arg.re_segs = segs; 2050 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, m, 2051 re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 2052 if (error && error != EFBIG) { 2053 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2054 goto back; 2055 } 2056 2057 /* 2058 * Too many segments to map, coalesce into a single mbuf 2059 */ 2060 if (!error && arg.re_nsegs == 0) { 2061 bus_dmamap_unload(sc->re_ldata.re_mtag, map); 2062 error = EFBIG; 2063 } 2064 if (error) { 2065 struct mbuf *m_new; 2066 2067 m_new = m_defrag(m, MB_DONTWAIT); 2068 if (m_new == NULL) { 2069 if_printf(ifp, "can't defrag TX mbuf\n"); 2070 error = ENOBUFS; 2071 goto back; 2072 } else { 2073 *m_head = m = m_new; 2074 } 2075 2076 arg.re_nsegs = maxsegs; 2077 arg.re_segs = segs; 2078 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, m, 2079 re_dma_map_desc, &arg, 2080 BUS_DMA_NOWAIT); 2081 if (error || arg.re_nsegs == 0) { 2082 if (!error) { 2083 bus_dmamap_unload(sc->re_ldata.re_mtag, map); 2084 error = EFBIG; 2085 } 2086 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2087 goto back; 2088 } 2089 } 2090 bus_dmamap_sync(sc->re_ldata.re_mtag, map, BUS_DMASYNC_PREWRITE); 2091 2092 /* 2093 * Map the segment array into descriptors. We also keep track 2094 * of the end of the ring and set the end-of-ring bits as needed, 2095 * and we set the ownership bits in all except the very first 2096 * descriptor, whose ownership bits will be turned on later. 2097 */ 2098 tx_ring = sc->re_ldata.re_tx_list; 2099 idx = *idx0; 2100 i = 0; 2101 for (;;) { 2102 uint32_t cmdstat; 2103 2104 d = &tx_ring[idx]; 2105 2106 cmdstat = segs[i].ds_len; 2107 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr)); 2108 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr)); 2109 if (i == 0) 2110 cmdstat |= RE_TDESC_CMD_SOF; 2111 else 2112 cmdstat |= RE_TDESC_CMD_OWN; 2113 if (idx == (RE_TX_DESC_CNT - 1)) 2114 cmdstat |= RE_TDESC_CMD_EOR; 2115 d->re_cmdstat = htole32(cmdstat | csum_flags); 2116 2117 i++; 2118 if (i == arg.re_nsegs) 2119 break; 2120 RE_DESC_INC(idx); 2121 } 2122 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF); 2123 2124 /* 2125 * Set up hardware VLAN tagging. Note: vlan tag info must 2126 * appear in the first descriptor of a multi-descriptor 2127 * transmission attempt. 2128 */ 2129 if (m->m_flags & M_VLANTAG) { 2130 tx_ring[*idx0].re_vlanctl = 2131 htole32(htobe16(m->m_pkthdr.ether_vlantag) | 2132 RE_TDESC_VLANCTL_TAG); 2133 } 2134 2135 /* Transfer ownership of packet to the chip. */ 2136 d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN); 2137 if (*idx0 != idx) 2138 tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN); 2139 2140 /* 2141 * Insure that the map for this transmission 2142 * is placed at the array index of the last descriptor 2143 * in this chain. 2144 */ 2145 sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx]; 2146 sc->re_ldata.re_tx_dmamap[idx] = map; 2147 2148 sc->re_ldata.re_tx_mbuf[idx] = m; 2149 sc->re_ldata.re_tx_free -= arg.re_nsegs; 2150 2151 RE_DESC_INC(idx); 2152 *idx0 = idx; 2153 back: 2154 if (error) { 2155 m_freem(m); 2156 *m_head = NULL; 2157 } 2158 return error; 2159 } 2160 2161 /* 2162 * Main transmit routine for C+ and gigE NICs. 2163 */ 2164 2165 static void 2166 re_start(struct ifnet *ifp) 2167 { 2168 struct re_softc *sc = ifp->if_softc; 2169 struct mbuf *m_head; 2170 int idx, need_trans; 2171 2172 ASSERT_SERIALIZED(ifp->if_serializer); 2173 2174 if (!sc->re_link) { 2175 ifq_purge(&ifp->if_snd); 2176 return; 2177 } 2178 2179 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 2180 return; 2181 2182 idx = sc->re_ldata.re_tx_prodidx; 2183 2184 need_trans = 0; 2185 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) { 2186 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) { 2187 ifp->if_flags |= IFF_OACTIVE; 2188 break; 2189 } 2190 2191 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2192 if (m_head == NULL) 2193 break; 2194 2195 if (re_encap(sc, &m_head, &idx)) { 2196 /* m_head is freed by re_encap(), if we reach here */ 2197 ifp->if_oerrors++; 2198 ifp->if_flags |= IFF_OACTIVE; 2199 break; 2200 } 2201 2202 need_trans = 1; 2203 2204 /* 2205 * If there's a BPF listener, bounce a copy of this frame 2206 * to him. 2207 */ 2208 ETHER_BPF_MTAP(ifp, m_head); 2209 } 2210 2211 if (!need_trans) { 2212 if (RE_TX_MODERATION_IS_ENABLED(sc) && 2213 sc->re_ldata.re_tx_free != RE_TX_DESC_CNT) 2214 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 2215 return; 2216 } 2217 2218 /* Flush the TX descriptors */ 2219 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 2220 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE); 2221 2222 sc->re_ldata.re_tx_prodidx = idx; 2223 2224 /* 2225 * RealTek put the TX poll request register in a different 2226 * location on the 8169 gigE chip. I don't know why. 2227 */ 2228 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2229 2230 if (RE_TX_MODERATION_IS_ENABLED(sc)) { 2231 /* 2232 * Use the countdown timer for interrupt moderation. 2233 * 'TX done' interrupts are disabled. Instead, we reset the 2234 * countdown timer, which will begin counting until it hits 2235 * the value in the TIMERINT register, and then trigger an 2236 * interrupt. Each time we write to the TIMERCNT register, 2237 * the timer count is reset to 0. 2238 */ 2239 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 2240 } 2241 2242 /* 2243 * Set a timeout in case the chip goes out to lunch. 2244 */ 2245 ifp->if_timer = 5; 2246 } 2247 2248 static void 2249 re_init(void *xsc) 2250 { 2251 struct re_softc *sc = xsc; 2252 struct ifnet *ifp = &sc->arpcom.ac_if; 2253 struct mii_data *mii; 2254 uint32_t rxcfg = 0; 2255 int error, framelen; 2256 2257 ASSERT_SERIALIZED(ifp->if_serializer); 2258 2259 mii = device_get_softc(sc->re_miibus); 2260 2261 /* 2262 * Cancel pending I/O and free all RX/TX buffers. 2263 */ 2264 re_stop(sc); 2265 2266 /* 2267 * Enable C+ RX and TX mode, as well as VLAN stripping and 2268 * RX checksum offload. We must configure the C+ register 2269 * before all others. 2270 */ 2271 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB | 2272 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP | 2273 (ifp->if_capenable & IFCAP_RXCSUM ? 2274 RE_CPLUSCMD_RXCSUM_ENB : 0)); 2275 2276 /* 2277 * Init our MAC address. Even though the chipset 2278 * documentation doesn't mention it, we need to enter "Config 2279 * register write enable" mode to modify the ID registers. 2280 */ 2281 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG); 2282 CSR_WRITE_4(sc, RE_IDR0, 2283 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0]))); 2284 CSR_WRITE_2(sc, RE_IDR4, 2285 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4]))); 2286 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 2287 2288 /* 2289 * For C+ mode, initialize the RX descriptors and mbufs. 2290 */ 2291 error = re_rx_list_init(sc); 2292 if (error) { 2293 re_stop(sc); 2294 return; 2295 } 2296 error = re_tx_list_init(sc); 2297 if (error) { 2298 re_stop(sc); 2299 return; 2300 } 2301 2302 /* 2303 * Load the addresses of the RX and TX lists into the chip. 2304 */ 2305 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI, 2306 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr)); 2307 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO, 2308 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr)); 2309 2310 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI, 2311 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr)); 2312 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO, 2313 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr)); 2314 2315 /* 2316 * Enable transmit and receive. 2317 */ 2318 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2319 2320 /* 2321 * Set the initial TX and RX configuration. 2322 */ 2323 if (sc->re_testmode) { 2324 if (sc->re_type == RE_8169) 2325 CSR_WRITE_4(sc, RE_TXCFG, 2326 RE_TXCFG_CONFIG | RE_LOOPTEST_ON); 2327 else 2328 CSR_WRITE_4(sc, RE_TXCFG, 2329 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS); 2330 } else 2331 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG); 2332 2333 framelen = RE_FRAMELEN(ifp->if_mtu); 2334 if (framelen < RE_FRAMELEN_2K) { 2335 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 2336 howmany(RE_FRAMELEN_2K, 128)); 2337 } else { 2338 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128)); 2339 } 2340 2341 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG); 2342 2343 /* Set the individual bit to receive frames for this host only. */ 2344 rxcfg = CSR_READ_4(sc, RE_RXCFG); 2345 rxcfg |= RE_RXCFG_RX_INDIV; 2346 2347 /* If we want promiscuous mode, set the allframes bit. */ 2348 if (ifp->if_flags & IFF_PROMISC) { 2349 rxcfg |= RE_RXCFG_RX_ALLPHYS; 2350 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 2351 } else { 2352 rxcfg &= ~RE_RXCFG_RX_ALLPHYS; 2353 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 2354 } 2355 2356 /* 2357 * Set capture broadcast bit to capture broadcast frames. 2358 */ 2359 if (ifp->if_flags & IFF_BROADCAST) { 2360 rxcfg |= RE_RXCFG_RX_BROAD; 2361 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 2362 } else { 2363 rxcfg &= ~RE_RXCFG_RX_BROAD; 2364 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 2365 } 2366 2367 /* 2368 * Program the multicast filter, if necessary. 2369 */ 2370 re_setmulti(sc); 2371 2372 #ifdef DEVICE_POLLING 2373 /* 2374 * Disable interrupts if we are polling. 2375 */ 2376 if (ifp->if_flags & IFF_POLLING) 2377 CSR_WRITE_2(sc, RE_IMR, 0); 2378 else /* otherwise ... */ 2379 #endif /* DEVICE_POLLING */ 2380 /* 2381 * Enable interrupts. 2382 */ 2383 if (sc->re_testmode) 2384 CSR_WRITE_2(sc, RE_IMR, 0); 2385 else 2386 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 2387 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs); 2388 2389 /* Set initial TX threshold */ 2390 sc->re_txthresh = RE_TX_THRESH_INIT; 2391 2392 /* Start RX/TX process. */ 2393 if (sc->re_flags & RE_F_HASMPC) 2394 CSR_WRITE_4(sc, RE_MISSEDPKT, 0); 2395 #ifdef notdef 2396 /* Enable receiver and transmitter. */ 2397 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2398 #endif 2399 2400 if (RE_TX_MODERATION_IS_ENABLED(sc)) { 2401 /* 2402 * Initialize the timer interrupt register so that 2403 * a timer interrupt will be generated once the timer 2404 * reaches a certain number of ticks. The timer is 2405 * reloaded on each transmit. This gives us TX interrupt 2406 * moderation, which dramatically improves TX frame rate. 2407 */ 2408 if (sc->re_type == RE_8169) 2409 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800); 2410 else 2411 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); 2412 } 2413 2414 /* 2415 * For 8169 gigE NICs, set the max allowed RX packet 2416 * size so we can receive jumbo frames. 2417 */ 2418 if (sc->re_type == RE_8169) 2419 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383); 2420 2421 if (sc->re_testmode) { 2422 return; 2423 } 2424 2425 mii_mediachg(mii); 2426 2427 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX); 2428 2429 ifp->if_flags |= IFF_RUNNING; 2430 ifp->if_flags &= ~IFF_OACTIVE; 2431 2432 sc->re_link = 0; 2433 callout_reset(&sc->re_timer, hz, re_tick, sc); 2434 } 2435 2436 /* 2437 * Set media options. 2438 */ 2439 static int 2440 re_ifmedia_upd(struct ifnet *ifp) 2441 { 2442 struct re_softc *sc = ifp->if_softc; 2443 struct mii_data *mii; 2444 2445 ASSERT_SERIALIZED(ifp->if_serializer); 2446 2447 mii = device_get_softc(sc->re_miibus); 2448 mii_mediachg(mii); 2449 2450 return(0); 2451 } 2452 2453 /* 2454 * Report current media status. 2455 */ 2456 static void 2457 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2458 { 2459 struct re_softc *sc = ifp->if_softc; 2460 struct mii_data *mii; 2461 2462 ASSERT_SERIALIZED(ifp->if_serializer); 2463 2464 mii = device_get_softc(sc->re_miibus); 2465 2466 mii_pollstat(mii); 2467 ifmr->ifm_active = mii->mii_media_active; 2468 ifmr->ifm_status = mii->mii_media_status; 2469 } 2470 2471 static int 2472 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2473 { 2474 struct re_softc *sc = ifp->if_softc; 2475 struct ifreq *ifr = (struct ifreq *) data; 2476 struct mii_data *mii; 2477 int error = 0; 2478 2479 ASSERT_SERIALIZED(ifp->if_serializer); 2480 2481 switch(command) { 2482 case SIOCSIFMTU: 2483 if (ifr->ifr_mtu > sc->re_maxmtu) { 2484 error = EINVAL; 2485 } else if (ifp->if_mtu != ifr->ifr_mtu) { 2486 ifp->if_mtu = ifr->ifr_mtu; 2487 if (ifp->if_flags & IFF_RUNNING) 2488 ifp->if_init(sc); 2489 } 2490 break; 2491 2492 case SIOCSIFFLAGS: 2493 if (ifp->if_flags & IFF_UP) 2494 re_init(sc); 2495 else if (ifp->if_flags & IFF_RUNNING) 2496 re_stop(sc); 2497 break; 2498 case SIOCADDMULTI: 2499 case SIOCDELMULTI: 2500 re_setmulti(sc); 2501 error = 0; 2502 break; 2503 case SIOCGIFMEDIA: 2504 case SIOCSIFMEDIA: 2505 mii = device_get_softc(sc->re_miibus); 2506 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2507 break; 2508 case SIOCSIFCAP: 2509 ifp->if_capenable &= ~(IFCAP_HWCSUM); 2510 ifp->if_capenable |= 2511 ifr->ifr_reqcap & (IFCAP_HWCSUM); 2512 if (ifp->if_capenable & IFCAP_TXCSUM) 2513 ifp->if_hwassist = RE_CSUM_FEATURES; 2514 else 2515 ifp->if_hwassist = 0; 2516 if (ifp->if_flags & IFF_RUNNING) 2517 re_init(sc); 2518 break; 2519 default: 2520 error = ether_ioctl(ifp, command, data); 2521 break; 2522 } 2523 return(error); 2524 } 2525 2526 static void 2527 re_watchdog(struct ifnet *ifp) 2528 { 2529 struct re_softc *sc = ifp->if_softc; 2530 2531 ASSERT_SERIALIZED(ifp->if_serializer); 2532 2533 if_printf(ifp, "watchdog timeout\n"); 2534 2535 ifp->if_oerrors++; 2536 2537 re_txeof(sc); 2538 re_rxeof(sc); 2539 2540 re_init(sc); 2541 2542 if (!ifq_is_empty(&ifp->if_snd)) 2543 if_devstart(ifp); 2544 } 2545 2546 /* 2547 * Stop the adapter and free any mbufs allocated to the 2548 * RX and TX lists. 2549 */ 2550 static void 2551 re_stop(struct re_softc *sc) 2552 { 2553 struct ifnet *ifp = &sc->arpcom.ac_if; 2554 int i; 2555 2556 ASSERT_SERIALIZED(ifp->if_serializer); 2557 2558 ifp->if_timer = 0; 2559 callout_stop(&sc->re_timer); 2560 2561 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2562 2563 CSR_WRITE_1(sc, RE_COMMAND, 0x00); 2564 CSR_WRITE_2(sc, RE_IMR, 0x0000); 2565 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 2566 2567 re_free_rxchain(sc); 2568 sc->re_drop_rxfrag = 0; 2569 2570 /* Free the TX list buffers. */ 2571 for (i = 0; i < RE_TX_DESC_CNT; i++) { 2572 if (sc->re_ldata.re_tx_mbuf[i] != NULL) { 2573 bus_dmamap_unload(sc->re_ldata.re_mtag, 2574 sc->re_ldata.re_tx_dmamap[i]); 2575 m_freem(sc->re_ldata.re_tx_mbuf[i]); 2576 sc->re_ldata.re_tx_mbuf[i] = NULL; 2577 } 2578 } 2579 2580 /* Free the RX list buffers. */ 2581 for (i = 0; i < RE_RX_DESC_CNT; i++) { 2582 if (sc->re_ldata.re_rx_mbuf[i] != NULL) { 2583 bus_dmamap_unload(sc->re_ldata.re_mtag, 2584 sc->re_ldata.re_rx_dmamap[i]); 2585 m_freem(sc->re_ldata.re_rx_mbuf[i]); 2586 sc->re_ldata.re_rx_mbuf[i] = NULL; 2587 } 2588 } 2589 } 2590 2591 /* 2592 * Device suspend routine. Stop the interface and save some PCI 2593 * settings in case the BIOS doesn't restore them properly on 2594 * resume. 2595 */ 2596 static int 2597 re_suspend(device_t dev) 2598 { 2599 #ifndef BURN_BRIDGES 2600 int i; 2601 #endif 2602 struct re_softc *sc = device_get_softc(dev); 2603 struct ifnet *ifp = &sc->arpcom.ac_if; 2604 2605 lwkt_serialize_enter(ifp->if_serializer); 2606 2607 re_stop(sc); 2608 2609 #ifndef BURN_BRIDGES 2610 for (i = 0; i < 5; i++) 2611 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2612 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2613 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2614 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2615 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2616 #endif 2617 2618 sc->suspended = 1; 2619 2620 lwkt_serialize_exit(ifp->if_serializer); 2621 2622 return (0); 2623 } 2624 2625 /* 2626 * Device resume routine. Restore some PCI settings in case the BIOS 2627 * doesn't, re-enable busmastering, and restart the interface if 2628 * appropriate. 2629 */ 2630 static int 2631 re_resume(device_t dev) 2632 { 2633 struct re_softc *sc = device_get_softc(dev); 2634 struct ifnet *ifp = &sc->arpcom.ac_if; 2635 #ifndef BURN_BRIDGES 2636 int i; 2637 #endif 2638 2639 lwkt_serialize_enter(ifp->if_serializer); 2640 2641 #ifndef BURN_BRIDGES 2642 /* better way to do this? */ 2643 for (i = 0; i < 5; i++) 2644 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2645 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2646 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2647 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2648 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2649 2650 /* reenable busmastering */ 2651 pci_enable_busmaster(dev); 2652 pci_enable_io(dev, SYS_RES_IOPORT); 2653 #endif 2654 2655 /* reinitialize interface if necessary */ 2656 if (ifp->if_flags & IFF_UP) 2657 re_init(sc); 2658 2659 sc->suspended = 0; 2660 2661 lwkt_serialize_exit(ifp->if_serializer); 2662 2663 return (0); 2664 } 2665 2666 /* 2667 * Stop all chip I/O so that the kernel's probe routines don't 2668 * get confused by errant DMAs when rebooting. 2669 */ 2670 static void 2671 re_shutdown(device_t dev) 2672 { 2673 struct re_softc *sc = device_get_softc(dev); 2674 struct ifnet *ifp = &sc->arpcom.ac_if; 2675 2676 lwkt_serialize_enter(ifp->if_serializer); 2677 re_stop(sc); 2678 lwkt_serialize_exit(ifp->if_serializer); 2679 } 2680 2681 static int 2682 re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS) 2683 { 2684 struct re_softc *sc = arg1; 2685 struct ifnet *ifp = &sc->arpcom.ac_if; 2686 int error = 0, mod, mod_old; 2687 2688 lwkt_serialize_enter(ifp->if_serializer); 2689 2690 mod_old = mod = RE_TX_MODERATION_IS_ENABLED(sc); 2691 2692 error = sysctl_handle_int(oidp, &mod, 0, req); 2693 if (error || req->newptr == NULL || mod == mod_old) 2694 goto back; 2695 if (mod != 0 && mod != 1) { 2696 error = EINVAL; 2697 goto back; 2698 } 2699 2700 if (mod) 2701 RE_ENABLE_TX_MODERATION(sc); 2702 else 2703 RE_DISABLE_TX_MODERATION(sc); 2704 2705 if ((ifp->if_flags & (IFF_RUNNING | IFF_UP)) == (IFF_RUNNING | IFF_UP)) 2706 re_init(sc); 2707 back: 2708 lwkt_serialize_exit(ifp->if_serializer); 2709 return error; 2710 } 2711 2712 static int 2713 re_pad_frame(struct mbuf *pkt) 2714 { 2715 struct mbuf *last = NULL; 2716 int padlen; 2717 2718 padlen = RE_MIN_FRAMELEN - pkt->m_pkthdr.len; 2719 2720 /* if there's only the packet-header and we can pad there, use it. */ 2721 if (pkt->m_pkthdr.len == pkt->m_len && 2722 M_TRAILINGSPACE(pkt) >= padlen) { 2723 last = pkt; 2724 } else { 2725 /* 2726 * Walk packet chain to find last mbuf. We will either 2727 * pad there, or append a new mbuf and pad it 2728 */ 2729 for (last = pkt; last->m_next != NULL; last = last->m_next) 2730 ; /* EMPTY */ 2731 2732 /* `last' now points to last in chain. */ 2733 if (M_TRAILINGSPACE(last) < padlen) { 2734 struct mbuf *n; 2735 2736 /* Allocate new empty mbuf, pad it. Compact later. */ 2737 MGET(n, MB_DONTWAIT, MT_DATA); 2738 if (n == NULL) 2739 return ENOBUFS; 2740 n->m_len = 0; 2741 last->m_next = n; 2742 last = n; 2743 } 2744 } 2745 KKASSERT(M_TRAILINGSPACE(last) >= padlen); 2746 KKASSERT(M_WRITABLE(last)); 2747 2748 /* Now zero the pad area, to avoid the re cksum-assist bug */ 2749 bzero(mtod(last, char *) + last->m_len, padlen); 2750 last->m_len += padlen; 2751 pkt->m_pkthdr.len += padlen; 2752 return 0; 2753 } 2754