1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $ 36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.22 2006/08/01 18:07:12 swildner Exp $ 37 */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul@windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 51 * and the RTL8110S. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7440, so the max MTU possible with this 111 * driver is 7422 bytes. 112 */ 113 114 #include "opt_polling.h" 115 116 #include <sys/param.h> 117 #include <sys/endian.h> 118 #include <sys/systm.h> 119 #include <sys/sockio.h> 120 #include <sys/mbuf.h> 121 #include <sys/malloc.h> 122 #include <sys/module.h> 123 #include <sys/kernel.h> 124 #include <sys/socket.h> 125 #include <sys/serialize.h> 126 #include <sys/thread2.h> 127 128 #include <net/if.h> 129 #include <net/ifq_var.h> 130 #include <net/if_arp.h> 131 #include <net/ethernet.h> 132 #include <net/if_dl.h> 133 #include <net/if_media.h> 134 #include <net/if_types.h> 135 #include <net/vlan/if_vlan_var.h> 136 137 #include <net/bpf.h> 138 139 #include <machine/bus_pio.h> 140 #include <machine/bus_memio.h> 141 #include <machine/bus.h> 142 #include <machine/resource.h> 143 #include <sys/bus.h> 144 #include <sys/rman.h> 145 146 #include <dev/netif/mii_layer/mii.h> 147 #include <dev/netif/mii_layer/miivar.h> 148 149 #include <bus/pci/pcidevs.h> 150 #include <bus/pci/pcireg.h> 151 #include <bus/pci/pcivar.h> 152 153 /* "controller miibus0" required. See GENERIC if you get errors here. */ 154 #include "miibus_if.h" 155 156 #include <dev/netif/re/if_rereg.h> 157 158 /* 159 * The hardware supports checksumming but, as usual, some chipsets screw it 160 * all up and produce bogus packets, so we disable it by default. 161 */ 162 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 163 #define RE_DISABLE_HWCSUM 164 165 /* 166 * Various supported device vendors/types and their names. 167 */ 168 static struct re_type re_devs[] = { 169 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, RE_HWREV_8169S, 170 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 171 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, RE_HWREV_8139CPLUS, 172 "RealTek 8139C+ 10/100BaseTX" }, 173 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169, 174 "RealTek 8169 Gigabit Ethernet" }, 175 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169S, 176 "RealTek 8169S Single-chip Gigabit Ethernet" }, 177 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8110S, 178 "RealTek 8110S Single-chip Gigabit Ethernet" }, 179 { 0, 0, 0, NULL } 180 }; 181 182 static struct re_hwrev re_hwrevs[] = { 183 { RE_HWREV_8139CPLUS, RE_8139CPLUS, "C+"}, 184 { RE_HWREV_8169, RE_8169, "8169"}, 185 { RE_HWREV_8169S, RE_8169, "8169S"}, 186 { RE_HWREV_8110S, RE_8169, "8110S"}, 187 { 0, 0, NULL } 188 }; 189 190 static int re_probe(device_t); 191 static int re_attach(device_t); 192 static int re_detach(device_t); 193 194 static int re_encap(struct re_softc *, struct mbuf **, int *, int *); 195 196 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int); 197 static void re_dma_map_desc(void *, bus_dma_segment_t *, int, 198 bus_size_t, int); 199 static int re_allocmem(device_t, struct re_softc *); 200 static int re_newbuf(struct re_softc *, int, struct mbuf *); 201 static int re_rx_list_init(struct re_softc *); 202 static int re_tx_list_init(struct re_softc *); 203 static void re_rxeof(struct re_softc *); 204 static void re_txeof(struct re_softc *); 205 static void re_intr(void *); 206 static void re_tick(void *); 207 static void re_tick_serialized(void *); 208 static void re_start(struct ifnet *); 209 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 210 static void re_init(void *); 211 static void re_stop(struct re_softc *); 212 static void re_watchdog(struct ifnet *); 213 static int re_suspend(device_t); 214 static int re_resume(device_t); 215 static void re_shutdown(device_t); 216 static int re_ifmedia_upd(struct ifnet *); 217 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 218 219 static void re_eeprom_putbyte(struct re_softc *, int); 220 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *); 221 static void re_read_eeprom(struct re_softc *, caddr_t, int, int, int); 222 static int re_gmii_readreg(device_t, int, int); 223 static int re_gmii_writereg(device_t, int, int, int); 224 225 static int re_miibus_readreg(device_t, int, int); 226 static int re_miibus_writereg(device_t, int, int, int); 227 static void re_miibus_statchg(device_t); 228 229 static void re_setmulti(struct re_softc *); 230 static void re_reset(struct re_softc *); 231 232 static int re_diag(struct re_softc *); 233 #ifdef DEVICE_POLLING 234 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 235 #endif 236 237 static device_method_t re_methods[] = { 238 /* Device interface */ 239 DEVMETHOD(device_probe, re_probe), 240 DEVMETHOD(device_attach, re_attach), 241 DEVMETHOD(device_detach, re_detach), 242 DEVMETHOD(device_suspend, re_suspend), 243 DEVMETHOD(device_resume, re_resume), 244 DEVMETHOD(device_shutdown, re_shutdown), 245 246 /* bus interface */ 247 DEVMETHOD(bus_print_child, bus_generic_print_child), 248 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 249 250 /* MII interface */ 251 DEVMETHOD(miibus_readreg, re_miibus_readreg), 252 DEVMETHOD(miibus_writereg, re_miibus_writereg), 253 DEVMETHOD(miibus_statchg, re_miibus_statchg), 254 255 { 0, 0 } 256 }; 257 258 static driver_t re_driver = { 259 "re", 260 re_methods, 261 sizeof(struct re_softc) 262 }; 263 264 static devclass_t re_devclass; 265 266 DECLARE_DUMMY_MODULE(if_re); 267 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0); 268 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0); 269 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 270 271 #define EE_SET(x) \ 272 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x)) 273 274 #define EE_CLR(x) \ 275 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x)) 276 277 /* 278 * Send a read command and address to the EEPROM, check for ACK. 279 */ 280 static void 281 re_eeprom_putbyte(struct re_softc *sc, int addr) 282 { 283 int d, i; 284 285 d = addr | sc->re_eecmd_read; 286 287 /* 288 * Feed in each bit and strobe the clock. 289 */ 290 for (i = 0x400; i != 0; i >>= 1) { 291 if (d & i) 292 EE_SET(RE_EE_DATAIN); 293 else 294 EE_CLR(RE_EE_DATAIN); 295 DELAY(100); 296 EE_SET(RE_EE_CLK); 297 DELAY(150); 298 EE_CLR(RE_EE_CLK); 299 DELAY(100); 300 } 301 } 302 303 /* 304 * Read a word of data stored in the EEPROM at address 'addr.' 305 */ 306 static void 307 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest) 308 { 309 int i; 310 uint16_t word = 0; 311 312 /* Enter EEPROM access mode. */ 313 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL); 314 315 /* 316 * Send address of word we want to read. 317 */ 318 re_eeprom_putbyte(sc, addr); 319 320 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL); 321 322 /* 323 * Start reading bits from EEPROM. 324 */ 325 for (i = 0x8000; i != 0; i >>= 1) { 326 EE_SET(RE_EE_CLK); 327 DELAY(100); 328 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT) 329 word |= i; 330 EE_CLR(RE_EE_CLK); 331 DELAY(100); 332 } 333 334 /* Turn off EEPROM access mode. */ 335 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 336 337 *dest = word; 338 } 339 340 /* 341 * Read a sequence of words from the EEPROM. 342 */ 343 static void 344 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt, int swap) 345 { 346 int i; 347 uint16_t word = 0, *ptr; 348 349 for (i = 0; i < cnt; i++) { 350 re_eeprom_getword(sc, off + i, &word); 351 ptr = (u_int16_t *)(dest + (i * 2)); 352 if (swap) 353 *ptr = be16toh(word); 354 else 355 *ptr = word; 356 } 357 } 358 359 static int 360 re_gmii_readreg(device_t dev, int phy, int reg) 361 { 362 struct re_softc *sc = device_get_softc(dev); 363 u_int32_t rval; 364 int i; 365 366 if (phy != 1) 367 return(0); 368 369 /* Let the rgephy driver read the GMEDIASTAT register */ 370 371 if (reg == RE_GMEDIASTAT) 372 return(CSR_READ_1(sc, RE_GMEDIASTAT)); 373 374 CSR_WRITE_4(sc, RE_PHYAR, reg << 16); 375 DELAY(1000); 376 377 for (i = 0; i < RE_TIMEOUT; i++) { 378 rval = CSR_READ_4(sc, RE_PHYAR); 379 if (rval & RE_PHYAR_BUSY) 380 break; 381 DELAY(100); 382 } 383 384 if (i == RE_TIMEOUT) { 385 device_printf(dev, "PHY read failed\n"); 386 return(0); 387 } 388 389 return(rval & RE_PHYAR_PHYDATA); 390 } 391 392 static int 393 re_gmii_writereg(device_t dev, int phy, int reg, int data) 394 { 395 struct re_softc *sc = device_get_softc(dev); 396 uint32_t rval; 397 int i; 398 399 CSR_WRITE_4(sc, RE_PHYAR, 400 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY); 401 DELAY(1000); 402 403 for (i = 0; i < RE_TIMEOUT; i++) { 404 rval = CSR_READ_4(sc, RE_PHYAR); 405 if ((rval & RE_PHYAR_BUSY) == 0) 406 break; 407 DELAY(100); 408 } 409 410 if (i == RE_TIMEOUT) 411 device_printf(dev, "PHY write failed\n"); 412 413 return(0); 414 } 415 416 static int 417 re_miibus_readreg(device_t dev, int phy, int reg) 418 { 419 struct re_softc *sc = device_get_softc(dev); 420 uint16_t rval = 0; 421 uint16_t re8139_reg = 0; 422 423 if (sc->re_type == RE_8169) { 424 rval = re_gmii_readreg(dev, phy, reg); 425 return(rval); 426 } 427 428 /* Pretend the internal PHY is only at address 0 */ 429 if (phy) 430 return(0); 431 432 switch(reg) { 433 case MII_BMCR: 434 re8139_reg = RE_BMCR; 435 break; 436 case MII_BMSR: 437 re8139_reg = RE_BMSR; 438 break; 439 case MII_ANAR: 440 re8139_reg = RE_ANAR; 441 break; 442 case MII_ANER: 443 re8139_reg = RE_ANER; 444 break; 445 case MII_ANLPAR: 446 re8139_reg = RE_LPAR; 447 break; 448 case MII_PHYIDR1: 449 case MII_PHYIDR2: 450 return(0); 451 /* 452 * Allow the rlphy driver to read the media status 453 * register. If we have a link partner which does not 454 * support NWAY, this is the register which will tell 455 * us the results of parallel detection. 456 */ 457 case RE_MEDIASTAT: 458 return(CSR_READ_1(sc, RE_MEDIASTAT)); 459 default: 460 device_printf(dev, "bad phy register\n"); 461 return(0); 462 } 463 rval = CSR_READ_2(sc, re8139_reg); 464 return(rval); 465 } 466 467 static int 468 re_miibus_writereg(device_t dev, int phy, int reg, int data) 469 { 470 struct re_softc *sc= device_get_softc(dev); 471 u_int16_t re8139_reg = 0; 472 473 if (sc->re_type == RE_8169) 474 return(re_gmii_writereg(dev, phy, reg, data)); 475 476 /* Pretend the internal PHY is only at address 0 */ 477 if (phy) 478 return(0); 479 480 switch(reg) { 481 case MII_BMCR: 482 re8139_reg = RE_BMCR; 483 break; 484 case MII_BMSR: 485 re8139_reg = RE_BMSR; 486 break; 487 case MII_ANAR: 488 re8139_reg = RE_ANAR; 489 break; 490 case MII_ANER: 491 re8139_reg = RE_ANER; 492 break; 493 case MII_ANLPAR: 494 re8139_reg = RE_LPAR; 495 break; 496 case MII_PHYIDR1: 497 case MII_PHYIDR2: 498 return(0); 499 default: 500 device_printf(dev, "bad phy register\n"); 501 return(0); 502 } 503 CSR_WRITE_2(sc, re8139_reg, data); 504 return(0); 505 } 506 507 static void 508 re_miibus_statchg(device_t dev) 509 { 510 } 511 512 /* 513 * Program the 64-bit multicast hash filter. 514 */ 515 static void 516 re_setmulti(struct re_softc *sc) 517 { 518 struct ifnet *ifp = &sc->arpcom.ac_if; 519 int h = 0; 520 uint32_t hashes[2] = { 0, 0 }; 521 struct ifmultiaddr *ifma; 522 uint32_t rxfilt; 523 int mcnt = 0; 524 525 rxfilt = CSR_READ_4(sc, RE_RXCFG); 526 527 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 528 rxfilt |= RE_RXCFG_RX_MULTI; 529 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 530 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF); 531 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF); 532 return; 533 } 534 535 /* first, zot all the existing hash bits */ 536 CSR_WRITE_4(sc, RE_MAR0, 0); 537 CSR_WRITE_4(sc, RE_MAR4, 0); 538 539 /* now program new ones */ 540 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 541 if (ifma->ifma_addr->sa_family != AF_LINK) 542 continue; 543 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 544 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 545 if (h < 32) 546 hashes[0] |= (1 << h); 547 else 548 hashes[1] |= (1 << (h - 32)); 549 mcnt++; 550 } 551 552 if (mcnt) 553 rxfilt |= RE_RXCFG_RX_MULTI; 554 else 555 rxfilt &= ~RE_RXCFG_RX_MULTI; 556 557 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 558 CSR_WRITE_4(sc, RE_MAR0, hashes[0]); 559 CSR_WRITE_4(sc, RE_MAR4, hashes[1]); 560 } 561 562 static void 563 re_reset(struct re_softc *sc) 564 { 565 int i; 566 567 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET); 568 569 for (i = 0; i < RE_TIMEOUT; i++) { 570 DELAY(10); 571 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0) 572 break; 573 } 574 if (i == RE_TIMEOUT) 575 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 576 577 CSR_WRITE_1(sc, 0x82, 1); 578 } 579 580 /* 581 * The following routine is designed to test for a defect on some 582 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 583 * lines connected to the bus, however for a 32-bit only card, they 584 * should be pulled high. The result of this defect is that the 585 * NIC will not work right if you plug it into a 64-bit slot: DMA 586 * operations will be done with 64-bit transfers, which will fail 587 * because the 64-bit data lines aren't connected. 588 * 589 * There's no way to work around this (short of talking a soldering 590 * iron to the board), however we can detect it. The method we use 591 * here is to put the NIC into digital loopback mode, set the receiver 592 * to promiscuous mode, and then try to send a frame. We then compare 593 * the frame data we sent to what was received. If the data matches, 594 * then the NIC is working correctly, otherwise we know the user has 595 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 596 * slot. In the latter case, there's no way the NIC can work correctly, 597 * so we print out a message on the console and abort the device attach. 598 */ 599 600 static int 601 re_diag(struct re_softc *sc) 602 { 603 struct ifnet *ifp = &sc->arpcom.ac_if; 604 struct mbuf *m0; 605 struct ether_header *eh; 606 struct re_desc *cur_rx; 607 uint16_t status; 608 uint32_t rxstat; 609 int total_len, i, error = 0; 610 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 611 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 612 613 /* Allocate a single mbuf */ 614 615 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 616 if (m0 == NULL) 617 return(ENOBUFS); 618 619 /* 620 * Initialize the NIC in test mode. This sets the chip up 621 * so that it can send and receive frames, but performs the 622 * following special functions: 623 * - Puts receiver in promiscuous mode 624 * - Enables digital loopback mode 625 * - Leaves interrupts turned off 626 */ 627 628 ifp->if_flags |= IFF_PROMISC; 629 sc->re_testmode = 1; 630 re_init(sc); 631 re_stop(sc); 632 DELAY(100000); 633 re_init(sc); 634 635 /* Put some data in the mbuf */ 636 637 eh = mtod(m0, struct ether_header *); 638 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN); 639 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN); 640 eh->ether_type = htons(ETHERTYPE_IP); 641 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 642 643 /* 644 * Queue the packet, start transmission. 645 * Note: ifq_handoff() ultimately calls re_start() for us. 646 */ 647 648 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 649 error = ifq_handoff(ifp, m0, NULL); 650 if (error) { 651 m0 = NULL; 652 goto done; 653 } 654 m0 = NULL; 655 656 /* Wait for it to propagate through the chip */ 657 658 DELAY(100000); 659 for (i = 0; i < RE_TIMEOUT; i++) { 660 status = CSR_READ_2(sc, RE_ISR); 661 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) == 662 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) 663 break; 664 DELAY(10); 665 } 666 667 if (i == RE_TIMEOUT) { 668 if_printf(ifp, "diagnostic failed to receive packet " 669 "in loopback mode\n"); 670 error = EIO; 671 goto done; 672 } 673 674 /* 675 * The packet should have been dumped into the first 676 * entry in the RX DMA ring. Grab it from there. 677 */ 678 679 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 680 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 681 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0], 682 BUS_DMASYNC_POSTWRITE); 683 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]); 684 685 m0 = sc->re_ldata.re_rx_mbuf[0]; 686 sc->re_ldata.re_rx_mbuf[0] = NULL; 687 eh = mtod(m0, struct ether_header *); 688 689 cur_rx = &sc->re_ldata.re_rx_list[0]; 690 total_len = RE_RXBYTES(cur_rx); 691 rxstat = le32toh(cur_rx->re_cmdstat); 692 693 if (total_len != ETHER_MIN_LEN) { 694 if_printf(ifp, "diagnostic failed, received short packet\n"); 695 error = EIO; 696 goto done; 697 } 698 699 /* Test that the received packet data matches what we sent. */ 700 701 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) || 702 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) || 703 be16toh(eh->ether_type) != ETHERTYPE_IP) { 704 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 705 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n", 706 dst, ":", src, ":", ETHERTYPE_IP); 707 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n", 708 eh->ether_dhost, ":", eh->ether_shost, ":", 709 ntohs(eh->ether_type)); 710 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 711 "into a 64-bit PCI slot.\n"); 712 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 713 "for proper operation.\n"); 714 if_printf(ifp, "Read the re(4) man page for more details.\n"); 715 error = EIO; 716 } 717 718 done: 719 /* Turn interface off, release resources */ 720 721 sc->re_testmode = 0; 722 ifp->if_flags &= ~IFF_PROMISC; 723 re_stop(sc); 724 if (m0 != NULL) 725 m_freem(m0); 726 727 return (error); 728 } 729 730 /* 731 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 732 * IDs against our list and return a device name if we find a match. 733 */ 734 static int 735 re_probe(device_t dev) 736 { 737 struct re_type *t; 738 struct re_softc *sc; 739 int rid; 740 uint32_t hwrev; 741 uint16_t vendor, product; 742 743 t = re_devs; 744 745 vendor = pci_get_vendor(dev); 746 product = pci_get_device(dev); 747 748 for (t = re_devs; t->re_name != NULL; t++) { 749 if (product == t->re_did && vendor == t->re_vid) 750 break; 751 } 752 753 /* 754 * Check if we found a RealTek device. 755 */ 756 if (t->re_name == NULL) 757 return(ENXIO); 758 759 /* 760 * Temporarily map the I/O space so we can read the chip ID register. 761 */ 762 sc = malloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO); 763 rid = RE_PCI_LOIO; 764 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 765 RF_ACTIVE); 766 if (sc->re_res == NULL) { 767 device_printf(dev, "couldn't map ports/memory\n"); 768 free(sc, M_TEMP); 769 return(ENXIO); 770 } 771 772 sc->re_btag = rman_get_bustag(sc->re_res); 773 sc->re_bhandle = rman_get_bushandle(sc->re_res); 774 775 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV; 776 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res); 777 free(sc, M_TEMP); 778 779 /* 780 * and continue matching for the specific chip... 781 */ 782 for (; t->re_name != NULL; t++) { 783 if (product == t->re_did && vendor == t->re_vid && 784 t->re_basetype == hwrev) { 785 device_set_desc(dev, t->re_name); 786 return(0); 787 } 788 } 789 return(ENXIO); 790 } 791 792 /* 793 * This routine takes the segment list provided as the result of 794 * a bus_dma_map_load() operation and assigns the addresses/lengths 795 * to RealTek DMA descriptors. This can be called either by the RX 796 * code or the TX code. In the RX case, we'll probably wind up mapping 797 * at most one segment. For the TX case, there could be any number of 798 * segments since TX packets may span multiple mbufs. In either case, 799 * if the number of segments is larger than the re_maxsegs limit 800 * specified by the caller, we abort the mapping operation. Sadly, 801 * whoever designed the buffer mapping API did not provide a way to 802 * return an error from here, so we have to fake it a bit. 803 */ 804 805 static void 806 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, 807 bus_size_t mapsize, int error) 808 { 809 struct re_dmaload_arg *ctx; 810 struct re_desc *d = NULL; 811 int i = 0, idx; 812 uint32_t cmdstat; 813 814 if (error) 815 return; 816 817 ctx = arg; 818 819 /* Signal error to caller if there's too many segments */ 820 if (nseg > ctx->re_maxsegs) { 821 ctx->re_maxsegs = 0; 822 return; 823 } 824 825 /* 826 * Map the segment array into descriptors. Note that we set the 827 * start-of-frame and end-of-frame markers for either TX or RX, but 828 * they really only have meaning in the TX case. (In the RX case, 829 * it's the chip that tells us where packets begin and end.) 830 * We also keep track of the end of the ring and set the 831 * end-of-ring bits as needed, and we set the ownership bits 832 * in all except the very first descriptor. (The caller will 833 * set this descriptor later when it start transmission or 834 * reception.) 835 */ 836 idx = ctx->re_idx; 837 for (;;) { 838 d = &ctx->re_ring[idx]; 839 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) { 840 ctx->re_maxsegs = 0; 841 return; 842 } 843 cmdstat = segs[i].ds_len; 844 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr)); 845 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr)); 846 if (i == 0) 847 cmdstat |= RE_TDESC_CMD_SOF; 848 else 849 cmdstat |= RE_TDESC_CMD_OWN; 850 if (idx == (RE_RX_DESC_CNT - 1)) 851 cmdstat |= RE_TDESC_CMD_EOR; 852 d->re_cmdstat = htole32(cmdstat | ctx->re_flags); 853 i++; 854 if (i == nseg) 855 break; 856 RE_DESC_INC(idx); 857 } 858 859 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF); 860 ctx->re_maxsegs = nseg; 861 ctx->re_idx = idx; 862 } 863 864 /* 865 * Map a single buffer address. 866 */ 867 868 static void 869 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 870 { 871 uint32_t *addr; 872 873 if (error) 874 return; 875 876 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 877 addr = arg; 878 *addr = segs->ds_addr; 879 } 880 881 static int 882 re_allocmem(device_t dev, struct re_softc *sc) 883 { 884 int error, i, nseg; 885 886 /* 887 * Allocate map for RX mbufs. 888 */ 889 nseg = 32; 890 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0, 891 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 892 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 893 &sc->re_ldata.re_mtag); 894 if (error) { 895 device_printf(dev, "could not allocate dma tag\n"); 896 return(error); 897 } 898 899 /* 900 * Allocate map for TX descriptor list. 901 */ 902 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN, 903 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 904 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 905 &sc->re_ldata.re_tx_list_tag); 906 if (error) { 907 device_printf(dev, "could not allocate dma tag\n"); 908 return(error); 909 } 910 911 /* Allocate DMA'able memory for the TX ring */ 912 913 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag, 914 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO, 915 &sc->re_ldata.re_tx_list_map); 916 if (error) { 917 device_printf(dev, "could not allocate TX ring\n"); 918 return(error); 919 } 920 921 /* Load the map for the TX ring. */ 922 923 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag, 924 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 925 RE_TX_LIST_SZ, re_dma_map_addr, 926 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT); 927 if (error) { 928 device_printf(dev, "could not get addres of TX ring\n"); 929 return(error); 930 } 931 932 /* Create DMA maps for TX buffers */ 933 934 for (i = 0; i < RE_TX_DESC_CNT; i++) { 935 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, 936 &sc->re_ldata.re_tx_dmamap[i]); 937 if (error) { 938 device_printf(dev, "can't create DMA map for TX\n"); 939 return(error); 940 } 941 } 942 943 /* 944 * Allocate map for RX descriptor list. 945 */ 946 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN, 947 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 948 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 949 &sc->re_ldata.re_rx_list_tag); 950 if (error) { 951 device_printf(dev, "could not allocate dma tag\n"); 952 return(error); 953 } 954 955 /* Allocate DMA'able memory for the RX ring */ 956 957 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag, 958 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO, 959 &sc->re_ldata.re_rx_list_map); 960 if (error) { 961 device_printf(dev, "could not allocate RX ring\n"); 962 return(error); 963 } 964 965 /* Load the map for the RX ring. */ 966 967 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag, 968 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 969 RE_TX_LIST_SZ, re_dma_map_addr, 970 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT); 971 if (error) { 972 device_printf(dev, "could not get address of RX ring\n"); 973 return(error); 974 } 975 976 /* Create DMA maps for RX buffers */ 977 978 for (i = 0; i < RE_RX_DESC_CNT; i++) { 979 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, 980 &sc->re_ldata.re_rx_dmamap[i]); 981 if (error) { 982 device_printf(dev, "can't create DMA map for RX\n"); 983 return(ENOMEM); 984 } 985 } 986 987 return(0); 988 } 989 990 /* 991 * Attach the interface. Allocate softc structures, do ifmedia 992 * setup and ethernet/BPF attach. 993 */ 994 static int 995 re_attach(device_t dev) 996 { 997 struct re_softc *sc = device_get_softc(dev); 998 struct ifnet *ifp; 999 struct re_hwrev *hw_rev; 1000 uint8_t eaddr[ETHER_ADDR_LEN]; 1001 int hwrev; 1002 u_int16_t re_did = 0; 1003 int error = 0, rid, i; 1004 1005 callout_init(&sc->re_timer); 1006 1007 #ifndef BURN_BRIDGES 1008 /* 1009 * Handle power management nonsense. 1010 */ 1011 1012 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1013 uint32_t membase, irq; 1014 1015 /* Save important PCI config data. */ 1016 membase = pci_read_config(dev, RE_PCI_LOMEM, 4); 1017 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1018 1019 /* Reset the power state. */ 1020 device_printf(dev, "chip is is in D%d power mode " 1021 "-- setting to D0\n", pci_get_powerstate(dev)); 1022 1023 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1024 1025 /* Restore PCI config data. */ 1026 pci_write_config(dev, RE_PCI_LOMEM, membase, 4); 1027 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1028 } 1029 #endif 1030 /* 1031 * Map control/status registers. 1032 */ 1033 pci_enable_busmaster(dev); 1034 1035 rid = RE_PCI_LOIO; 1036 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1037 RF_ACTIVE); 1038 1039 if (sc->re_res == NULL) { 1040 device_printf(dev, "couldn't map ports/memory\n"); 1041 error = ENXIO; 1042 goto fail; 1043 } 1044 1045 sc->re_btag = rman_get_bustag(sc->re_res); 1046 sc->re_bhandle = rman_get_bushandle(sc->re_res); 1047 1048 /* Allocate interrupt */ 1049 rid = 0; 1050 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1051 RF_SHAREABLE | RF_ACTIVE); 1052 1053 if (sc->re_irq == NULL) { 1054 device_printf(dev, "couldn't map interrupt\n"); 1055 error = ENXIO; 1056 goto fail; 1057 } 1058 1059 /* Reset the adapter. */ 1060 re_reset(sc); 1061 1062 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV; 1063 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) { 1064 if (hw_rev->re_rev == hwrev) { 1065 sc->re_type = hw_rev->re_type; 1066 break; 1067 } 1068 } 1069 1070 if (sc->re_type == RE_8169) { 1071 /* Set RX length mask */ 1072 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 1073 1074 /* Force station address autoload from the EEPROM */ 1075 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_AUTOLOAD); 1076 for (i = 0; i < RE_TIMEOUT; i++) { 1077 if ((CSR_READ_1(sc, RE_EECMD) & RE_EEMODE_AUTOLOAD) == 0) 1078 break; 1079 DELAY(100); 1080 } 1081 if (i == RE_TIMEOUT) 1082 device_printf(dev, "eeprom autoload timed out\n"); 1083 1084 for (i = 0; i < ETHER_ADDR_LEN; i++) 1085 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i); 1086 } else { 1087 uint16_t as[3]; 1088 1089 /* Set RX length mask */ 1090 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 1091 1092 sc->re_eecmd_read = RE_EECMD_READ_6BIT; 1093 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1094 if (re_did != 0x8129) 1095 sc->re_eecmd_read = RE_EECMD_READ_8BIT; 1096 1097 /* 1098 * Get station address from the EEPROM. 1099 */ 1100 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3, 0); 1101 for (i = 0; i < 3; i++) { 1102 eaddr[(i * 2) + 0] = as[i] & 0xff; 1103 eaddr[(i * 2) + 1] = as[i] >> 8; 1104 } 1105 } 1106 1107 /* 1108 * Allocate the parent bus DMA tag appropriate for PCI. 1109 */ 1110 #define RE_NSEG_NEW 32 1111 error = bus_dma_tag_create(NULL, /* parent */ 1112 1, 0, /* alignment, boundary */ 1113 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1114 BUS_SPACE_MAXADDR, /* highaddr */ 1115 NULL, NULL, /* filter, filterarg */ 1116 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */ 1117 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1118 BUS_DMA_ALLOCNOW, /* flags */ 1119 &sc->re_parent_tag); 1120 if (error) 1121 goto fail; 1122 1123 error = re_allocmem(dev, sc); 1124 1125 if (error) 1126 goto fail; 1127 1128 /* Do MII setup */ 1129 if (mii_phy_probe(dev, &sc->re_miibus, 1130 re_ifmedia_upd, re_ifmedia_sts)) { 1131 device_printf(dev, "MII without any phy!\n"); 1132 error = ENXIO; 1133 goto fail; 1134 } 1135 1136 ifp = &sc->arpcom.ac_if; 1137 ifp->if_softc = sc; 1138 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1139 ifp->if_mtu = ETHERMTU; 1140 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1141 ifp->if_ioctl = re_ioctl; 1142 ifp->if_capabilities = IFCAP_VLAN_MTU; 1143 ifp->if_start = re_start; 1144 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1145 #ifdef DEVICE_POLLING 1146 ifp->if_poll = re_poll; 1147 #endif 1148 ifp->if_watchdog = re_watchdog; 1149 ifp->if_init = re_init; 1150 if (sc->re_type == RE_8169) 1151 ifp->if_baudrate = 1000000000; 1152 else 1153 ifp->if_baudrate = 100000000; 1154 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN); 1155 ifq_set_ready(&ifp->if_snd); 1156 #ifdef RE_DISABLE_HWCSUM 1157 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1158 ifp->if_hwassist = 0; 1159 #else 1160 ifp->if_capenable = ifp->if_capabilities; 1161 ifp->if_hwassist = RE_CSUM_FEATURES; 1162 #endif 1163 1164 /* 1165 * Call MI attach routine. 1166 */ 1167 ether_ifattach(ifp, eaddr, NULL); 1168 1169 lwkt_serialize_enter(ifp->if_serializer); 1170 /* Perform hardware diagnostic. */ 1171 error = re_diag(sc); 1172 lwkt_serialize_exit(ifp->if_serializer); 1173 1174 if (error) { 1175 device_printf(dev, "hardware diagnostic failure\n"); 1176 ether_ifdetach(ifp); 1177 goto fail; 1178 } 1179 1180 /* Hook interrupt last to avoid having to lock softc */ 1181 error = bus_setup_intr(dev, sc->re_irq, INTR_NETSAFE, re_intr, sc, 1182 &sc->re_intrhand, ifp->if_serializer); 1183 1184 if (error) { 1185 device_printf(dev, "couldn't set up irq\n"); 1186 ether_ifdetach(ifp); 1187 goto fail; 1188 } 1189 1190 fail: 1191 if (error) 1192 re_detach(dev); 1193 1194 return (error); 1195 } 1196 1197 /* 1198 * Shutdown hardware and free up resources. This can be called any 1199 * time after the mutex has been initialized. It is called in both 1200 * the error case in attach and the normal detach case so it needs 1201 * to be careful about only freeing resources that have actually been 1202 * allocated. 1203 */ 1204 static int 1205 re_detach(device_t dev) 1206 { 1207 struct re_softc *sc = device_get_softc(dev); 1208 struct ifnet *ifp = &sc->arpcom.ac_if; 1209 int i; 1210 1211 /* These should only be active if attach succeeded */ 1212 if (device_is_attached(dev)) { 1213 lwkt_serialize_enter(ifp->if_serializer); 1214 re_stop(sc); 1215 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand); 1216 lwkt_serialize_exit(ifp->if_serializer); 1217 1218 ether_ifdetach(ifp); 1219 } 1220 if (sc->re_miibus) 1221 device_delete_child(dev, sc->re_miibus); 1222 bus_generic_detach(dev); 1223 1224 if (sc->re_irq) 1225 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq); 1226 if (sc->re_res) { 1227 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, 1228 sc->re_res); 1229 } 1230 1231 /* Unload and free the RX DMA ring memory and map */ 1232 1233 if (sc->re_ldata.re_rx_list_tag) { 1234 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag, 1235 sc->re_ldata.re_rx_list_map); 1236 bus_dmamem_free(sc->re_ldata.re_rx_list_tag, 1237 sc->re_ldata.re_rx_list, 1238 sc->re_ldata.re_rx_list_map); 1239 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1240 } 1241 1242 /* Unload and free the TX DMA ring memory and map */ 1243 1244 if (sc->re_ldata.re_tx_list_tag) { 1245 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag, 1246 sc->re_ldata.re_tx_list_map); 1247 bus_dmamem_free(sc->re_ldata.re_tx_list_tag, 1248 sc->re_ldata.re_tx_list, 1249 sc->re_ldata.re_tx_list_map); 1250 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1251 } 1252 1253 /* Destroy all the RX and TX buffer maps */ 1254 1255 if (sc->re_ldata.re_mtag) { 1256 for (i = 0; i < RE_TX_DESC_CNT; i++) 1257 bus_dmamap_destroy(sc->re_ldata.re_mtag, 1258 sc->re_ldata.re_tx_dmamap[i]); 1259 for (i = 0; i < RE_RX_DESC_CNT; i++) 1260 bus_dmamap_destroy(sc->re_ldata.re_mtag, 1261 sc->re_ldata.re_rx_dmamap[i]); 1262 bus_dma_tag_destroy(sc->re_ldata.re_mtag); 1263 } 1264 1265 /* Unload and free the stats buffer and map */ 1266 1267 if (sc->re_ldata.re_stag) { 1268 bus_dmamap_unload(sc->re_ldata.re_stag, 1269 sc->re_ldata.re_rx_list_map); 1270 bus_dmamem_free(sc->re_ldata.re_stag, 1271 sc->re_ldata.re_stats, 1272 sc->re_ldata.re_smap); 1273 bus_dma_tag_destroy(sc->re_ldata.re_stag); 1274 } 1275 1276 if (sc->re_parent_tag) 1277 bus_dma_tag_destroy(sc->re_parent_tag); 1278 1279 return(0); 1280 } 1281 1282 static int 1283 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m) 1284 { 1285 struct re_dmaload_arg arg; 1286 struct mbuf *n = NULL; 1287 int error; 1288 1289 if (m == NULL) { 1290 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1291 if (n == NULL) 1292 return(ENOBUFS); 1293 m = n; 1294 } else 1295 m->m_data = m->m_ext.ext_buf; 1296 1297 /* 1298 * Initialize mbuf length fields and fixup 1299 * alignment so that the frame payload is 1300 * longword aligned. 1301 */ 1302 m->m_len = m->m_pkthdr.len = MCLBYTES; 1303 m_adj(m, ETHER_ALIGN); 1304 1305 arg.sc = sc; 1306 arg.re_idx = idx; 1307 arg.re_maxsegs = 1; 1308 arg.re_flags = 0; 1309 arg.re_ring = sc->re_ldata.re_rx_list; 1310 1311 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, 1312 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc, 1313 &arg, BUS_DMA_NOWAIT); 1314 if (error || arg.re_maxsegs != 1) { 1315 if (n != NULL) 1316 m_freem(n); 1317 return (ENOMEM); 1318 } 1319 1320 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN); 1321 sc->re_ldata.re_rx_mbuf[idx] = m; 1322 1323 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx], 1324 BUS_DMASYNC_PREREAD); 1325 1326 return(0); 1327 } 1328 1329 static int 1330 re_tx_list_init(struct re_softc *sc) 1331 { 1332 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ); 1333 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *)); 1334 1335 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1336 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE); 1337 sc->re_ldata.re_tx_prodidx = 0; 1338 sc->re_ldata.re_tx_considx = 0; 1339 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT; 1340 1341 return(0); 1342 } 1343 1344 static int 1345 re_rx_list_init(struct re_softc *sc) 1346 { 1347 int i, error; 1348 1349 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ); 1350 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *)); 1351 1352 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1353 error = re_newbuf(sc, i, NULL); 1354 if (error) 1355 return(error); 1356 } 1357 1358 /* Flush the RX descriptors */ 1359 1360 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1361 sc->re_ldata.re_rx_list_map, 1362 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1363 1364 sc->re_ldata.re_rx_prodidx = 0; 1365 sc->re_head = sc->re_tail = NULL; 1366 1367 return(0); 1368 } 1369 1370 /* 1371 * RX handler for C+ and 8169. For the gigE chips, we support 1372 * the reception of jumbo frames that have been fragmented 1373 * across multiple 2K mbuf cluster buffers. 1374 */ 1375 static void 1376 re_rxeof(struct re_softc *sc) 1377 { 1378 struct ifnet *ifp = &sc->arpcom.ac_if; 1379 struct mbuf *m; 1380 struct re_desc *cur_rx; 1381 uint32_t rxstat, rxvlan; 1382 int i, total_len; 1383 1384 /* Invalidate the descriptor memory */ 1385 1386 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1387 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 1388 1389 for (i = sc->re_ldata.re_rx_prodidx; 1390 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) { 1391 cur_rx = &sc->re_ldata.re_rx_list[i]; 1392 m = sc->re_ldata.re_rx_mbuf[i]; 1393 total_len = RE_RXBYTES(cur_rx); 1394 rxstat = le32toh(cur_rx->re_cmdstat); 1395 rxvlan = le32toh(cur_rx->re_vlanctl); 1396 1397 /* Invalidate the RX mbuf and unload its map */ 1398 1399 bus_dmamap_sync(sc->re_ldata.re_mtag, 1400 sc->re_ldata.re_rx_dmamap[i], 1401 BUS_DMASYNC_POSTWRITE); 1402 bus_dmamap_unload(sc->re_ldata.re_mtag, 1403 sc->re_ldata.re_rx_dmamap[i]); 1404 1405 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1406 m->m_len = MCLBYTES - ETHER_ALIGN; 1407 if (sc->re_head == NULL) { 1408 sc->re_head = sc->re_tail = m; 1409 } else { 1410 sc->re_tail->m_next = m; 1411 sc->re_tail = m; 1412 } 1413 re_newbuf(sc, i, NULL); 1414 continue; 1415 } 1416 1417 /* 1418 * NOTE: for the 8139C+, the frame length field 1419 * is always 12 bits in size, but for the gigE chips, 1420 * it is 13 bits (since the max RX frame length is 16K). 1421 * Unfortunately, all 32 bits in the status word 1422 * were already used, so to make room for the extra 1423 * length bit, RealTek took out the 'frame alignment 1424 * error' bit and shifted the other status bits 1425 * over one slot. The OWN, EOR, FS and LS bits are 1426 * still in the same places. We have already extracted 1427 * the frame length and checked the OWN bit, so rather 1428 * than using an alternate bit mapping, we shift the 1429 * status bits one space to the right so we can evaluate 1430 * them using the 8169 status as though it was in the 1431 * same format as that of the 8139C+. 1432 */ 1433 if (sc->re_type == RE_8169) 1434 rxstat >>= 1; 1435 1436 if (rxstat & RE_RDESC_STAT_RXERRSUM) { 1437 ifp->if_ierrors++; 1438 /* 1439 * If this is part of a multi-fragment packet, 1440 * discard all the pieces. 1441 */ 1442 if (sc->re_head != NULL) { 1443 m_freem(sc->re_head); 1444 sc->re_head = sc->re_tail = NULL; 1445 } 1446 re_newbuf(sc, i, m); 1447 continue; 1448 } 1449 1450 /* 1451 * If allocating a replacement mbuf fails, 1452 * reload the current one. 1453 */ 1454 1455 if (re_newbuf(sc, i, NULL)) { 1456 ifp->if_ierrors++; 1457 if (sc->re_head != NULL) { 1458 m_freem(sc->re_head); 1459 sc->re_head = sc->re_tail = NULL; 1460 } 1461 re_newbuf(sc, i, m); 1462 continue; 1463 } 1464 1465 if (sc->re_head != NULL) { 1466 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN); 1467 /* 1468 * Special case: if there's 4 bytes or less 1469 * in this buffer, the mbuf can be discarded: 1470 * the last 4 bytes is the CRC, which we don't 1471 * care about anyway. 1472 */ 1473 if (m->m_len <= ETHER_CRC_LEN) { 1474 sc->re_tail->m_len -= 1475 (ETHER_CRC_LEN - m->m_len); 1476 m_freem(m); 1477 } else { 1478 m->m_len -= ETHER_CRC_LEN; 1479 sc->re_tail->m_next = m; 1480 } 1481 m = sc->re_head; 1482 sc->re_head = sc->re_tail = NULL; 1483 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1484 } else 1485 m->m_pkthdr.len = m->m_len = 1486 (total_len - ETHER_CRC_LEN); 1487 1488 ifp->if_ipackets++; 1489 m->m_pkthdr.rcvif = ifp; 1490 1491 /* Do RX checksumming if enabled */ 1492 1493 if (ifp->if_capenable & IFCAP_RXCSUM) { 1494 1495 /* Check IP header checksum */ 1496 if (rxstat & RE_RDESC_STAT_PROTOID) 1497 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1498 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0) 1499 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1500 1501 /* Check TCP/UDP checksum */ 1502 if ((RE_TCPPKT(rxstat) && 1503 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) || 1504 (RE_UDPPKT(rxstat) && 1505 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) { 1506 m->m_pkthdr.csum_flags |= 1507 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1508 m->m_pkthdr.csum_data = 0xffff; 1509 } 1510 } 1511 1512 if (rxvlan & RE_RDESC_VLANCTL_TAG) { 1513 VLAN_INPUT_TAG(m, 1514 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA))); 1515 } else { 1516 ifp->if_input(ifp, m); 1517 } 1518 } 1519 1520 /* Flush the RX DMA ring */ 1521 1522 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1523 sc->re_ldata.re_rx_list_map, 1524 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1525 1526 sc->re_ldata.re_rx_prodidx = i; 1527 } 1528 1529 static void 1530 re_txeof(struct re_softc *sc) 1531 { 1532 struct ifnet *ifp = &sc->arpcom.ac_if; 1533 uint32_t txstat; 1534 int idx; 1535 1536 /* Invalidate the TX descriptor list */ 1537 1538 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1539 sc->re_ldata.re_tx_list_map, 1540 BUS_DMASYNC_POSTREAD); 1541 1542 for (idx = sc->re_ldata.re_tx_considx; 1543 idx != sc->re_ldata.re_tx_prodidx; RE_DESC_INC(idx)) { 1544 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat); 1545 if (txstat & RE_TDESC_CMD_OWN) 1546 break; 1547 1548 /* 1549 * We only stash mbufs in the last descriptor 1550 * in a fragment chain, which also happens to 1551 * be the only place where the TX status bits 1552 * are valid. 1553 */ 1554 if (txstat & RE_TDESC_CMD_EOF) { 1555 m_freem(sc->re_ldata.re_tx_mbuf[idx]); 1556 sc->re_ldata.re_tx_mbuf[idx] = NULL; 1557 bus_dmamap_unload(sc->re_ldata.re_mtag, 1558 sc->re_ldata.re_tx_dmamap[idx]); 1559 if (txstat & (RE_TDESC_STAT_EXCESSCOL| 1560 RE_TDESC_STAT_COLCNT)) 1561 ifp->if_collisions++; 1562 if (txstat & RE_TDESC_STAT_TXERRSUM) 1563 ifp->if_oerrors++; 1564 else 1565 ifp->if_opackets++; 1566 } 1567 sc->re_ldata.re_tx_free++; 1568 } 1569 1570 /* No changes made to the TX ring, so no flush needed */ 1571 if (idx != sc->re_ldata.re_tx_considx) { 1572 sc->re_ldata.re_tx_considx = idx; 1573 ifp->if_flags &= ~IFF_OACTIVE; 1574 ifp->if_timer = 0; 1575 } 1576 1577 /* 1578 * If not all descriptors have been released reaped yet, 1579 * reload the timer so that we will eventually get another 1580 * interrupt that will cause us to re-enter this routine. 1581 * This is done in case the transmitter has gone idle. 1582 */ 1583 if (sc->re_ldata.re_tx_free != RE_TX_DESC_CNT) 1584 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 1585 } 1586 1587 static void 1588 re_tick(void *xsc) 1589 { 1590 struct re_softc *sc = xsc; 1591 1592 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1593 re_tick_serialized(xsc); 1594 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1595 } 1596 1597 static void 1598 re_tick_serialized(void *xsc) 1599 { 1600 struct re_softc *sc = xsc; 1601 struct mii_data *mii; 1602 1603 mii = device_get_softc(sc->re_miibus); 1604 mii_tick(mii); 1605 1606 callout_reset(&sc->re_timer, hz, re_tick, sc); 1607 } 1608 1609 #ifdef DEVICE_POLLING 1610 1611 static void 1612 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1613 { 1614 struct re_softc *sc = ifp->if_softc; 1615 1616 switch(cmd) { 1617 case POLL_REGISTER: 1618 /* disable interrupts */ 1619 CSR_WRITE_2(sc, RE_IMR, 0x0000); 1620 break; 1621 case POLL_DEREGISTER: 1622 /* enable interrupts */ 1623 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS); 1624 break; 1625 default: 1626 sc->rxcycles = count; 1627 re_rxeof(sc); 1628 re_txeof(sc); 1629 1630 if (!ifq_is_empty(&ifp->if_snd)) 1631 (*ifp->if_start)(ifp); 1632 1633 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1634 uint16_t status; 1635 1636 status = CSR_READ_2(sc, RE_ISR); 1637 if (status == 0xffff) 1638 return; 1639 if (status) 1640 CSR_WRITE_2(sc, RE_ISR, status); 1641 1642 /* 1643 * XXX check behaviour on receiver stalls. 1644 */ 1645 1646 if (status & RE_ISR_SYSTEM_ERR) { 1647 re_reset(sc); 1648 re_init(sc); 1649 } 1650 } 1651 break; 1652 } 1653 } 1654 #endif /* DEVICE_POLLING */ 1655 1656 static void 1657 re_intr(void *arg) 1658 { 1659 struct re_softc *sc = arg; 1660 struct ifnet *ifp = &sc->arpcom.ac_if; 1661 uint16_t status; 1662 1663 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0) 1664 return; 1665 1666 for (;;) { 1667 status = CSR_READ_2(sc, RE_ISR); 1668 /* If the card has gone away the read returns 0xffff. */ 1669 if (status == 0xffff) 1670 break; 1671 if (status) 1672 CSR_WRITE_2(sc, RE_ISR, status); 1673 1674 if ((status & RE_INTRS_CPLUS) == 0) 1675 break; 1676 1677 if (status & RE_ISR_RX_OK) 1678 re_rxeof(sc); 1679 1680 if (status & RE_ISR_RX_ERR) 1681 re_rxeof(sc); 1682 1683 if ((status & RE_ISR_TIMEOUT_EXPIRED) || 1684 (status & RE_ISR_TX_ERR) || 1685 (status & RE_ISR_TX_DESC_UNAVAIL)) 1686 re_txeof(sc); 1687 1688 if (status & RE_ISR_SYSTEM_ERR) { 1689 re_reset(sc); 1690 re_init(sc); 1691 } 1692 1693 if (status & RE_ISR_LINKCHG) 1694 re_tick_serialized(sc); 1695 } 1696 1697 if (!ifq_is_empty(&ifp->if_snd)) 1698 (*ifp->if_start)(ifp); 1699 } 1700 1701 static int 1702 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx, int *called_defrag) 1703 { 1704 struct ifnet *ifp = &sc->arpcom.ac_if; 1705 struct mbuf *m, *m_new = NULL; 1706 struct re_dmaload_arg arg; 1707 bus_dmamap_t map; 1708 int error; 1709 1710 *called_defrag = 0; 1711 if (sc->re_ldata.re_tx_free <= 4) 1712 return(EFBIG); 1713 1714 m = *m_head; 1715 1716 /* 1717 * Set up checksum offload. Note: checksum offload bits must 1718 * appear in all descriptors of a multi-descriptor transmit 1719 * attempt. (This is according to testing done with an 8169 1720 * chip. I'm not sure if this is a requirement or a bug.) 1721 */ 1722 1723 arg.re_flags = 0; 1724 1725 if (m->m_pkthdr.csum_flags & CSUM_IP) 1726 arg.re_flags |= RE_TDESC_CMD_IPCSUM; 1727 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1728 arg.re_flags |= RE_TDESC_CMD_TCPCSUM; 1729 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1730 arg.re_flags |= RE_TDESC_CMD_UDPCSUM; 1731 1732 arg.sc = sc; 1733 arg.re_idx = *idx; 1734 arg.re_maxsegs = sc->re_ldata.re_tx_free; 1735 if (arg.re_maxsegs > 4) 1736 arg.re_maxsegs -= 4; 1737 arg.re_ring = sc->re_ldata.re_tx_list; 1738 1739 map = sc->re_ldata.re_tx_dmamap[*idx]; 1740 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, 1741 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1742 1743 if (error && error != EFBIG) { 1744 if_printf(ifp, "can't map mbuf (error %d)\n", error); 1745 return(ENOBUFS); 1746 } 1747 1748 /* Too many segments to map, coalesce into a single mbuf */ 1749 1750 if (error || arg.re_maxsegs == 0) { 1751 m_new = m_defrag_nofree(m, MB_DONTWAIT); 1752 if (m_new == NULL) 1753 return(1); 1754 else { 1755 m = m_new; 1756 *m_head = m; 1757 } 1758 1759 *called_defrag = 1; 1760 arg.sc = sc; 1761 arg.re_idx = *idx; 1762 arg.re_maxsegs = sc->re_ldata.re_tx_free; 1763 arg.re_ring = sc->re_ldata.re_tx_list; 1764 1765 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, 1766 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1767 if (error) { 1768 m_freem(m); 1769 if_printf(ifp, "can't map mbuf (error %d)\n", error); 1770 return(EFBIG); 1771 } 1772 } 1773 1774 /* 1775 * Insure that the map for this transmission 1776 * is placed at the array index of the last descriptor 1777 * in this chain. 1778 */ 1779 sc->re_ldata.re_tx_dmamap[*idx] = 1780 sc->re_ldata.re_tx_dmamap[arg.re_idx]; 1781 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map; 1782 1783 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m; 1784 sc->re_ldata.re_tx_free -= arg.re_maxsegs; 1785 1786 /* 1787 * Set up hardware VLAN tagging. Note: vlan tag info must 1788 * appear in the first descriptor of a multi-descriptor 1789 * transmission attempt. 1790 */ 1791 1792 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1793 m->m_pkthdr.rcvif != NULL && 1794 m->m_pkthdr.rcvif->if_type == IFT_L2VLAN) { 1795 struct ifvlan *ifv; 1796 ifv = m->m_pkthdr.rcvif->if_softc; 1797 if (ifv != NULL) 1798 sc->re_ldata.re_tx_list[*idx].re_vlanctl = 1799 htole32(htobe16(ifv->ifv_tag) | RE_TDESC_VLANCTL_TAG); 1800 } 1801 1802 /* Transfer ownership of packet to the chip. */ 1803 1804 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |= 1805 htole32(RE_TDESC_CMD_OWN); 1806 if (*idx != arg.re_idx) 1807 sc->re_ldata.re_tx_list[*idx].re_cmdstat |= 1808 htole32(RE_TDESC_CMD_OWN); 1809 1810 RE_DESC_INC(arg.re_idx); 1811 *idx = arg.re_idx; 1812 1813 return(0); 1814 } 1815 1816 /* 1817 * Main transmit routine for C+ and gigE NICs. 1818 */ 1819 1820 static void 1821 re_start(struct ifnet *ifp) 1822 { 1823 struct re_softc *sc = ifp->if_softc; 1824 struct mbuf *m_head; 1825 struct mbuf *m_head2; 1826 int called_defrag, idx, need_trans; 1827 1828 idx = sc->re_ldata.re_tx_prodidx; 1829 1830 need_trans = 0; 1831 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) { 1832 m_head = ifq_poll(&ifp->if_snd); 1833 if (m_head == NULL) 1834 break; 1835 m_head2 = m_head; 1836 if (re_encap(sc, &m_head2, &idx, &called_defrag)) { 1837 /* 1838 * If we could not encapsulate the defragged packet, 1839 * the returned m_head2 is garbage and we must dequeue 1840 * and throw away the original packet. 1841 */ 1842 if (called_defrag) { 1843 ifq_dequeue(&ifp->if_snd, m_head); 1844 m_freem(m_head); 1845 } 1846 ifp->if_flags |= IFF_OACTIVE; 1847 break; 1848 } 1849 1850 /* 1851 * Clean out the packet we encapsulated. If we defragged 1852 * the packet the m_head2 is the one that got encapsulated 1853 * and the original must be thrown away. Otherwise m_head2 1854 * *IS* the original. 1855 */ 1856 ifq_dequeue(&ifp->if_snd, m_head); 1857 if (called_defrag) 1858 m_freem(m_head); 1859 need_trans = 1; 1860 1861 /* 1862 * If there's a BPF listener, bounce a copy of this frame 1863 * to him. 1864 */ 1865 BPF_MTAP(ifp, m_head2); 1866 } 1867 1868 if (!need_trans) { 1869 return; 1870 } 1871 1872 /* Flush the TX descriptors */ 1873 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1874 sc->re_ldata.re_tx_list_map, 1875 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1876 1877 sc->re_ldata.re_tx_prodidx = idx; 1878 1879 /* 1880 * RealTek put the TX poll request register in a different 1881 * location on the 8169 gigE chip. I don't know why. 1882 */ 1883 if (sc->re_type == RE_8169) 1884 CSR_WRITE_2(sc, RE_GTXSTART, RE_TXSTART_START); 1885 else 1886 CSR_WRITE_2(sc, RE_TXSTART, RE_TXSTART_START); 1887 1888 /* 1889 * Use the countdown timer for interrupt moderation. 1890 * 'TX done' interrupts are disabled. Instead, we reset the 1891 * countdown timer, which will begin counting until it hits 1892 * the value in the TIMERINT register, and then trigger an 1893 * interrupt. Each time we write to the TIMERCNT register, 1894 * the timer count is reset to 0. 1895 */ 1896 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 1897 1898 /* 1899 * Set a timeout in case the chip goes out to lunch. 1900 */ 1901 ifp->if_timer = 5; 1902 } 1903 1904 static void 1905 re_init(void *xsc) 1906 { 1907 struct re_softc *sc = xsc; 1908 struct ifnet *ifp = &sc->arpcom.ac_if; 1909 struct mii_data *mii; 1910 uint32_t rxcfg = 0; 1911 1912 mii = device_get_softc(sc->re_miibus); 1913 1914 /* 1915 * Cancel pending I/O and free all RX/TX buffers. 1916 */ 1917 re_stop(sc); 1918 1919 /* 1920 * Enable C+ RX and TX mode, as well as VLAN stripping and 1921 * RX checksum offload. We must configure the C+ register 1922 * before all others. 1923 */ 1924 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB | 1925 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP | 1926 (ifp->if_capenable & IFCAP_RXCSUM ? 1927 RE_CPLUSCMD_RXCSUM_ENB : 0)); 1928 1929 /* 1930 * Init our MAC address. Even though the chipset 1931 * documentation doesn't mention it, we need to enter "Config 1932 * register write enable" mode to modify the ID registers. 1933 */ 1934 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG); 1935 CSR_WRITE_STREAM_4(sc, RE_IDR0, 1936 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1937 CSR_WRITE_STREAM_4(sc, RE_IDR4, 1938 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1939 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 1940 1941 /* 1942 * For C+ mode, initialize the RX descriptors and mbufs. 1943 */ 1944 re_rx_list_init(sc); 1945 re_tx_list_init(sc); 1946 1947 /* 1948 * Enable transmit and receive. 1949 */ 1950 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 1951 1952 /* 1953 * Set the initial TX and RX configuration. 1954 */ 1955 if (sc->re_testmode) { 1956 if (sc->re_type == RE_8169) 1957 CSR_WRITE_4(sc, RE_TXCFG, 1958 RE_TXCFG_CONFIG | RE_LOOPTEST_ON); 1959 else 1960 CSR_WRITE_4(sc, RE_TXCFG, 1961 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS); 1962 } else 1963 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG); 1964 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG); 1965 1966 /* Set the individual bit to receive frames for this host only. */ 1967 rxcfg = CSR_READ_4(sc, RE_RXCFG); 1968 rxcfg |= RE_RXCFG_RX_INDIV; 1969 1970 /* If we want promiscuous mode, set the allframes bit. */ 1971 if (ifp->if_flags & IFF_PROMISC) { 1972 rxcfg |= RE_RXCFG_RX_ALLPHYS; 1973 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 1974 } else { 1975 rxcfg &= ~RE_RXCFG_RX_ALLPHYS; 1976 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 1977 } 1978 1979 /* 1980 * Set capture broadcast bit to capture broadcast frames. 1981 */ 1982 if (ifp->if_flags & IFF_BROADCAST) { 1983 rxcfg |= RE_RXCFG_RX_BROAD; 1984 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 1985 } else { 1986 rxcfg &= ~RE_RXCFG_RX_BROAD; 1987 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 1988 } 1989 1990 /* 1991 * Program the multicast filter, if necessary. 1992 */ 1993 re_setmulti(sc); 1994 1995 #ifdef DEVICE_POLLING 1996 /* 1997 * Disable interrupts if we are polling. 1998 */ 1999 if (ifp->if_flags & IFF_POLLING) 2000 CSR_WRITE_2(sc, RE_IMR, 0); 2001 else /* otherwise ... */ 2002 #endif /* DEVICE_POLLING */ 2003 /* 2004 * Enable interrupts. 2005 */ 2006 if (sc->re_testmode) 2007 CSR_WRITE_2(sc, RE_IMR, 0); 2008 else 2009 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS); 2010 2011 /* Set initial TX threshold */ 2012 sc->re_txthresh = RE_TX_THRESH_INIT; 2013 2014 /* Start RX/TX process. */ 2015 CSR_WRITE_4(sc, RE_MISSEDPKT, 0); 2016 #ifdef notdef 2017 /* Enable receiver and transmitter. */ 2018 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2019 #endif 2020 /* 2021 * Load the addresses of the RX and TX lists into the chip. 2022 */ 2023 2024 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI, 2025 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr)); 2026 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO, 2027 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr)); 2028 2029 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI, 2030 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr)); 2031 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO, 2032 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr)); 2033 2034 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16); 2035 2036 /* 2037 * Initialize the timer interrupt register so that 2038 * a timer interrupt will be generated once the timer 2039 * reaches a certain number of ticks. The timer is 2040 * reloaded on each transmit. This gives us TX interrupt 2041 * moderation, which dramatically improves TX frame rate. 2042 */ 2043 2044 if (sc->re_type == RE_8169) 2045 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800); 2046 else 2047 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); 2048 2049 /* 2050 * For 8169 gigE NICs, set the max allowed RX packet 2051 * size so we can receive jumbo frames. 2052 */ 2053 if (sc->re_type == RE_8169) 2054 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383); 2055 2056 if (sc->re_testmode) { 2057 return; 2058 } 2059 2060 mii_mediachg(mii); 2061 2062 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX); 2063 2064 ifp->if_flags |= IFF_RUNNING; 2065 ifp->if_flags &= ~IFF_OACTIVE; 2066 2067 callout_reset(&sc->re_timer, hz, re_tick, sc); 2068 } 2069 2070 /* 2071 * Set media options. 2072 */ 2073 static int 2074 re_ifmedia_upd(struct ifnet *ifp) 2075 { 2076 struct re_softc *sc = ifp->if_softc; 2077 struct mii_data *mii; 2078 2079 mii = device_get_softc(sc->re_miibus); 2080 mii_mediachg(mii); 2081 2082 return(0); 2083 } 2084 2085 /* 2086 * Report current media status. 2087 */ 2088 static void 2089 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2090 { 2091 struct re_softc *sc = ifp->if_softc; 2092 struct mii_data *mii; 2093 2094 mii = device_get_softc(sc->re_miibus); 2095 2096 mii_pollstat(mii); 2097 ifmr->ifm_active = mii->mii_media_active; 2098 ifmr->ifm_status = mii->mii_media_status; 2099 } 2100 2101 static int 2102 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2103 { 2104 struct re_softc *sc = ifp->if_softc; 2105 struct ifreq *ifr = (struct ifreq *) data; 2106 struct mii_data *mii; 2107 int error = 0; 2108 2109 switch(command) { 2110 case SIOCSIFMTU: 2111 if (ifr->ifr_mtu > RE_JUMBO_MTU) 2112 error = EINVAL; 2113 ifp->if_mtu = ifr->ifr_mtu; 2114 break; 2115 case SIOCSIFFLAGS: 2116 if (ifp->if_flags & IFF_UP) 2117 re_init(sc); 2118 else if (ifp->if_flags & IFF_RUNNING) 2119 re_stop(sc); 2120 error = 0; 2121 break; 2122 case SIOCADDMULTI: 2123 case SIOCDELMULTI: 2124 re_setmulti(sc); 2125 error = 0; 2126 break; 2127 case SIOCGIFMEDIA: 2128 case SIOCSIFMEDIA: 2129 mii = device_get_softc(sc->re_miibus); 2130 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2131 break; 2132 case SIOCSIFCAP: 2133 ifp->if_capenable &= ~(IFCAP_HWCSUM); 2134 ifp->if_capenable |= 2135 ifr->ifr_reqcap & (IFCAP_HWCSUM); 2136 if (ifp->if_capenable & IFCAP_TXCSUM) 2137 ifp->if_hwassist = RE_CSUM_FEATURES; 2138 else 2139 ifp->if_hwassist = 0; 2140 if (ifp->if_flags & IFF_RUNNING) 2141 re_init(sc); 2142 break; 2143 default: 2144 error = ether_ioctl(ifp, command, data); 2145 break; 2146 } 2147 return(error); 2148 } 2149 2150 static void 2151 re_watchdog(struct ifnet *ifp) 2152 { 2153 struct re_softc *sc = ifp->if_softc; 2154 2155 if_printf(ifp, "watchdog timeout\n"); 2156 2157 ifp->if_oerrors++; 2158 2159 re_txeof(sc); 2160 re_rxeof(sc); 2161 2162 re_init(sc); 2163 2164 if (!ifq_is_empty(&ifp->if_snd)) 2165 ifp->if_start(ifp); 2166 } 2167 2168 /* 2169 * Stop the adapter and free any mbufs allocated to the 2170 * RX and TX lists. 2171 */ 2172 static void 2173 re_stop(struct re_softc *sc) 2174 { 2175 struct ifnet *ifp = &sc->arpcom.ac_if; 2176 int i; 2177 2178 ifp->if_timer = 0; 2179 callout_stop(&sc->re_timer); 2180 2181 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2182 2183 CSR_WRITE_1(sc, RE_COMMAND, 0x00); 2184 CSR_WRITE_2(sc, RE_IMR, 0x0000); 2185 2186 if (sc->re_head != NULL) { 2187 m_freem(sc->re_head); 2188 sc->re_head = sc->re_tail = NULL; 2189 } 2190 2191 /* Free the TX list buffers. */ 2192 for (i = 0; i < RE_TX_DESC_CNT; i++) { 2193 if (sc->re_ldata.re_tx_mbuf[i] != NULL) { 2194 bus_dmamap_unload(sc->re_ldata.re_mtag, 2195 sc->re_ldata.re_tx_dmamap[i]); 2196 m_freem(sc->re_ldata.re_tx_mbuf[i]); 2197 sc->re_ldata.re_tx_mbuf[i] = NULL; 2198 } 2199 } 2200 2201 /* Free the RX list buffers. */ 2202 for (i = 0; i < RE_RX_DESC_CNT; i++) { 2203 if (sc->re_ldata.re_rx_mbuf[i] != NULL) { 2204 bus_dmamap_unload(sc->re_ldata.re_mtag, 2205 sc->re_ldata.re_rx_dmamap[i]); 2206 m_freem(sc->re_ldata.re_rx_mbuf[i]); 2207 sc->re_ldata.re_rx_mbuf[i] = NULL; 2208 } 2209 } 2210 } 2211 2212 /* 2213 * Device suspend routine. Stop the interface and save some PCI 2214 * settings in case the BIOS doesn't restore them properly on 2215 * resume. 2216 */ 2217 static int 2218 re_suspend(device_t dev) 2219 { 2220 #ifndef BURN_BRIDGES 2221 int i; 2222 #endif 2223 struct re_softc *sc = device_get_softc(dev); 2224 2225 re_stop(sc); 2226 2227 #ifndef BURN_BRIDGES 2228 for (i = 0; i < 5; i++) 2229 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2230 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2231 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2232 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2233 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2234 #endif 2235 2236 sc->suspended = 1; 2237 2238 return (0); 2239 } 2240 2241 /* 2242 * Device resume routine. Restore some PCI settings in case the BIOS 2243 * doesn't, re-enable busmastering, and restart the interface if 2244 * appropriate. 2245 */ 2246 static int 2247 re_resume(device_t dev) 2248 { 2249 struct re_softc *sc = device_get_softc(dev); 2250 struct ifnet *ifp = &sc->arpcom.ac_if; 2251 #ifndef BURN_BRIDGES 2252 int i; 2253 #endif 2254 2255 #ifndef BURN_BRIDGES 2256 /* better way to do this? */ 2257 for (i = 0; i < 5; i++) 2258 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2259 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2260 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2261 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2262 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2263 2264 /* reenable busmastering */ 2265 pci_enable_busmaster(dev); 2266 pci_enable_io(dev, SYS_RES_IOPORT); 2267 #endif 2268 2269 /* reinitialize interface if necessary */ 2270 if (ifp->if_flags & IFF_UP) 2271 re_init(sc); 2272 2273 sc->suspended = 0; 2274 2275 return (0); 2276 } 2277 2278 /* 2279 * Stop all chip I/O so that the kernel's probe routines don't 2280 * get confused by errant DMAs when rebooting. 2281 */ 2282 static void 2283 re_shutdown(device_t dev) 2284 { 2285 struct re_softc *sc = device_get_softc(dev); 2286 2287 re_stop(sc); 2288 } 2289