1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $ 36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.33 2007/06/26 07:47:28 hasso Exp $ 37 */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul@windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 51 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7440, so the max MTU possible with this 111 * driver is 7422 bytes. 112 */ 113 114 #include "opt_polling.h" 115 116 #include <sys/param.h> 117 #include <sys/bus.h> 118 #include <sys/endian.h> 119 #include <sys/kernel.h> 120 #include <sys/malloc.h> 121 #include <sys/mbuf.h> 122 /* #include <sys/module.h> */ 123 #include <sys/rman.h> 124 #include <sys/serialize.h> 125 #include <sys/socket.h> 126 #include <sys/sockio.h> 127 #include <sys/sysctl.h> 128 129 #include <net/bpf.h> 130 #include <net/ethernet.h> 131 #include <net/if.h> 132 #include <net/ifq_var.h> 133 #include <net/if_arp.h> 134 #include <net/if_dl.h> 135 #include <net/if_media.h> 136 #include <net/if_types.h> 137 #include <net/vlan/if_vlan_var.h> 138 139 #include <dev/netif/mii_layer/mii.h> 140 #include <dev/netif/mii_layer/miivar.h> 141 142 #include <bus/pci/pcidevs.h> 143 #include <bus/pci/pcireg.h> 144 #include <bus/pci/pcivar.h> 145 146 /* "device miibus" required. See GENERIC if you get errors here. */ 147 #include "miibus_if.h" 148 149 #include <dev/netif/re/if_rereg.h> 150 #include <dev/netif/re/if_revar.h> 151 152 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 153 #if 0 154 #define RE_DISABLE_HWCSUM 155 #endif 156 157 /* 158 * Various supported device vendors/types and their names. 159 */ 160 static const struct re_type re_devs[] = { 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, RE_HWREV_8169S, 162 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 163 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, RE_HWREV_8139CPLUS, 164 "RealTek 8139C+ 10/100BaseTX" }, 165 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, RE_HWREV_8101E, 166 "RealTek 8101E PCIe 10/100baseTX" }, 167 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN1, 168 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 169 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN2, 170 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 171 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169, 172 "RealTek 8169 Gigabit Ethernet" }, 173 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169S, 174 "RealTek 8169S Single-chip Gigabit Ethernet" }, 175 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SB, 176 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" }, 177 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SC, 178 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 179 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, RE_HWREV_8169_8110SC, 180 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 181 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8110S, 182 "RealTek 8110S Single-chip Gigabit Ethernet" }, 183 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, RE_HWREV_8169S, 184 "Corega CG-LAPCIGT Gigabit Ethernet" }, 185 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, RE_HWREV_8169S, 186 "Linksys EG1032 Gigabit Ethernet" }, 187 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, RE_HWREV_8169S, 188 "US Robotics 997902 Gigabit Ethernet" }, 189 { 0, 0, 0, NULL } 190 }; 191 192 static const struct re_hwrev re_hwrevs[] = { 193 { RE_HWREV_8139CPLUS, RE_8139CPLUS, RE_F_HASMPC, "C+" }, 194 { RE_HWREV_8168_SPIN1, RE_8169, RE_F_PCIE, "8168" }, 195 { RE_HWREV_8168_SPIN2, RE_8169, RE_F_PCIE, "8168" }, 196 { RE_HWREV_8169, RE_8169, RE_F_HASMPC, "8169" }, 197 { RE_HWREV_8169S, RE_8169, RE_F_HASMPC, "8169S" }, 198 { RE_HWREV_8110S, RE_8169, RE_F_HASMPC, "8110S" }, 199 { RE_HWREV_8169_8110SB, RE_8169, RE_F_HASMPC, "8169SB" }, 200 { RE_HWREV_8169_8110SC, RE_8169, 0, "8169SC" }, 201 { RE_HWREV_8100E, RE_8169, RE_F_HASMPC, "8100E" }, 202 { RE_HWREV_8101E, RE_8169, RE_F_PCIE, "8101E" }, 203 { 0, 0, 0, NULL } 204 }; 205 206 static int re_probe(device_t); 207 static int re_attach(device_t); 208 static int re_detach(device_t); 209 210 static int re_encap(struct re_softc *, struct mbuf **, int *, int *); 211 212 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int); 213 static void re_dma_map_desc(void *, bus_dma_segment_t *, int, 214 bus_size_t, int); 215 static int re_allocmem(device_t, struct re_softc *); 216 static int re_newbuf(struct re_softc *, int, struct mbuf *); 217 static int re_rx_list_init(struct re_softc *); 218 static int re_tx_list_init(struct re_softc *); 219 static void re_rxeof(struct re_softc *); 220 static void re_txeof(struct re_softc *); 221 static void re_intr(void *); 222 static void re_tick(void *); 223 static void re_tick_serialized(void *); 224 static void re_start(struct ifnet *); 225 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 226 static void re_init(void *); 227 static void re_stop(struct re_softc *); 228 static void re_watchdog(struct ifnet *); 229 static int re_suspend(device_t); 230 static int re_resume(device_t); 231 static void re_shutdown(device_t); 232 static int re_ifmedia_upd(struct ifnet *); 233 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 234 235 static void re_eeprom_putbyte(struct re_softc *, int); 236 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *); 237 static void re_read_eeprom(struct re_softc *, caddr_t, int, int); 238 static int re_gmii_readreg(device_t, int, int); 239 static int re_gmii_writereg(device_t, int, int, int); 240 241 static int re_miibus_readreg(device_t, int, int); 242 static int re_miibus_writereg(device_t, int, int, int); 243 static void re_miibus_statchg(device_t); 244 245 static void re_setmulti(struct re_softc *); 246 static void re_reset(struct re_softc *); 247 248 #ifdef RE_DIAG 249 static int re_diag(struct re_softc *); 250 #endif 251 252 #ifdef DEVICE_POLLING 253 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 254 #endif 255 256 static int re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS); 257 258 static device_method_t re_methods[] = { 259 /* Device interface */ 260 DEVMETHOD(device_probe, re_probe), 261 DEVMETHOD(device_attach, re_attach), 262 DEVMETHOD(device_detach, re_detach), 263 DEVMETHOD(device_suspend, re_suspend), 264 DEVMETHOD(device_resume, re_resume), 265 DEVMETHOD(device_shutdown, re_shutdown), 266 267 /* bus interface */ 268 DEVMETHOD(bus_print_child, bus_generic_print_child), 269 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 270 271 /* MII interface */ 272 DEVMETHOD(miibus_readreg, re_miibus_readreg), 273 DEVMETHOD(miibus_writereg, re_miibus_writereg), 274 DEVMETHOD(miibus_statchg, re_miibus_statchg), 275 276 { 0, 0 } 277 }; 278 279 static driver_t re_driver = { 280 "re", 281 re_methods, 282 sizeof(struct re_softc) 283 }; 284 285 static devclass_t re_devclass; 286 287 DECLARE_DUMMY_MODULE(if_re); 288 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0); 289 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0); 290 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 291 292 #define EE_SET(x) \ 293 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x)) 294 295 #define EE_CLR(x) \ 296 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x)) 297 298 /* 299 * Send a read command and address to the EEPROM, check for ACK. 300 */ 301 static void 302 re_eeprom_putbyte(struct re_softc *sc, int addr) 303 { 304 int d, i; 305 306 d = addr | (RE_9346_READ << sc->re_eewidth); 307 308 /* 309 * Feed in each bit and strobe the clock. 310 */ 311 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) { 312 if (d & i) 313 EE_SET(RE_EE_DATAIN); 314 else 315 EE_CLR(RE_EE_DATAIN); 316 DELAY(100); 317 EE_SET(RE_EE_CLK); 318 DELAY(150); 319 EE_CLR(RE_EE_CLK); 320 DELAY(100); 321 } 322 } 323 324 /* 325 * Read a word of data stored in the EEPROM at address 'addr.' 326 */ 327 static void 328 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest) 329 { 330 int i; 331 uint16_t word = 0; 332 333 /* 334 * Send address of word we want to read. 335 */ 336 re_eeprom_putbyte(sc, addr); 337 338 /* 339 * Start reading bits from EEPROM. 340 */ 341 for (i = 0x8000; i != 0; i >>= 1) { 342 EE_SET(RE_EE_CLK); 343 DELAY(100); 344 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT) 345 word |= i; 346 EE_CLR(RE_EE_CLK); 347 DELAY(100); 348 } 349 350 *dest = word; 351 } 352 353 /* 354 * Read a sequence of words from the EEPROM. 355 */ 356 static void 357 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt) 358 { 359 int i; 360 uint16_t word = 0, *ptr; 361 362 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 363 DELAY(100); 364 365 for (i = 0; i < cnt; i++) { 366 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL); 367 re_eeprom_getword(sc, off + i, &word); 368 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL); 369 ptr = (uint16_t *)(dest + (i * 2)); 370 *ptr = word; 371 } 372 373 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 374 } 375 376 static int 377 re_gmii_readreg(device_t dev, int phy, int reg) 378 { 379 struct re_softc *sc = device_get_softc(dev); 380 u_int32_t rval; 381 int i; 382 383 if (phy != 1) 384 return(0); 385 386 /* Let the rgephy driver read the GMEDIASTAT register */ 387 388 if (reg == RE_GMEDIASTAT) 389 return(CSR_READ_1(sc, RE_GMEDIASTAT)); 390 391 CSR_WRITE_4(sc, RE_PHYAR, reg << 16); 392 DELAY(1000); 393 394 for (i = 0; i < RE_TIMEOUT; i++) { 395 rval = CSR_READ_4(sc, RE_PHYAR); 396 if (rval & RE_PHYAR_BUSY) 397 break; 398 DELAY(100); 399 } 400 401 if (i == RE_TIMEOUT) { 402 device_printf(dev, "PHY read failed\n"); 403 return(0); 404 } 405 406 return(rval & RE_PHYAR_PHYDATA); 407 } 408 409 static int 410 re_gmii_writereg(device_t dev, int phy, int reg, int data) 411 { 412 struct re_softc *sc = device_get_softc(dev); 413 uint32_t rval; 414 int i; 415 416 CSR_WRITE_4(sc, RE_PHYAR, 417 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY); 418 DELAY(1000); 419 420 for (i = 0; i < RE_TIMEOUT; i++) { 421 rval = CSR_READ_4(sc, RE_PHYAR); 422 if ((rval & RE_PHYAR_BUSY) == 0) 423 break; 424 DELAY(100); 425 } 426 427 if (i == RE_TIMEOUT) 428 device_printf(dev, "PHY write failed\n"); 429 430 return(0); 431 } 432 433 static int 434 re_miibus_readreg(device_t dev, int phy, int reg) 435 { 436 struct re_softc *sc = device_get_softc(dev); 437 uint16_t rval = 0; 438 uint16_t re8139_reg = 0; 439 440 if (sc->re_type == RE_8169) { 441 rval = re_gmii_readreg(dev, phy, reg); 442 return(rval); 443 } 444 445 /* Pretend the internal PHY is only at address 0 */ 446 if (phy) 447 return(0); 448 449 switch(reg) { 450 case MII_BMCR: 451 re8139_reg = RE_BMCR; 452 break; 453 case MII_BMSR: 454 re8139_reg = RE_BMSR; 455 break; 456 case MII_ANAR: 457 re8139_reg = RE_ANAR; 458 break; 459 case MII_ANER: 460 re8139_reg = RE_ANER; 461 break; 462 case MII_ANLPAR: 463 re8139_reg = RE_LPAR; 464 break; 465 case MII_PHYIDR1: 466 case MII_PHYIDR2: 467 return(0); 468 /* 469 * Allow the rlphy driver to read the media status 470 * register. If we have a link partner which does not 471 * support NWAY, this is the register which will tell 472 * us the results of parallel detection. 473 */ 474 case RE_MEDIASTAT: 475 return(CSR_READ_1(sc, RE_MEDIASTAT)); 476 default: 477 device_printf(dev, "bad phy register\n"); 478 return(0); 479 } 480 rval = CSR_READ_2(sc, re8139_reg); 481 if (sc->re_type == RE_8139CPLUS && re8139_reg == RE_BMCR) { 482 /* 8139C+ has different bit layout. */ 483 rval &= ~(BMCR_LOOP | BMCR_ISO); 484 } 485 return(rval); 486 } 487 488 static int 489 re_miibus_writereg(device_t dev, int phy, int reg, int data) 490 { 491 struct re_softc *sc= device_get_softc(dev); 492 u_int16_t re8139_reg = 0; 493 494 if (sc->re_type == RE_8169) 495 return(re_gmii_writereg(dev, phy, reg, data)); 496 497 /* Pretend the internal PHY is only at address 0 */ 498 if (phy) 499 return(0); 500 501 switch(reg) { 502 case MII_BMCR: 503 re8139_reg = RE_BMCR; 504 if (sc->re_type == RE_8139CPLUS) { 505 /* 8139C+ has different bit layout. */ 506 data &= ~(BMCR_LOOP | BMCR_ISO); 507 } 508 break; 509 case MII_BMSR: 510 re8139_reg = RE_BMSR; 511 break; 512 case MII_ANAR: 513 re8139_reg = RE_ANAR; 514 break; 515 case MII_ANER: 516 re8139_reg = RE_ANER; 517 break; 518 case MII_ANLPAR: 519 re8139_reg = RE_LPAR; 520 break; 521 case MII_PHYIDR1: 522 case MII_PHYIDR2: 523 return(0); 524 default: 525 device_printf(dev, "bad phy register\n"); 526 return(0); 527 } 528 CSR_WRITE_2(sc, re8139_reg, data); 529 return(0); 530 } 531 532 static void 533 re_miibus_statchg(device_t dev) 534 { 535 } 536 537 /* 538 * Program the 64-bit multicast hash filter. 539 */ 540 static void 541 re_setmulti(struct re_softc *sc) 542 { 543 struct ifnet *ifp = &sc->arpcom.ac_if; 544 int h = 0; 545 uint32_t hashes[2] = { 0, 0 }; 546 struct ifmultiaddr *ifma; 547 uint32_t rxfilt; 548 int mcnt = 0; 549 550 rxfilt = CSR_READ_4(sc, RE_RXCFG); 551 552 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 553 rxfilt |= RE_RXCFG_RX_MULTI; 554 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 555 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF); 556 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF); 557 return; 558 } 559 560 /* first, zot all the existing hash bits */ 561 CSR_WRITE_4(sc, RE_MAR0, 0); 562 CSR_WRITE_4(sc, RE_MAR4, 0); 563 564 /* now program new ones */ 565 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 566 if (ifma->ifma_addr->sa_family != AF_LINK) 567 continue; 568 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 569 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 570 if (h < 32) 571 hashes[0] |= (1 << h); 572 else 573 hashes[1] |= (1 << (h - 32)); 574 mcnt++; 575 } 576 577 if (mcnt) 578 rxfilt |= RE_RXCFG_RX_MULTI; 579 else 580 rxfilt &= ~RE_RXCFG_RX_MULTI; 581 582 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 583 CSR_WRITE_4(sc, RE_MAR0, hashes[0]); 584 CSR_WRITE_4(sc, RE_MAR4, hashes[1]); 585 } 586 587 static void 588 re_reset(struct re_softc *sc) 589 { 590 int i; 591 592 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET); 593 594 for (i = 0; i < RE_TIMEOUT; i++) { 595 DELAY(10); 596 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0) 597 break; 598 } 599 if (i == RE_TIMEOUT) 600 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 601 602 CSR_WRITE_1(sc, 0x82, 1); 603 } 604 605 #ifdef RE_DIAG 606 /* 607 * The following routine is designed to test for a defect on some 608 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 609 * lines connected to the bus, however for a 32-bit only card, they 610 * should be pulled high. The result of this defect is that the 611 * NIC will not work right if you plug it into a 64-bit slot: DMA 612 * operations will be done with 64-bit transfers, which will fail 613 * because the 64-bit data lines aren't connected. 614 * 615 * There's no way to work around this (short of talking a soldering 616 * iron to the board), however we can detect it. The method we use 617 * here is to put the NIC into digital loopback mode, set the receiver 618 * to promiscuous mode, and then try to send a frame. We then compare 619 * the frame data we sent to what was received. If the data matches, 620 * then the NIC is working correctly, otherwise we know the user has 621 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 622 * slot. In the latter case, there's no way the NIC can work correctly, 623 * so we print out a message on the console and abort the device attach. 624 */ 625 626 static int 627 re_diag(struct re_softc *sc) 628 { 629 struct ifnet *ifp = &sc->arpcom.ac_if; 630 struct mbuf *m0; 631 struct ether_header *eh; 632 struct re_desc *cur_rx; 633 uint16_t status; 634 uint32_t rxstat; 635 int total_len, i, error = 0, phyaddr; 636 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 637 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 638 639 /* Allocate a single mbuf */ 640 641 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 642 if (m0 == NULL) 643 return(ENOBUFS); 644 645 /* 646 * Initialize the NIC in test mode. This sets the chip up 647 * so that it can send and receive frames, but performs the 648 * following special functions: 649 * - Puts receiver in promiscuous mode 650 * - Enables digital loopback mode 651 * - Leaves interrupts turned off 652 */ 653 654 ifp->if_flags |= IFF_PROMISC; 655 sc->re_testmode = 1; 656 re_reset(sc); 657 re_init(sc); 658 sc->re_link = 1; 659 if (sc->re_type == RE_8169) 660 phyaddr = 1; 661 else 662 phyaddr = 0; 663 664 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET); 665 for (i = 0; i < RE_TIMEOUT; i++) { 666 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR); 667 if (!(status & BMCR_RESET)) 668 break; 669 } 670 671 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP); 672 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG); 673 674 DELAY(100000); 675 676 /* Put some data in the mbuf */ 677 678 eh = mtod(m0, struct ether_header *); 679 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN); 680 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN); 681 eh->ether_type = htons(ETHERTYPE_IP); 682 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 683 684 /* 685 * Queue the packet, start transmission. 686 * Note: ifq_handoff() ultimately calls re_start() for us. 687 */ 688 689 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 690 error = ifq_handoff(ifp, m0, NULL); 691 if (error) { 692 m0 = NULL; 693 goto done; 694 } 695 m0 = NULL; 696 697 /* Wait for it to propagate through the chip */ 698 699 DELAY(100000); 700 for (i = 0; i < RE_TIMEOUT; i++) { 701 status = CSR_READ_2(sc, RE_ISR); 702 CSR_WRITE_2(sc, RE_ISR, status); 703 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) == 704 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) 705 break; 706 DELAY(10); 707 } 708 709 if (i == RE_TIMEOUT) { 710 if_printf(ifp, "diagnostic failed to receive packet " 711 "in loopback mode\n"); 712 error = EIO; 713 goto done; 714 } 715 716 /* 717 * The packet should have been dumped into the first 718 * entry in the RX DMA ring. Grab it from there. 719 */ 720 721 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 722 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 723 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0], 724 BUS_DMASYNC_POSTWRITE); 725 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]); 726 727 m0 = sc->re_ldata.re_rx_mbuf[0]; 728 sc->re_ldata.re_rx_mbuf[0] = NULL; 729 eh = mtod(m0, struct ether_header *); 730 731 cur_rx = &sc->re_ldata.re_rx_list[0]; 732 total_len = RE_RXBYTES(cur_rx); 733 rxstat = le32toh(cur_rx->re_cmdstat); 734 735 if (total_len != ETHER_MIN_LEN) { 736 if_printf(ifp, "diagnostic failed, received short packet\n"); 737 error = EIO; 738 goto done; 739 } 740 741 /* Test that the received packet data matches what we sent. */ 742 743 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) || 744 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) || 745 be16toh(eh->ether_type) != ETHERTYPE_IP) { 746 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 747 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n", 748 dst, ":", src, ":", ETHERTYPE_IP); 749 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n", 750 eh->ether_dhost, ":", eh->ether_shost, ":", 751 ntohs(eh->ether_type)); 752 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 753 "into a 64-bit PCI slot.\n"); 754 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 755 "for proper operation.\n"); 756 if_printf(ifp, "Read the re(4) man page for more details.\n"); 757 error = EIO; 758 } 759 760 done: 761 /* Turn interface off, release resources */ 762 763 sc->re_testmode = 0; 764 sc->re_link = 0; 765 ifp->if_flags &= ~IFF_PROMISC; 766 re_stop(sc); 767 if (m0 != NULL) 768 m_freem(m0); 769 770 return (error); 771 } 772 #endif /* RE_DIAG */ 773 774 /* 775 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 776 * IDs against our list and return a device name if we find a match. 777 */ 778 static int 779 re_probe(device_t dev) 780 { 781 const struct re_type *t; 782 struct re_softc *sc; 783 int rid; 784 uint32_t hwrev; 785 uint16_t vendor, product; 786 787 t = re_devs; 788 789 vendor = pci_get_vendor(dev); 790 product = pci_get_device(dev); 791 792 /* 793 * Only attach to rev.3 of the Linksys EG1032 adapter. 794 * Rev.2 is supported by sk(4). 795 */ 796 if (vendor == PCI_VENDOR_LINKSYS && 797 product == PCI_PRODUCT_LINKSYS_EG1032 && 798 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3) 799 return ENXIO; 800 801 for (t = re_devs; t->re_name != NULL; t++) { 802 if (product == t->re_did && vendor == t->re_vid) 803 break; 804 } 805 806 /* 807 * Check if we found a RealTek device. 808 */ 809 if (t->re_name == NULL) 810 return(ENXIO); 811 812 /* 813 * Temporarily map the I/O space so we can read the chip ID register. 814 */ 815 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO); 816 rid = RE_PCI_LOIO; 817 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 818 RF_ACTIVE); 819 if (sc->re_res == NULL) { 820 device_printf(dev, "couldn't map ports/memory\n"); 821 kfree(sc, M_TEMP); 822 return(ENXIO); 823 } 824 825 sc->re_btag = rman_get_bustag(sc->re_res); 826 sc->re_bhandle = rman_get_bushandle(sc->re_res); 827 828 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV; 829 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res); 830 kfree(sc, M_TEMP); 831 832 /* 833 * and continue matching for the specific chip... 834 */ 835 for (; t->re_name != NULL; t++) { 836 if (product == t->re_did && vendor == t->re_vid && 837 t->re_basetype == hwrev) { 838 device_set_desc(dev, t->re_name); 839 return(0); 840 } 841 } 842 return(ENXIO); 843 } 844 845 /* 846 * This routine takes the segment list provided as the result of 847 * a bus_dma_map_load() operation and assigns the addresses/lengths 848 * to RealTek DMA descriptors. This can be called either by the RX 849 * code or the TX code. In the RX case, we'll probably wind up mapping 850 * at most one segment. For the TX case, there could be any number of 851 * segments since TX packets may span multiple mbufs. In either case, 852 * if the number of segments is larger than the re_maxsegs limit 853 * specified by the caller, we abort the mapping operation. Sadly, 854 * whoever designed the buffer mapping API did not provide a way to 855 * return an error from here, so we have to fake it a bit. 856 */ 857 858 static void 859 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, 860 bus_size_t mapsize, int error) 861 { 862 struct re_dmaload_arg *ctx; 863 struct re_desc *d = NULL; 864 int i = 0, idx; 865 uint32_t cmdstat; 866 867 if (error) 868 return; 869 870 ctx = arg; 871 872 /* Signal error to caller if there's too many segments */ 873 if (nseg > ctx->re_maxsegs) { 874 ctx->re_maxsegs = 0; 875 return; 876 } 877 878 /* 879 * Map the segment array into descriptors. Note that we set the 880 * start-of-frame and end-of-frame markers for either TX or RX, but 881 * they really only have meaning in the TX case. (In the RX case, 882 * it's the chip that tells us where packets begin and end.) 883 * We also keep track of the end of the ring and set the 884 * end-of-ring bits as needed, and we set the ownership bits 885 * in all except the very first descriptor. (The caller will 886 * set this descriptor later when it start transmission or 887 * reception.) 888 */ 889 idx = ctx->re_idx; 890 for (;;) { 891 d = &ctx->re_ring[idx]; 892 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) { 893 ctx->re_maxsegs = 0; 894 return; 895 } 896 cmdstat = segs[i].ds_len; 897 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr)); 898 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr)); 899 if (i == 0) 900 cmdstat |= RE_TDESC_CMD_SOF; 901 else 902 cmdstat |= RE_TDESC_CMD_OWN; 903 if (idx == (RE_RX_DESC_CNT - 1)) 904 cmdstat |= RE_TDESC_CMD_EOR; 905 d->re_cmdstat = htole32(cmdstat | ctx->re_flags); 906 i++; 907 if (i == nseg) 908 break; 909 RE_DESC_INC(idx); 910 } 911 912 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF); 913 ctx->re_maxsegs = nseg; 914 ctx->re_idx = idx; 915 } 916 917 /* 918 * Map a single buffer address. 919 */ 920 921 static void 922 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 923 { 924 uint32_t *addr; 925 926 if (error) 927 return; 928 929 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 930 addr = arg; 931 *addr = segs->ds_addr; 932 } 933 934 static int 935 re_allocmem(device_t dev, struct re_softc *sc) 936 { 937 int error, i, nseg; 938 939 /* 940 * Allocate map for RX mbufs. 941 */ 942 nseg = 32; 943 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0, 944 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 945 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 946 &sc->re_ldata.re_mtag); 947 if (error) { 948 device_printf(dev, "could not allocate dma tag\n"); 949 return(error); 950 } 951 952 /* 953 * Allocate map for TX descriptor list. 954 */ 955 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN, 956 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 957 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 958 &sc->re_ldata.re_tx_list_tag); 959 if (error) { 960 device_printf(dev, "could not allocate dma tag\n"); 961 return(error); 962 } 963 964 /* Allocate DMA'able memory for the TX ring */ 965 966 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag, 967 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO, 968 &sc->re_ldata.re_tx_list_map); 969 if (error) { 970 device_printf(dev, "could not allocate TX ring\n"); 971 return(error); 972 } 973 974 /* Load the map for the TX ring. */ 975 976 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag, 977 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 978 RE_TX_LIST_SZ, re_dma_map_addr, 979 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT); 980 if (error) { 981 device_printf(dev, "could not get addres of TX ring\n"); 982 return(error); 983 } 984 985 /* Create DMA maps for TX buffers */ 986 987 for (i = 0; i < RE_TX_DESC_CNT; i++) { 988 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, 989 &sc->re_ldata.re_tx_dmamap[i]); 990 if (error) { 991 device_printf(dev, "can't create DMA map for TX\n"); 992 return(error); 993 } 994 } 995 996 /* 997 * Allocate map for RX descriptor list. 998 */ 999 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN, 1000 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1001 NULL, RE_RX_LIST_SZ, 1, RE_RX_LIST_SZ, BUS_DMA_ALLOCNOW, 1002 &sc->re_ldata.re_rx_list_tag); 1003 if (error) { 1004 device_printf(dev, "could not allocate dma tag\n"); 1005 return(error); 1006 } 1007 1008 /* Allocate DMA'able memory for the RX ring */ 1009 1010 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag, 1011 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO, 1012 &sc->re_ldata.re_rx_list_map); 1013 if (error) { 1014 device_printf(dev, "could not allocate RX ring\n"); 1015 return(error); 1016 } 1017 1018 /* Load the map for the RX ring. */ 1019 1020 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag, 1021 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 1022 RE_RX_LIST_SZ, re_dma_map_addr, 1023 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT); 1024 if (error) { 1025 device_printf(dev, "could not get address of RX ring\n"); 1026 return(error); 1027 } 1028 1029 /* Create DMA maps for RX buffers */ 1030 1031 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1032 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, 1033 &sc->re_ldata.re_rx_dmamap[i]); 1034 if (error) { 1035 device_printf(dev, "can't create DMA map for RX\n"); 1036 return(ENOMEM); 1037 } 1038 } 1039 1040 return(0); 1041 } 1042 1043 /* 1044 * Attach the interface. Allocate softc structures, do ifmedia 1045 * setup and ethernet/BPF attach. 1046 */ 1047 static int 1048 re_attach(device_t dev) 1049 { 1050 struct re_softc *sc = device_get_softc(dev); 1051 struct ifnet *ifp; 1052 const struct re_hwrev *hw_rev; 1053 uint8_t eaddr[ETHER_ADDR_LEN]; 1054 uint16_t as[ETHER_ADDR_LEN / 2]; 1055 uint16_t re_did = 0; 1056 uint32_t hwrev; 1057 int error = 0, rid, i; 1058 1059 callout_init(&sc->re_timer); 1060 #ifdef RE_DIAG 1061 sc->re_dev = dev; 1062 #endif 1063 1064 RE_ENABLE_TX_MODERATION(sc); 1065 1066 sysctl_ctx_init(&sc->re_sysctl_ctx); 1067 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx, 1068 SYSCTL_STATIC_CHILDREN(_hw), 1069 OID_AUTO, 1070 device_get_nameunit(dev), 1071 CTLFLAG_RD, 0, ""); 1072 if (sc->re_sysctl_tree == NULL) { 1073 device_printf(dev, "can't add sysctl node\n"); 1074 error = ENXIO; 1075 goto fail; 1076 } 1077 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1078 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1079 OID_AUTO, "tx_moderation", 1080 CTLTYPE_INT | CTLFLAG_RW, 1081 sc, 0, re_sysctl_tx_moderation, "I", 1082 "Enable/Disable TX moderation"); 1083 1084 #ifndef BURN_BRIDGES 1085 /* 1086 * Handle power management nonsense. 1087 */ 1088 1089 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1090 uint32_t membase, irq; 1091 1092 /* Save important PCI config data. */ 1093 membase = pci_read_config(dev, RE_PCI_LOMEM, 4); 1094 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1095 1096 /* Reset the power state. */ 1097 device_printf(dev, "chip is in D%d power mode " 1098 "-- setting to D0\n", pci_get_powerstate(dev)); 1099 1100 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1101 1102 /* Restore PCI config data. */ 1103 pci_write_config(dev, RE_PCI_LOMEM, membase, 4); 1104 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1105 } 1106 #endif 1107 /* 1108 * Map control/status registers. 1109 */ 1110 pci_enable_busmaster(dev); 1111 1112 rid = RE_PCI_LOIO; 1113 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1114 RF_ACTIVE); 1115 1116 if (sc->re_res == NULL) { 1117 device_printf(dev, "couldn't map ports\n"); 1118 error = ENXIO; 1119 goto fail; 1120 } 1121 1122 sc->re_btag = rman_get_bustag(sc->re_res); 1123 sc->re_bhandle = rman_get_bushandle(sc->re_res); 1124 1125 /* Allocate interrupt */ 1126 rid = 0; 1127 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1128 RF_SHAREABLE | RF_ACTIVE); 1129 1130 if (sc->re_irq == NULL) { 1131 device_printf(dev, "couldn't map interrupt\n"); 1132 error = ENXIO; 1133 goto fail; 1134 } 1135 1136 /* Reset the adapter. */ 1137 re_reset(sc); 1138 1139 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV; 1140 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) { 1141 if (hw_rev->re_rev == hwrev) { 1142 sc->re_type = hw_rev->re_type; 1143 sc->re_flags = hw_rev->re_flags; 1144 break; 1145 } 1146 } 1147 1148 sc->re_eewidth = 6; 1149 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1150 if (re_did != 0x8129) 1151 sc->re_eewidth = 8; 1152 1153 /* 1154 * Get station address from the EEPROM. 1155 */ 1156 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3); 1157 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1158 as[i] = le16toh(as[i]); 1159 bcopy(as, eaddr, sizeof(eaddr)); 1160 1161 if (sc->re_type == RE_8169) { 1162 /* Set RX length mask */ 1163 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 1164 sc->re_txstart = RE_GTXSTART; 1165 } else { 1166 /* Set RX length mask */ 1167 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 1168 sc->re_txstart = RE_TXSTART; 1169 } 1170 1171 /* 1172 * Allocate the parent bus DMA tag appropriate for PCI. 1173 */ 1174 #define RE_NSEG_NEW 32 1175 error = bus_dma_tag_create(NULL, /* parent */ 1176 1, 0, /* alignment, boundary */ 1177 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1178 BUS_SPACE_MAXADDR, /* highaddr */ 1179 NULL, NULL, /* filter, filterarg */ 1180 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */ 1181 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1182 BUS_DMA_ALLOCNOW, /* flags */ 1183 &sc->re_parent_tag); 1184 if (error) 1185 goto fail; 1186 1187 error = re_allocmem(dev, sc); 1188 1189 if (error) 1190 goto fail; 1191 1192 /* Do MII setup */ 1193 if (mii_phy_probe(dev, &sc->re_miibus, 1194 re_ifmedia_upd, re_ifmedia_sts)) { 1195 device_printf(dev, "MII without any phy!\n"); 1196 error = ENXIO; 1197 goto fail; 1198 } 1199 1200 ifp = &sc->arpcom.ac_if; 1201 ifp->if_softc = sc; 1202 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1203 ifp->if_mtu = ETHERMTU; 1204 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1205 ifp->if_ioctl = re_ioctl; 1206 ifp->if_capabilities = IFCAP_VLAN_MTU; 1207 ifp->if_start = re_start; 1208 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1209 #ifdef DEVICE_POLLING 1210 ifp->if_poll = re_poll; 1211 #endif 1212 ifp->if_watchdog = re_watchdog; 1213 ifp->if_init = re_init; 1214 if (sc->re_type == RE_8169) 1215 ifp->if_baudrate = 1000000000; 1216 else 1217 ifp->if_baudrate = 100000000; 1218 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN); 1219 ifq_set_ready(&ifp->if_snd); 1220 1221 #ifdef RE_DISABLE_HWCSUM 1222 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1223 ifp->if_hwassist = 0; 1224 #else 1225 ifp->if_capenable = ifp->if_capabilities; 1226 ifp->if_hwassist = RE_CSUM_FEATURES; 1227 #endif /* RE_DISABLE_HWCSUM */ 1228 1229 /* 1230 * Call MI attach routine. 1231 */ 1232 ether_ifattach(ifp, eaddr, NULL); 1233 1234 #ifdef RE_DIAG 1235 /* 1236 * Perform hardware diagnostic on the original RTL8169. 1237 * Some 32-bit cards were incorrectly wired and would 1238 * malfunction if plugged into a 64-bit slot. 1239 */ 1240 if (hwrev == RE_HWREV_8169) { 1241 lwkt_serialize_enter(ifp->if_serializer); 1242 error = re_diag(sc); 1243 lwkt_serialize_exit(ifp->if_serializer); 1244 1245 if (error) { 1246 device_printf(dev, "hardware diagnostic failure\n"); 1247 ether_ifdetach(ifp); 1248 goto fail; 1249 } 1250 } 1251 #endif /* RE_DIAG */ 1252 1253 /* Hook interrupt last to avoid having to lock softc */ 1254 error = bus_setup_intr(dev, sc->re_irq, INTR_NETSAFE, re_intr, sc, 1255 &sc->re_intrhand, ifp->if_serializer); 1256 1257 if (error) { 1258 device_printf(dev, "couldn't set up irq\n"); 1259 ether_ifdetach(ifp); 1260 goto fail; 1261 } 1262 1263 fail: 1264 if (error) 1265 re_detach(dev); 1266 1267 return (error); 1268 } 1269 1270 /* 1271 * Shutdown hardware and free up resources. This can be called any 1272 * time after the mutex has been initialized. It is called in both 1273 * the error case in attach and the normal detach case so it needs 1274 * to be careful about only freeing resources that have actually been 1275 * allocated. 1276 */ 1277 static int 1278 re_detach(device_t dev) 1279 { 1280 struct re_softc *sc = device_get_softc(dev); 1281 struct ifnet *ifp = &sc->arpcom.ac_if; 1282 int i; 1283 1284 /* These should only be active if attach succeeded */ 1285 if (device_is_attached(dev)) { 1286 lwkt_serialize_enter(ifp->if_serializer); 1287 re_stop(sc); 1288 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand); 1289 lwkt_serialize_exit(ifp->if_serializer); 1290 1291 ether_ifdetach(ifp); 1292 } 1293 if (sc->re_miibus) 1294 device_delete_child(dev, sc->re_miibus); 1295 bus_generic_detach(dev); 1296 1297 if (sc->re_irq) 1298 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq); 1299 if (sc->re_res) { 1300 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, 1301 sc->re_res); 1302 } 1303 1304 /* Unload and free the RX DMA ring memory and map */ 1305 1306 if (sc->re_ldata.re_rx_list_tag) { 1307 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag, 1308 sc->re_ldata.re_rx_list_map); 1309 bus_dmamem_free(sc->re_ldata.re_rx_list_tag, 1310 sc->re_ldata.re_rx_list, 1311 sc->re_ldata.re_rx_list_map); 1312 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1313 } 1314 1315 /* Unload and free the TX DMA ring memory and map */ 1316 1317 if (sc->re_ldata.re_tx_list_tag) { 1318 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag, 1319 sc->re_ldata.re_tx_list_map); 1320 bus_dmamem_free(sc->re_ldata.re_tx_list_tag, 1321 sc->re_ldata.re_tx_list, 1322 sc->re_ldata.re_tx_list_map); 1323 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1324 } 1325 1326 /* Destroy all the RX and TX buffer maps */ 1327 1328 if (sc->re_ldata.re_mtag) { 1329 for (i = 0; i < RE_TX_DESC_CNT; i++) 1330 bus_dmamap_destroy(sc->re_ldata.re_mtag, 1331 sc->re_ldata.re_tx_dmamap[i]); 1332 for (i = 0; i < RE_RX_DESC_CNT; i++) 1333 bus_dmamap_destroy(sc->re_ldata.re_mtag, 1334 sc->re_ldata.re_rx_dmamap[i]); 1335 bus_dma_tag_destroy(sc->re_ldata.re_mtag); 1336 } 1337 1338 /* Unload and free the stats buffer and map */ 1339 1340 if (sc->re_ldata.re_stag) { 1341 bus_dmamap_unload(sc->re_ldata.re_stag, 1342 sc->re_ldata.re_rx_list_map); 1343 bus_dmamem_free(sc->re_ldata.re_stag, 1344 sc->re_ldata.re_stats, 1345 sc->re_ldata.re_smap); 1346 bus_dma_tag_destroy(sc->re_ldata.re_stag); 1347 } 1348 1349 if (sc->re_parent_tag) 1350 bus_dma_tag_destroy(sc->re_parent_tag); 1351 1352 return(0); 1353 } 1354 1355 static int 1356 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m) 1357 { 1358 struct re_dmaload_arg arg; 1359 struct mbuf *n = NULL; 1360 int error; 1361 1362 if (m == NULL) { 1363 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1364 if (n == NULL) 1365 return(ENOBUFS); 1366 m = n; 1367 } else 1368 m->m_data = m->m_ext.ext_buf; 1369 1370 m->m_len = m->m_pkthdr.len = MCLBYTES; 1371 1372 /* 1373 * NOTE: 1374 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer 1375 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1376 */ 1377 1378 arg.sc = sc; 1379 arg.re_idx = idx; 1380 arg.re_maxsegs = 1; 1381 arg.re_flags = 0; 1382 arg.re_ring = sc->re_ldata.re_rx_list; 1383 1384 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, 1385 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc, 1386 &arg, BUS_DMA_NOWAIT); 1387 if (error || arg.re_maxsegs != 1) { 1388 if (n != NULL) 1389 m_freem(n); 1390 return (ENOMEM); 1391 } 1392 1393 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN); 1394 sc->re_ldata.re_rx_mbuf[idx] = m; 1395 1396 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx], 1397 BUS_DMASYNC_PREREAD); 1398 1399 return(0); 1400 } 1401 1402 static int 1403 re_tx_list_init(struct re_softc *sc) 1404 { 1405 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ); 1406 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *)); 1407 1408 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1409 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE); 1410 sc->re_ldata.re_tx_prodidx = 0; 1411 sc->re_ldata.re_tx_considx = 0; 1412 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT; 1413 1414 return(0); 1415 } 1416 1417 static int 1418 re_rx_list_init(struct re_softc *sc) 1419 { 1420 int i, error; 1421 1422 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ); 1423 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *)); 1424 1425 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1426 error = re_newbuf(sc, i, NULL); 1427 if (error) 1428 return(error); 1429 } 1430 1431 /* Flush the RX descriptors */ 1432 1433 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1434 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE); 1435 1436 sc->re_ldata.re_rx_prodidx = 0; 1437 sc->re_head = sc->re_tail = NULL; 1438 1439 return(0); 1440 } 1441 1442 /* 1443 * RX handler for C+ and 8169. For the gigE chips, we support 1444 * the reception of jumbo frames that have been fragmented 1445 * across multiple 2K mbuf cluster buffers. 1446 */ 1447 static void 1448 re_rxeof(struct re_softc *sc) 1449 { 1450 struct ifnet *ifp = &sc->arpcom.ac_if; 1451 struct mbuf *m; 1452 struct re_desc *cur_rx; 1453 uint32_t rxstat, rxvlan; 1454 int i, total_len; 1455 1456 /* Invalidate the descriptor memory */ 1457 1458 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1459 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 1460 1461 for (i = sc->re_ldata.re_rx_prodidx; 1462 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) { 1463 cur_rx = &sc->re_ldata.re_rx_list[i]; 1464 m = sc->re_ldata.re_rx_mbuf[i]; 1465 total_len = RE_RXBYTES(cur_rx); 1466 rxstat = le32toh(cur_rx->re_cmdstat); 1467 rxvlan = le32toh(cur_rx->re_vlanctl); 1468 1469 /* Invalidate the RX mbuf and unload its map */ 1470 1471 bus_dmamap_sync(sc->re_ldata.re_mtag, 1472 sc->re_ldata.re_rx_dmamap[i], 1473 BUS_DMASYNC_POSTWRITE); 1474 bus_dmamap_unload(sc->re_ldata.re_mtag, 1475 sc->re_ldata.re_rx_dmamap[i]); 1476 1477 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1478 m->m_len = MCLBYTES - ETHER_ALIGN; 1479 if (sc->re_head == NULL) { 1480 sc->re_head = sc->re_tail = m; 1481 } else { 1482 sc->re_tail->m_next = m; 1483 sc->re_tail = m; 1484 } 1485 re_newbuf(sc, i, NULL); 1486 continue; 1487 } 1488 1489 /* 1490 * NOTE: for the 8139C+, the frame length field 1491 * is always 12 bits in size, but for the gigE chips, 1492 * it is 13 bits (since the max RX frame length is 16K). 1493 * Unfortunately, all 32 bits in the status word 1494 * were already used, so to make room for the extra 1495 * length bit, RealTek took out the 'frame alignment 1496 * error' bit and shifted the other status bits 1497 * over one slot. The OWN, EOR, FS and LS bits are 1498 * still in the same places. We have already extracted 1499 * the frame length and checked the OWN bit, so rather 1500 * than using an alternate bit mapping, we shift the 1501 * status bits one space to the right so we can evaluate 1502 * them using the 8169 status as though it was in the 1503 * same format as that of the 8139C+. 1504 */ 1505 if (sc->re_type == RE_8169) 1506 rxstat >>= 1; 1507 1508 if (rxstat & RE_RDESC_STAT_RXERRSUM) { 1509 ifp->if_ierrors++; 1510 /* 1511 * If this is part of a multi-fragment packet, 1512 * discard all the pieces. 1513 */ 1514 if (sc->re_head != NULL) { 1515 m_freem(sc->re_head); 1516 sc->re_head = sc->re_tail = NULL; 1517 } 1518 re_newbuf(sc, i, m); 1519 continue; 1520 } 1521 1522 /* 1523 * If allocating a replacement mbuf fails, 1524 * reload the current one. 1525 */ 1526 1527 if (re_newbuf(sc, i, NULL)) { 1528 ifp->if_ierrors++; 1529 if (sc->re_head != NULL) { 1530 m_freem(sc->re_head); 1531 sc->re_head = sc->re_tail = NULL; 1532 } 1533 re_newbuf(sc, i, m); 1534 continue; 1535 } 1536 1537 if (sc->re_head != NULL) { 1538 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN); 1539 /* 1540 * Special case: if there's 4 bytes or less 1541 * in this buffer, the mbuf can be discarded: 1542 * the last 4 bytes is the CRC, which we don't 1543 * care about anyway. 1544 */ 1545 if (m->m_len <= ETHER_CRC_LEN) { 1546 sc->re_tail->m_len -= 1547 (ETHER_CRC_LEN - m->m_len); 1548 m_freem(m); 1549 } else { 1550 m->m_len -= ETHER_CRC_LEN; 1551 sc->re_tail->m_next = m; 1552 } 1553 m = sc->re_head; 1554 sc->re_head = sc->re_tail = NULL; 1555 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1556 } else 1557 m->m_pkthdr.len = m->m_len = 1558 (total_len - ETHER_CRC_LEN); 1559 1560 ifp->if_ipackets++; 1561 m->m_pkthdr.rcvif = ifp; 1562 1563 /* Do RX checksumming if enabled */ 1564 1565 if (ifp->if_capenable & IFCAP_RXCSUM) { 1566 1567 /* Check IP header checksum */ 1568 if (rxstat & RE_RDESC_STAT_PROTOID) 1569 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1570 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0) 1571 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1572 1573 /* Check TCP/UDP checksum */ 1574 if ((RE_TCPPKT(rxstat) && 1575 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) || 1576 (RE_UDPPKT(rxstat) && 1577 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) { 1578 m->m_pkthdr.csum_flags |= 1579 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1580 m->m_pkthdr.csum_data = 0xffff; 1581 } 1582 } 1583 1584 if (rxvlan & RE_RDESC_VLANCTL_TAG) { 1585 VLAN_INPUT_TAG(m, 1586 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA))); 1587 } else { 1588 ifp->if_input(ifp, m); 1589 } 1590 } 1591 1592 /* Flush the RX DMA ring */ 1593 1594 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1595 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE); 1596 1597 sc->re_ldata.re_rx_prodidx = i; 1598 } 1599 1600 static void 1601 re_txeof(struct re_softc *sc) 1602 { 1603 struct ifnet *ifp = &sc->arpcom.ac_if; 1604 uint32_t txstat; 1605 int idx; 1606 1607 /* Invalidate the TX descriptor list */ 1608 1609 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1610 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_POSTREAD); 1611 1612 for (idx = sc->re_ldata.re_tx_considx; 1613 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT; RE_DESC_INC(idx)) { 1614 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat); 1615 if (txstat & RE_TDESC_CMD_OWN) 1616 break; 1617 1618 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0; 1619 1620 /* 1621 * We only stash mbufs in the last descriptor 1622 * in a fragment chain, which also happens to 1623 * be the only place where the TX status bits 1624 * are valid. 1625 */ 1626 if (txstat & RE_TDESC_CMD_EOF) { 1627 m_freem(sc->re_ldata.re_tx_mbuf[idx]); 1628 sc->re_ldata.re_tx_mbuf[idx] = NULL; 1629 bus_dmamap_unload(sc->re_ldata.re_mtag, 1630 sc->re_ldata.re_tx_dmamap[idx]); 1631 if (txstat & (RE_TDESC_STAT_EXCESSCOL| 1632 RE_TDESC_STAT_COLCNT)) 1633 ifp->if_collisions++; 1634 if (txstat & RE_TDESC_STAT_TXERRSUM) 1635 ifp->if_oerrors++; 1636 else 1637 ifp->if_opackets++; 1638 } 1639 sc->re_ldata.re_tx_free++; 1640 } 1641 1642 /* No changes made to the TX ring, so no flush needed */ 1643 if (sc->re_ldata.re_tx_free) { 1644 sc->re_ldata.re_tx_considx = idx; 1645 ifp->if_flags &= ~IFF_OACTIVE; 1646 ifp->if_timer = 0; 1647 } 1648 1649 /* 1650 * Some chips will ignore a second TX request issued while an 1651 * existing transmission is in progress. If the transmitter goes 1652 * idle but there are still packets waiting to be sent, we need 1653 * to restart the channel here to flush them out. This only seems 1654 * to be required with the PCIe devices. 1655 */ 1656 if (sc->re_ldata.re_tx_free < RE_TX_DESC_CNT) 1657 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 1658 1659 /* 1660 * If not all descriptors have been released reaped yet, 1661 * reload the timer so that we will eventually get another 1662 * interrupt that will cause us to re-enter this routine. 1663 * This is done in case the transmitter has gone idle. 1664 */ 1665 if (RE_TX_MODERATION_IS_ENABLED(sc) && 1666 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT) 1667 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 1668 } 1669 1670 static void 1671 re_tick(void *xsc) 1672 { 1673 struct re_softc *sc = xsc; 1674 1675 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1676 re_tick_serialized(xsc); 1677 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1678 } 1679 1680 static void 1681 re_tick_serialized(void *xsc) 1682 { 1683 struct re_softc *sc = xsc; 1684 struct ifnet *ifp = &sc->arpcom.ac_if; 1685 struct mii_data *mii; 1686 1687 mii = device_get_softc(sc->re_miibus); 1688 mii_tick(mii); 1689 if (sc->re_link) { 1690 if (!(mii->mii_media_status & IFM_ACTIVE)) 1691 sc->re_link = 0; 1692 } else { 1693 if (mii->mii_media_status & IFM_ACTIVE && 1694 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1695 sc->re_link = 1; 1696 if (!ifq_is_empty(&ifp->if_snd)) 1697 ifp->if_start(ifp); 1698 } 1699 } 1700 1701 callout_reset(&sc->re_timer, hz, re_tick, sc); 1702 } 1703 1704 #ifdef DEVICE_POLLING 1705 1706 static void 1707 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1708 { 1709 struct re_softc *sc = ifp->if_softc; 1710 1711 switch(cmd) { 1712 case POLL_REGISTER: 1713 /* disable interrupts */ 1714 CSR_WRITE_2(sc, RE_IMR, 0x0000); 1715 break; 1716 case POLL_DEREGISTER: 1717 /* enable interrupts */ 1718 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 1719 break; 1720 default: 1721 sc->rxcycles = count; 1722 re_rxeof(sc); 1723 re_txeof(sc); 1724 1725 if (!ifq_is_empty(&ifp->if_snd)) 1726 (*ifp->if_start)(ifp); 1727 1728 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1729 uint16_t status; 1730 1731 status = CSR_READ_2(sc, RE_ISR); 1732 if (status == 0xffff) 1733 return; 1734 if (status) 1735 CSR_WRITE_2(sc, RE_ISR, status); 1736 1737 /* 1738 * XXX check behaviour on receiver stalls. 1739 */ 1740 1741 if (status & RE_ISR_SYSTEM_ERR) { 1742 re_reset(sc); 1743 re_init(sc); 1744 } 1745 } 1746 break; 1747 } 1748 } 1749 #endif /* DEVICE_POLLING */ 1750 1751 static void 1752 re_intr(void *arg) 1753 { 1754 struct re_softc *sc = arg; 1755 struct ifnet *ifp = &sc->arpcom.ac_if; 1756 uint16_t status; 1757 1758 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0) 1759 return; 1760 1761 for (;;) { 1762 status = CSR_READ_2(sc, RE_ISR); 1763 /* If the card has gone away the read returns 0xffff. */ 1764 if (status == 0xffff) 1765 break; 1766 if (status) 1767 CSR_WRITE_2(sc, RE_ISR, status); 1768 1769 if ((status & sc->re_intrs) == 0) 1770 break; 1771 1772 if (status & (RE_ISR_RX_OK | RE_ISR_RX_ERR | RE_ISR_FIFO_OFLOW)) 1773 re_rxeof(sc); 1774 1775 if ((status & sc->re_tx_ack) || 1776 (status & RE_ISR_TX_ERR) || 1777 (status & RE_ISR_TX_DESC_UNAVAIL)) 1778 re_txeof(sc); 1779 1780 if (status & RE_ISR_SYSTEM_ERR) { 1781 re_reset(sc); 1782 re_init(sc); 1783 } 1784 1785 if (status & RE_ISR_LINKCHG) { 1786 callout_stop(&sc->re_timer); 1787 re_tick_serialized(sc); 1788 } 1789 } 1790 1791 if (!ifq_is_empty(&ifp->if_snd)) 1792 (*ifp->if_start)(ifp); 1793 } 1794 1795 static int 1796 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx, int *called_defrag) 1797 { 1798 struct ifnet *ifp = &sc->arpcom.ac_if; 1799 struct mbuf *m, *m_new = NULL; 1800 struct re_dmaload_arg arg; 1801 bus_dmamap_t map; 1802 int error; 1803 1804 *called_defrag = 0; 1805 if (sc->re_ldata.re_tx_free <= 4) 1806 return(EFBIG); 1807 1808 m = *m_head; 1809 1810 /* 1811 * Set up checksum offload. Note: checksum offload bits must 1812 * appear in all descriptors of a multi-descriptor transmit 1813 * attempt. (This is according to testing done with an 8169 1814 * chip. I'm not sure if this is a requirement or a bug.) 1815 */ 1816 1817 arg.re_flags = 0; 1818 1819 if (m->m_pkthdr.csum_flags & CSUM_IP) 1820 arg.re_flags |= RE_TDESC_CMD_IPCSUM; 1821 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1822 arg.re_flags |= RE_TDESC_CMD_TCPCSUM; 1823 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1824 arg.re_flags |= RE_TDESC_CMD_UDPCSUM; 1825 1826 arg.sc = sc; 1827 arg.re_idx = *idx; 1828 arg.re_maxsegs = sc->re_ldata.re_tx_free; 1829 if (arg.re_maxsegs > 4) 1830 arg.re_maxsegs -= 4; 1831 arg.re_ring = sc->re_ldata.re_tx_list; 1832 1833 map = sc->re_ldata.re_tx_dmamap[*idx]; 1834 1835 /* 1836 * With some of the RealTek chips, using the checksum offload 1837 * support in conjunction with the autopadding feature results 1838 * in the transmission of corrupt frames. For example, if we 1839 * need to send a really small IP fragment that's less than 60 1840 * bytes in size, and IP header checksumming is enabled, the 1841 * resulting ethernet frame that appears on the wire will 1842 * have garbled payload. To work around this, if TX checksum 1843 * offload is enabled, we always manually pad short frames out 1844 * to the minimum ethernet frame size. We do this by pretending 1845 * the mbuf chain has too many fragments so the coalescing code 1846 * below can assemble the packet into a single buffer that's 1847 * padded out to the mininum frame size. 1848 * 1849 * Note: this appears unnecessary for TCP, and doing it for TCP 1850 * with PCIe adapters seems to result in bad checksums. 1851 */ 1852 if (arg.re_flags && !(arg.re_flags & RE_TDESC_CMD_TCPCSUM) && 1853 m->m_pkthdr.len < RE_MIN_FRAMELEN) { 1854 error = EFBIG; 1855 } else { 1856 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, 1857 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1858 } 1859 1860 if (error && error != EFBIG) { 1861 if_printf(ifp, "can't map mbuf (error %d)\n", error); 1862 return(ENOBUFS); 1863 } 1864 1865 /* Too many segments to map, coalesce into a single mbuf */ 1866 1867 if (error || arg.re_maxsegs == 0) { 1868 m_new = m_defrag_nofree(m, MB_DONTWAIT); 1869 if (m_new == NULL) { 1870 return(1); 1871 } else { 1872 m = m_new; 1873 *m_head = m; 1874 } 1875 1876 /* 1877 * Manually pad short frames, and zero the pad space 1878 * to avoid leaking data. 1879 */ 1880 if (m_new->m_pkthdr.len < RE_MIN_FRAMELEN) { 1881 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, 1882 RE_MIN_FRAMELEN - m_new->m_pkthdr.len); 1883 m_new->m_pkthdr.len += RE_MIN_FRAMELEN - 1884 m_new->m_pkthdr.len; 1885 m_new->m_len = m_new->m_pkthdr.len; 1886 } 1887 1888 *called_defrag = 1; 1889 arg.sc = sc; 1890 arg.re_idx = *idx; 1891 arg.re_maxsegs = sc->re_ldata.re_tx_free; 1892 arg.re_ring = sc->re_ldata.re_tx_list; 1893 1894 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, 1895 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1896 if (error) { 1897 m_freem(m); 1898 if_printf(ifp, "can't map mbuf (error %d)\n", error); 1899 return(EFBIG); 1900 } 1901 } 1902 1903 /* 1904 * Insure that the map for this transmission 1905 * is placed at the array index of the last descriptor 1906 * in this chain. 1907 */ 1908 sc->re_ldata.re_tx_dmamap[*idx] = 1909 sc->re_ldata.re_tx_dmamap[arg.re_idx]; 1910 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map; 1911 1912 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m; 1913 sc->re_ldata.re_tx_free -= arg.re_maxsegs; 1914 1915 /* 1916 * Set up hardware VLAN tagging. Note: vlan tag info must 1917 * appear in the first descriptor of a multi-descriptor 1918 * transmission attempt. 1919 */ 1920 1921 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1922 m->m_pkthdr.rcvif != NULL && 1923 m->m_pkthdr.rcvif->if_type == IFT_L2VLAN) { 1924 struct ifvlan *ifv; 1925 ifv = m->m_pkthdr.rcvif->if_softc; 1926 if (ifv != NULL) 1927 sc->re_ldata.re_tx_list[*idx].re_vlanctl = 1928 htole32(htobe16(ifv->ifv_tag) | RE_TDESC_VLANCTL_TAG); 1929 } 1930 1931 /* Transfer ownership of packet to the chip. */ 1932 1933 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |= 1934 htole32(RE_TDESC_CMD_OWN); 1935 if (*idx != arg.re_idx) 1936 sc->re_ldata.re_tx_list[*idx].re_cmdstat |= 1937 htole32(RE_TDESC_CMD_OWN); 1938 1939 RE_DESC_INC(arg.re_idx); 1940 *idx = arg.re_idx; 1941 1942 return(0); 1943 } 1944 1945 /* 1946 * Main transmit routine for C+ and gigE NICs. 1947 */ 1948 1949 static void 1950 re_start(struct ifnet *ifp) 1951 { 1952 struct re_softc *sc = ifp->if_softc; 1953 struct mbuf *m_head; 1954 struct mbuf *m_head2; 1955 int called_defrag, idx, need_trans; 1956 1957 if (!sc->re_link || (ifp->if_flags & IFF_OACTIVE)) 1958 return; 1959 1960 idx = sc->re_ldata.re_tx_prodidx; 1961 1962 need_trans = 0; 1963 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) { 1964 m_head = ifq_poll(&ifp->if_snd); 1965 if (m_head == NULL) 1966 break; 1967 m_head2 = m_head; 1968 if (re_encap(sc, &m_head2, &idx, &called_defrag)) { 1969 /* 1970 * If we could not encapsulate the defragged packet, 1971 * the returned m_head2 is garbage and we must dequeue 1972 * and throw away the original packet. 1973 */ 1974 if (called_defrag) { 1975 ifq_dequeue(&ifp->if_snd, m_head); 1976 m_freem(m_head); 1977 } 1978 ifp->if_flags |= IFF_OACTIVE; 1979 break; 1980 } 1981 1982 /* 1983 * Clean out the packet we encapsulated. If we defragged 1984 * the packet the m_head2 is the one that got encapsulated 1985 * and the original must be thrown away. Otherwise m_head2 1986 * *IS* the original. 1987 */ 1988 ifq_dequeue(&ifp->if_snd, m_head); 1989 if (called_defrag) 1990 m_freem(m_head); 1991 need_trans = 1; 1992 1993 /* 1994 * If there's a BPF listener, bounce a copy of this frame 1995 * to him. 1996 */ 1997 BPF_MTAP(ifp, m_head2); 1998 } 1999 2000 if (!need_trans) { 2001 if (RE_TX_MODERATION_IS_ENABLED(sc) && 2002 sc->re_ldata.re_tx_free != RE_TX_DESC_CNT) 2003 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 2004 return; 2005 } 2006 2007 /* Flush the TX descriptors */ 2008 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 2009 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE); 2010 2011 sc->re_ldata.re_tx_prodidx = idx; 2012 2013 /* 2014 * RealTek put the TX poll request register in a different 2015 * location on the 8169 gigE chip. I don't know why. 2016 */ 2017 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2018 2019 if (RE_TX_MODERATION_IS_ENABLED(sc)) { 2020 /* 2021 * Use the countdown timer for interrupt moderation. 2022 * 'TX done' interrupts are disabled. Instead, we reset the 2023 * countdown timer, which will begin counting until it hits 2024 * the value in the TIMERINT register, and then trigger an 2025 * interrupt. Each time we write to the TIMERCNT register, 2026 * the timer count is reset to 0. 2027 */ 2028 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 2029 } 2030 2031 /* 2032 * Set a timeout in case the chip goes out to lunch. 2033 */ 2034 ifp->if_timer = 5; 2035 } 2036 2037 static void 2038 re_init(void *xsc) 2039 { 2040 struct re_softc *sc = xsc; 2041 struct ifnet *ifp = &sc->arpcom.ac_if; 2042 struct mii_data *mii; 2043 uint32_t rxcfg = 0; 2044 2045 mii = device_get_softc(sc->re_miibus); 2046 2047 /* 2048 * Cancel pending I/O and free all RX/TX buffers. 2049 */ 2050 re_stop(sc); 2051 2052 /* 2053 * Enable C+ RX and TX mode, as well as VLAN stripping and 2054 * RX checksum offload. We must configure the C+ register 2055 * before all others. 2056 */ 2057 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB | 2058 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP | 2059 (ifp->if_capenable & IFCAP_RXCSUM ? 2060 RE_CPLUSCMD_RXCSUM_ENB : 0)); 2061 2062 /* 2063 * Init our MAC address. Even though the chipset 2064 * documentation doesn't mention it, we need to enter "Config 2065 * register write enable" mode to modify the ID registers. 2066 */ 2067 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG); 2068 CSR_WRITE_4(sc, RE_IDR0, 2069 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0]))); 2070 CSR_WRITE_2(sc, RE_IDR4, 2071 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4]))); 2072 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 2073 2074 /* 2075 * For C+ mode, initialize the RX descriptors and mbufs. 2076 */ 2077 re_rx_list_init(sc); 2078 re_tx_list_init(sc); 2079 2080 /* 2081 * Load the addresses of the RX and TX lists into the chip. 2082 */ 2083 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI, 2084 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr)); 2085 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO, 2086 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr)); 2087 2088 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI, 2089 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr)); 2090 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO, 2091 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr)); 2092 2093 /* 2094 * Enable transmit and receive. 2095 */ 2096 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2097 2098 /* 2099 * Set the initial TX and RX configuration. 2100 */ 2101 if (sc->re_testmode) { 2102 if (sc->re_type == RE_8169) 2103 CSR_WRITE_4(sc, RE_TXCFG, 2104 RE_TXCFG_CONFIG | RE_LOOPTEST_ON); 2105 else 2106 CSR_WRITE_4(sc, RE_TXCFG, 2107 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS); 2108 } else 2109 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG); 2110 2111 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16); 2112 2113 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG); 2114 2115 /* Set the individual bit to receive frames for this host only. */ 2116 rxcfg = CSR_READ_4(sc, RE_RXCFG); 2117 rxcfg |= RE_RXCFG_RX_INDIV; 2118 2119 /* If we want promiscuous mode, set the allframes bit. */ 2120 if (ifp->if_flags & IFF_PROMISC) { 2121 rxcfg |= RE_RXCFG_RX_ALLPHYS; 2122 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 2123 } else { 2124 rxcfg &= ~RE_RXCFG_RX_ALLPHYS; 2125 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 2126 } 2127 2128 /* 2129 * Set capture broadcast bit to capture broadcast frames. 2130 */ 2131 if (ifp->if_flags & IFF_BROADCAST) { 2132 rxcfg |= RE_RXCFG_RX_BROAD; 2133 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 2134 } else { 2135 rxcfg &= ~RE_RXCFG_RX_BROAD; 2136 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 2137 } 2138 2139 /* 2140 * Program the multicast filter, if necessary. 2141 */ 2142 re_setmulti(sc); 2143 2144 #ifdef DEVICE_POLLING 2145 /* 2146 * Disable interrupts if we are polling. 2147 */ 2148 if (ifp->if_flags & IFF_POLLING) 2149 CSR_WRITE_2(sc, RE_IMR, 0); 2150 else /* otherwise ... */ 2151 #endif /* DEVICE_POLLING */ 2152 /* 2153 * Enable interrupts. 2154 */ 2155 if (sc->re_testmode) 2156 CSR_WRITE_2(sc, RE_IMR, 0); 2157 else 2158 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 2159 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs); 2160 2161 /* Set initial TX threshold */ 2162 sc->re_txthresh = RE_TX_THRESH_INIT; 2163 2164 /* Start RX/TX process. */ 2165 if (sc->re_flags & RE_F_HASMPC) 2166 CSR_WRITE_4(sc, RE_MISSEDPKT, 0); 2167 #ifdef notdef 2168 /* Enable receiver and transmitter. */ 2169 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2170 #endif 2171 2172 if (RE_TX_MODERATION_IS_ENABLED(sc)) { 2173 /* 2174 * Initialize the timer interrupt register so that 2175 * a timer interrupt will be generated once the timer 2176 * reaches a certain number of ticks. The timer is 2177 * reloaded on each transmit. This gives us TX interrupt 2178 * moderation, which dramatically improves TX frame rate. 2179 */ 2180 if (sc->re_type == RE_8169) 2181 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800); 2182 else 2183 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); 2184 } 2185 2186 /* 2187 * For 8169 gigE NICs, set the max allowed RX packet 2188 * size so we can receive jumbo frames. 2189 */ 2190 if (sc->re_type == RE_8169) 2191 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383); 2192 2193 if (sc->re_testmode) { 2194 return; 2195 } 2196 2197 mii_mediachg(mii); 2198 2199 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX); 2200 2201 ifp->if_flags |= IFF_RUNNING; 2202 ifp->if_flags &= ~IFF_OACTIVE; 2203 2204 sc->re_link = 0; 2205 callout_reset(&sc->re_timer, hz, re_tick, sc); 2206 } 2207 2208 /* 2209 * Set media options. 2210 */ 2211 static int 2212 re_ifmedia_upd(struct ifnet *ifp) 2213 { 2214 struct re_softc *sc = ifp->if_softc; 2215 struct mii_data *mii; 2216 2217 mii = device_get_softc(sc->re_miibus); 2218 mii_mediachg(mii); 2219 2220 return(0); 2221 } 2222 2223 /* 2224 * Report current media status. 2225 */ 2226 static void 2227 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2228 { 2229 struct re_softc *sc = ifp->if_softc; 2230 struct mii_data *mii; 2231 2232 mii = device_get_softc(sc->re_miibus); 2233 2234 mii_pollstat(mii); 2235 ifmr->ifm_active = mii->mii_media_active; 2236 ifmr->ifm_status = mii->mii_media_status; 2237 } 2238 2239 static int 2240 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2241 { 2242 struct re_softc *sc = ifp->if_softc; 2243 struct ifreq *ifr = (struct ifreq *) data; 2244 struct mii_data *mii; 2245 int error = 0; 2246 2247 switch(command) { 2248 case SIOCSIFMTU: 2249 if (ifr->ifr_mtu > RE_JUMBO_MTU) 2250 error = EINVAL; 2251 ifp->if_mtu = ifr->ifr_mtu; 2252 break; 2253 case SIOCSIFFLAGS: 2254 if (ifp->if_flags & IFF_UP) 2255 re_init(sc); 2256 else if (ifp->if_flags & IFF_RUNNING) 2257 re_stop(sc); 2258 break; 2259 case SIOCADDMULTI: 2260 case SIOCDELMULTI: 2261 re_setmulti(sc); 2262 error = 0; 2263 break; 2264 case SIOCGIFMEDIA: 2265 case SIOCSIFMEDIA: 2266 mii = device_get_softc(sc->re_miibus); 2267 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2268 break; 2269 case SIOCSIFCAP: 2270 ifp->if_capenable &= ~(IFCAP_HWCSUM); 2271 ifp->if_capenable |= 2272 ifr->ifr_reqcap & (IFCAP_HWCSUM); 2273 if (ifp->if_capenable & IFCAP_TXCSUM) 2274 ifp->if_hwassist = RE_CSUM_FEATURES; 2275 else 2276 ifp->if_hwassist = 0; 2277 if (ifp->if_flags & IFF_RUNNING) 2278 re_init(sc); 2279 break; 2280 default: 2281 error = ether_ioctl(ifp, command, data); 2282 break; 2283 } 2284 return(error); 2285 } 2286 2287 static void 2288 re_watchdog(struct ifnet *ifp) 2289 { 2290 struct re_softc *sc = ifp->if_softc; 2291 2292 if_printf(ifp, "watchdog timeout\n"); 2293 2294 ifp->if_oerrors++; 2295 2296 re_txeof(sc); 2297 re_rxeof(sc); 2298 2299 re_init(sc); 2300 2301 if (!ifq_is_empty(&ifp->if_snd)) 2302 ifp->if_start(ifp); 2303 } 2304 2305 /* 2306 * Stop the adapter and free any mbufs allocated to the 2307 * RX and TX lists. 2308 */ 2309 static void 2310 re_stop(struct re_softc *sc) 2311 { 2312 struct ifnet *ifp = &sc->arpcom.ac_if; 2313 int i; 2314 2315 ifp->if_timer = 0; 2316 callout_stop(&sc->re_timer); 2317 2318 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2319 2320 CSR_WRITE_1(sc, RE_COMMAND, 0x00); 2321 CSR_WRITE_2(sc, RE_IMR, 0x0000); 2322 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 2323 2324 if (sc->re_head != NULL) { 2325 m_freem(sc->re_head); 2326 sc->re_head = sc->re_tail = NULL; 2327 } 2328 2329 /* Free the TX list buffers. */ 2330 for (i = 0; i < RE_TX_DESC_CNT; i++) { 2331 if (sc->re_ldata.re_tx_mbuf[i] != NULL) { 2332 bus_dmamap_unload(sc->re_ldata.re_mtag, 2333 sc->re_ldata.re_tx_dmamap[i]); 2334 m_freem(sc->re_ldata.re_tx_mbuf[i]); 2335 sc->re_ldata.re_tx_mbuf[i] = NULL; 2336 } 2337 } 2338 2339 /* Free the RX list buffers. */ 2340 for (i = 0; i < RE_RX_DESC_CNT; i++) { 2341 if (sc->re_ldata.re_rx_mbuf[i] != NULL) { 2342 bus_dmamap_unload(sc->re_ldata.re_mtag, 2343 sc->re_ldata.re_rx_dmamap[i]); 2344 m_freem(sc->re_ldata.re_rx_mbuf[i]); 2345 sc->re_ldata.re_rx_mbuf[i] = NULL; 2346 } 2347 } 2348 } 2349 2350 /* 2351 * Device suspend routine. Stop the interface and save some PCI 2352 * settings in case the BIOS doesn't restore them properly on 2353 * resume. 2354 */ 2355 static int 2356 re_suspend(device_t dev) 2357 { 2358 #ifndef BURN_BRIDGES 2359 int i; 2360 #endif 2361 struct re_softc *sc = device_get_softc(dev); 2362 2363 re_stop(sc); 2364 2365 #ifndef BURN_BRIDGES 2366 for (i = 0; i < 5; i++) 2367 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2368 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2369 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2370 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2371 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2372 #endif 2373 2374 sc->suspended = 1; 2375 2376 return (0); 2377 } 2378 2379 /* 2380 * Device resume routine. Restore some PCI settings in case the BIOS 2381 * doesn't, re-enable busmastering, and restart the interface if 2382 * appropriate. 2383 */ 2384 static int 2385 re_resume(device_t dev) 2386 { 2387 struct re_softc *sc = device_get_softc(dev); 2388 struct ifnet *ifp = &sc->arpcom.ac_if; 2389 #ifndef BURN_BRIDGES 2390 int i; 2391 #endif 2392 2393 #ifndef BURN_BRIDGES 2394 /* better way to do this? */ 2395 for (i = 0; i < 5; i++) 2396 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2397 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2398 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2399 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2400 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2401 2402 /* reenable busmastering */ 2403 pci_enable_busmaster(dev); 2404 pci_enable_io(dev, SYS_RES_IOPORT); 2405 #endif 2406 2407 /* reinitialize interface if necessary */ 2408 if (ifp->if_flags & IFF_UP) 2409 re_init(sc); 2410 2411 sc->suspended = 0; 2412 2413 return (0); 2414 } 2415 2416 /* 2417 * Stop all chip I/O so that the kernel's probe routines don't 2418 * get confused by errant DMAs when rebooting. 2419 */ 2420 static void 2421 re_shutdown(device_t dev) 2422 { 2423 struct re_softc *sc = device_get_softc(dev); 2424 struct ifnet *ifp = &sc->arpcom.ac_if; 2425 2426 lwkt_serialize_enter(ifp->if_serializer); 2427 re_stop(sc); 2428 lwkt_serialize_exit(ifp->if_serializer); 2429 } 2430 2431 static int 2432 re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS) 2433 { 2434 struct re_softc *sc = arg1; 2435 struct ifnet *ifp = &sc->arpcom.ac_if; 2436 int error = 0, mod, mod_old; 2437 2438 lwkt_serialize_enter(ifp->if_serializer); 2439 2440 mod_old = mod = RE_TX_MODERATION_IS_ENABLED(sc); 2441 2442 error = sysctl_handle_int(oidp, &mod, 0, req); 2443 if (error || req->newptr == NULL || mod == mod_old) 2444 goto back; 2445 if (mod != 0 && mod != 1) { 2446 error = EINVAL; 2447 goto back; 2448 } 2449 2450 if (mod) 2451 RE_ENABLE_TX_MODERATION(sc); 2452 else 2453 RE_DISABLE_TX_MODERATION(sc); 2454 2455 if ((ifp->if_flags & (IFF_RUNNING | IFF_UP)) == (IFF_RUNNING | IFF_UP)) 2456 re_init(sc); 2457 back: 2458 lwkt_serialize_exit(ifp->if_serializer); 2459 return error; 2460 } 2461