1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $ 36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.99 2008/10/30 11:27:40 sephe Exp $ 37 */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul@windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 51 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7440, so the max MTU possible with this 111 * driver is 7422 bytes. 112 */ 113 114 #define _IP_VHL 115 116 #include "opt_polling.h" 117 118 #include <sys/param.h> 119 #include <sys/bus.h> 120 #include <sys/endian.h> 121 #include <sys/kernel.h> 122 #include <sys/in_cksum.h> 123 #include <sys/interrupt.h> 124 #include <sys/malloc.h> 125 #include <sys/mbuf.h> 126 #include <sys/rman.h> 127 #include <sys/serialize.h> 128 #include <sys/socket.h> 129 #include <sys/sockio.h> 130 #include <sys/sysctl.h> 131 132 #include <net/bpf.h> 133 #include <net/ethernet.h> 134 #include <net/if.h> 135 #include <net/ifq_var.h> 136 #include <net/if_arp.h> 137 #include <net/if_dl.h> 138 #include <net/if_media.h> 139 #include <net/if_types.h> 140 #include <net/vlan/if_vlan_var.h> 141 #include <net/vlan/if_vlan_ether.h> 142 143 #include <netinet/ip.h> 144 145 #include <dev/netif/mii_layer/mii.h> 146 #include <dev/netif/mii_layer/miivar.h> 147 148 #include <bus/pci/pcidevs.h> 149 #include <bus/pci/pcireg.h> 150 #include <bus/pci/pcivar.h> 151 152 /* "device miibus" required. See GENERIC if you get errors here. */ 153 #include "miibus_if.h" 154 155 #include <dev/netif/re/if_rereg.h> 156 #include <dev/netif/re/if_revar.h> 157 158 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 159 160 /* 161 * Various supported device vendors/types and their names. 162 */ 163 static const struct re_type { 164 uint16_t re_vid; 165 uint16_t re_did; 166 const char *re_name; 167 } re_devs[] = { 168 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, 169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 170 171 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, 172 "RealTek 8139C+ 10/100BaseTX" }, 173 174 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, 175 "RealTek 810x PCIe 10/100baseTX" }, 176 177 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, 178 "RealTek 8111/8168 PCIe Gigabit Ethernet" }, 179 180 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, 181 "RealTek 8110/8169 Gigabit Ethernet" }, 182 183 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, 184 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 185 186 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, 187 "Corega CG-LAPCIGT Gigabit Ethernet" }, 188 189 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, 190 "Linksys EG1032 Gigabit Ethernet" }, 191 192 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, 193 "US Robotics 997902 Gigabit Ethernet" }, 194 195 { PCI_VENDOR_TTTECH, PCI_PRODUCT_TTTECH_MC322, 196 "TTTech MC322 Gigabit Ethernet" }, 197 198 { 0, 0, NULL } 199 }; 200 201 static const struct re_hwrev re_hwrevs[] = { 202 { RE_HWREV_8139CPLUS, RE_MACVER_UNKN, ETHERMTU, 203 RE_C_HWCSUM | RE_C_8139CP | RE_C_FASTE }, 204 205 { RE_HWREV_8169, RE_MACVER_UNKN, ETHERMTU, 206 RE_C_HWCSUM | RE_C_8169 }, 207 208 { RE_HWREV_8110S, RE_MACVER_03, RE_MTU_6K, 209 RE_C_HWCSUM | RE_C_8169 }, 210 211 { RE_HWREV_8169S, RE_MACVER_03, RE_MTU_6K, 212 RE_C_HWCSUM | RE_C_8169 }, 213 214 { RE_HWREV_8169SB, RE_MACVER_04, RE_MTU_6K, 215 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 216 217 { RE_HWREV_8169SC1, RE_MACVER_05, RE_MTU_6K, 218 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 219 220 { RE_HWREV_8169SC2, RE_MACVER_06, RE_MTU_6K, 221 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 222 223 { RE_HWREV_8168B1, RE_MACVER_21, RE_MTU_6K, 224 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT }, 225 226 { RE_HWREV_8168B2, RE_MACVER_23, RE_MTU_6K, 227 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD }, 228 229 { RE_HWREV_8168B3, RE_MACVER_23, RE_MTU_6K, 230 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD }, 231 232 { RE_HWREV_8168C, RE_MACVER_29, RE_MTU_6K, 233 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 234 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 235 236 { RE_HWREV_8168CP, RE_MACVER_2B, RE_MTU_6K, 237 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 238 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 239 240 { RE_HWREV_8168D, RE_MACVER_2A, RE_MTU_9K, 241 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 242 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 243 244 { RE_HWREV_8100E, RE_MACVER_UNKN, ETHERMTU, 245 RE_C_HWCSUM | RE_C_FASTE }, 246 247 { RE_HWREV_8101E1, RE_MACVER_16, ETHERMTU, 248 RE_C_HWCSUM | RE_C_FASTE }, 249 250 { RE_HWREV_8101E2, RE_MACVER_16, ETHERMTU, 251 RE_C_HWCSUM | RE_C_FASTE }, 252 253 { RE_HWREV_8102E, RE_MACVER_15, ETHERMTU, 254 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX | 255 RE_C_FASTE }, 256 257 { RE_HWREV_8102EL, RE_MACVER_15, ETHERMTU, 258 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX | 259 RE_C_FASTE }, 260 261 { RE_HWREV_NULL, 0, 0, 0 } 262 }; 263 264 static int re_probe(device_t); 265 static int re_attach(device_t); 266 static int re_detach(device_t); 267 static int re_suspend(device_t); 268 static int re_resume(device_t); 269 static void re_shutdown(device_t); 270 271 static int re_allocmem(device_t); 272 static void re_freemem(device_t); 273 static void re_freebufmem(struct re_softc *, int, int); 274 static int re_encap(struct re_softc *, struct mbuf **, int *); 275 static int re_newbuf_std(struct re_softc *, int, int); 276 static int re_newbuf_jumbo(struct re_softc *, int, int); 277 static void re_setup_rxdesc(struct re_softc *, int); 278 static int re_rx_list_init(struct re_softc *); 279 static int re_tx_list_init(struct re_softc *); 280 static int re_rxeof(struct re_softc *); 281 static int re_txeof(struct re_softc *); 282 static int re_tx_collect(struct re_softc *); 283 static void re_intr(void *); 284 static void re_tick(void *); 285 static void re_tick_serialized(void *); 286 287 static void re_start(struct ifnet *); 288 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 289 static void re_init(void *); 290 static void re_stop(struct re_softc *); 291 static void re_watchdog(struct ifnet *); 292 static int re_ifmedia_upd(struct ifnet *); 293 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 294 295 static void re_eeprom_putbyte(struct re_softc *, int); 296 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *); 297 static void re_read_eeprom(struct re_softc *, caddr_t, int, int); 298 static void re_get_eewidth(struct re_softc *); 299 300 static int re_gmii_readreg(device_t, int, int); 301 static int re_gmii_writereg(device_t, int, int, int); 302 303 static int re_miibus_readreg(device_t, int, int); 304 static int re_miibus_writereg(device_t, int, int, int); 305 static void re_miibus_statchg(device_t); 306 307 static void re_setmulti(struct re_softc *); 308 static void re_reset(struct re_softc *, int); 309 static void re_get_eaddr(struct re_softc *, uint8_t *); 310 311 static void re_setup_hw_im(struct re_softc *); 312 static void re_setup_sim_im(struct re_softc *); 313 static void re_disable_hw_im(struct re_softc *); 314 static void re_disable_sim_im(struct re_softc *); 315 static void re_config_imtype(struct re_softc *, int); 316 static void re_setup_intr(struct re_softc *, int, int); 317 318 static int re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *); 319 static int re_sysctl_rxtime(SYSCTL_HANDLER_ARGS); 320 static int re_sysctl_txtime(SYSCTL_HANDLER_ARGS); 321 static int re_sysctl_simtime(SYSCTL_HANDLER_ARGS); 322 static int re_sysctl_imtype(SYSCTL_HANDLER_ARGS); 323 324 static int re_jpool_alloc(struct re_softc *); 325 static void re_jpool_free(struct re_softc *); 326 static struct re_jbuf *re_jbuf_alloc(struct re_softc *); 327 static void re_jbuf_free(void *); 328 static void re_jbuf_ref(void *); 329 330 #ifdef RE_DIAG 331 static int re_diag(struct re_softc *); 332 #endif 333 334 #ifdef DEVICE_POLLING 335 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 336 #endif 337 338 static device_method_t re_methods[] = { 339 /* Device interface */ 340 DEVMETHOD(device_probe, re_probe), 341 DEVMETHOD(device_attach, re_attach), 342 DEVMETHOD(device_detach, re_detach), 343 DEVMETHOD(device_suspend, re_suspend), 344 DEVMETHOD(device_resume, re_resume), 345 DEVMETHOD(device_shutdown, re_shutdown), 346 347 /* bus interface */ 348 DEVMETHOD(bus_print_child, bus_generic_print_child), 349 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 350 351 /* MII interface */ 352 DEVMETHOD(miibus_readreg, re_miibus_readreg), 353 DEVMETHOD(miibus_writereg, re_miibus_writereg), 354 DEVMETHOD(miibus_statchg, re_miibus_statchg), 355 356 { 0, 0 } 357 }; 358 359 static driver_t re_driver = { 360 "re", 361 re_methods, 362 sizeof(struct re_softc) 363 }; 364 365 static devclass_t re_devclass; 366 367 DECLARE_DUMMY_MODULE(if_re); 368 MODULE_DEPEND(if_re, miibus, 1, 1, 1); 369 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0); 370 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0); 371 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 372 373 static int re_rx_desc_count = RE_RX_DESC_CNT_DEF; 374 static int re_tx_desc_count = RE_TX_DESC_CNT_DEF; 375 376 TUNABLE_INT("hw.re.rx_desc_count", &re_rx_desc_count); 377 TUNABLE_INT("hw.re.tx_desc_count", &re_tx_desc_count); 378 379 #define EE_SET(x) \ 380 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x)) 381 382 #define EE_CLR(x) \ 383 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x)) 384 385 static __inline void 386 re_free_rxchain(struct re_softc *sc) 387 { 388 if (sc->re_head != NULL) { 389 m_freem(sc->re_head); 390 sc->re_head = sc->re_tail = NULL; 391 } 392 } 393 394 /* 395 * Send a read command and address to the EEPROM, check for ACK. 396 */ 397 static void 398 re_eeprom_putbyte(struct re_softc *sc, int addr) 399 { 400 int d, i; 401 402 d = addr | (RE_9346_READ << sc->re_eewidth); 403 404 /* 405 * Feed in each bit and strobe the clock. 406 */ 407 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) { 408 if (d & i) 409 EE_SET(RE_EE_DATAIN); 410 else 411 EE_CLR(RE_EE_DATAIN); 412 DELAY(100); 413 EE_SET(RE_EE_CLK); 414 DELAY(150); 415 EE_CLR(RE_EE_CLK); 416 DELAY(100); 417 } 418 } 419 420 /* 421 * Read a word of data stored in the EEPROM at address 'addr.' 422 */ 423 static void 424 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest) 425 { 426 int i; 427 uint16_t word = 0; 428 429 /* 430 * Send address of word we want to read. 431 */ 432 re_eeprom_putbyte(sc, addr); 433 434 /* 435 * Start reading bits from EEPROM. 436 */ 437 for (i = 0x8000; i != 0; i >>= 1) { 438 EE_SET(RE_EE_CLK); 439 DELAY(100); 440 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT) 441 word |= i; 442 EE_CLR(RE_EE_CLK); 443 DELAY(100); 444 } 445 446 *dest = word; 447 } 448 449 /* 450 * Read a sequence of words from the EEPROM. 451 */ 452 static void 453 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt) 454 { 455 int i; 456 uint16_t word = 0, *ptr; 457 458 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 459 DELAY(100); 460 461 for (i = 0; i < cnt; i++) { 462 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL); 463 re_eeprom_getword(sc, off + i, &word); 464 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL); 465 ptr = (uint16_t *)(dest + (i * 2)); 466 *ptr = word; 467 } 468 469 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 470 } 471 472 static void 473 re_get_eewidth(struct re_softc *sc) 474 { 475 uint16_t re_did = 0; 476 477 sc->re_eewidth = 6; 478 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 479 if (re_did != 0x8129) 480 sc->re_eewidth = 8; 481 } 482 483 static int 484 re_gmii_readreg(device_t dev, int phy, int reg) 485 { 486 struct re_softc *sc = device_get_softc(dev); 487 u_int32_t rval; 488 int i; 489 490 if (phy != 1) 491 return(0); 492 493 /* Let the rgephy driver read the GMEDIASTAT register */ 494 495 if (reg == RE_GMEDIASTAT) 496 return(CSR_READ_1(sc, RE_GMEDIASTAT)); 497 498 CSR_WRITE_4(sc, RE_PHYAR, reg << 16); 499 DELAY(1000); 500 501 for (i = 0; i < RE_TIMEOUT; i++) { 502 rval = CSR_READ_4(sc, RE_PHYAR); 503 if (rval & RE_PHYAR_BUSY) 504 break; 505 DELAY(100); 506 } 507 508 if (i == RE_TIMEOUT) { 509 device_printf(dev, "PHY read failed\n"); 510 return(0); 511 } 512 513 return(rval & RE_PHYAR_PHYDATA); 514 } 515 516 static int 517 re_gmii_writereg(device_t dev, int phy, int reg, int data) 518 { 519 struct re_softc *sc = device_get_softc(dev); 520 uint32_t rval; 521 int i; 522 523 CSR_WRITE_4(sc, RE_PHYAR, 524 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY); 525 DELAY(1000); 526 527 for (i = 0; i < RE_TIMEOUT; i++) { 528 rval = CSR_READ_4(sc, RE_PHYAR); 529 if ((rval & RE_PHYAR_BUSY) == 0) 530 break; 531 DELAY(100); 532 } 533 534 if (i == RE_TIMEOUT) 535 device_printf(dev, "PHY write failed\n"); 536 537 return(0); 538 } 539 540 static int 541 re_miibus_readreg(device_t dev, int phy, int reg) 542 { 543 struct re_softc *sc = device_get_softc(dev); 544 uint16_t rval = 0; 545 uint16_t re8139_reg = 0; 546 547 if (!RE_IS_8139CP(sc)) { 548 rval = re_gmii_readreg(dev, phy, reg); 549 return(rval); 550 } 551 552 /* Pretend the internal PHY is only at address 0 */ 553 if (phy) 554 return(0); 555 556 switch(reg) { 557 case MII_BMCR: 558 re8139_reg = RE_BMCR; 559 break; 560 case MII_BMSR: 561 re8139_reg = RE_BMSR; 562 break; 563 case MII_ANAR: 564 re8139_reg = RE_ANAR; 565 break; 566 case MII_ANER: 567 re8139_reg = RE_ANER; 568 break; 569 case MII_ANLPAR: 570 re8139_reg = RE_LPAR; 571 break; 572 case MII_PHYIDR1: 573 case MII_PHYIDR2: 574 return(0); 575 /* 576 * Allow the rlphy driver to read the media status 577 * register. If we have a link partner which does not 578 * support NWAY, this is the register which will tell 579 * us the results of parallel detection. 580 */ 581 case RE_MEDIASTAT: 582 return(CSR_READ_1(sc, RE_MEDIASTAT)); 583 default: 584 device_printf(dev, "bad phy register\n"); 585 return(0); 586 } 587 rval = CSR_READ_2(sc, re8139_reg); 588 if (re8139_reg == RE_BMCR) { 589 /* 8139C+ has different bit layout. */ 590 rval &= ~(BMCR_LOOP | BMCR_ISO); 591 } 592 return(rval); 593 } 594 595 static int 596 re_miibus_writereg(device_t dev, int phy, int reg, int data) 597 { 598 struct re_softc *sc= device_get_softc(dev); 599 u_int16_t re8139_reg = 0; 600 601 if (!RE_IS_8139CP(sc)) 602 return(re_gmii_writereg(dev, phy, reg, data)); 603 604 /* Pretend the internal PHY is only at address 0 */ 605 if (phy) 606 return(0); 607 608 switch(reg) { 609 case MII_BMCR: 610 re8139_reg = RE_BMCR; 611 /* 8139C+ has different bit layout. */ 612 data &= ~(BMCR_LOOP | BMCR_ISO); 613 break; 614 case MII_BMSR: 615 re8139_reg = RE_BMSR; 616 break; 617 case MII_ANAR: 618 re8139_reg = RE_ANAR; 619 break; 620 case MII_ANER: 621 re8139_reg = RE_ANER; 622 break; 623 case MII_ANLPAR: 624 re8139_reg = RE_LPAR; 625 break; 626 case MII_PHYIDR1: 627 case MII_PHYIDR2: 628 return(0); 629 default: 630 device_printf(dev, "bad phy register\n"); 631 return(0); 632 } 633 CSR_WRITE_2(sc, re8139_reg, data); 634 return(0); 635 } 636 637 static void 638 re_miibus_statchg(device_t dev) 639 { 640 } 641 642 /* 643 * Program the 64-bit multicast hash filter. 644 */ 645 static void 646 re_setmulti(struct re_softc *sc) 647 { 648 struct ifnet *ifp = &sc->arpcom.ac_if; 649 int h = 0; 650 uint32_t hashes[2] = { 0, 0 }; 651 struct ifmultiaddr *ifma; 652 uint32_t rxfilt; 653 int mcnt = 0; 654 655 rxfilt = CSR_READ_4(sc, RE_RXCFG); 656 657 /* Set the individual bit to receive frames for this host only. */ 658 rxfilt |= RE_RXCFG_RX_INDIV; 659 /* Set capture broadcast bit to capture broadcast frames. */ 660 rxfilt |= RE_RXCFG_RX_BROAD; 661 662 rxfilt &= ~(RE_RXCFG_RX_ALLPHYS | RE_RXCFG_RX_MULTI); 663 if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) { 664 rxfilt |= RE_RXCFG_RX_MULTI; 665 666 /* If we want promiscuous mode, set the allframes bit. */ 667 if (ifp->if_flags & IFF_PROMISC) 668 rxfilt |= RE_RXCFG_RX_ALLPHYS; 669 670 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 671 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF); 672 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF); 673 return; 674 } 675 676 /* first, zot all the existing hash bits */ 677 CSR_WRITE_4(sc, RE_MAR0, 0); 678 CSR_WRITE_4(sc, RE_MAR4, 0); 679 680 /* now program new ones */ 681 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 682 if (ifma->ifma_addr->sa_family != AF_LINK) 683 continue; 684 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 685 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 686 if (h < 32) 687 hashes[0] |= (1 << h); 688 else 689 hashes[1] |= (1 << (h - 32)); 690 mcnt++; 691 } 692 693 if (mcnt) 694 rxfilt |= RE_RXCFG_RX_MULTI; 695 else 696 rxfilt &= ~RE_RXCFG_RX_MULTI; 697 698 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 699 700 /* 701 * For some unfathomable reason, RealTek decided to reverse 702 * the order of the multicast hash registers in the PCI Express 703 * parts. This means we have to write the hash pattern in reverse 704 * order for those devices. 705 */ 706 if (sc->re_caps & RE_C_PCIE) { 707 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[1])); 708 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[0])); 709 } else { 710 CSR_WRITE_4(sc, RE_MAR0, hashes[0]); 711 CSR_WRITE_4(sc, RE_MAR4, hashes[1]); 712 } 713 } 714 715 static void 716 re_reset(struct re_softc *sc, int running) 717 { 718 int i; 719 720 if ((sc->re_caps & RE_C_STOP_RXTX) && running) { 721 CSR_WRITE_1(sc, RE_COMMAND, 722 RE_CMD_STOPREQ | RE_CMD_TX_ENB | RE_CMD_RX_ENB); 723 DELAY(100); 724 } 725 726 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET); 727 728 for (i = 0; i < RE_TIMEOUT; i++) { 729 DELAY(10); 730 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0) 731 break; 732 } 733 if (i == RE_TIMEOUT) 734 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 735 } 736 737 #ifdef RE_DIAG 738 /* 739 * The following routine is designed to test for a defect on some 740 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 741 * lines connected to the bus, however for a 32-bit only card, they 742 * should be pulled high. The result of this defect is that the 743 * NIC will not work right if you plug it into a 64-bit slot: DMA 744 * operations will be done with 64-bit transfers, which will fail 745 * because the 64-bit data lines aren't connected. 746 * 747 * There's no way to work around this (short of talking a soldering 748 * iron to the board), however we can detect it. The method we use 749 * here is to put the NIC into digital loopback mode, set the receiver 750 * to promiscuous mode, and then try to send a frame. We then compare 751 * the frame data we sent to what was received. If the data matches, 752 * then the NIC is working correctly, otherwise we know the user has 753 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 754 * slot. In the latter case, there's no way the NIC can work correctly, 755 * so we print out a message on the console and abort the device attach. 756 */ 757 758 static int 759 re_diag(struct re_softc *sc) 760 { 761 struct ifnet *ifp = &sc->arpcom.ac_if; 762 struct mbuf *m0; 763 struct ether_header *eh; 764 struct re_desc *cur_rx; 765 uint16_t status; 766 uint32_t rxstat; 767 int total_len, i, error = 0, phyaddr; 768 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 769 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 770 771 /* Allocate a single mbuf */ 772 773 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 774 if (m0 == NULL) 775 return(ENOBUFS); 776 777 /* 778 * Initialize the NIC in test mode. This sets the chip up 779 * so that it can send and receive frames, but performs the 780 * following special functions: 781 * - Puts receiver in promiscuous mode 782 * - Enables digital loopback mode 783 * - Leaves interrupts turned off 784 */ 785 786 ifp->if_flags |= IFF_PROMISC; 787 sc->re_flags |= RE_F_TESTMODE; 788 re_init(sc); 789 sc->re_flags |= RE_F_LINKED; 790 if (!RE_IS_8139CP(sc)) 791 phyaddr = 1; 792 else 793 phyaddr = 0; 794 795 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET); 796 for (i = 0; i < RE_TIMEOUT; i++) { 797 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR); 798 if (!(status & BMCR_RESET)) 799 break; 800 } 801 802 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP); 803 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG); 804 805 DELAY(100000); 806 807 /* Put some data in the mbuf */ 808 809 eh = mtod(m0, struct ether_header *); 810 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN); 811 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN); 812 eh->ether_type = htons(ETHERTYPE_IP); 813 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 814 815 /* 816 * Queue the packet, start transmission. 817 * Note: ifq_handoff() ultimately calls re_start() for us. 818 */ 819 820 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 821 error = ifq_handoff(ifp, m0, NULL); 822 if (error) { 823 m0 = NULL; 824 goto done; 825 } 826 m0 = NULL; 827 828 /* Wait for it to propagate through the chip */ 829 830 DELAY(100000); 831 for (i = 0; i < RE_TIMEOUT; i++) { 832 status = CSR_READ_2(sc, RE_ISR); 833 CSR_WRITE_2(sc, RE_ISR, status); 834 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) == 835 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) 836 break; 837 DELAY(10); 838 } 839 840 if (i == RE_TIMEOUT) { 841 if_printf(ifp, "diagnostic failed to receive packet " 842 "in loopback mode\n"); 843 error = EIO; 844 goto done; 845 } 846 847 /* 848 * The packet should have been dumped into the first 849 * entry in the RX DMA ring. Grab it from there. 850 */ 851 852 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, sc->re_ldata.re_rx_dmamap[0], 853 BUS_DMASYNC_POSTREAD); 854 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 855 sc->re_ldata.re_rx_dmamap[0]); 856 857 m0 = sc->re_ldata.re_rx_mbuf[0]; 858 sc->re_ldata.re_rx_mbuf[0] = NULL; 859 eh = mtod(m0, struct ether_header *); 860 861 cur_rx = &sc->re_ldata.re_rx_list[0]; 862 total_len = RE_RXBYTES(cur_rx); 863 rxstat = le32toh(cur_rx->re_cmdstat); 864 865 if (total_len != ETHER_MIN_LEN) { 866 if_printf(ifp, "diagnostic failed, received short packet\n"); 867 error = EIO; 868 goto done; 869 } 870 871 /* Test that the received packet data matches what we sent. */ 872 873 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) || 874 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) || 875 be16toh(eh->ether_type) != ETHERTYPE_IP) { 876 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 877 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n", 878 dst, ":", src, ":", ETHERTYPE_IP); 879 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n", 880 eh->ether_dhost, ":", eh->ether_shost, ":", 881 ntohs(eh->ether_type)); 882 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 883 "into a 64-bit PCI slot.\n"); 884 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 885 "for proper operation.\n"); 886 if_printf(ifp, "Read the re(4) man page for more details.\n"); 887 error = EIO; 888 } 889 890 done: 891 /* Turn interface off, release resources */ 892 893 sc->re_flags &= ~(RE_F_LINKED | RE_F_TESTMODE); 894 ifp->if_flags &= ~IFF_PROMISC; 895 re_stop(sc); 896 if (m0 != NULL) 897 m_freem(m0); 898 899 return (error); 900 } 901 #endif /* RE_DIAG */ 902 903 /* 904 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 905 * IDs against our list and return a device name if we find a match. 906 */ 907 static int 908 re_probe(device_t dev) 909 { 910 const struct re_type *t; 911 const struct re_hwrev *hw_rev; 912 struct re_softc *sc; 913 int rid; 914 uint32_t hwrev, macmode, txcfg; 915 uint16_t vendor, product; 916 917 vendor = pci_get_vendor(dev); 918 product = pci_get_device(dev); 919 920 /* 921 * Only attach to rev.3 of the Linksys EG1032 adapter. 922 * Rev.2 is supported by sk(4). 923 */ 924 if (vendor == PCI_VENDOR_LINKSYS && 925 product == PCI_PRODUCT_LINKSYS_EG1032 && 926 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3) 927 return ENXIO; 928 929 if (vendor == PCI_VENDOR_REALTEK && 930 product == PCI_PRODUCT_REALTEK_RT8139 && 931 pci_get_revid(dev) != PCI_REVID_REALTEK_RT8139CP) { 932 /* Poor 8139 */ 933 return ENXIO; 934 } 935 936 for (t = re_devs; t->re_name != NULL; t++) { 937 if (product == t->re_did && vendor == t->re_vid) 938 break; 939 } 940 941 /* 942 * Check if we found a RealTek device. 943 */ 944 if (t->re_name == NULL) 945 return ENXIO; 946 947 /* 948 * Temporarily map the I/O space so we can read the chip ID register. 949 */ 950 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO); 951 rid = RE_PCI_LOIO; 952 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 953 RF_ACTIVE); 954 if (sc->re_res == NULL) { 955 device_printf(dev, "couldn't map ports/memory\n"); 956 kfree(sc, M_TEMP); 957 return ENXIO; 958 } 959 960 sc->re_btag = rman_get_bustag(sc->re_res); 961 sc->re_bhandle = rman_get_bushandle(sc->re_res); 962 963 txcfg = CSR_READ_4(sc, RE_TXCFG); 964 hwrev = txcfg & RE_TXCFG_HWREV; 965 macmode = txcfg & RE_TXCFG_MACMODE; 966 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res); 967 kfree(sc, M_TEMP); 968 969 /* 970 * and continue matching for the specific chip... 971 */ 972 for (hw_rev = re_hwrevs; hw_rev->re_hwrev != RE_HWREV_NULL; hw_rev++) { 973 if (hw_rev->re_hwrev == hwrev) { 974 sc = device_get_softc(dev); 975 976 sc->re_hwrev = hw_rev->re_hwrev; 977 sc->re_macver = hw_rev->re_macver; 978 sc->re_caps = hw_rev->re_caps; 979 sc->re_maxmtu = hw_rev->re_maxmtu; 980 981 /* 982 * Apply chip property fixup 983 */ 984 switch (sc->re_hwrev) { 985 case RE_HWREV_8101E1: 986 case RE_HWREV_8101E2: 987 if (macmode == 0) 988 sc->re_macver = RE_MACVER_11; 989 else if (macmode == 0x200000) 990 sc->re_macver = RE_MACVER_12; 991 break; 992 case RE_HWREV_8102E: 993 case RE_HWREV_8102EL: 994 if (macmode == 0) 995 sc->re_macver = RE_MACVER_13; 996 else if (macmode == 0x100000) 997 sc->re_macver = RE_MACVER_14; 998 break; 999 case RE_HWREV_8168B2: 1000 case RE_HWREV_8168B3: 1001 if (macmode == 0) 1002 sc->re_macver = RE_MACVER_22; 1003 break; 1004 case RE_HWREV_8168C: 1005 if (macmode == 0) 1006 sc->re_macver = RE_MACVER_24; 1007 else if (macmode == 0x200000) 1008 sc->re_macver = RE_MACVER_25; 1009 else if (macmode == 0x300000) 1010 sc->re_macver = RE_MACVER_27; 1011 break; 1012 case RE_HWREV_8168CP: 1013 if (macmode == 0) 1014 sc->re_macver = RE_MACVER_26; 1015 else if (macmode == 0x100000) 1016 sc->re_macver = RE_MACVER_28; 1017 break; 1018 } 1019 if (pci_is_pcie(dev)) 1020 sc->re_caps |= RE_C_PCIE; 1021 1022 device_set_desc(dev, t->re_name); 1023 return 0; 1024 } 1025 } 1026 1027 if (bootverbose) { 1028 device_printf(dev, "unknown hwrev 0x%08x, macmode 0x%08x\n", 1029 hwrev, macmode); 1030 } 1031 return ENXIO; 1032 } 1033 1034 static int 1035 re_allocmem(device_t dev) 1036 { 1037 struct re_softc *sc = device_get_softc(dev); 1038 bus_dmamem_t dmem; 1039 int error, i; 1040 1041 /* 1042 * Allocate list data 1043 */ 1044 sc->re_ldata.re_tx_mbuf = 1045 kmalloc(sc->re_tx_desc_cnt * sizeof(struct mbuf *), 1046 M_DEVBUF, M_ZERO | M_WAITOK); 1047 1048 sc->re_ldata.re_rx_mbuf = 1049 kmalloc(sc->re_rx_desc_cnt * sizeof(struct mbuf *), 1050 M_DEVBUF, M_ZERO | M_WAITOK); 1051 1052 sc->re_ldata.re_rx_paddr = 1053 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_addr_t), 1054 M_DEVBUF, M_ZERO | M_WAITOK); 1055 1056 sc->re_ldata.re_tx_dmamap = 1057 kmalloc(sc->re_tx_desc_cnt * sizeof(bus_dmamap_t), 1058 M_DEVBUF, M_ZERO | M_WAITOK); 1059 1060 sc->re_ldata.re_rx_dmamap = 1061 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_dmamap_t), 1062 M_DEVBUF, M_ZERO | M_WAITOK); 1063 1064 /* 1065 * Allocate the parent bus DMA tag appropriate for PCI. 1066 */ 1067 error = bus_dma_tag_create(NULL, /* parent */ 1068 1, 0, /* alignment, boundary */ 1069 BUS_SPACE_MAXADDR, /* lowaddr */ 1070 BUS_SPACE_MAXADDR, /* highaddr */ 1071 NULL, NULL, /* filter, filterarg */ 1072 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 1073 0, /* nsegments */ 1074 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1075 0, /* flags */ 1076 &sc->re_parent_tag); 1077 if (error) { 1078 device_printf(dev, "could not allocate parent dma tag\n"); 1079 return error; 1080 } 1081 1082 /* Allocate TX descriptor list. */ 1083 error = bus_dmamem_coherent(sc->re_parent_tag, 1084 RE_RING_ALIGN, 0, 1085 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1086 RE_TX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO, 1087 &dmem); 1088 if (error) { 1089 device_printf(dev, "could not allocate TX ring\n"); 1090 return error; 1091 } 1092 sc->re_ldata.re_tx_list_tag = dmem.dmem_tag; 1093 sc->re_ldata.re_tx_list_map = dmem.dmem_map; 1094 sc->re_ldata.re_tx_list = dmem.dmem_addr; 1095 sc->re_ldata.re_tx_list_addr = dmem.dmem_busaddr; 1096 1097 /* Allocate RX descriptor list. */ 1098 error = bus_dmamem_coherent(sc->re_parent_tag, 1099 RE_RING_ALIGN, 0, 1100 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1101 RE_RX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO, 1102 &dmem); 1103 if (error) { 1104 device_printf(dev, "could not allocate RX ring\n"); 1105 return error; 1106 } 1107 sc->re_ldata.re_rx_list_tag = dmem.dmem_tag; 1108 sc->re_ldata.re_rx_list_map = dmem.dmem_map; 1109 sc->re_ldata.re_rx_list = dmem.dmem_addr; 1110 sc->re_ldata.re_rx_list_addr = dmem.dmem_busaddr; 1111 1112 /* Allocate maps for TX mbufs. */ 1113 error = bus_dma_tag_create(sc->re_parent_tag, 1114 1, 0, 1115 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1116 NULL, NULL, 1117 RE_FRAMELEN_MAX, RE_MAXSEGS, MCLBYTES, 1118 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1119 &sc->re_ldata.re_tx_mtag); 1120 if (error) { 1121 device_printf(dev, "could not allocate TX buf dma tag\n"); 1122 return(error); 1123 } 1124 1125 /* Create DMA maps for TX buffers */ 1126 for (i = 0; i < sc->re_tx_desc_cnt; i++) { 1127 error = bus_dmamap_create(sc->re_ldata.re_tx_mtag, 1128 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1129 &sc->re_ldata.re_tx_dmamap[i]); 1130 if (error) { 1131 device_printf(dev, "can't create DMA map for TX buf\n"); 1132 re_freebufmem(sc, i, 0); 1133 return(error); 1134 } 1135 } 1136 1137 /* Allocate maps for RX mbufs. */ 1138 error = bus_dma_tag_create(sc->re_parent_tag, 1139 RE_RXBUF_ALIGN, 0, 1140 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1141 NULL, NULL, 1142 MCLBYTES, 1, MCLBYTES, 1143 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED, 1144 &sc->re_ldata.re_rx_mtag); 1145 if (error) { 1146 device_printf(dev, "could not allocate RX buf dma tag\n"); 1147 return(error); 1148 } 1149 1150 /* Create spare DMA map for RX */ 1151 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, BUS_DMA_WAITOK, 1152 &sc->re_ldata.re_rx_spare); 1153 if (error) { 1154 device_printf(dev, "can't create spare DMA map for RX\n"); 1155 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag); 1156 sc->re_ldata.re_rx_mtag = NULL; 1157 return error; 1158 } 1159 1160 /* Create DMA maps for RX buffers */ 1161 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 1162 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, 1163 BUS_DMA_WAITOK, &sc->re_ldata.re_rx_dmamap[i]); 1164 if (error) { 1165 device_printf(dev, "can't create DMA map for RX buf\n"); 1166 re_freebufmem(sc, sc->re_tx_desc_cnt, i); 1167 return(error); 1168 } 1169 } 1170 1171 /* Create jumbo buffer pool for RX if required */ 1172 if (sc->re_caps & RE_C_CONTIGRX) { 1173 error = re_jpool_alloc(sc); 1174 if (error) { 1175 re_jpool_free(sc); 1176 /* Disable jumbo frame support */ 1177 sc->re_maxmtu = ETHERMTU; 1178 } 1179 } 1180 return(0); 1181 } 1182 1183 static void 1184 re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt) 1185 { 1186 int i; 1187 1188 /* Destroy all the RX and TX buffer maps */ 1189 if (sc->re_ldata.re_tx_mtag) { 1190 for (i = 0; i < tx_cnt; i++) { 1191 bus_dmamap_destroy(sc->re_ldata.re_tx_mtag, 1192 sc->re_ldata.re_tx_dmamap[i]); 1193 } 1194 bus_dma_tag_destroy(sc->re_ldata.re_tx_mtag); 1195 sc->re_ldata.re_tx_mtag = NULL; 1196 } 1197 1198 if (sc->re_ldata.re_rx_mtag) { 1199 for (i = 0; i < rx_cnt; i++) { 1200 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag, 1201 sc->re_ldata.re_rx_dmamap[i]); 1202 } 1203 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag, 1204 sc->re_ldata.re_rx_spare); 1205 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag); 1206 sc->re_ldata.re_rx_mtag = NULL; 1207 } 1208 } 1209 1210 static void 1211 re_freemem(device_t dev) 1212 { 1213 struct re_softc *sc = device_get_softc(dev); 1214 1215 /* Unload and free the RX DMA ring memory and map */ 1216 if (sc->re_ldata.re_rx_list_tag) { 1217 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag, 1218 sc->re_ldata.re_rx_list_map); 1219 bus_dmamem_free(sc->re_ldata.re_rx_list_tag, 1220 sc->re_ldata.re_rx_list, 1221 sc->re_ldata.re_rx_list_map); 1222 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1223 } 1224 1225 /* Unload and free the TX DMA ring memory and map */ 1226 if (sc->re_ldata.re_tx_list_tag) { 1227 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag, 1228 sc->re_ldata.re_tx_list_map); 1229 bus_dmamem_free(sc->re_ldata.re_tx_list_tag, 1230 sc->re_ldata.re_tx_list, 1231 sc->re_ldata.re_tx_list_map); 1232 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1233 } 1234 1235 /* Free RX/TX buf DMA stuffs */ 1236 re_freebufmem(sc, sc->re_tx_desc_cnt, sc->re_rx_desc_cnt); 1237 1238 /* Unload and free the stats buffer and map */ 1239 if (sc->re_ldata.re_stag) { 1240 bus_dmamap_unload(sc->re_ldata.re_stag, sc->re_ldata.re_smap); 1241 bus_dmamem_free(sc->re_ldata.re_stag, 1242 sc->re_ldata.re_stats, 1243 sc->re_ldata.re_smap); 1244 bus_dma_tag_destroy(sc->re_ldata.re_stag); 1245 } 1246 1247 if (sc->re_caps & RE_C_CONTIGRX) 1248 re_jpool_free(sc); 1249 1250 if (sc->re_parent_tag) 1251 bus_dma_tag_destroy(sc->re_parent_tag); 1252 1253 if (sc->re_ldata.re_tx_mbuf != NULL) 1254 kfree(sc->re_ldata.re_tx_mbuf, M_DEVBUF); 1255 if (sc->re_ldata.re_rx_mbuf != NULL) 1256 kfree(sc->re_ldata.re_rx_mbuf, M_DEVBUF); 1257 if (sc->re_ldata.re_rx_paddr != NULL) 1258 kfree(sc->re_ldata.re_rx_paddr, M_DEVBUF); 1259 if (sc->re_ldata.re_tx_dmamap != NULL) 1260 kfree(sc->re_ldata.re_tx_dmamap, M_DEVBUF); 1261 if (sc->re_ldata.re_rx_dmamap != NULL) 1262 kfree(sc->re_ldata.re_rx_dmamap, M_DEVBUF); 1263 } 1264 1265 /* 1266 * Attach the interface. Allocate softc structures, do ifmedia 1267 * setup and ethernet/BPF attach. 1268 */ 1269 static int 1270 re_attach(device_t dev) 1271 { 1272 struct re_softc *sc = device_get_softc(dev); 1273 struct ifnet *ifp; 1274 uint8_t eaddr[ETHER_ADDR_LEN]; 1275 int error = 0, rid, qlen; 1276 1277 callout_init(&sc->re_timer); 1278 sc->re_dev = dev; 1279 1280 if (RE_IS_8139CP(sc)) { 1281 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_8139CP; 1282 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_8139CP; 1283 } else { 1284 sc->re_rx_desc_cnt = re_rx_desc_count; 1285 if (sc->re_rx_desc_cnt > RE_RX_DESC_CNT_MAX) 1286 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_MAX; 1287 1288 sc->re_tx_desc_cnt = re_tx_desc_count; 1289 if (sc->re_tx_desc_cnt > RE_TX_DESC_CNT_MAX) 1290 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_MAX; 1291 } 1292 1293 qlen = RE_IFQ_MAXLEN; 1294 if (sc->re_tx_desc_cnt > qlen) 1295 qlen = sc->re_tx_desc_cnt; 1296 1297 sc->re_rxbuf_size = MCLBYTES; 1298 sc->re_newbuf = re_newbuf_std; 1299 1300 sc->re_tx_time = 5; /* 125us */ 1301 sc->re_rx_time = 2; /* 50us */ 1302 if (sc->re_caps & RE_C_PCIE) 1303 sc->re_sim_time = 75; /* 75us */ 1304 else 1305 sc->re_sim_time = 125; /* 125us */ 1306 if (!RE_IS_8139CP(sc)) { 1307 /* simulated interrupt moderation */ 1308 sc->re_imtype = RE_IMTYPE_SIM; 1309 } else { 1310 sc->re_imtype = RE_IMTYPE_NONE; 1311 } 1312 re_config_imtype(sc, sc->re_imtype); 1313 1314 sysctl_ctx_init(&sc->re_sysctl_ctx); 1315 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx, 1316 SYSCTL_STATIC_CHILDREN(_hw), 1317 OID_AUTO, 1318 device_get_nameunit(dev), 1319 CTLFLAG_RD, 0, ""); 1320 if (sc->re_sysctl_tree == NULL) { 1321 device_printf(dev, "can't add sysctl node\n"); 1322 error = ENXIO; 1323 goto fail; 1324 } 1325 SYSCTL_ADD_INT(&sc->re_sysctl_ctx, 1326 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO, 1327 "rx_desc_count", CTLFLAG_RD, &sc->re_rx_desc_cnt, 1328 0, "RX desc count"); 1329 SYSCTL_ADD_INT(&sc->re_sysctl_ctx, 1330 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO, 1331 "tx_desc_count", CTLFLAG_RD, &sc->re_tx_desc_cnt, 1332 0, "TX desc count"); 1333 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1334 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1335 OID_AUTO, "sim_time", 1336 CTLTYPE_INT | CTLFLAG_RW, 1337 sc, 0, re_sysctl_simtime, "I", 1338 "Simulated interrupt moderation time (usec)."); 1339 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1340 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1341 OID_AUTO, "imtype", 1342 CTLTYPE_INT | CTLFLAG_RW, 1343 sc, 0, re_sysctl_imtype, "I", 1344 "Interrupt moderation type -- " 1345 "0:disable, 1:simulated, " 1346 "2:hardware(if supported)"); 1347 if (sc->re_caps & RE_C_HWIM) { 1348 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1349 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1350 OID_AUTO, "hw_rxtime", 1351 CTLTYPE_INT | CTLFLAG_RW, 1352 sc, 0, re_sysctl_rxtime, "I", 1353 "Hardware interrupt moderation time " 1354 "(unit: 25usec)."); 1355 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1356 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1357 OID_AUTO, "hw_txtime", 1358 CTLTYPE_INT | CTLFLAG_RW, 1359 sc, 0, re_sysctl_txtime, "I", 1360 "Hardware interrupt moderation time " 1361 "(unit: 25usec)."); 1362 } 1363 1364 #ifndef BURN_BRIDGES 1365 /* 1366 * Handle power management nonsense. 1367 */ 1368 1369 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1370 uint32_t membase, irq; 1371 1372 /* Save important PCI config data. */ 1373 membase = pci_read_config(dev, RE_PCI_LOMEM, 4); 1374 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1375 1376 /* Reset the power state. */ 1377 device_printf(dev, "chip is in D%d power mode " 1378 "-- setting to D0\n", pci_get_powerstate(dev)); 1379 1380 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1381 1382 /* Restore PCI config data. */ 1383 pci_write_config(dev, RE_PCI_LOMEM, membase, 4); 1384 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1385 } 1386 #endif 1387 /* 1388 * Map control/status registers. 1389 */ 1390 pci_enable_busmaster(dev); 1391 1392 rid = RE_PCI_LOIO; 1393 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1394 RF_ACTIVE); 1395 1396 if (sc->re_res == NULL) { 1397 device_printf(dev, "couldn't map ports\n"); 1398 error = ENXIO; 1399 goto fail; 1400 } 1401 1402 sc->re_btag = rman_get_bustag(sc->re_res); 1403 sc->re_bhandle = rman_get_bushandle(sc->re_res); 1404 1405 /* Allocate interrupt */ 1406 rid = 0; 1407 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1408 RF_SHAREABLE | RF_ACTIVE); 1409 1410 if (sc->re_irq == NULL) { 1411 device_printf(dev, "couldn't map interrupt\n"); 1412 error = ENXIO; 1413 goto fail; 1414 } 1415 1416 /* Reset the adapter. */ 1417 re_reset(sc, 0); 1418 1419 if (RE_IS_8139CP(sc)) { 1420 sc->re_bus_speed = 33; /* XXX */ 1421 } else if (sc->re_caps & RE_C_PCIE) { 1422 sc->re_bus_speed = 125; 1423 } else { 1424 uint8_t cfg2; 1425 1426 cfg2 = CSR_READ_1(sc, RE_CFG2); 1427 switch (cfg2 & RE_CFG2_PCICLK_MASK) { 1428 case RE_CFG2_PCICLK_33MHZ: 1429 sc->re_bus_speed = 33; 1430 break; 1431 case RE_CFG2_PCICLK_66MHZ: 1432 sc->re_bus_speed = 66; 1433 break; 1434 default: 1435 device_printf(dev, "unknown bus speed, assume 33MHz\n"); 1436 sc->re_bus_speed = 33; 1437 break; 1438 } 1439 if (cfg2 & RE_CFG2_PCI64) 1440 sc->re_caps |= RE_C_PCI64; 1441 } 1442 device_printf(dev, "Hardware rev. 0x%08x; MAC ver. 0x%02x; " 1443 "PCI%s %dMHz\n", 1444 sc->re_hwrev, sc->re_macver, 1445 (sc->re_caps & RE_C_PCIE) ? 1446 "-E" : ((sc->re_caps & RE_C_PCI64) ? "64" : "32"), 1447 sc->re_bus_speed); 1448 1449 /* 1450 * NOTE: 1451 * DO NOT try to adjust config1 and config5 which was spotted in 1452 * Realtek's Linux drivers. It will _permanently_ damage certain 1453 * cards EEPROM, e.g. one of my 8168B (0x38000000) card ... 1454 */ 1455 1456 re_get_eaddr(sc, eaddr); 1457 1458 if (!RE_IS_8139CP(sc)) { 1459 /* Set RX length mask */ 1460 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 1461 sc->re_txstart = RE_GTXSTART; 1462 } else { 1463 /* Set RX length mask */ 1464 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 1465 sc->re_txstart = RE_TXSTART; 1466 } 1467 1468 /* Allocate DMA stuffs */ 1469 error = re_allocmem(dev); 1470 if (error) 1471 goto fail; 1472 1473 /* 1474 * Apply some magic PCI settings from Realtek ... 1475 */ 1476 if (RE_IS_8169(sc)) { 1477 CSR_WRITE_1(sc, 0x82, 1); 1478 pci_write_config(dev, PCIR_CACHELNSZ, 0x8, 1); 1479 } 1480 pci_write_config(dev, PCIR_LATTIMER, 0x40, 1); 1481 1482 if (sc->re_caps & RE_C_MAC2) { 1483 /* 1484 * Following part is extracted from Realtek BSD driver v176. 1485 * However, this does _not_ make much/any sense: 1486 * 8168C's PCI Express device control is located at 0x78, 1487 * so the reading from 0x79 (higher part of 0x78) and setting 1488 * the 4~6bits intend to enlarge the "max read request size" 1489 * (we will do it). The content of the rest part of this 1490 * register is not meaningful to other PCI registers, so 1491 * writing the value to 0x54 could be completely wrong. 1492 * 0x80 is the lower part of PCI Express device status, non- 1493 * reserved bits are RW1C, writing 0 to them will not have 1494 * any effect at all. 1495 */ 1496 #ifdef foo 1497 uint8_t val; 1498 1499 val = pci_read_config(dev, 0x79, 1); 1500 val = (val & ~0x70) | 0x50; 1501 pci_write_config(dev, 0x54, val, 1); 1502 pci_write_config(dev, 0x80, 0, 1); 1503 #endif 1504 } 1505 1506 /* 1507 * Apply some PHY fixup from Realtek ... 1508 */ 1509 if (sc->re_hwrev == RE_HWREV_8110S) { 1510 CSR_WRITE_1(sc, 0x82, 1); 1511 re_miibus_writereg(dev, 1, 0xb, 0); 1512 } 1513 if (sc->re_caps & RE_C_PHYPMGT) { 1514 /* Power up PHY */ 1515 re_miibus_writereg(dev, 1, 0x1f, 0); 1516 re_miibus_writereg(dev, 1, 0xe, 0); 1517 } 1518 1519 /* Do MII setup */ 1520 if (mii_phy_probe(dev, &sc->re_miibus, 1521 re_ifmedia_upd, re_ifmedia_sts)) { 1522 device_printf(dev, "MII without any phy!\n"); 1523 error = ENXIO; 1524 goto fail; 1525 } 1526 1527 ifp = &sc->arpcom.ac_if; 1528 ifp->if_softc = sc; 1529 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1530 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1531 ifp->if_ioctl = re_ioctl; 1532 ifp->if_start = re_start; 1533 #ifdef DEVICE_POLLING 1534 ifp->if_poll = re_poll; 1535 #endif 1536 ifp->if_watchdog = re_watchdog; 1537 ifp->if_init = re_init; 1538 if (!RE_IS_8139CP(sc)) /* XXX */ 1539 ifp->if_baudrate = 1000000000; 1540 else 1541 ifp->if_baudrate = 100000000; 1542 ifq_set_maxlen(&ifp->if_snd, qlen); 1543 ifq_set_ready(&ifp->if_snd); 1544 1545 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1546 if (sc->re_caps & RE_C_HWCSUM) 1547 ifp->if_capabilities |= IFCAP_HWCSUM; 1548 1549 ifp->if_capenable = ifp->if_capabilities; 1550 if (ifp->if_capabilities & IFCAP_HWCSUM) 1551 ifp->if_hwassist = RE_CSUM_FEATURES; 1552 else 1553 ifp->if_hwassist = 0; 1554 1555 /* 1556 * Call MI attach routine. 1557 */ 1558 ether_ifattach(ifp, eaddr, NULL); 1559 1560 #ifdef RE_DIAG 1561 /* 1562 * Perform hardware diagnostic on the original RTL8169. 1563 * Some 32-bit cards were incorrectly wired and would 1564 * malfunction if plugged into a 64-bit slot. 1565 */ 1566 if (sc->re_hwrev == RE_HWREV_8169) { 1567 lwkt_serialize_enter(ifp->if_serializer); 1568 error = re_diag(sc); 1569 lwkt_serialize_exit(ifp->if_serializer); 1570 1571 if (error) { 1572 device_printf(dev, "hardware diagnostic failure\n"); 1573 ether_ifdetach(ifp); 1574 goto fail; 1575 } 1576 } 1577 #endif /* RE_DIAG */ 1578 1579 /* Hook interrupt last to avoid having to lock softc */ 1580 error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc, 1581 &sc->re_intrhand, ifp->if_serializer); 1582 1583 if (error) { 1584 device_printf(dev, "couldn't set up irq\n"); 1585 ether_ifdetach(ifp); 1586 goto fail; 1587 } 1588 1589 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->re_irq)); 1590 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 1591 1592 fail: 1593 if (error) 1594 re_detach(dev); 1595 1596 return (error); 1597 } 1598 1599 /* 1600 * Shutdown hardware and free up resources. This can be called any 1601 * time after the mutex has been initialized. It is called in both 1602 * the error case in attach and the normal detach case so it needs 1603 * to be careful about only freeing resources that have actually been 1604 * allocated. 1605 */ 1606 static int 1607 re_detach(device_t dev) 1608 { 1609 struct re_softc *sc = device_get_softc(dev); 1610 struct ifnet *ifp = &sc->arpcom.ac_if; 1611 1612 /* These should only be active if attach succeeded */ 1613 if (device_is_attached(dev)) { 1614 lwkt_serialize_enter(ifp->if_serializer); 1615 re_stop(sc); 1616 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand); 1617 lwkt_serialize_exit(ifp->if_serializer); 1618 1619 ether_ifdetach(ifp); 1620 } 1621 if (sc->re_miibus) 1622 device_delete_child(dev, sc->re_miibus); 1623 bus_generic_detach(dev); 1624 1625 if (sc->re_sysctl_tree != NULL) 1626 sysctl_ctx_free(&sc->re_sysctl_ctx); 1627 1628 if (sc->re_irq) 1629 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq); 1630 if (sc->re_res) { 1631 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, 1632 sc->re_res); 1633 } 1634 1635 /* Free DMA stuffs */ 1636 re_freemem(dev); 1637 1638 return(0); 1639 } 1640 1641 static void 1642 re_setup_rxdesc(struct re_softc *sc, int idx) 1643 { 1644 bus_addr_t paddr; 1645 uint32_t cmdstat; 1646 struct re_desc *d; 1647 1648 paddr = sc->re_ldata.re_rx_paddr[idx]; 1649 d = &sc->re_ldata.re_rx_list[idx]; 1650 1651 d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr)); 1652 d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr)); 1653 1654 cmdstat = sc->re_rxbuf_size | RE_RDESC_CMD_OWN; 1655 if (idx == (sc->re_rx_desc_cnt - 1)) 1656 cmdstat |= RE_RDESC_CMD_EOR; 1657 d->re_cmdstat = htole32(cmdstat); 1658 } 1659 1660 static int 1661 re_newbuf_std(struct re_softc *sc, int idx, int init) 1662 { 1663 bus_dma_segment_t seg; 1664 bus_dmamap_t map; 1665 struct mbuf *m; 1666 int error, nsegs; 1667 1668 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 1669 if (m == NULL) { 1670 error = ENOBUFS; 1671 1672 if (init) { 1673 if_printf(&sc->arpcom.ac_if, "m_getcl failed\n"); 1674 return error; 1675 } else { 1676 goto back; 1677 } 1678 } 1679 m->m_len = m->m_pkthdr.len = MCLBYTES; 1680 1681 /* 1682 * NOTE: 1683 * re(4) chips need address of the receive buffer to be 8-byte 1684 * aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1685 */ 1686 1687 error = bus_dmamap_load_mbuf_segment(sc->re_ldata.re_rx_mtag, 1688 sc->re_ldata.re_rx_spare, m, 1689 &seg, 1, &nsegs, BUS_DMA_NOWAIT); 1690 if (error) { 1691 m_freem(m); 1692 if (init) { 1693 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 1694 return error; 1695 } else { 1696 goto back; 1697 } 1698 } 1699 1700 if (!init) { 1701 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, 1702 sc->re_ldata.re_rx_dmamap[idx], 1703 BUS_DMASYNC_POSTREAD); 1704 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 1705 sc->re_ldata.re_rx_dmamap[idx]); 1706 } 1707 sc->re_ldata.re_rx_mbuf[idx] = m; 1708 sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr; 1709 1710 map = sc->re_ldata.re_rx_dmamap[idx]; 1711 sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare; 1712 sc->re_ldata.re_rx_spare = map; 1713 back: 1714 re_setup_rxdesc(sc, idx); 1715 return error; 1716 } 1717 1718 static int 1719 re_newbuf_jumbo(struct re_softc *sc, int idx, int init) 1720 { 1721 struct mbuf *m; 1722 struct re_jbuf *jbuf; 1723 int error = 0; 1724 1725 MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA); 1726 if (m == NULL) { 1727 error = ENOBUFS; 1728 if (init) { 1729 if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n"); 1730 return error; 1731 } else { 1732 goto back; 1733 } 1734 } 1735 1736 jbuf = re_jbuf_alloc(sc); 1737 if (jbuf == NULL) { 1738 m_freem(m); 1739 1740 error = ENOBUFS; 1741 if (init) { 1742 if_printf(&sc->arpcom.ac_if, "jpool is empty\n"); 1743 return error; 1744 } else { 1745 goto back; 1746 } 1747 } 1748 1749 m->m_ext.ext_arg = jbuf; 1750 m->m_ext.ext_buf = jbuf->re_buf; 1751 m->m_ext.ext_free = re_jbuf_free; 1752 m->m_ext.ext_ref = re_jbuf_ref; 1753 m->m_ext.ext_size = sc->re_rxbuf_size; 1754 1755 m->m_data = m->m_ext.ext_buf; 1756 m->m_flags |= M_EXT; 1757 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1758 1759 /* 1760 * NOTE: 1761 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer 1762 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1763 */ 1764 1765 sc->re_ldata.re_rx_mbuf[idx] = m; 1766 sc->re_ldata.re_rx_paddr[idx] = jbuf->re_paddr; 1767 back: 1768 re_setup_rxdesc(sc, idx); 1769 return error; 1770 } 1771 1772 static int 1773 re_tx_list_init(struct re_softc *sc) 1774 { 1775 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 1776 1777 sc->re_ldata.re_tx_prodidx = 0; 1778 sc->re_ldata.re_tx_considx = 0; 1779 sc->re_ldata.re_tx_free = sc->re_tx_desc_cnt; 1780 1781 return(0); 1782 } 1783 1784 static int 1785 re_rx_list_init(struct re_softc *sc) 1786 { 1787 int i, error; 1788 1789 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc)); 1790 1791 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 1792 error = sc->re_newbuf(sc, i, 1); 1793 if (error) 1794 return(error); 1795 } 1796 1797 sc->re_ldata.re_rx_prodidx = 0; 1798 sc->re_head = sc->re_tail = NULL; 1799 1800 return(0); 1801 } 1802 1803 #define RE_IP4_PACKET 0x1 1804 #define RE_TCP_PACKET 0x2 1805 #define RE_UDP_PACKET 0x4 1806 1807 static __inline uint8_t 1808 re_packet_type(struct re_softc *sc, uint32_t rxstat, uint32_t rxctrl) 1809 { 1810 uint8_t packet_type = 0; 1811 1812 if (sc->re_caps & RE_C_MAC2) { 1813 if (rxctrl & RE_RDESC_CTL_PROTOIP4) 1814 packet_type |= RE_IP4_PACKET; 1815 } else { 1816 if (rxstat & RE_RDESC_STAT_PROTOID) 1817 packet_type |= RE_IP4_PACKET; 1818 } 1819 if (RE_TCPPKT(rxstat)) 1820 packet_type |= RE_TCP_PACKET; 1821 else if (RE_UDPPKT(rxstat)) 1822 packet_type |= RE_UDP_PACKET; 1823 return packet_type; 1824 } 1825 1826 /* 1827 * RX handler for C+ and 8169. For the gigE chips, we support 1828 * the reception of jumbo frames that have been fragmented 1829 * across multiple 2K mbuf cluster buffers. 1830 */ 1831 static int 1832 re_rxeof(struct re_softc *sc) 1833 { 1834 struct ifnet *ifp = &sc->arpcom.ac_if; 1835 struct mbuf *m; 1836 struct re_desc *cur_rx; 1837 uint32_t rxstat, rxctrl; 1838 int i, total_len, rx = 0; 1839 struct mbuf_chain chain[MAXCPU]; 1840 1841 ether_input_chain_init(chain); 1842 1843 for (i = sc->re_ldata.re_rx_prodidx; 1844 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_RXDESC_INC(sc, i)) { 1845 cur_rx = &sc->re_ldata.re_rx_list[i]; 1846 m = sc->re_ldata.re_rx_mbuf[i]; 1847 total_len = RE_RXBYTES(cur_rx); 1848 rxstat = le32toh(cur_rx->re_cmdstat); 1849 rxctrl = le32toh(cur_rx->re_control); 1850 1851 rx = 1; 1852 1853 #ifdef INVARIANTS 1854 if (sc->re_flags & RE_F_USE_JPOOL) 1855 KKASSERT(rxstat & RE_RDESC_STAT_EOF); 1856 #endif 1857 1858 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1859 if (sc->re_flags & RE_F_DROP_RXFRAG) { 1860 re_setup_rxdesc(sc, i); 1861 continue; 1862 } 1863 1864 if (sc->re_newbuf(sc, i, 0)) { 1865 /* Drop upcoming fragments */ 1866 sc->re_flags |= RE_F_DROP_RXFRAG; 1867 continue; 1868 } 1869 1870 m->m_len = MCLBYTES; 1871 if (sc->re_head == NULL) { 1872 sc->re_head = sc->re_tail = m; 1873 } else { 1874 sc->re_tail->m_next = m; 1875 sc->re_tail = m; 1876 } 1877 continue; 1878 } else if (sc->re_flags & RE_F_DROP_RXFRAG) { 1879 /* 1880 * Last fragment of a multi-fragment packet. 1881 * 1882 * Since error already happened, this fragment 1883 * must be dropped as well as the fragment chain. 1884 */ 1885 re_setup_rxdesc(sc, i); 1886 re_free_rxchain(sc); 1887 sc->re_flags &= ~RE_F_DROP_RXFRAG; 1888 continue; 1889 } 1890 1891 /* 1892 * NOTE: for the 8139C+, the frame length field 1893 * is always 12 bits in size, but for the gigE chips, 1894 * it is 13 bits (since the max RX frame length is 16K). 1895 * Unfortunately, all 32 bits in the status word 1896 * were already used, so to make room for the extra 1897 * length bit, RealTek took out the 'frame alignment 1898 * error' bit and shifted the other status bits 1899 * over one slot. The OWN, EOR, FS and LS bits are 1900 * still in the same places. We have already extracted 1901 * the frame length and checked the OWN bit, so rather 1902 * than using an alternate bit mapping, we shift the 1903 * status bits one space to the right so we can evaluate 1904 * them using the 8169 status as though it was in the 1905 * same format as that of the 8139C+. 1906 */ 1907 if (!RE_IS_8139CP(sc)) 1908 rxstat >>= 1; 1909 1910 if (rxstat & RE_RDESC_STAT_RXERRSUM) { 1911 ifp->if_ierrors++; 1912 /* 1913 * If this is part of a multi-fragment packet, 1914 * discard all the pieces. 1915 */ 1916 re_free_rxchain(sc); 1917 re_setup_rxdesc(sc, i); 1918 continue; 1919 } 1920 1921 /* 1922 * If allocating a replacement mbuf fails, 1923 * reload the current one. 1924 */ 1925 1926 if (sc->re_newbuf(sc, i, 0)) { 1927 ifp->if_ierrors++; 1928 continue; 1929 } 1930 1931 if (sc->re_head != NULL) { 1932 m->m_len = total_len % MCLBYTES; 1933 /* 1934 * Special case: if there's 4 bytes or less 1935 * in this buffer, the mbuf can be discarded: 1936 * the last 4 bytes is the CRC, which we don't 1937 * care about anyway. 1938 */ 1939 if (m->m_len <= ETHER_CRC_LEN) { 1940 sc->re_tail->m_len -= 1941 (ETHER_CRC_LEN - m->m_len); 1942 m_freem(m); 1943 } else { 1944 m->m_len -= ETHER_CRC_LEN; 1945 sc->re_tail->m_next = m; 1946 } 1947 m = sc->re_head; 1948 sc->re_head = sc->re_tail = NULL; 1949 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1950 } else { 1951 m->m_pkthdr.len = m->m_len = 1952 (total_len - ETHER_CRC_LEN); 1953 } 1954 1955 ifp->if_ipackets++; 1956 m->m_pkthdr.rcvif = ifp; 1957 1958 /* Do RX checksumming if enabled */ 1959 1960 if (ifp->if_capenable & IFCAP_RXCSUM) { 1961 uint8_t packet_type; 1962 1963 packet_type = re_packet_type(sc, rxstat, rxctrl); 1964 1965 /* Check IP header checksum */ 1966 if (packet_type & RE_IP4_PACKET) { 1967 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1968 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0) 1969 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1970 } 1971 1972 /* Check TCP/UDP checksum */ 1973 if (((packet_type & RE_TCP_PACKET) && 1974 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) || 1975 ((packet_type & RE_UDP_PACKET) && 1976 (rxstat & RE_RDESC_STAT_UDPSUMBAD) == 0)) { 1977 m->m_pkthdr.csum_flags |= 1978 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 1979 CSUM_FRAG_NOT_CHECKED; 1980 m->m_pkthdr.csum_data = 0xffff; 1981 } 1982 } 1983 1984 if (rxctrl & RE_RDESC_CTL_HASTAG) { 1985 m->m_flags |= M_VLANTAG; 1986 m->m_pkthdr.ether_vlantag = 1987 be16toh((rxctrl & RE_RDESC_CTL_TAGDATA)); 1988 } 1989 ether_input_chain(ifp, m, NULL, chain); 1990 } 1991 1992 ether_input_dispatch(chain); 1993 1994 sc->re_ldata.re_rx_prodidx = i; 1995 1996 return rx; 1997 } 1998 1999 #undef RE_IP4_PACKET 2000 #undef RE_TCP_PACKET 2001 #undef RE_UDP_PACKET 2002 2003 static int 2004 re_tx_collect(struct re_softc *sc) 2005 { 2006 struct ifnet *ifp = &sc->arpcom.ac_if; 2007 uint32_t txstat; 2008 int idx, tx = 0; 2009 2010 for (idx = sc->re_ldata.re_tx_considx; 2011 sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt; 2012 RE_TXDESC_INC(sc, idx)) { 2013 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat); 2014 if (txstat & RE_TDESC_CMD_OWN) 2015 break; 2016 2017 tx = 1; 2018 2019 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0; 2020 2021 /* 2022 * We only stash mbufs in the last descriptor 2023 * in a fragment chain, which also happens to 2024 * be the only place where the TX status bits 2025 * are valid. 2026 */ 2027 if (txstat & RE_TDESC_CMD_EOF) { 2028 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, 2029 sc->re_ldata.re_tx_dmamap[idx]); 2030 m_freem(sc->re_ldata.re_tx_mbuf[idx]); 2031 sc->re_ldata.re_tx_mbuf[idx] = NULL; 2032 if (txstat & (RE_TDESC_STAT_EXCESSCOL| 2033 RE_TDESC_STAT_COLCNT)) 2034 ifp->if_collisions++; 2035 if (txstat & RE_TDESC_STAT_TXERRSUM) 2036 ifp->if_oerrors++; 2037 else 2038 ifp->if_opackets++; 2039 } 2040 sc->re_ldata.re_tx_free++; 2041 } 2042 sc->re_ldata.re_tx_considx = idx; 2043 2044 return tx; 2045 } 2046 2047 static int 2048 re_txeof(struct re_softc *sc) 2049 { 2050 struct ifnet *ifp = &sc->arpcom.ac_if; 2051 int tx; 2052 2053 tx = re_tx_collect(sc); 2054 2055 /* There is enough free TX descs */ 2056 if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE) 2057 ifp->if_flags &= ~IFF_OACTIVE; 2058 2059 /* 2060 * Some chips will ignore a second TX request issued while an 2061 * existing transmission is in progress. If the transmitter goes 2062 * idle but there are still packets waiting to be sent, we need 2063 * to restart the channel here to flush them out. This only seems 2064 * to be required with the PCIe devices. 2065 */ 2066 if (sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt) 2067 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2068 else 2069 ifp->if_timer = 0; 2070 2071 return tx; 2072 } 2073 2074 static void 2075 re_tick(void *xsc) 2076 { 2077 struct re_softc *sc = xsc; 2078 2079 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 2080 re_tick_serialized(xsc); 2081 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 2082 } 2083 2084 static void 2085 re_tick_serialized(void *xsc) 2086 { 2087 struct re_softc *sc = xsc; 2088 struct ifnet *ifp = &sc->arpcom.ac_if; 2089 struct mii_data *mii; 2090 2091 ASSERT_SERIALIZED(ifp->if_serializer); 2092 2093 mii = device_get_softc(sc->re_miibus); 2094 mii_tick(mii); 2095 if (sc->re_flags & RE_F_LINKED) { 2096 if (!(mii->mii_media_status & IFM_ACTIVE)) 2097 sc->re_flags &= ~RE_F_LINKED; 2098 } else { 2099 if (mii->mii_media_status & IFM_ACTIVE && 2100 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2101 sc->re_flags |= RE_F_LINKED; 2102 if (!ifq_is_empty(&ifp->if_snd)) 2103 if_devstart(ifp); 2104 } 2105 } 2106 2107 callout_reset(&sc->re_timer, hz, re_tick, sc); 2108 } 2109 2110 #ifdef DEVICE_POLLING 2111 2112 static void 2113 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2114 { 2115 struct re_softc *sc = ifp->if_softc; 2116 2117 ASSERT_SERIALIZED(ifp->if_serializer); 2118 2119 switch(cmd) { 2120 case POLL_REGISTER: 2121 /* disable interrupts */ 2122 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 2123 break; 2124 2125 case POLL_DEREGISTER: 2126 /* enable interrupts */ 2127 re_setup_intr(sc, 1, sc->re_imtype); 2128 break; 2129 2130 default: 2131 sc->rxcycles = count; 2132 re_rxeof(sc); 2133 re_txeof(sc); 2134 2135 if (!ifq_is_empty(&ifp->if_snd)) 2136 if_devstart(ifp); 2137 2138 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2139 uint16_t status; 2140 2141 status = CSR_READ_2(sc, RE_ISR); 2142 if (status == 0xffff) 2143 return; 2144 if (status) 2145 CSR_WRITE_2(sc, RE_ISR, status); 2146 2147 /* 2148 * XXX check behaviour on receiver stalls. 2149 */ 2150 2151 if (status & RE_ISR_SYSTEM_ERR) 2152 re_init(sc); 2153 } 2154 break; 2155 } 2156 } 2157 #endif /* DEVICE_POLLING */ 2158 2159 static void 2160 re_intr(void *arg) 2161 { 2162 struct re_softc *sc = arg; 2163 struct ifnet *ifp = &sc->arpcom.ac_if; 2164 uint16_t status; 2165 int rx, tx; 2166 2167 ASSERT_SERIALIZED(ifp->if_serializer); 2168 2169 if ((sc->re_flags & RE_F_SUSPENDED) || 2170 (ifp->if_flags & IFF_RUNNING) == 0) 2171 return; 2172 2173 rx = tx = 0; 2174 for (;;) { 2175 status = CSR_READ_2(sc, RE_ISR); 2176 /* If the card has gone away the read returns 0xffff. */ 2177 if (status == 0xffff) 2178 break; 2179 if (status) 2180 CSR_WRITE_2(sc, RE_ISR, status); 2181 2182 if ((status & sc->re_intrs) == 0) 2183 break; 2184 2185 if (status & (sc->re_rx_ack | RE_ISR_RX_ERR)) 2186 rx |= re_rxeof(sc); 2187 2188 if (status & (sc->re_tx_ack | RE_ISR_TX_ERR)) 2189 tx |= re_txeof(sc); 2190 2191 if (status & RE_ISR_SYSTEM_ERR) 2192 re_init(sc); 2193 2194 if (status & RE_ISR_LINKCHG) { 2195 callout_stop(&sc->re_timer); 2196 re_tick_serialized(sc); 2197 } 2198 } 2199 2200 if (sc->re_imtype == RE_IMTYPE_SIM) { 2201 if ((sc->re_flags & RE_F_TIMER_INTR)) { 2202 if ((tx | rx) == 0) { 2203 /* 2204 * Nothing needs to be processed, fallback 2205 * to use TX/RX interrupts. 2206 */ 2207 re_setup_intr(sc, 1, RE_IMTYPE_NONE); 2208 2209 /* 2210 * Recollect, mainly to avoid the possible 2211 * race introduced by changing interrupt 2212 * masks. 2213 */ 2214 re_rxeof(sc); 2215 tx = re_txeof(sc); 2216 } else { 2217 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */ 2218 } 2219 } else if (tx | rx) { 2220 /* 2221 * Assume that using simulated interrupt moderation 2222 * (hardware timer based) could reduce the interript 2223 * rate. 2224 */ 2225 re_setup_intr(sc, 1, RE_IMTYPE_SIM); 2226 } 2227 } 2228 2229 if (tx && !ifq_is_empty(&ifp->if_snd)) 2230 if_devstart(ifp); 2231 } 2232 2233 static int 2234 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0) 2235 { 2236 struct mbuf *m = *m_head; 2237 bus_dma_segment_t segs[RE_MAXSEGS]; 2238 bus_dmamap_t map; 2239 int error, maxsegs, idx, i, nsegs; 2240 struct re_desc *d, *tx_ring; 2241 uint32_t cmd_csum, ctl_csum, vlantag; 2242 2243 KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE, 2244 ("not enough free TX desc\n")); 2245 2246 map = sc->re_ldata.re_tx_dmamap[*idx0]; 2247 2248 /* 2249 * Set up checksum offload. Note: checksum offload bits must 2250 * appear in all descriptors of a multi-descriptor transmit 2251 * attempt. (This is according to testing done with an 8169 2252 * chip. I'm not sure if this is a requirement or a bug.) 2253 */ 2254 cmd_csum = ctl_csum = 0; 2255 if (m->m_pkthdr.csum_flags & CSUM_IP) { 2256 cmd_csum |= RE_TDESC_CMD_IPCSUM; 2257 ctl_csum |= RE_TDESC_CTL_IPCSUM; 2258 } 2259 if (m->m_pkthdr.csum_flags & CSUM_TCP) { 2260 cmd_csum |= RE_TDESC_CMD_TCPCSUM; 2261 ctl_csum |= RE_TDESC_CTL_TCPCSUM; 2262 } 2263 if (m->m_pkthdr.csum_flags & CSUM_UDP) { 2264 cmd_csum |= RE_TDESC_CMD_UDPCSUM; 2265 ctl_csum |= RE_TDESC_CTL_UDPCSUM; 2266 } 2267 2268 /* For MAC2 chips, csum flags are set on re_control */ 2269 if (sc->re_caps & RE_C_MAC2) 2270 cmd_csum = 0; 2271 else 2272 ctl_csum = 0; 2273 2274 if ((sc->re_caps & RE_C_AUTOPAD) == 0) { 2275 /* 2276 * With some of the RealTek chips, using the checksum offload 2277 * support in conjunction with the autopadding feature results 2278 * in the transmission of corrupt frames. For example, if we 2279 * need to send a really small IP fragment that's less than 60 2280 * bytes in size, and IP header checksumming is enabled, the 2281 * resulting ethernet frame that appears on the wire will 2282 * have garbled payload. To work around this, if TX checksum 2283 * offload is enabled, we always manually pad short frames out 2284 * to the minimum ethernet frame size. 2285 * 2286 * Note: this appears unnecessary for TCP, and doing it for TCP 2287 * with PCIe adapters seems to result in bad checksums. 2288 */ 2289 if ((m->m_pkthdr.csum_flags & 2290 (CSUM_DELAY_IP | CSUM_DELAY_DATA)) && 2291 (m->m_pkthdr.csum_flags & CSUM_TCP) == 0 && 2292 m->m_pkthdr.len < RE_MIN_FRAMELEN) { 2293 error = m_devpad(m, RE_MIN_FRAMELEN); 2294 if (error) 2295 goto back; 2296 } 2297 } 2298 2299 vlantag = 0; 2300 if (m->m_flags & M_VLANTAG) { 2301 vlantag = htobe16(m->m_pkthdr.ether_vlantag) | 2302 RE_TDESC_CTL_INSTAG; 2303 } 2304 2305 maxsegs = sc->re_ldata.re_tx_free; 2306 if (maxsegs > RE_MAXSEGS) 2307 maxsegs = RE_MAXSEGS; 2308 2309 error = bus_dmamap_load_mbuf_defrag(sc->re_ldata.re_tx_mtag, map, 2310 m_head, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 2311 if (error) 2312 goto back; 2313 2314 m = *m_head; 2315 bus_dmamap_sync(sc->re_ldata.re_tx_mtag, map, BUS_DMASYNC_PREWRITE); 2316 2317 /* 2318 * Map the segment array into descriptors. We also keep track 2319 * of the end of the ring and set the end-of-ring bits as needed, 2320 * and we set the ownership bits in all except the very first 2321 * descriptor, whose ownership bits will be turned on later. 2322 */ 2323 tx_ring = sc->re_ldata.re_tx_list; 2324 idx = *idx0; 2325 i = 0; 2326 for (;;) { 2327 uint32_t cmdstat; 2328 2329 d = &tx_ring[idx]; 2330 2331 cmdstat = segs[i].ds_len; 2332 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr)); 2333 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr)); 2334 if (i == 0) 2335 cmdstat |= RE_TDESC_CMD_SOF; 2336 else 2337 cmdstat |= RE_TDESC_CMD_OWN; 2338 if (idx == (sc->re_tx_desc_cnt - 1)) 2339 cmdstat |= RE_TDESC_CMD_EOR; 2340 d->re_cmdstat = htole32(cmdstat | cmd_csum); 2341 d->re_control = htole32(ctl_csum | vlantag); 2342 2343 i++; 2344 if (i == nsegs) 2345 break; 2346 RE_TXDESC_INC(sc, idx); 2347 } 2348 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF); 2349 2350 /* Transfer ownership of packet to the chip. */ 2351 d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN); 2352 if (*idx0 != idx) 2353 tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN); 2354 2355 /* 2356 * Insure that the map for this transmission 2357 * is placed at the array index of the last descriptor 2358 * in this chain. 2359 */ 2360 sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx]; 2361 sc->re_ldata.re_tx_dmamap[idx] = map; 2362 2363 sc->re_ldata.re_tx_mbuf[idx] = m; 2364 sc->re_ldata.re_tx_free -= nsegs; 2365 2366 RE_TXDESC_INC(sc, idx); 2367 *idx0 = idx; 2368 back: 2369 if (error) { 2370 m_freem(*m_head); 2371 *m_head = NULL; 2372 } 2373 return error; 2374 } 2375 2376 /* 2377 * Main transmit routine for C+ and gigE NICs. 2378 */ 2379 2380 static void 2381 re_start(struct ifnet *ifp) 2382 { 2383 struct re_softc *sc = ifp->if_softc; 2384 struct mbuf *m_head; 2385 int idx, need_trans, oactive, error; 2386 2387 ASSERT_SERIALIZED(ifp->if_serializer); 2388 2389 if ((sc->re_flags & RE_F_LINKED) == 0) { 2390 ifq_purge(&ifp->if_snd); 2391 return; 2392 } 2393 2394 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 2395 return; 2396 2397 idx = sc->re_ldata.re_tx_prodidx; 2398 2399 need_trans = 0; 2400 oactive = 0; 2401 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) { 2402 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) { 2403 if (!oactive) { 2404 if (re_tx_collect(sc)) { 2405 oactive = 1; 2406 continue; 2407 } 2408 } 2409 ifp->if_flags |= IFF_OACTIVE; 2410 break; 2411 } 2412 2413 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2414 if (m_head == NULL) 2415 break; 2416 2417 error = re_encap(sc, &m_head, &idx); 2418 if (error) { 2419 /* m_head is freed by re_encap(), if we reach here */ 2420 ifp->if_oerrors++; 2421 2422 if (error == EFBIG && !oactive) { 2423 if (re_tx_collect(sc)) { 2424 oactive = 1; 2425 continue; 2426 } 2427 } 2428 ifp->if_flags |= IFF_OACTIVE; 2429 break; 2430 } 2431 2432 oactive = 0; 2433 need_trans = 1; 2434 2435 /* 2436 * If there's a BPF listener, bounce a copy of this frame 2437 * to him. 2438 */ 2439 ETHER_BPF_MTAP(ifp, m_head); 2440 } 2441 2442 if (!need_trans) 2443 return; 2444 2445 sc->re_ldata.re_tx_prodidx = idx; 2446 2447 /* 2448 * RealTek put the TX poll request register in a different 2449 * location on the 8169 gigE chip. I don't know why. 2450 */ 2451 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2452 2453 /* 2454 * Set a timeout in case the chip goes out to lunch. 2455 */ 2456 ifp->if_timer = 5; 2457 } 2458 2459 static void 2460 re_init(void *xsc) 2461 { 2462 struct re_softc *sc = xsc; 2463 struct ifnet *ifp = &sc->arpcom.ac_if; 2464 struct mii_data *mii; 2465 int error, framelen; 2466 2467 ASSERT_SERIALIZED(ifp->if_serializer); 2468 2469 mii = device_get_softc(sc->re_miibus); 2470 2471 /* 2472 * Cancel pending I/O and free all RX/TX buffers. 2473 */ 2474 re_stop(sc); 2475 2476 if (sc->re_caps & RE_C_CONTIGRX) { 2477 if (ifp->if_mtu > ETHERMTU) { 2478 KKASSERT(sc->re_ldata.re_jbuf != NULL); 2479 sc->re_flags |= RE_F_USE_JPOOL; 2480 sc->re_rxbuf_size = RE_FRAMELEN_MAX; 2481 sc->re_newbuf = re_newbuf_jumbo; 2482 } else { 2483 sc->re_flags &= ~RE_F_USE_JPOOL; 2484 sc->re_rxbuf_size = MCLBYTES; 2485 sc->re_newbuf = re_newbuf_std; 2486 } 2487 } 2488 2489 /* 2490 * Adjust max read request size according to MTU; mainly to 2491 * improve TX performance for common case (ETHERMTU) on GigE 2492 * NICs. However, this could _not_ be done on 10/100 only 2493 * NICs; their DMA engines will malfunction using non-default 2494 * max read request size. 2495 */ 2496 if ((sc->re_caps & (RE_C_PCIE | RE_C_FASTE)) == RE_C_PCIE) { 2497 if (ifp->if_mtu > ETHERMTU) { 2498 /* 2499 * 512 seems to be the only value that works 2500 * reliably with jumbo frame 2501 */ 2502 pcie_set_max_readrq(sc->re_dev, 2503 PCIEM_DEVCTL_MAX_READRQ_512); 2504 } else { 2505 pcie_set_max_readrq(sc->re_dev, 2506 PCIEM_DEVCTL_MAX_READRQ_4096); 2507 } 2508 } 2509 2510 /* 2511 * Enable C+ RX and TX mode, as well as VLAN stripping and 2512 * RX checksum offload. We must configure the C+ register 2513 * before all others. 2514 */ 2515 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB | 2516 RE_CPLUSCMD_PCI_MRW | 2517 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 2518 RE_CPLUSCMD_VLANSTRIP : 0) | 2519 (ifp->if_capenable & IFCAP_RXCSUM ? 2520 RE_CPLUSCMD_RXCSUM_ENB : 0)); 2521 2522 /* 2523 * Init our MAC address. Even though the chipset 2524 * documentation doesn't mention it, we need to enter "Config 2525 * register write enable" mode to modify the ID registers. 2526 */ 2527 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG); 2528 CSR_WRITE_4(sc, RE_IDR0, 2529 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0]))); 2530 CSR_WRITE_2(sc, RE_IDR4, 2531 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4]))); 2532 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 2533 2534 /* 2535 * For C+ mode, initialize the RX descriptors and mbufs. 2536 */ 2537 error = re_rx_list_init(sc); 2538 if (error) { 2539 re_stop(sc); 2540 return; 2541 } 2542 error = re_tx_list_init(sc); 2543 if (error) { 2544 re_stop(sc); 2545 return; 2546 } 2547 2548 /* 2549 * Load the addresses of the RX and TX lists into the chip. 2550 */ 2551 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI, 2552 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr)); 2553 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO, 2554 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr)); 2555 2556 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI, 2557 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr)); 2558 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO, 2559 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr)); 2560 2561 /* 2562 * Enable transmit and receive. 2563 */ 2564 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2565 2566 /* 2567 * Set the initial TX and RX configuration. 2568 */ 2569 if (sc->re_flags & RE_F_TESTMODE) { 2570 if (!RE_IS_8139CP(sc)) 2571 CSR_WRITE_4(sc, RE_TXCFG, 2572 RE_TXCFG_CONFIG | RE_LOOPTEST_ON); 2573 else 2574 CSR_WRITE_4(sc, RE_TXCFG, 2575 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS); 2576 } else 2577 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG); 2578 2579 framelen = RE_FRAMELEN(ifp->if_mtu); 2580 if (framelen < MCLBYTES) 2581 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(MCLBYTES, 128)); 2582 else 2583 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128)); 2584 2585 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG); 2586 2587 /* 2588 * Program the multicast filter, if necessary. 2589 */ 2590 re_setmulti(sc); 2591 2592 #ifdef DEVICE_POLLING 2593 /* 2594 * Disable interrupts if we are polling. 2595 */ 2596 if (ifp->if_flags & IFF_POLLING) 2597 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 2598 else /* otherwise ... */ 2599 #endif /* DEVICE_POLLING */ 2600 /* 2601 * Enable interrupts. 2602 */ 2603 if (sc->re_flags & RE_F_TESTMODE) 2604 CSR_WRITE_2(sc, RE_IMR, 0); 2605 else 2606 re_setup_intr(sc, 1, sc->re_imtype); 2607 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs); 2608 2609 /* Start RX/TX process. */ 2610 CSR_WRITE_4(sc, RE_MISSEDPKT, 0); 2611 2612 #ifdef notdef 2613 /* Enable receiver and transmitter. */ 2614 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2615 #endif 2616 2617 /* 2618 * For 8169 gigE NICs, set the max allowed RX packet 2619 * size so we can receive jumbo frames. 2620 */ 2621 if (!RE_IS_8139CP(sc)) { 2622 if (sc->re_caps & RE_C_CONTIGRX) 2623 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, sc->re_rxbuf_size); 2624 else 2625 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383); 2626 } 2627 2628 if (sc->re_flags & RE_F_TESTMODE) 2629 return; 2630 2631 mii_mediachg(mii); 2632 2633 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX); 2634 2635 ifp->if_flags |= IFF_RUNNING; 2636 ifp->if_flags &= ~IFF_OACTIVE; 2637 2638 callout_reset(&sc->re_timer, hz, re_tick, sc); 2639 } 2640 2641 /* 2642 * Set media options. 2643 */ 2644 static int 2645 re_ifmedia_upd(struct ifnet *ifp) 2646 { 2647 struct re_softc *sc = ifp->if_softc; 2648 struct mii_data *mii; 2649 2650 ASSERT_SERIALIZED(ifp->if_serializer); 2651 2652 mii = device_get_softc(sc->re_miibus); 2653 mii_mediachg(mii); 2654 2655 return(0); 2656 } 2657 2658 /* 2659 * Report current media status. 2660 */ 2661 static void 2662 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2663 { 2664 struct re_softc *sc = ifp->if_softc; 2665 struct mii_data *mii; 2666 2667 ASSERT_SERIALIZED(ifp->if_serializer); 2668 2669 mii = device_get_softc(sc->re_miibus); 2670 2671 mii_pollstat(mii); 2672 ifmr->ifm_active = mii->mii_media_active; 2673 ifmr->ifm_status = mii->mii_media_status; 2674 } 2675 2676 static int 2677 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2678 { 2679 struct re_softc *sc = ifp->if_softc; 2680 struct ifreq *ifr = (struct ifreq *) data; 2681 struct mii_data *mii; 2682 int error = 0, mask; 2683 2684 ASSERT_SERIALIZED(ifp->if_serializer); 2685 2686 switch(command) { 2687 case SIOCSIFMTU: 2688 if (ifr->ifr_mtu > sc->re_maxmtu) { 2689 error = EINVAL; 2690 } else if (ifp->if_mtu != ifr->ifr_mtu) { 2691 ifp->if_mtu = ifr->ifr_mtu; 2692 if (ifp->if_flags & IFF_RUNNING) 2693 ifp->if_init(sc); 2694 } 2695 break; 2696 2697 case SIOCSIFFLAGS: 2698 if (ifp->if_flags & IFF_UP) { 2699 if (ifp->if_flags & IFF_RUNNING) { 2700 if ((ifp->if_flags ^ sc->re_if_flags) & 2701 (IFF_PROMISC | IFF_ALLMULTI)) 2702 re_setmulti(sc); 2703 } else { 2704 re_init(sc); 2705 } 2706 } else if (ifp->if_flags & IFF_RUNNING) { 2707 re_stop(sc); 2708 } 2709 sc->re_if_flags = ifp->if_flags; 2710 break; 2711 2712 case SIOCADDMULTI: 2713 case SIOCDELMULTI: 2714 re_setmulti(sc); 2715 break; 2716 2717 case SIOCGIFMEDIA: 2718 case SIOCSIFMEDIA: 2719 mii = device_get_softc(sc->re_miibus); 2720 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2721 break; 2722 2723 case SIOCSIFCAP: 2724 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & 2725 ifp->if_capabilities; 2726 ifp->if_capenable ^= mask; 2727 2728 if (mask & IFCAP_HWCSUM) { 2729 if (ifp->if_capenable & IFCAP_TXCSUM) 2730 ifp->if_hwassist = RE_CSUM_FEATURES; 2731 else 2732 ifp->if_hwassist = 0; 2733 } 2734 if (mask && (ifp->if_flags & IFF_RUNNING)) 2735 re_init(sc); 2736 break; 2737 2738 default: 2739 error = ether_ioctl(ifp, command, data); 2740 break; 2741 } 2742 return(error); 2743 } 2744 2745 static void 2746 re_watchdog(struct ifnet *ifp) 2747 { 2748 struct re_softc *sc = ifp->if_softc; 2749 2750 ASSERT_SERIALIZED(ifp->if_serializer); 2751 2752 if_printf(ifp, "watchdog timeout\n"); 2753 2754 ifp->if_oerrors++; 2755 2756 re_txeof(sc); 2757 re_rxeof(sc); 2758 2759 re_init(sc); 2760 2761 if (!ifq_is_empty(&ifp->if_snd)) 2762 if_devstart(ifp); 2763 } 2764 2765 /* 2766 * Stop the adapter and free any mbufs allocated to the 2767 * RX and TX lists. 2768 */ 2769 static void 2770 re_stop(struct re_softc *sc) 2771 { 2772 struct ifnet *ifp = &sc->arpcom.ac_if; 2773 int i; 2774 2775 ASSERT_SERIALIZED(ifp->if_serializer); 2776 2777 /* Reset the adapter. */ 2778 re_reset(sc, ifp->if_flags & IFF_RUNNING); 2779 2780 ifp->if_timer = 0; 2781 callout_stop(&sc->re_timer); 2782 2783 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2784 sc->re_flags &= ~(RE_F_TIMER_INTR | RE_F_DROP_RXFRAG | RE_F_LINKED); 2785 2786 CSR_WRITE_1(sc, RE_COMMAND, 0x00); 2787 CSR_WRITE_2(sc, RE_IMR, 0x0000); 2788 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 2789 2790 re_free_rxchain(sc); 2791 2792 /* Free the TX list buffers. */ 2793 for (i = 0; i < sc->re_tx_desc_cnt; i++) { 2794 if (sc->re_ldata.re_tx_mbuf[i] != NULL) { 2795 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, 2796 sc->re_ldata.re_tx_dmamap[i]); 2797 m_freem(sc->re_ldata.re_tx_mbuf[i]); 2798 sc->re_ldata.re_tx_mbuf[i] = NULL; 2799 } 2800 } 2801 2802 /* Free the RX list buffers. */ 2803 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 2804 if (sc->re_ldata.re_rx_mbuf[i] != NULL) { 2805 if ((sc->re_flags & RE_F_USE_JPOOL) == 0) { 2806 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 2807 sc->re_ldata.re_rx_dmamap[i]); 2808 } 2809 m_freem(sc->re_ldata.re_rx_mbuf[i]); 2810 sc->re_ldata.re_rx_mbuf[i] = NULL; 2811 } 2812 } 2813 } 2814 2815 /* 2816 * Device suspend routine. Stop the interface and save some PCI 2817 * settings in case the BIOS doesn't restore them properly on 2818 * resume. 2819 */ 2820 static int 2821 re_suspend(device_t dev) 2822 { 2823 #ifndef BURN_BRIDGES 2824 int i; 2825 #endif 2826 struct re_softc *sc = device_get_softc(dev); 2827 struct ifnet *ifp = &sc->arpcom.ac_if; 2828 2829 lwkt_serialize_enter(ifp->if_serializer); 2830 2831 re_stop(sc); 2832 2833 #ifndef BURN_BRIDGES 2834 for (i = 0; i < 5; i++) 2835 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2836 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2837 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2838 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2839 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2840 #endif 2841 2842 sc->re_flags |= RE_F_SUSPENDED; 2843 2844 lwkt_serialize_exit(ifp->if_serializer); 2845 2846 return (0); 2847 } 2848 2849 /* 2850 * Device resume routine. Restore some PCI settings in case the BIOS 2851 * doesn't, re-enable busmastering, and restart the interface if 2852 * appropriate. 2853 */ 2854 static int 2855 re_resume(device_t dev) 2856 { 2857 struct re_softc *sc = device_get_softc(dev); 2858 struct ifnet *ifp = &sc->arpcom.ac_if; 2859 #ifndef BURN_BRIDGES 2860 int i; 2861 #endif 2862 2863 lwkt_serialize_enter(ifp->if_serializer); 2864 2865 #ifndef BURN_BRIDGES 2866 /* better way to do this? */ 2867 for (i = 0; i < 5; i++) 2868 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2869 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2870 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2871 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2872 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2873 2874 /* reenable busmastering */ 2875 pci_enable_busmaster(dev); 2876 pci_enable_io(dev, SYS_RES_IOPORT); 2877 #endif 2878 2879 /* reinitialize interface if necessary */ 2880 if (ifp->if_flags & IFF_UP) 2881 re_init(sc); 2882 2883 sc->re_flags &= ~RE_F_SUSPENDED; 2884 2885 lwkt_serialize_exit(ifp->if_serializer); 2886 2887 return (0); 2888 } 2889 2890 /* 2891 * Stop all chip I/O so that the kernel's probe routines don't 2892 * get confused by errant DMAs when rebooting. 2893 */ 2894 static void 2895 re_shutdown(device_t dev) 2896 { 2897 struct re_softc *sc = device_get_softc(dev); 2898 struct ifnet *ifp = &sc->arpcom.ac_if; 2899 2900 lwkt_serialize_enter(ifp->if_serializer); 2901 re_stop(sc); 2902 lwkt_serialize_exit(ifp->if_serializer); 2903 } 2904 2905 static int 2906 re_sysctl_rxtime(SYSCTL_HANDLER_ARGS) 2907 { 2908 struct re_softc *sc = arg1; 2909 2910 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_rx_time); 2911 } 2912 2913 static int 2914 re_sysctl_txtime(SYSCTL_HANDLER_ARGS) 2915 { 2916 struct re_softc *sc = arg1; 2917 2918 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_tx_time); 2919 } 2920 2921 static int 2922 re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *hwtime) 2923 { 2924 struct re_softc *sc = arg1; 2925 struct ifnet *ifp = &sc->arpcom.ac_if; 2926 int error, v; 2927 2928 lwkt_serialize_enter(ifp->if_serializer); 2929 2930 v = *hwtime; 2931 error = sysctl_handle_int(oidp, &v, 0, req); 2932 if (error || req->newptr == NULL) 2933 goto back; 2934 2935 if (v <= 0) { 2936 error = EINVAL; 2937 goto back; 2938 } 2939 2940 if (v != *hwtime) { 2941 *hwtime = v; 2942 2943 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) == 2944 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_HW) 2945 re_setup_hw_im(sc); 2946 } 2947 back: 2948 lwkt_serialize_exit(ifp->if_serializer); 2949 return error; 2950 } 2951 2952 static int 2953 re_sysctl_simtime(SYSCTL_HANDLER_ARGS) 2954 { 2955 struct re_softc *sc = arg1; 2956 struct ifnet *ifp = &sc->arpcom.ac_if; 2957 int error, v; 2958 2959 lwkt_serialize_enter(ifp->if_serializer); 2960 2961 v = sc->re_sim_time; 2962 error = sysctl_handle_int(oidp, &v, 0, req); 2963 if (error || req->newptr == NULL) 2964 goto back; 2965 2966 if (v <= 0) { 2967 error = EINVAL; 2968 goto back; 2969 } 2970 2971 if (v != sc->re_sim_time) { 2972 sc->re_sim_time = v; 2973 2974 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) == 2975 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_SIM) { 2976 #ifdef foo 2977 int reg; 2978 2979 /* 2980 * Following code causes various strange 2981 * performance problems. Hmm ... 2982 */ 2983 CSR_WRITE_2(sc, RE_IMR, 0); 2984 if (!RE_IS_8139CP(sc)) 2985 reg = RE_TIMERINT_8169; 2986 else 2987 reg = RE_TIMERINT; 2988 CSR_WRITE_4(sc, reg, 0); 2989 CSR_READ_4(sc, reg); /* flush */ 2990 2991 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 2992 re_setup_sim_im(sc); 2993 #else 2994 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 2995 DELAY(10); 2996 re_setup_intr(sc, 1, RE_IMTYPE_SIM); 2997 #endif 2998 } 2999 } 3000 back: 3001 lwkt_serialize_exit(ifp->if_serializer); 3002 return error; 3003 } 3004 3005 static int 3006 re_sysctl_imtype(SYSCTL_HANDLER_ARGS) 3007 { 3008 struct re_softc *sc = arg1; 3009 struct ifnet *ifp = &sc->arpcom.ac_if; 3010 int error, v; 3011 3012 lwkt_serialize_enter(ifp->if_serializer); 3013 3014 v = sc->re_imtype; 3015 error = sysctl_handle_int(oidp, &v, 0, req); 3016 if (error || req->newptr == NULL) 3017 goto back; 3018 3019 if (v != RE_IMTYPE_HW && v != RE_IMTYPE_SIM && v != RE_IMTYPE_NONE) { 3020 error = EINVAL; 3021 goto back; 3022 } 3023 if (v == RE_IMTYPE_HW && (sc->re_caps & RE_C_HWIM) == 0) { 3024 /* Can't do hardware interrupt moderation */ 3025 error = EOPNOTSUPP; 3026 goto back; 3027 } 3028 3029 if (v != sc->re_imtype) { 3030 sc->re_imtype = v; 3031 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) == 3032 IFF_RUNNING) 3033 re_setup_intr(sc, 1, sc->re_imtype); 3034 } 3035 back: 3036 lwkt_serialize_exit(ifp->if_serializer); 3037 return error; 3038 } 3039 3040 static void 3041 re_setup_hw_im(struct re_softc *sc) 3042 { 3043 KKASSERT(sc->re_caps & RE_C_HWIM); 3044 3045 /* 3046 * Interrupt moderation 3047 * 3048 * 0xABCD 3049 * A - unknown (maybe TX related) 3050 * B - TX timer (unit: 25us) 3051 * C - unknown (maybe RX related) 3052 * D - RX timer (unit: 25us) 3053 * 3054 * 3055 * re(4)'s interrupt moderation is actually controlled by 3056 * two variables, like most other NICs (bge, bce etc.) 3057 * o timer 3058 * o number of packets [P] 3059 * 3060 * The logic relationship between these two variables is 3061 * similar to other NICs too: 3062 * if (timer expire || packets > [P]) 3063 * Interrupt is delivered 3064 * 3065 * Currently we only know how to set 'timer', but not 3066 * 'number of packets', which should be ~30, as far as I 3067 * tested (sink ~900Kpps, interrupt rate is 30KHz) 3068 */ 3069 CSR_WRITE_2(sc, RE_IM, 3070 RE_IM_RXTIME(sc->re_rx_time) | 3071 RE_IM_TXTIME(sc->re_tx_time) | 3072 RE_IM_MAGIC); 3073 } 3074 3075 static void 3076 re_disable_hw_im(struct re_softc *sc) 3077 { 3078 if (sc->re_caps & RE_C_HWIM) 3079 CSR_WRITE_2(sc, RE_IM, 0); 3080 } 3081 3082 static void 3083 re_setup_sim_im(struct re_softc *sc) 3084 { 3085 if (!RE_IS_8139CP(sc)) { 3086 uint32_t ticks; 3087 3088 /* 3089 * Datasheet says tick decreases at bus speed, 3090 * but it seems the clock runs a little bit 3091 * faster, so we do some compensation here. 3092 */ 3093 ticks = (sc->re_sim_time * sc->re_bus_speed * 8) / 5; 3094 CSR_WRITE_4(sc, RE_TIMERINT_8169, ticks); 3095 } else { 3096 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); /* XXX */ 3097 } 3098 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */ 3099 sc->re_flags |= RE_F_TIMER_INTR; 3100 } 3101 3102 static void 3103 re_disable_sim_im(struct re_softc *sc) 3104 { 3105 if (!RE_IS_8139CP(sc)) 3106 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0); 3107 else 3108 CSR_WRITE_4(sc, RE_TIMERINT, 0); 3109 sc->re_flags &= ~RE_F_TIMER_INTR; 3110 } 3111 3112 static void 3113 re_config_imtype(struct re_softc *sc, int imtype) 3114 { 3115 switch (imtype) { 3116 case RE_IMTYPE_HW: 3117 KKASSERT(sc->re_caps & RE_C_HWIM); 3118 /* FALL THROUGH */ 3119 case RE_IMTYPE_NONE: 3120 sc->re_intrs = RE_INTRS; 3121 sc->re_rx_ack = RE_ISR_RX_OK | RE_ISR_FIFO_OFLOW | 3122 RE_ISR_RX_OVERRUN; 3123 sc->re_tx_ack = RE_ISR_TX_OK; 3124 break; 3125 3126 case RE_IMTYPE_SIM: 3127 sc->re_intrs = RE_INTRS_TIMER; 3128 sc->re_rx_ack = RE_ISR_TIMEOUT_EXPIRED; 3129 sc->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED; 3130 break; 3131 3132 default: 3133 panic("%s: unknown imtype %d\n", 3134 sc->arpcom.ac_if.if_xname, imtype); 3135 } 3136 } 3137 3138 static void 3139 re_setup_intr(struct re_softc *sc, int enable_intrs, int imtype) 3140 { 3141 re_config_imtype(sc, imtype); 3142 3143 if (enable_intrs) 3144 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 3145 else 3146 CSR_WRITE_2(sc, RE_IMR, 0); 3147 3148 switch (imtype) { 3149 case RE_IMTYPE_NONE: 3150 re_disable_sim_im(sc); 3151 re_disable_hw_im(sc); 3152 break; 3153 3154 case RE_IMTYPE_HW: 3155 KKASSERT(sc->re_caps & RE_C_HWIM); 3156 re_disable_sim_im(sc); 3157 re_setup_hw_im(sc); 3158 break; 3159 3160 case RE_IMTYPE_SIM: 3161 re_disable_hw_im(sc); 3162 re_setup_sim_im(sc); 3163 break; 3164 3165 default: 3166 panic("%s: unknown imtype %d\n", 3167 sc->arpcom.ac_if.if_xname, imtype); 3168 } 3169 } 3170 3171 static void 3172 re_get_eaddr(struct re_softc *sc, uint8_t *eaddr) 3173 { 3174 int i; 3175 3176 if (sc->re_macver == RE_MACVER_11 || sc->re_macver == RE_MACVER_12) { 3177 uint16_t re_did; 3178 3179 re_get_eewidth(sc); 3180 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 3181 if (re_did == 0x8128) { 3182 uint16_t as[ETHER_ADDR_LEN / 2]; 3183 3184 /* 3185 * Get station address from the EEPROM. 3186 */ 3187 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3); 3188 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 3189 as[i] = le16toh(as[i]); 3190 bcopy(as, eaddr, sizeof(eaddr)); 3191 return; 3192 } 3193 } 3194 3195 /* 3196 * Get station address from IDRx. 3197 */ 3198 for (i = 0; i < ETHER_ADDR_LEN; ++i) 3199 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i); 3200 } 3201 3202 static int 3203 re_jpool_alloc(struct re_softc *sc) 3204 { 3205 struct re_list_data *ldata = &sc->re_ldata; 3206 struct re_jbuf *jbuf; 3207 bus_addr_t paddr; 3208 bus_size_t jpool_size; 3209 bus_dmamem_t dmem; 3210 caddr_t buf; 3211 int i, error; 3212 3213 lwkt_serialize_init(&ldata->re_jbuf_serializer); 3214 3215 ldata->re_jbuf = kmalloc(sizeof(struct re_jbuf) * RE_JBUF_COUNT(sc), 3216 M_DEVBUF, M_WAITOK | M_ZERO); 3217 3218 jpool_size = RE_JBUF_COUNT(sc) * RE_JBUF_SIZE; 3219 3220 error = bus_dmamem_coherent(sc->re_parent_tag, 3221 RE_RXBUF_ALIGN, 0, 3222 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3223 jpool_size, BUS_DMA_WAITOK, &dmem); 3224 if (error) { 3225 device_printf(sc->re_dev, "could not allocate jumbo memory\n"); 3226 return error; 3227 } 3228 ldata->re_jpool_tag = dmem.dmem_tag; 3229 ldata->re_jpool_map = dmem.dmem_map; 3230 ldata->re_jpool = dmem.dmem_addr; 3231 paddr = dmem.dmem_busaddr; 3232 3233 /* ..and split it into 9KB chunks */ 3234 SLIST_INIT(&ldata->re_jbuf_free); 3235 3236 buf = ldata->re_jpool; 3237 for (i = 0; i < RE_JBUF_COUNT(sc); i++) { 3238 jbuf = &ldata->re_jbuf[i]; 3239 3240 jbuf->re_sc = sc; 3241 jbuf->re_inuse = 0; 3242 jbuf->re_slot = i; 3243 jbuf->re_buf = buf; 3244 jbuf->re_paddr = paddr; 3245 3246 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link); 3247 3248 buf += RE_JBUF_SIZE; 3249 paddr += RE_JBUF_SIZE; 3250 } 3251 return 0; 3252 } 3253 3254 static void 3255 re_jpool_free(struct re_softc *sc) 3256 { 3257 struct re_list_data *ldata = &sc->re_ldata; 3258 3259 if (ldata->re_jpool_tag != NULL) { 3260 bus_dmamap_unload(ldata->re_jpool_tag, ldata->re_jpool_map); 3261 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool, 3262 ldata->re_jpool_map); 3263 bus_dma_tag_destroy(ldata->re_jpool_tag); 3264 ldata->re_jpool_tag = NULL; 3265 } 3266 3267 if (ldata->re_jbuf != NULL) { 3268 kfree(ldata->re_jbuf, M_DEVBUF); 3269 ldata->re_jbuf = NULL; 3270 } 3271 } 3272 3273 static struct re_jbuf * 3274 re_jbuf_alloc(struct re_softc *sc) 3275 { 3276 struct re_list_data *ldata = &sc->re_ldata; 3277 struct re_jbuf *jbuf; 3278 3279 lwkt_serialize_enter(&ldata->re_jbuf_serializer); 3280 3281 jbuf = SLIST_FIRST(&ldata->re_jbuf_free); 3282 if (jbuf != NULL) { 3283 SLIST_REMOVE_HEAD(&ldata->re_jbuf_free, re_link); 3284 jbuf->re_inuse = 1; 3285 } 3286 3287 lwkt_serialize_exit(&ldata->re_jbuf_serializer); 3288 3289 return jbuf; 3290 } 3291 3292 static void 3293 re_jbuf_free(void *arg) 3294 { 3295 struct re_jbuf *jbuf = arg; 3296 struct re_softc *sc = jbuf->re_sc; 3297 struct re_list_data *ldata = &sc->re_ldata; 3298 3299 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) { 3300 panic("%s: free wrong jumbo buffer\n", 3301 sc->arpcom.ac_if.if_xname); 3302 } else if (jbuf->re_inuse == 0) { 3303 panic("%s: jumbo buffer already freed\n", 3304 sc->arpcom.ac_if.if_xname); 3305 } 3306 3307 lwkt_serialize_enter(&ldata->re_jbuf_serializer); 3308 atomic_subtract_int(&jbuf->re_inuse, 1); 3309 if (jbuf->re_inuse == 0) 3310 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link); 3311 lwkt_serialize_exit(&ldata->re_jbuf_serializer); 3312 } 3313 3314 static void 3315 re_jbuf_ref(void *arg) 3316 { 3317 struct re_jbuf *jbuf = arg; 3318 struct re_softc *sc = jbuf->re_sc; 3319 struct re_list_data *ldata = &sc->re_ldata; 3320 3321 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) { 3322 panic("%s: ref wrong jumbo buffer\n", 3323 sc->arpcom.ac_if.if_xname); 3324 } else if (jbuf->re_inuse == 0) { 3325 panic("%s: jumbo buffer already freed\n", 3326 sc->arpcom.ac_if.if_xname); 3327 } 3328 atomic_add_int(&jbuf->re_inuse, 1); 3329 } 3330