1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $ 36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.2 2004/07/14 07:40:26 joerg Exp $ 37 */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul@windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 51 * and the RTL8110S. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7.5K, so the max MTU possible with this 111 * driver is 7500 bytes. 112 */ 113 114 #include <sys/param.h> 115 #include <sys/endian.h> 116 #include <sys/systm.h> 117 #include <sys/sockio.h> 118 #include <sys/mbuf.h> 119 #include <sys/malloc.h> 120 #include <sys/module.h> 121 #include <sys/kernel.h> 122 #include <sys/socket.h> 123 124 #include <net/if.h> 125 #include <net/if_arp.h> 126 #include <net/ethernet.h> 127 #include <net/if_dl.h> 128 #include <net/if_media.h> 129 #include <net/if_types.h> 130 #include <net/vlan/if_vlan_var.h> 131 132 #include <net/bpf.h> 133 134 #include <machine/bus_pio.h> 135 #include <machine/bus_memio.h> 136 #include <machine/bus.h> 137 #include <machine/resource.h> 138 #include <sys/bus.h> 139 #include <sys/rman.h> 140 141 #include <dev/netif/mii_layer/mii.h> 142 #include <dev/netif/mii_layer/miivar.h> 143 144 #include <bus/pci/pcireg.h> 145 #include <bus/pci/pcivar.h> 146 147 /* "controller miibus0" required. See GENERIC if you get errors here. */ 148 #include "miibus_if.h" 149 150 #include <dev/netif/re/if_rereg.h> 151 152 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 153 154 /* 155 * Various supported device vendors/types and their names. 156 */ 157 static struct re_type re_devs[] = { 158 { RT_VENDORID, RT_DEVICEID_8139, RE_HWREV_8139CPLUS, 159 "RealTek 8139C+ 10/100BaseTX" }, 160 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8169, 161 "RealTek 8169 Gigabit Ethernet" }, 162 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8169S, 163 "RealTek 8169S Single-chip Gigabit Ethernet" }, 164 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8110S, 165 "RealTek 8110S Single-chip Gigabit Ethernet" }, 166 { 0, 0, 0, NULL } 167 }; 168 169 static struct re_hwrev re_hwrevs[] = { 170 { RE_HWREV_8139CPLUS, RE_8139CPLUS, "C+"}, 171 { RE_HWREV_8169, RE_8169, "8169"}, 172 { RE_HWREV_8169S, RE_8169, "8169S"}, 173 { RE_HWREV_8110S, RE_8169, "8110S"}, 174 { 0, 0, NULL } 175 }; 176 177 static int re_probe(device_t); 178 static int re_attach(device_t); 179 static int re_detach(device_t); 180 181 static int re_encap(struct re_softc *, struct mbuf *, int *); 182 183 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int); 184 static void re_dma_map_desc(void *, bus_dma_segment_t *, int, 185 bus_size_t, int); 186 static int re_allocmem(device_t, struct re_softc *); 187 static int re_newbuf(struct re_softc *, int, struct mbuf *); 188 static int re_rx_list_init(struct re_softc *); 189 static int re_tx_list_init(struct re_softc *); 190 static void re_rxeof(struct re_softc *); 191 static void re_txeof(struct re_softc *); 192 static void re_intr(void *); 193 static void re_tick(void *); 194 static void re_start(struct ifnet *); 195 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 196 static void re_init(void *); 197 static void re_stop(struct re_softc *); 198 static void re_watchdog(struct ifnet *); 199 static int re_suspend(device_t); 200 static int re_resume(device_t); 201 static void re_shutdown(device_t); 202 static int re_ifmedia_upd(struct ifnet *); 203 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 204 205 static void re_eeprom_putbyte(struct re_softc *, int); 206 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *); 207 static void re_read_eeprom(struct re_softc *, caddr_t, int, int, int); 208 static int re_gmii_readreg(device_t, int, int); 209 static int re_gmii_writereg(device_t, int, int, int); 210 211 static int re_miibus_readreg(device_t, int, int); 212 static int re_miibus_writereg(device_t, int, int, int); 213 static void re_miibus_statchg(device_t); 214 215 static void re_setmulti(struct re_softc *); 216 static void re_reset(struct re_softc *); 217 218 static int re_diag(struct re_softc *); 219 220 static device_method_t re_methods[] = { 221 /* Device interface */ 222 DEVMETHOD(device_probe, re_probe), 223 DEVMETHOD(device_attach, re_attach), 224 DEVMETHOD(device_detach, re_detach), 225 DEVMETHOD(device_suspend, re_suspend), 226 DEVMETHOD(device_resume, re_resume), 227 DEVMETHOD(device_shutdown, re_shutdown), 228 229 /* bus interface */ 230 DEVMETHOD(bus_print_child, bus_generic_print_child), 231 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 232 233 /* MII interface */ 234 DEVMETHOD(miibus_readreg, re_miibus_readreg), 235 DEVMETHOD(miibus_writereg, re_miibus_writereg), 236 DEVMETHOD(miibus_statchg, re_miibus_statchg), 237 238 { 0, 0 } 239 }; 240 241 static driver_t re_driver = { 242 "re", 243 re_methods, 244 sizeof(struct re_softc) 245 }; 246 247 static devclass_t re_devclass; 248 249 DECLARE_DUMMY_MODULE(if_re); 250 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0); 251 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0); 252 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 253 254 #define EE_SET(x) \ 255 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x)) 256 257 #define EE_CLR(x) \ 258 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x)) 259 260 /* 261 * Send a read command and address to the EEPROM, check for ACK. 262 */ 263 static void 264 re_eeprom_putbyte(struct re_softc *sc, int addr) 265 { 266 int d, i; 267 268 d = addr | sc->re_eecmd_read; 269 270 /* 271 * Feed in each bit and strobe the clock. 272 */ 273 for (i = 0x400; i != 0; i >>= 1) { 274 if (d & i) 275 EE_SET(RE_EE_DATAIN); 276 else 277 EE_CLR(RE_EE_DATAIN); 278 DELAY(100); 279 EE_SET(RE_EE_CLK); 280 DELAY(150); 281 EE_CLR(RE_EE_CLK); 282 DELAY(100); 283 } 284 } 285 286 /* 287 * Read a word of data stored in the EEPROM at address 'addr.' 288 */ 289 static void 290 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest) 291 { 292 int i; 293 uint16_t word = 0; 294 295 /* Enter EEPROM access mode. */ 296 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL); 297 298 /* 299 * Send address of word we want to read. 300 */ 301 re_eeprom_putbyte(sc, addr); 302 303 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL); 304 305 /* 306 * Start reading bits from EEPROM. 307 */ 308 for (i = 0x8000; i != 0; i >>= 1) { 309 EE_SET(RE_EE_CLK); 310 DELAY(100); 311 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT) 312 word |= i; 313 EE_CLR(RE_EE_CLK); 314 DELAY(100); 315 } 316 317 /* Turn off EEPROM access mode. */ 318 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 319 320 *dest = word; 321 } 322 323 /* 324 * Read a sequence of words from the EEPROM. 325 */ 326 static void 327 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt, int swap) 328 { 329 int i; 330 uint16_t word = 0, *ptr; 331 332 for (i = 0; i < cnt; i++) { 333 re_eeprom_getword(sc, off + i, &word); 334 ptr = (u_int16_t *)(dest + (i * 2)); 335 if (swap) 336 *ptr = be16toh(word); 337 else 338 *ptr = word; 339 } 340 } 341 342 static int 343 re_gmii_readreg(device_t dev, int phy, int reg) 344 { 345 struct re_softc *sc = device_get_softc(dev); 346 u_int32_t rval; 347 int i; 348 349 if (phy != 1) 350 return(0); 351 352 /* Let the rgephy driver read the GMEDIASTAT register */ 353 354 if (reg == RE_GMEDIASTAT) 355 return(CSR_READ_1(sc, RE_GMEDIASTAT)); 356 357 CSR_WRITE_4(sc, RE_PHYAR, reg << 16); 358 DELAY(1000); 359 360 for (i = 0; i < RE_TIMEOUT; i++) { 361 rval = CSR_READ_4(sc, RE_PHYAR); 362 if (rval & RE_PHYAR_BUSY) 363 break; 364 DELAY(100); 365 } 366 367 if (i == RE_TIMEOUT) { 368 device_printf(dev, "PHY read failed\n"); 369 return(0); 370 } 371 372 return(rval & RE_PHYAR_PHYDATA); 373 } 374 375 static int 376 re_gmii_writereg(device_t dev, int phy, int reg, int data) 377 { 378 struct re_softc *sc = device_get_softc(dev); 379 uint32_t rval; 380 int i; 381 382 CSR_WRITE_4(sc, RE_PHYAR, 383 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY); 384 DELAY(1000); 385 386 for (i = 0; i < RE_TIMEOUT; i++) { 387 rval = CSR_READ_4(sc, RE_PHYAR); 388 if ((rval & RE_PHYAR_BUSY) == 0) 389 break; 390 DELAY(100); 391 } 392 393 if (i == RE_TIMEOUT) 394 device_printf(dev, "PHY write failed\n"); 395 396 return(0); 397 } 398 399 static int 400 re_miibus_readreg(device_t dev, int phy, int reg) 401 { 402 struct re_softc *sc = device_get_softc(dev); 403 uint16_t rval = 0; 404 uint16_t re8139_reg = 0; 405 406 if (sc->re_type == RE_8169) { 407 rval = re_gmii_readreg(dev, phy, reg); 408 return(rval); 409 } 410 411 /* Pretend the internal PHY is only at address 0 */ 412 if (phy) 413 return(0); 414 415 switch(reg) { 416 case MII_BMCR: 417 re8139_reg = RE_BMCR; 418 break; 419 case MII_BMSR: 420 re8139_reg = RE_BMSR; 421 break; 422 case MII_ANAR: 423 re8139_reg = RE_ANAR; 424 break; 425 case MII_ANER: 426 re8139_reg = RE_ANER; 427 break; 428 case MII_ANLPAR: 429 re8139_reg = RE_LPAR; 430 break; 431 case MII_PHYIDR1: 432 case MII_PHYIDR2: 433 return(0); 434 /* 435 * Allow the rlphy driver to read the media status 436 * register. If we have a link partner which does not 437 * support NWAY, this is the register which will tell 438 * us the results of parallel detection. 439 */ 440 case RE_MEDIASTAT: 441 return(CSR_READ_1(sc, RE_MEDIASTAT)); 442 default: 443 device_printf(dev, "bad phy register\n"); 444 return(0); 445 } 446 rval = CSR_READ_2(sc, re8139_reg); 447 return(rval); 448 } 449 450 static int 451 re_miibus_writereg(device_t dev, int phy, int reg, int data) 452 { 453 struct re_softc *sc= device_get_softc(dev); 454 u_int16_t re8139_reg = 0; 455 456 if (sc->re_type == RE_8169) 457 return(re_gmii_writereg(dev, phy, reg, data)); 458 459 /* Pretend the internal PHY is only at address 0 */ 460 if (phy) 461 return(0); 462 463 switch(reg) { 464 case MII_BMCR: 465 re8139_reg = RE_BMCR; 466 break; 467 case MII_BMSR: 468 re8139_reg = RE_BMSR; 469 break; 470 case MII_ANAR: 471 re8139_reg = RE_ANAR; 472 break; 473 case MII_ANER: 474 re8139_reg = RE_ANER; 475 break; 476 case MII_ANLPAR: 477 re8139_reg = RE_LPAR; 478 break; 479 case MII_PHYIDR1: 480 case MII_PHYIDR2: 481 return(0); 482 default: 483 device_printf(dev, "bad phy register\n"); 484 return(0); 485 } 486 CSR_WRITE_2(sc, re8139_reg, data); 487 return(0); 488 } 489 490 static void 491 re_miibus_statchg(device_t dev) 492 { 493 } 494 495 /* 496 * Program the 64-bit multicast hash filter. 497 */ 498 static void 499 re_setmulti(struct re_softc *sc) 500 { 501 struct ifnet *ifp = &sc->arpcom.ac_if; 502 int h = 0; 503 uint32_t hashes[2] = { 0, 0 }; 504 struct ifmultiaddr *ifma; 505 uint32_t rxfilt; 506 int mcnt = 0; 507 508 rxfilt = CSR_READ_4(sc, RE_RXCFG); 509 510 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 511 rxfilt |= RE_RXCFG_RX_MULTI; 512 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 513 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF); 514 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF); 515 return; 516 } 517 518 /* first, zot all the existing hash bits */ 519 CSR_WRITE_4(sc, RE_MAR0, 0); 520 CSR_WRITE_4(sc, RE_MAR4, 0); 521 522 /* now program new ones */ 523 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 524 if (ifma->ifma_addr->sa_family != AF_LINK) 525 continue; 526 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 527 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 528 if (h < 32) 529 hashes[0] |= (1 << h); 530 else 531 hashes[1] |= (1 << (h - 32)); 532 mcnt++; 533 } 534 535 if (mcnt) 536 rxfilt |= RE_RXCFG_RX_MULTI; 537 else 538 rxfilt &= ~RE_RXCFG_RX_MULTI; 539 540 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 541 CSR_WRITE_4(sc, RE_MAR0, hashes[0]); 542 CSR_WRITE_4(sc, RE_MAR4, hashes[1]); 543 } 544 545 static void 546 re_reset(struct re_softc *sc) 547 { 548 int i; 549 550 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET); 551 552 for (i = 0; i < RE_TIMEOUT; i++) { 553 DELAY(10); 554 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0) 555 break; 556 } 557 if (i == RE_TIMEOUT) 558 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 559 560 CSR_WRITE_1(sc, 0x82, 1); 561 } 562 563 /* 564 * The following routine is designed to test for a defect on some 565 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 566 * lines connected to the bus, however for a 32-bit only card, they 567 * should be pulled high. The result of this defect is that the 568 * NIC will not work right if you plug it into a 64-bit slot: DMA 569 * operations will be done with 64-bit transfers, which will fail 570 * because the 64-bit data lines aren't connected. 571 * 572 * There's no way to work around this (short of talking a soldering 573 * iron to the board), however we can detect it. The method we use 574 * here is to put the NIC into digital loopback mode, set the receiver 575 * to promiscuous mode, and then try to send a frame. We then compare 576 * the frame data we sent to what was received. If the data matches, 577 * then the NIC is working correctly, otherwise we know the user has 578 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 579 * slot. In the latter case, there's no way the NIC can work correctly, 580 * so we print out a message on the console and abort the device attach. 581 */ 582 583 static int 584 re_diag(struct re_softc *sc) 585 { 586 struct ifnet *ifp = &sc->arpcom.ac_if; 587 struct mbuf *m0; 588 struct ether_header *eh; 589 struct re_desc *cur_rx; 590 uint16_t status; 591 uint32_t rxstat; 592 int total_len, i, error = 0; 593 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 594 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 595 596 /* Allocate a single mbuf */ 597 598 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 599 if (m0 == NULL) 600 return(ENOBUFS); 601 602 /* 603 * Initialize the NIC in test mode. This sets the chip up 604 * so that it can send and receive frames, but performs the 605 * following special functions: 606 * - Puts receiver in promiscuous mode 607 * - Enables digital loopback mode 608 * - Leaves interrupts turned off 609 */ 610 611 ifp->if_flags |= IFF_PROMISC; 612 sc->re_testmode = 1; 613 re_init(sc); 614 re_stop(sc); 615 DELAY(100000); 616 re_init(sc); 617 618 /* Put some data in the mbuf */ 619 620 eh = mtod(m0, struct ether_header *); 621 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN); 622 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN); 623 eh->ether_type = htons(ETHERTYPE_IP); 624 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 625 626 /* 627 * Queue the packet, start transmission. 628 * Note: IF_HANDOFF() ultimately calls re_start() for us. 629 */ 630 631 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 632 IF_HANDOFF(&ifp->if_snd, m0, ifp); 633 m0 = NULL; 634 635 /* Wait for it to propagate through the chip */ 636 637 DELAY(100000); 638 for (i = 0; i < RE_TIMEOUT; i++) { 639 status = CSR_READ_2(sc, RE_ISR); 640 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) == 641 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) 642 break; 643 DELAY(10); 644 } 645 646 if (i == RE_TIMEOUT) { 647 if_printf(ifp, "diagnostic failed to receive packet " 648 "in loopback mode\n"); 649 error = EIO; 650 goto done; 651 } 652 653 /* 654 * The packet should have been dumped into the first 655 * entry in the RX DMA ring. Grab it from there. 656 */ 657 658 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 659 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 660 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0], 661 BUS_DMASYNC_POSTWRITE); 662 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]); 663 664 m0 = sc->re_ldata.re_rx_mbuf[0]; 665 sc->re_ldata.re_rx_mbuf[0] = NULL; 666 eh = mtod(m0, struct ether_header *); 667 668 cur_rx = &sc->re_ldata.re_rx_list[0]; 669 total_len = RE_RXBYTES(cur_rx); 670 rxstat = le32toh(cur_rx->re_cmdstat); 671 672 if (total_len != ETHER_MIN_LEN) { 673 if_printf(ifp, "diagnostic failed, received short packet\n"); 674 error = EIO; 675 goto done; 676 } 677 678 /* Test that the received packet data matches what we sent. */ 679 680 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) || 681 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) || 682 be16toh(eh->ether_type) != ETHERTYPE_IP) { 683 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 684 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n", 685 dst, ":", src, ":", ETHERTYPE_IP); 686 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n", 687 eh->ether_dhost, ":", eh->ether_shost, ":", 688 ntohs(eh->ether_type)); 689 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 690 "into a 64-bit PCI slot.\n"); 691 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 692 "for proper operation.\n"); 693 if_printf(ifp, "Read the re(4) man page for more details.\n"); 694 error = EIO; 695 } 696 697 done: 698 /* Turn interface off, release resources */ 699 700 sc->re_testmode = 0; 701 ifp->if_flags &= ~IFF_PROMISC; 702 re_stop(sc); 703 if (m0 != NULL) 704 m_freem(m0); 705 706 return (error); 707 } 708 709 /* 710 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 711 * IDs against our list and return a device name if we find a match. 712 */ 713 static int 714 re_probe(device_t dev) 715 { 716 struct re_type *t; 717 struct re_softc *sc; 718 int rid; 719 uint32_t hwrev; 720 uint16_t vendor, product; 721 722 t = re_devs; 723 724 vendor = pci_get_vendor(dev); 725 product = pci_get_device(dev); 726 727 for (t = re_devs; t->re_name != NULL; t++) { 728 if (product == t->re_did && vendor == t->re_vid) 729 break; 730 } 731 732 /* 733 * Check if we found a RealTek device. 734 */ 735 if (t->re_name == NULL) 736 return(ENXIO); 737 738 /* 739 * Temporarily map the I/O space so we can read the chip ID register. 740 */ 741 sc = malloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO); 742 rid = RE_PCI_LOMEM; 743 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 744 RF_ACTIVE); 745 if (sc->re_res == NULL) { 746 device_printf(dev, "couldn't map ports/memory\n"); 747 free(sc, M_TEMP); 748 return(ENXIO); 749 } 750 751 sc->re_btag = rman_get_bustag(sc->re_res); 752 sc->re_bhandle = rman_get_bushandle(sc->re_res); 753 754 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV; 755 bus_release_resource(dev, SYS_RES_MEMORY, RE_PCI_LOMEM, sc->re_res); 756 free(sc, M_TEMP); 757 758 /* 759 * and continue matching for the specific chip... 760 */ 761 for (; t->re_name != NULL; t++) { 762 if (product == t->re_did && vendor == t->re_vid && 763 t->re_basetype == hwrev) { 764 device_set_desc(dev, t->re_name); 765 return(0); 766 } 767 } 768 return(ENXIO); 769 } 770 771 /* 772 * This routine takes the segment list provided as the result of 773 * a bus_dma_map_load() operation and assigns the addresses/lengths 774 * to RealTek DMA descriptors. This can be called either by the RX 775 * code or the TX code. In the RX case, we'll probably wind up mapping 776 * at most one segment. For the TX case, there could be any number of 777 * segments since TX packets may span multiple mbufs. In either case, 778 * if the number of segments is larger than the re_maxsegs limit 779 * specified by the caller, we abort the mapping operation. Sadly, 780 * whoever designed the buffer mapping API did not provide a way to 781 * return an error from here, so we have to fake it a bit. 782 */ 783 784 static void 785 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, 786 bus_size_t mapsize, int error) 787 { 788 struct re_dmaload_arg *ctx; 789 struct re_desc *d = NULL; 790 int i = 0, idx; 791 uint32_t cmdstat; 792 793 if (error) 794 return; 795 796 ctx = arg; 797 798 /* Signal error to caller if there's too many segments */ 799 if (nseg > ctx->re_maxsegs) { 800 ctx->re_maxsegs = 0; 801 return; 802 } 803 804 /* 805 * Map the segment array into descriptors. Note that we set the 806 * start-of-frame and end-of-frame markers for either TX or RX, but 807 * they really only have meaning in the TX case. (In the RX case, 808 * it's the chip that tells us where packets begin and end.) 809 * We also keep track of the end of the ring and set the 810 * end-of-ring bits as needed, and we set the ownership bits 811 * in all except the very first descriptor. (The caller will 812 * set this descriptor later when it start transmission or 813 * reception.) 814 */ 815 idx = ctx->re_idx; 816 for (;;) { 817 d = &ctx->re_ring[idx]; 818 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) { 819 ctx->re_maxsegs = 0; 820 return; 821 } 822 cmdstat = segs[i].ds_len; 823 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr)); 824 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr)); 825 if (i == 0) 826 cmdstat |= RE_TDESC_CMD_SOF; 827 else 828 cmdstat |= RE_TDESC_CMD_OWN; 829 if (idx == (RE_RX_DESC_CNT - 1)) 830 cmdstat |= RE_TDESC_CMD_EOR; 831 d->re_cmdstat = htole32(cmdstat | ctx->re_flags); 832 i++; 833 if (i == nseg) 834 break; 835 RE_DESC_INC(idx); 836 } 837 838 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF); 839 ctx->re_maxsegs = nseg; 840 ctx->re_idx = idx; 841 } 842 843 /* 844 * Map a single buffer address. 845 */ 846 847 static void 848 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 849 { 850 uint32_t *addr; 851 852 if (error) 853 return; 854 855 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 856 addr = arg; 857 *addr = segs->ds_addr; 858 } 859 860 static int 861 re_allocmem(device_t dev, struct re_softc *sc) 862 { 863 int error, i, nseg; 864 865 /* 866 * Allocate map for RX mbufs. 867 */ 868 nseg = 32; 869 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0, 870 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 871 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 872 &sc->re_ldata.re_mtag); 873 if (error) { 874 device_printf(dev, "could not allocate dma tag\n"); 875 return(error); 876 } 877 878 /* 879 * Allocate map for TX descriptor list. 880 */ 881 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN, 882 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 883 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 884 &sc->re_ldata.re_tx_list_tag); 885 if (error) { 886 device_printf(dev, "could not allocate dma tag\n"); 887 return(error); 888 } 889 890 /* Allocate DMA'able memory for the TX ring */ 891 892 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag, 893 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO, 894 &sc->re_ldata.re_tx_list_map); 895 if (error) { 896 device_printf(dev, "could not allocate TX ring\n"); 897 return(error); 898 } 899 900 /* Load the map for the TX ring. */ 901 902 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag, 903 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 904 RE_TX_LIST_SZ, re_dma_map_addr, 905 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT); 906 if (error) { 907 device_printf(dev, "could not get addres of TX ring\n"); 908 return(error); 909 } 910 911 /* Create DMA maps for TX buffers */ 912 913 for (i = 0; i < RE_TX_DESC_CNT; i++) { 914 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, 915 &sc->re_ldata.re_tx_dmamap[i]); 916 if (error) { 917 device_printf(dev, "can't create DMA map for TX\n"); 918 return(error); 919 } 920 } 921 922 /* 923 * Allocate map for RX descriptor list. 924 */ 925 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN, 926 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 927 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 928 &sc->re_ldata.re_rx_list_tag); 929 if (error) { 930 device_printf(dev, "could not allocate dma tag\n"); 931 return(error); 932 } 933 934 /* Allocate DMA'able memory for the RX ring */ 935 936 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag, 937 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO, 938 &sc->re_ldata.re_rx_list_map); 939 if (error) { 940 device_printf(dev, "could not allocate RX ring\n"); 941 return(error); 942 } 943 944 /* Load the map for the RX ring. */ 945 946 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag, 947 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 948 RE_TX_LIST_SZ, re_dma_map_addr, 949 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT); 950 if (error) { 951 device_printf(dev, "could not get address of RX ring\n"); 952 return(error); 953 } 954 955 /* Create DMA maps for RX buffers */ 956 957 for (i = 0; i < RE_RX_DESC_CNT; i++) { 958 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, 959 &sc->re_ldata.re_rx_dmamap[i]); 960 if (error) { 961 device_printf(dev, "can't create DMA map for RX\n"); 962 return(ENOMEM); 963 } 964 } 965 966 return(0); 967 } 968 969 /* 970 * Attach the interface. Allocate softc structures, do ifmedia 971 * setup and ethernet/BPF attach. 972 */ 973 static int 974 re_attach(device_t dev) 975 { 976 struct re_softc *sc = device_get_softc(dev); 977 struct ifnet *ifp; 978 struct re_hwrev *hw_rev; 979 uint8_t eaddr[ETHER_ADDR_LEN]; 980 int hwrev; 981 u_int16_t re_did = 0; 982 int error = 0, rid, i; 983 984 callout_init(&sc->re_timer); 985 986 #ifndef BURN_BRIDGES 987 /* 988 * Handle power management nonsense. 989 */ 990 991 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 992 uint32_t membase, irq; 993 994 /* Save important PCI config data. */ 995 membase = pci_read_config(dev, RE_PCI_LOMEM, 4); 996 irq = pci_read_config(dev, PCIR_INTLINE, 4); 997 998 /* Reset the power state. */ 999 device_printf(dev, "chip is is in D%d power mode " 1000 "-- setting to D0\n", pci_get_powerstate(dev)); 1001 1002 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1003 1004 /* Restore PCI config data. */ 1005 pci_write_config(dev, RE_PCI_LOMEM, membase, 4); 1006 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1007 } 1008 #endif 1009 /* 1010 * Map control/status registers. 1011 */ 1012 pci_enable_busmaster(dev); 1013 1014 rid = RE_PCI_LOMEM; 1015 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1016 RF_ACTIVE); 1017 1018 if (sc->re_res == NULL) { 1019 device_printf(dev, "couldn't map ports/memory\n"); 1020 error = ENXIO; 1021 goto fail; 1022 } 1023 1024 sc->re_btag = rman_get_bustag(sc->re_res); 1025 sc->re_bhandle = rman_get_bushandle(sc->re_res); 1026 1027 /* Allocate interrupt */ 1028 rid = 0; 1029 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1030 RF_SHAREABLE | RF_ACTIVE); 1031 1032 if (sc->re_irq == NULL) { 1033 device_printf(dev, "couldn't map interrupt\n"); 1034 error = ENXIO; 1035 goto fail; 1036 } 1037 1038 /* Reset the adapter. */ 1039 re_reset(sc); 1040 1041 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV; 1042 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) { 1043 if (hw_rev->re_rev == hwrev) { 1044 sc->re_type = hw_rev->re_type; 1045 break; 1046 } 1047 } 1048 1049 if (sc->re_type == RE_8169) { 1050 /* Set RX length mask */ 1051 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 1052 1053 /* Force station address autoload from the EEPROM */ 1054 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_AUTOLOAD); 1055 for (i = 0; i < RE_TIMEOUT; i++) { 1056 if ((CSR_READ_1(sc, RE_EECMD) & RE_EEMODE_AUTOLOAD) == 0) 1057 break; 1058 DELAY(100); 1059 } 1060 if (i == RE_TIMEOUT) 1061 device_printf(dev, "eeprom autoload timed out\n"); 1062 1063 for (i = 0; i < ETHER_ADDR_LEN; i++) 1064 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i); 1065 } else { 1066 uint16_t as[3]; 1067 1068 /* Set RX length mask */ 1069 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 1070 1071 sc->re_eecmd_read = RE_EECMD_READ_6BIT; 1072 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1073 if (re_did != 0x8129) 1074 sc->re_eecmd_read = RE_EECMD_READ_8BIT; 1075 1076 /* 1077 * Get station address from the EEPROM. 1078 */ 1079 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3, 0); 1080 for (i = 0; i < 3; i++) { 1081 eaddr[(i * 2) + 0] = as[i] & 0xff; 1082 eaddr[(i * 2) + 1] = as[i] >> 8; 1083 } 1084 } 1085 1086 /* 1087 * Allocate the parent bus DMA tag appropriate for PCI. 1088 */ 1089 #define RE_NSEG_NEW 32 1090 error = bus_dma_tag_create(NULL, /* parent */ 1091 1, 0, /* alignment, boundary */ 1092 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1093 BUS_SPACE_MAXADDR, /* highaddr */ 1094 NULL, NULL, /* filter, filterarg */ 1095 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */ 1096 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1097 BUS_DMA_ALLOCNOW, /* flags */ 1098 &sc->re_parent_tag); 1099 if (error) 1100 goto fail; 1101 1102 error = re_allocmem(dev, sc); 1103 1104 if (error) 1105 goto fail; 1106 1107 /* Do MII setup */ 1108 if (mii_phy_probe(dev, &sc->re_miibus, 1109 re_ifmedia_upd, re_ifmedia_sts)) { 1110 device_printf(dev, "MII without any phy!\n"); 1111 error = ENXIO; 1112 goto fail; 1113 } 1114 1115 ifp = &sc->arpcom.ac_if; 1116 ifp->if_softc = sc; 1117 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1118 ifp->if_mtu = ETHERMTU; 1119 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1120 ifp->if_ioctl = re_ioctl; 1121 ifp->if_output = ether_output; 1122 ifp->if_capabilities = IFCAP_VLAN_MTU; 1123 ifp->if_start = re_start; 1124 ifp->if_hwassist = RE_CSUM_FEATURES; 1125 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1126 #ifdef DEVICE_POLLING 1127 ifp->if_capabilities |= IFCAP_POLLING; 1128 #endif 1129 ifp->if_watchdog = re_watchdog; 1130 ifp->if_init = re_init; 1131 if (sc->re_type == RE_8169) 1132 ifp->if_baudrate = 1000000000; 1133 else 1134 ifp->if_baudrate = 100000000; 1135 ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN; 1136 ifp->if_capenable = ifp->if_capabilities; 1137 1138 /* 1139 * Call MI attach routine. 1140 */ 1141 ether_ifattach(ifp, eaddr); 1142 1143 /* Perform hardware diagnostic. */ 1144 error = re_diag(sc); 1145 1146 if (error) { 1147 device_printf(dev, "hardware diagnostic failure\n"); 1148 ether_ifdetach(ifp); 1149 goto fail; 1150 } 1151 1152 /* Hook interrupt last to avoid having to lock softc */ 1153 error = bus_setup_intr(dev, sc->re_irq, INTR_TYPE_NET, re_intr, sc, 1154 &sc->re_intrhand); 1155 1156 if (error) { 1157 device_printf(dev, "couldn't set up irq\n"); 1158 ether_ifdetach(ifp); 1159 goto fail; 1160 } 1161 1162 fail: 1163 if (error) 1164 re_detach(dev); 1165 1166 return (error); 1167 } 1168 1169 /* 1170 * Shutdown hardware and free up resources. This can be called any 1171 * time after the mutex has been initialized. It is called in both 1172 * the error case in attach and the normal detach case so it needs 1173 * to be careful about only freeing resources that have actually been 1174 * allocated. 1175 */ 1176 static int 1177 re_detach(device_t dev) 1178 { 1179 struct re_softc *sc = device_get_softc(dev); 1180 struct ifnet *ifp = &sc->arpcom.ac_if; 1181 int i, s; 1182 1183 s = splimp(); 1184 1185 /* These should only be active if attach succeeded */ 1186 if (device_is_attached(dev)) { 1187 re_stop(sc); 1188 ether_ifdetach(ifp); 1189 } 1190 if (sc->re_miibus) 1191 device_delete_child(dev, sc->re_miibus); 1192 bus_generic_detach(dev); 1193 1194 if (sc->re_intrhand) 1195 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand); 1196 if (sc->re_irq) 1197 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq); 1198 if (sc->re_res) 1199 bus_release_resource(dev, SYS_RES_MEMORY, RE_PCI_LOMEM, 1200 sc->re_res); 1201 1202 /* Unload and free the RX DMA ring memory and map */ 1203 1204 if (sc->re_ldata.re_rx_list_tag) { 1205 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag, 1206 sc->re_ldata.re_rx_list_map); 1207 bus_dmamem_free(sc->re_ldata.re_rx_list_tag, 1208 sc->re_ldata.re_rx_list, 1209 sc->re_ldata.re_rx_list_map); 1210 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1211 } 1212 1213 /* Unload and free the TX DMA ring memory and map */ 1214 1215 if (sc->re_ldata.re_tx_list_tag) { 1216 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag, 1217 sc->re_ldata.re_tx_list_map); 1218 bus_dmamem_free(sc->re_ldata.re_tx_list_tag, 1219 sc->re_ldata.re_tx_list, 1220 sc->re_ldata.re_tx_list_map); 1221 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1222 } 1223 1224 /* Destroy all the RX and TX buffer maps */ 1225 1226 if (sc->re_ldata.re_mtag) { 1227 for (i = 0; i < RE_TX_DESC_CNT; i++) 1228 bus_dmamap_destroy(sc->re_ldata.re_mtag, 1229 sc->re_ldata.re_tx_dmamap[i]); 1230 for (i = 0; i < RE_RX_DESC_CNT; i++) 1231 bus_dmamap_destroy(sc->re_ldata.re_mtag, 1232 sc->re_ldata.re_rx_dmamap[i]); 1233 bus_dma_tag_destroy(sc->re_ldata.re_mtag); 1234 } 1235 1236 /* Unload and free the stats buffer and map */ 1237 1238 if (sc->re_ldata.re_stag) { 1239 bus_dmamap_unload(sc->re_ldata.re_stag, 1240 sc->re_ldata.re_rx_list_map); 1241 bus_dmamem_free(sc->re_ldata.re_stag, 1242 sc->re_ldata.re_stats, 1243 sc->re_ldata.re_smap); 1244 bus_dma_tag_destroy(sc->re_ldata.re_stag); 1245 } 1246 1247 if (sc->re_parent_tag) 1248 bus_dma_tag_destroy(sc->re_parent_tag); 1249 1250 splx(s); 1251 1252 return(0); 1253 } 1254 1255 static int 1256 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m) 1257 { 1258 struct re_dmaload_arg arg; 1259 struct mbuf *n = NULL; 1260 int error; 1261 1262 if (m == NULL) { 1263 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1264 if (n == NULL) 1265 return(ENOBUFS); 1266 m = n; 1267 } else 1268 m->m_data = m->m_ext.ext_buf; 1269 1270 /* 1271 * Initialize mbuf length fields and fixup 1272 * alignment so that the frame payload is 1273 * longword aligned. 1274 */ 1275 m->m_len = m->m_pkthdr.len = MCLBYTES; 1276 m_adj(m, ETHER_ALIGN); 1277 1278 arg.sc = sc; 1279 arg.re_idx = idx; 1280 arg.re_maxsegs = 1; 1281 arg.re_flags = 0; 1282 arg.re_ring = sc->re_ldata.re_rx_list; 1283 1284 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, 1285 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc, 1286 &arg, BUS_DMA_NOWAIT); 1287 if (error || arg.re_maxsegs != 1) { 1288 if (n != NULL) 1289 m_freem(n); 1290 return (ENOMEM); 1291 } 1292 1293 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN); 1294 sc->re_ldata.re_rx_mbuf[idx] = m; 1295 1296 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx], 1297 BUS_DMASYNC_PREREAD); 1298 1299 return(0); 1300 } 1301 1302 static int 1303 re_tx_list_init(struct re_softc *sc) 1304 { 1305 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ); 1306 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *)); 1307 1308 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1309 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE); 1310 sc->re_ldata.re_tx_prodidx = 0; 1311 sc->re_ldata.re_tx_considx = 0; 1312 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT; 1313 1314 return(0); 1315 } 1316 1317 static int 1318 re_rx_list_init(struct re_softc *sc) 1319 { 1320 int i, error; 1321 1322 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ); 1323 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *)); 1324 1325 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1326 error = re_newbuf(sc, i, NULL); 1327 if (error) 1328 return(error); 1329 } 1330 1331 /* Flush the RX descriptors */ 1332 1333 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1334 sc->re_ldata.re_rx_list_map, 1335 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1336 1337 sc->re_ldata.re_rx_prodidx = 0; 1338 sc->re_head = sc->re_tail = NULL; 1339 1340 return(0); 1341 } 1342 1343 /* 1344 * RX handler for C+ and 8169. For the gigE chips, we support 1345 * the reception of jumbo frames that have been fragmented 1346 * across multiple 2K mbuf cluster buffers. 1347 */ 1348 static void 1349 re_rxeof(struct re_softc *sc) 1350 { 1351 struct ifnet *ifp = &sc->arpcom.ac_if; 1352 struct mbuf *m; 1353 struct re_desc *cur_rx; 1354 struct ether_header *eh; 1355 uint32_t rxstat, rxvlan; 1356 int i, total_len; 1357 1358 /* Invalidate the descriptor memory */ 1359 1360 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1361 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 1362 1363 for (i = sc->re_ldata.re_rx_prodidx; 1364 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) { 1365 cur_rx = &sc->re_ldata.re_rx_list[i]; 1366 m = sc->re_ldata.re_rx_mbuf[i]; 1367 total_len = RE_RXBYTES(cur_rx); 1368 rxstat = le32toh(cur_rx->re_cmdstat); 1369 rxvlan = le32toh(cur_rx->re_vlanctl); 1370 1371 /* Invalidate the RX mbuf and unload its map */ 1372 1373 bus_dmamap_sync(sc->re_ldata.re_mtag, 1374 sc->re_ldata.re_rx_dmamap[i], 1375 BUS_DMASYNC_POSTWRITE); 1376 bus_dmamap_unload(sc->re_ldata.re_mtag, 1377 sc->re_ldata.re_rx_dmamap[i]); 1378 1379 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1380 m->m_len = MCLBYTES - ETHER_ALIGN; 1381 if (sc->re_head == NULL) { 1382 sc->re_head = sc->re_tail = m; 1383 } else { 1384 m->m_flags &= ~M_PKTHDR; 1385 sc->re_tail->m_next = m; 1386 sc->re_tail = m; 1387 } 1388 re_newbuf(sc, i, NULL); 1389 continue; 1390 } 1391 1392 /* 1393 * NOTE: for the 8139C+, the frame length field 1394 * is always 12 bits in size, but for the gigE chips, 1395 * it is 13 bits (since the max RX frame length is 16K). 1396 * Unfortunately, all 32 bits in the status word 1397 * were already used, so to make room for the extra 1398 * length bit, RealTek took out the 'frame alignment 1399 * error' bit and shifted the other status bits 1400 * over one slot. The OWN, EOR, FS and LS bits are 1401 * still in the same places. We have already extracted 1402 * the frame length and checked the OWN bit, so rather 1403 * than using an alternate bit mapping, we shift the 1404 * status bits one space to the right so we can evaluate 1405 * them using the 8169 status as though it was in the 1406 * same format as that of the 8139C+. 1407 */ 1408 if (sc->re_type == RE_8169) 1409 rxstat >>= 1; 1410 1411 if (rxstat & RE_RDESC_STAT_RXERRSUM) { 1412 ifp->if_ierrors++; 1413 /* 1414 * If this is part of a multi-fragment packet, 1415 * discard all the pieces. 1416 */ 1417 if (sc->re_head != NULL) { 1418 m_freem(sc->re_head); 1419 sc->re_head = sc->re_tail = NULL; 1420 } 1421 re_newbuf(sc, i, m); 1422 continue; 1423 } 1424 1425 /* 1426 * If allocating a replacement mbuf fails, 1427 * reload the current one. 1428 */ 1429 1430 if (re_newbuf(sc, i, NULL)) { 1431 ifp->if_ierrors++; 1432 if (sc->re_head != NULL) { 1433 m_freem(sc->re_head); 1434 sc->re_head = sc->re_tail = NULL; 1435 } 1436 re_newbuf(sc, i, m); 1437 continue; 1438 } 1439 1440 RE_DESC_INC(i); 1441 1442 if (sc->re_head != NULL) { 1443 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN); 1444 /* 1445 * Special case: if there's 4 bytes or less 1446 * in this buffer, the mbuf can be discarded: 1447 * the last 4 bytes is the CRC, which we don't 1448 * care about anyway. 1449 */ 1450 if (m->m_len <= ETHER_CRC_LEN) { 1451 sc->re_tail->m_len -= 1452 (ETHER_CRC_LEN - m->m_len); 1453 m_freem(m); 1454 } else { 1455 m->m_len -= ETHER_CRC_LEN; 1456 m->m_flags &= ~M_PKTHDR; 1457 sc->re_tail->m_next = m; 1458 } 1459 m = sc->re_head; 1460 sc->re_head = sc->re_tail = NULL; 1461 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1462 } else 1463 m->m_pkthdr.len = m->m_len = 1464 (total_len - ETHER_CRC_LEN); 1465 1466 ifp->if_ipackets++; 1467 eh = mtod(m, struct ether_header *); 1468 m->m_pkthdr.rcvif = ifp; 1469 m_adj(m, sizeof(struct ether_header)); 1470 1471 /* Do RX checksumming if enabled */ 1472 1473 if (ifp->if_capenable & IFCAP_RXCSUM) { 1474 1475 /* Check IP header checksum */ 1476 if (rxstat & RE_RDESC_STAT_PROTOID) 1477 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1478 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0) 1479 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1480 1481 /* Check TCP/UDP checksum */ 1482 if ((RE_TCPPKT(rxstat) && 1483 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) || 1484 (RE_UDPPKT(rxstat) && 1485 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) { 1486 m->m_pkthdr.csum_flags |= 1487 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1488 m->m_pkthdr.csum_data = 0xffff; 1489 } 1490 } 1491 1492 if (rxvlan & RE_RDESC_VLANCTL_TAG) 1493 VLAN_INPUT_TAG(eh, m, 1494 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA))); 1495 else 1496 ether_input(ifp, eh, m); 1497 } 1498 1499 /* Flush the RX DMA ring */ 1500 1501 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1502 sc->re_ldata.re_rx_list_map, 1503 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1504 1505 sc->re_ldata.re_rx_prodidx = i; 1506 } 1507 1508 static void 1509 re_txeof(struct re_softc *sc) 1510 { 1511 struct ifnet *ifp = &sc->arpcom.ac_if; 1512 uint32_t txstat; 1513 int idx; 1514 1515 /* Invalidate the TX descriptor list */ 1516 1517 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1518 sc->re_ldata.re_tx_list_map, 1519 BUS_DMASYNC_POSTREAD); 1520 1521 for (idx = sc->re_ldata.re_tx_considx; 1522 idx != sc->re_ldata.re_tx_prodidx; RE_DESC_INC(idx)) { 1523 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat); 1524 if (txstat & RE_TDESC_CMD_OWN) 1525 break; 1526 1527 /* 1528 * We only stash mbufs in the last descriptor 1529 * in a fragment chain, which also happens to 1530 * be the only place where the TX status bits 1531 * are valid. 1532 */ 1533 if (txstat & RE_TDESC_CMD_EOF) { 1534 m_freem(sc->re_ldata.re_tx_mbuf[idx]); 1535 sc->re_ldata.re_tx_mbuf[idx] = NULL; 1536 bus_dmamap_unload(sc->re_ldata.re_mtag, 1537 sc->re_ldata.re_tx_dmamap[idx]); 1538 if (txstat & (RE_TDESC_STAT_EXCESSCOL| 1539 RE_TDESC_STAT_COLCNT)) 1540 ifp->if_collisions++; 1541 if (txstat & RE_TDESC_STAT_TXERRSUM) 1542 ifp->if_oerrors++; 1543 else 1544 ifp->if_opackets++; 1545 } 1546 sc->re_ldata.re_tx_free++; 1547 } 1548 1549 /* No changes made to the TX ring, so no flush needed */ 1550 if (idx != sc->re_ldata.re_tx_considx) { 1551 sc->re_ldata.re_tx_considx = idx; 1552 ifp->if_flags &= ~IFF_OACTIVE; 1553 ifp->if_timer = 0; 1554 } 1555 1556 /* 1557 * If not all descriptors have been released reaped yet, 1558 * reload the timer so that we will eventually get another 1559 * interrupt that will cause us to re-enter this routine. 1560 * This is done in case the transmitter has gone idle. 1561 */ 1562 if (sc->re_ldata.re_tx_free != RE_TX_DESC_CNT) 1563 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 1564 } 1565 1566 static void 1567 re_tick(void *xsc) 1568 { 1569 struct re_softc *sc = xsc; 1570 struct mii_data *mii; 1571 int s; 1572 1573 s = splimp(); 1574 1575 mii = device_get_softc(sc->re_miibus); 1576 mii_tick(mii); 1577 1578 callout_reset(&sc->re_timer, hz, re_tick, sc); 1579 splx(s); 1580 } 1581 1582 #ifdef DEVICE_POLLING 1583 static void 1584 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1585 { 1586 struct re_softc *sc = ifp->if_softc; 1587 1588 if ((ifp->if_capenable & IFCAP_POLLING) == 0) { 1589 ether_poll_deregister(ifp); 1590 cmd = POLL_DEREGISTER; 1591 } 1592 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1593 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS); 1594 return; 1595 } 1596 1597 sc->rxcycles = count; 1598 re_rxeof(sc); 1599 re_txeof(sc); 1600 1601 if (ifp->if_snd.ifq_head != NULL) 1602 (*ifp->if_start)(ifp); 1603 1604 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1605 uint16_t status; 1606 1607 status = CSR_READ_2(sc, RE_ISR); 1608 if (status == 0xffff) 1609 return; 1610 if (status) 1611 CSR_WRITE_2(sc, RE_ISR, status); 1612 1613 /* 1614 * XXX check behaviour on receiver stalls. 1615 */ 1616 1617 if (status & RE_ISR_SYSTEM_ERR) { 1618 re_reset(sc); 1619 re_init(sc); 1620 } 1621 } 1622 } 1623 #endif /* DEVICE_POLLING */ 1624 1625 static void 1626 re_intr(void *arg) 1627 { 1628 struct re_softc *sc = arg; 1629 struct ifnet *ifp = &sc->arpcom.ac_if; 1630 uint16_t status; 1631 int s; 1632 1633 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0) 1634 return; 1635 1636 #ifdef DEVICE_POLLING 1637 if (ifp->if_flags & IFF_POLLING) 1638 return; 1639 if ((ifp->if_capenable & IFCAP_POLLING) && 1640 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */ 1641 CSR_WRITE_2(sc, RE_IMR, 0x0000); 1642 re_poll(ifp, 0, 1); 1643 return; 1644 } 1645 #endif /* DEVICE_POLLING */ 1646 1647 s = splimp(); 1648 1649 for (;;) { 1650 status = CSR_READ_2(sc, RE_ISR); 1651 /* If the card has gone away the read returns 0xffff. */ 1652 if (status == 0xffff) 1653 break; 1654 if (status) 1655 CSR_WRITE_2(sc, RE_ISR, status); 1656 1657 if ((status & RE_INTRS_CPLUS) == 0) 1658 break; 1659 1660 if (status & RE_ISR_RX_OK) 1661 re_rxeof(sc); 1662 1663 if (status & RE_ISR_RX_ERR) 1664 re_rxeof(sc); 1665 1666 if ((status & RE_ISR_TIMEOUT_EXPIRED) || 1667 (status & RE_ISR_TX_ERR) || 1668 (status & RE_ISR_TX_DESC_UNAVAIL)) 1669 re_txeof(sc); 1670 1671 if (status & RE_ISR_SYSTEM_ERR) { 1672 re_reset(sc); 1673 re_init(sc); 1674 } 1675 1676 if (status & RE_ISR_LINKCHG) 1677 re_tick(sc); 1678 } 1679 1680 if (ifp->if_snd.ifq_head != NULL) 1681 (*ifp->if_start)(ifp); 1682 1683 splx(s); 1684 } 1685 1686 static int 1687 re_encap(sc, m_head, idx) 1688 struct re_softc *sc; 1689 struct mbuf *m_head; 1690 int *idx; 1691 { 1692 struct ifnet *ifp = &sc->arpcom.ac_if; 1693 struct mbuf *m_new = NULL; 1694 struct re_dmaload_arg arg; 1695 bus_dmamap_t map; 1696 int error; 1697 1698 if (sc->re_ldata.re_tx_free <= 4) 1699 return(EFBIG); 1700 1701 /* 1702 * Set up checksum offload. Note: checksum offload bits must 1703 * appear in all descriptors of a multi-descriptor transmit 1704 * attempt. (This is according to testing done with an 8169 1705 * chip. I'm not sure if this is a requirement or a bug.) 1706 */ 1707 1708 arg.re_flags = 0; 1709 1710 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1711 arg.re_flags |= RE_TDESC_CMD_IPCSUM; 1712 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1713 arg.re_flags |= RE_TDESC_CMD_TCPCSUM; 1714 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1715 arg.re_flags |= RE_TDESC_CMD_UDPCSUM; 1716 1717 arg.sc = sc; 1718 arg.re_idx = *idx; 1719 arg.re_maxsegs = sc->re_ldata.re_tx_free; 1720 if (arg.re_maxsegs > 4) 1721 arg.re_maxsegs -= 4; 1722 arg.re_ring = sc->re_ldata.re_tx_list; 1723 1724 map = sc->re_ldata.re_tx_dmamap[*idx]; 1725 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, 1726 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1727 1728 if (error && error != EFBIG) { 1729 if_printf(ifp, "can't map mbuf (error %d)\n", error); 1730 return(ENOBUFS); 1731 } 1732 1733 /* Too many segments to map, coalesce into a single mbuf */ 1734 1735 if (error || arg.re_maxsegs == 0) { 1736 m_new = m_defrag(m_head, MB_DONTWAIT); 1737 if (m_new == NULL) 1738 return(1); 1739 else 1740 m_head = m_new; 1741 1742 arg.sc = sc; 1743 arg.re_idx = *idx; 1744 arg.re_maxsegs = sc->re_ldata.re_tx_free; 1745 arg.re_ring = sc->re_ldata.re_tx_list; 1746 1747 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, 1748 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1749 if (error) { 1750 if_printf(ifp, "can't map mbuf (error %d)\n", error); 1751 return(EFBIG); 1752 } 1753 } 1754 1755 /* 1756 * Insure that the map for this transmission 1757 * is placed at the array index of the last descriptor 1758 * in this chain. 1759 */ 1760 sc->re_ldata.re_tx_dmamap[*idx] = 1761 sc->re_ldata.re_tx_dmamap[arg.re_idx]; 1762 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map; 1763 1764 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m_head; 1765 sc->re_ldata.re_tx_free -= arg.re_maxsegs; 1766 1767 /* 1768 * Set up hardware VLAN tagging. Note: vlan tag info must 1769 * appear in the first descriptor of a multi-descriptor 1770 * transmission attempt. 1771 */ 1772 1773 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1774 m_head->m_pkthdr.rcvif != NULL && 1775 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) { 1776 struct ifvlan *ifv; 1777 ifv = m_head->m_pkthdr.rcvif->if_softc; 1778 if (ifv != NULL) 1779 sc->re_ldata.re_tx_list[*idx].re_vlanctl = 1780 htole32(htobe16(ifv->ifv_tag) | RE_TDESC_VLANCTL_TAG); 1781 } 1782 1783 /* Transfer ownership of packet to the chip. */ 1784 1785 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |= 1786 htole32(RE_TDESC_CMD_OWN); 1787 if (*idx != arg.re_idx) 1788 sc->re_ldata.re_tx_list[*idx].re_cmdstat |= 1789 htole32(RE_TDESC_CMD_OWN); 1790 1791 RE_DESC_INC(arg.re_idx); 1792 *idx = arg.re_idx; 1793 1794 return(0); 1795 } 1796 1797 /* 1798 * Main transmit routine for C+ and gigE NICs. 1799 */ 1800 1801 static void 1802 re_start(struct ifnet *ifp) 1803 { 1804 struct re_softc *sc = ifp->if_softc; 1805 struct mbuf *m_head = NULL; 1806 int idx, s; 1807 1808 s = splimp(); 1809 1810 idx = sc->re_ldata.re_tx_prodidx; 1811 1812 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) { 1813 IF_DEQUEUE(&ifp->if_snd, m_head); 1814 if (m_head == NULL) 1815 break; 1816 1817 if (re_encap(sc, m_head, &idx)) { 1818 IF_PREPEND(&ifp->if_snd, m_head); 1819 ifp->if_flags |= IFF_OACTIVE; 1820 break; 1821 } 1822 1823 /* 1824 * If there's a BPF listener, bounce a copy of this frame 1825 * to him. 1826 */ 1827 BPF_MTAP(ifp, m_head); 1828 } 1829 1830 /* Flush the TX descriptors */ 1831 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1832 sc->re_ldata.re_tx_list_map, 1833 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1834 1835 sc->re_ldata.re_tx_prodidx = idx; 1836 1837 /* 1838 * RealTek put the TX poll request register in a different 1839 * location on the 8169 gigE chip. I don't know why. 1840 */ 1841 if (sc->re_type == RE_8169) 1842 CSR_WRITE_2(sc, RE_GTXSTART, RE_TXSTART_START); 1843 else 1844 CSR_WRITE_2(sc, RE_TXSTART, RE_TXSTART_START); 1845 1846 /* 1847 * Use the countdown timer for interrupt moderation. 1848 * 'TX done' interrupts are disabled. Instead, we reset the 1849 * countdown timer, which will begin counting until it hits 1850 * the value in the TIMERINT register, and then trigger an 1851 * interrupt. Each time we write to the TIMERCNT register, 1852 * the timer count is reset to 0. 1853 */ 1854 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 1855 1856 splx(s); 1857 1858 /* 1859 * Set a timeout in case the chip goes out to lunch. 1860 */ 1861 ifp->if_timer = 5; 1862 } 1863 1864 static void 1865 re_init(void *xsc) 1866 { 1867 struct re_softc *sc = xsc; 1868 struct ifnet *ifp = &sc->arpcom.ac_if; 1869 struct mii_data *mii; 1870 uint32_t rxcfg = 0; 1871 int s; 1872 1873 s = splimp(); 1874 mii = device_get_softc(sc->re_miibus); 1875 1876 /* 1877 * Cancel pending I/O and free all RX/TX buffers. 1878 */ 1879 re_stop(sc); 1880 1881 /* 1882 * Enable C+ RX and TX mode, as well as VLAN stripping and 1883 * RX checksum offload. We must configure the C+ register 1884 * before all others. 1885 */ 1886 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB | 1887 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP | 1888 (ifp->if_capenable & IFCAP_RXCSUM ? 1889 RE_CPLUSCMD_RXCSUM_ENB : 0)); 1890 1891 /* 1892 * Init our MAC address. Even though the chipset 1893 * documentation doesn't mention it, we need to enter "Config 1894 * register write enable" mode to modify the ID registers. 1895 */ 1896 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG); 1897 CSR_WRITE_STREAM_4(sc, RE_IDR0, 1898 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1899 CSR_WRITE_STREAM_4(sc, RE_IDR4, 1900 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1901 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 1902 1903 /* 1904 * For C+ mode, initialize the RX descriptors and mbufs. 1905 */ 1906 re_rx_list_init(sc); 1907 re_tx_list_init(sc); 1908 1909 /* 1910 * Enable transmit and receive. 1911 */ 1912 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 1913 1914 /* 1915 * Set the initial TX and RX configuration. 1916 */ 1917 if (sc->re_testmode) { 1918 if (sc->re_type == RE_8169) 1919 CSR_WRITE_4(sc, RE_TXCFG, 1920 RE_TXCFG_CONFIG | RE_LOOPTEST_ON); 1921 else 1922 CSR_WRITE_4(sc, RE_TXCFG, 1923 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS); 1924 } else 1925 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG); 1926 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG); 1927 1928 /* Set the individual bit to receive frames for this host only. */ 1929 rxcfg = CSR_READ_4(sc, RE_RXCFG); 1930 rxcfg |= RE_RXCFG_RX_INDIV; 1931 1932 /* If we want promiscuous mode, set the allframes bit. */ 1933 if (ifp->if_flags & IFF_PROMISC) { 1934 rxcfg |= RE_RXCFG_RX_ALLPHYS; 1935 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 1936 } else { 1937 rxcfg &= ~RE_RXCFG_RX_ALLPHYS; 1938 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 1939 } 1940 1941 /* 1942 * Set capture broadcast bit to capture broadcast frames. 1943 */ 1944 if (ifp->if_flags & IFF_BROADCAST) { 1945 rxcfg |= RE_RXCFG_RX_BROAD; 1946 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 1947 } else { 1948 rxcfg &= ~RE_RXCFG_RX_BROAD; 1949 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 1950 } 1951 1952 /* 1953 * Program the multicast filter, if necessary. 1954 */ 1955 re_setmulti(sc); 1956 1957 #ifdef DEVICE_POLLING 1958 /* 1959 * Disable interrupts if we are polling. 1960 */ 1961 if (ifp->if_flags & IFF_POLLING) 1962 CSR_WRITE_2(sc, RE_IMR, 0); 1963 else /* otherwise ... */ 1964 #endif /* DEVICE_POLLING */ 1965 /* 1966 * Enable interrupts. 1967 */ 1968 if (sc->re_testmode) 1969 CSR_WRITE_2(sc, RE_IMR, 0); 1970 else 1971 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS); 1972 1973 /* Set initial TX threshold */ 1974 sc->re_txthresh = RE_TX_THRESH_INIT; 1975 1976 /* Start RX/TX process. */ 1977 CSR_WRITE_4(sc, RE_MISSEDPKT, 0); 1978 #ifdef notdef 1979 /* Enable receiver and transmitter. */ 1980 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 1981 #endif 1982 /* 1983 * Load the addresses of the RX and TX lists into the chip. 1984 */ 1985 1986 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI, 1987 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr)); 1988 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO, 1989 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr)); 1990 1991 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI, 1992 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr)); 1993 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO, 1994 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr)); 1995 1996 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16); 1997 1998 /* 1999 * Initialize the timer interrupt register so that 2000 * a timer interrupt will be generated once the timer 2001 * reaches a certain number of ticks. The timer is 2002 * reloaded on each transmit. This gives us TX interrupt 2003 * moderation, which dramatically improves TX frame rate. 2004 */ 2005 2006 if (sc->re_type == RE_8169) 2007 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800); 2008 else 2009 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); 2010 2011 /* 2012 * For 8169 gigE NICs, set the max allowed RX packet 2013 * size so we can receive jumbo frames. 2014 */ 2015 if (sc->re_type == RE_8169) 2016 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383); 2017 2018 if (sc->re_testmode) { 2019 splx(s); 2020 return; 2021 } 2022 2023 mii_mediachg(mii); 2024 2025 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX); 2026 2027 ifp->if_flags |= IFF_RUNNING; 2028 ifp->if_flags &= ~IFF_OACTIVE; 2029 2030 callout_reset(&sc->re_timer, hz, re_tick, sc); 2031 splx(s); 2032 } 2033 2034 /* 2035 * Set media options. 2036 */ 2037 static int 2038 re_ifmedia_upd(struct ifnet *ifp) 2039 { 2040 struct re_softc *sc = ifp->if_softc; 2041 struct mii_data *mii; 2042 2043 mii = device_get_softc(sc->re_miibus); 2044 mii_mediachg(mii); 2045 2046 return(0); 2047 } 2048 2049 /* 2050 * Report current media status. 2051 */ 2052 static void 2053 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2054 { 2055 struct re_softc *sc = ifp->if_softc; 2056 struct mii_data *mii; 2057 2058 mii = device_get_softc(sc->re_miibus); 2059 2060 mii_pollstat(mii); 2061 ifmr->ifm_active = mii->mii_media_active; 2062 ifmr->ifm_status = mii->mii_media_status; 2063 } 2064 2065 static int 2066 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2067 { 2068 struct re_softc *sc = ifp->if_softc; 2069 struct ifreq *ifr = (struct ifreq *) data; 2070 struct mii_data *mii; 2071 int error = 0, s; 2072 2073 s = splimp(); 2074 2075 switch(command) { 2076 case SIOCSIFMTU: 2077 if (ifr->ifr_mtu > RE_JUMBO_MTU) 2078 error = EINVAL; 2079 ifp->if_mtu = ifr->ifr_mtu; 2080 break; 2081 case SIOCSIFFLAGS: 2082 if (ifp->if_flags & IFF_UP) 2083 re_init(sc); 2084 else if (ifp->if_flags & IFF_RUNNING) 2085 re_stop(sc); 2086 error = 0; 2087 break; 2088 case SIOCADDMULTI: 2089 case SIOCDELMULTI: 2090 re_setmulti(sc); 2091 error = 0; 2092 break; 2093 case SIOCGIFMEDIA: 2094 case SIOCSIFMEDIA: 2095 mii = device_get_softc(sc->re_miibus); 2096 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2097 break; 2098 case SIOCSIFCAP: 2099 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING); 2100 ifp->if_capenable |= 2101 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING); 2102 if (ifp->if_capenable & IFCAP_TXCSUM) 2103 ifp->if_hwassist = RE_CSUM_FEATURES; 2104 else 2105 ifp->if_hwassist = 0; 2106 if (ifp->if_flags & IFF_RUNNING) 2107 re_init(sc); 2108 break; 2109 default: 2110 error = ether_ioctl(ifp, command, data); 2111 break; 2112 } 2113 2114 splx(s); 2115 2116 return(error); 2117 } 2118 2119 static void 2120 re_watchdog(struct ifnet *ifp) 2121 { 2122 struct re_softc *sc = ifp->if_softc; 2123 int s; 2124 2125 s = splimp(); 2126 if_printf(ifp, "watchdog timeout\n"); 2127 ifp->if_oerrors++; 2128 2129 re_txeof(sc); 2130 re_rxeof(sc); 2131 2132 re_init(sc); 2133 2134 splx(s); 2135 } 2136 2137 /* 2138 * Stop the adapter and free any mbufs allocated to the 2139 * RX and TX lists. 2140 */ 2141 static void 2142 re_stop(struct re_softc *sc) 2143 { 2144 struct ifnet *ifp = &sc->arpcom.ac_if; 2145 int i, s; 2146 2147 s = splimp(); 2148 ifp->if_timer = 0; 2149 callout_stop(&sc->re_timer); 2150 2151 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2152 #ifdef DEVICE_POLLING 2153 ether_poll_deregister(ifp); 2154 #endif /* DEVICE_POLLING */ 2155 2156 CSR_WRITE_1(sc, RE_COMMAND, 0x00); 2157 CSR_WRITE_2(sc, RE_IMR, 0x0000); 2158 2159 if (sc->re_head != NULL) { 2160 m_freem(sc->re_head); 2161 sc->re_head = sc->re_tail = NULL; 2162 } 2163 2164 /* Free the TX list buffers. */ 2165 for (i = 0; i < RE_TX_DESC_CNT; i++) { 2166 if (sc->re_ldata.re_tx_mbuf[i] != NULL) { 2167 bus_dmamap_unload(sc->re_ldata.re_mtag, 2168 sc->re_ldata.re_tx_dmamap[i]); 2169 m_freem(sc->re_ldata.re_tx_mbuf[i]); 2170 sc->re_ldata.re_tx_mbuf[i] = NULL; 2171 } 2172 } 2173 2174 /* Free the RX list buffers. */ 2175 for (i = 0; i < RE_RX_DESC_CNT; i++) { 2176 if (sc->re_ldata.re_rx_mbuf[i] != NULL) { 2177 bus_dmamap_unload(sc->re_ldata.re_mtag, 2178 sc->re_ldata.re_rx_dmamap[i]); 2179 m_freem(sc->re_ldata.re_rx_mbuf[i]); 2180 sc->re_ldata.re_rx_mbuf[i] = NULL; 2181 } 2182 } 2183 2184 splx(s); 2185 } 2186 2187 /* 2188 * Device suspend routine. Stop the interface and save some PCI 2189 * settings in case the BIOS doesn't restore them properly on 2190 * resume. 2191 */ 2192 static int 2193 re_suspend(device_t dev) 2194 { 2195 #ifndef BURN_BRIDGES 2196 int i; 2197 #endif 2198 struct re_softc *sc = device_get_softc(dev); 2199 2200 re_stop(sc); 2201 2202 #ifndef BURN_BRIDGES 2203 for (i = 0; i < 5; i++) 2204 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2205 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2206 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2207 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2208 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2209 #endif 2210 2211 sc->suspended = 1; 2212 2213 return (0); 2214 } 2215 2216 /* 2217 * Device resume routine. Restore some PCI settings in case the BIOS 2218 * doesn't, re-enable busmastering, and restart the interface if 2219 * appropriate. 2220 */ 2221 static int 2222 re_resume(device_t dev) 2223 { 2224 struct re_softc *sc = device_get_softc(dev); 2225 struct ifnet *ifp = &sc->arpcom.ac_if; 2226 #ifndef BURN_BRIDGES 2227 int i; 2228 #endif 2229 2230 #ifndef BURN_BRIDGES 2231 /* better way to do this? */ 2232 for (i = 0; i < 5; i++) 2233 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2234 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2235 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2236 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2237 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2238 2239 /* reenable busmastering */ 2240 pci_enable_busmaster(dev); 2241 pci_enable_io(dev, SYS_RES_MEMORY); 2242 #endif 2243 2244 /* reinitialize interface if necessary */ 2245 if (ifp->if_flags & IFF_UP) 2246 re_init(sc); 2247 2248 sc->suspended = 0; 2249 2250 return (0); 2251 } 2252 2253 /* 2254 * Stop all chip I/O so that the kernel's probe routines don't 2255 * get confused by errant DMAs when rebooting. 2256 */ 2257 static void 2258 re_shutdown(device_t dev) 2259 { 2260 struct re_softc *sc = device_get_softc(dev); 2261 2262 re_stop(sc); 2263 } 2264