1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $ 36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.36 2007/08/14 13:30:35 sephe Exp $ 37 */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul@windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 51 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7440, so the max MTU possible with this 111 * driver is 7422 bytes. 112 */ 113 114 #include "opt_polling.h" 115 116 #include <sys/param.h> 117 #include <sys/bus.h> 118 #include <sys/endian.h> 119 #include <sys/kernel.h> 120 #include <sys/malloc.h> 121 #include <sys/mbuf.h> 122 /* #include <sys/module.h> */ 123 #include <sys/rman.h> 124 #include <sys/serialize.h> 125 #include <sys/socket.h> 126 #include <sys/sockio.h> 127 #include <sys/sysctl.h> 128 129 #include <net/bpf.h> 130 #include <net/ethernet.h> 131 #include <net/if.h> 132 #include <net/ifq_var.h> 133 #include <net/if_arp.h> 134 #include <net/if_dl.h> 135 #include <net/if_media.h> 136 #include <net/if_types.h> 137 #include <net/vlan/if_vlan_var.h> 138 139 #include <dev/netif/mii_layer/mii.h> 140 #include <dev/netif/mii_layer/miivar.h> 141 142 #include <bus/pci/pcidevs.h> 143 #include <bus/pci/pcireg.h> 144 #include <bus/pci/pcivar.h> 145 146 /* "device miibus" required. See GENERIC if you get errors here. */ 147 #include "miibus_if.h" 148 149 #include <dev/netif/re/if_rereg.h> 150 #include <dev/netif/re/if_revar.h> 151 152 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 153 #if 0 154 #define RE_DISABLE_HWCSUM 155 #endif 156 157 /* 158 * Various supported device vendors/types and their names. 159 */ 160 static const struct re_type re_devs[] = { 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, RE_HWREV_8169S, 162 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 163 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, RE_HWREV_8139CPLUS, 164 "RealTek 8139C+ 10/100BaseTX" }, 165 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, RE_HWREV_8101E, 166 "RealTek 8101E PCIe 10/100baseTX" }, 167 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN1, 168 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 169 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN2, 170 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 171 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN3, 172 "RealTek 8168B/8111B PCIe Gigabit Ethernet" }, 173 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169, 174 "RealTek 8169 Gigabit Ethernet" }, 175 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169S, 176 "RealTek 8169S Single-chip Gigabit Ethernet" }, 177 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SB, 178 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" }, 179 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SC, 180 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 181 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, RE_HWREV_8169_8110SC, 182 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 183 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8110S, 184 "RealTek 8110S Single-chip Gigabit Ethernet" }, 185 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, RE_HWREV_8169S, 186 "Corega CG-LAPCIGT Gigabit Ethernet" }, 187 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, RE_HWREV_8169S, 188 "Linksys EG1032 Gigabit Ethernet" }, 189 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, RE_HWREV_8169S, 190 "US Robotics 997902 Gigabit Ethernet" }, 191 { 0, 0, 0, NULL } 192 }; 193 194 static const struct re_hwrev re_hwrevs[] = { 195 { RE_HWREV_8139CPLUS, RE_8139CPLUS, RE_F_HASMPC, "C+" }, 196 { RE_HWREV_8168_SPIN1, RE_8169, RE_F_PCIE, "8168" }, 197 { RE_HWREV_8168_SPIN2, RE_8169, RE_F_PCIE, "8168" }, 198 { RE_HWREV_8168_SPIN3, RE_8169, RE_F_PCIE, "8168" }, 199 { RE_HWREV_8169, RE_8169, RE_F_HASMPC, "8169" }, 200 { RE_HWREV_8169S, RE_8169, RE_F_HASMPC, "8169S" }, 201 { RE_HWREV_8110S, RE_8169, RE_F_HASMPC, "8110S" }, 202 { RE_HWREV_8169_8110SB, RE_8169, RE_F_HASMPC, "8169SB" }, 203 { RE_HWREV_8169_8110SC, RE_8169, 0, "8169SC" }, 204 { RE_HWREV_8100E, RE_8169, RE_F_HASMPC, "8100E" }, 205 { RE_HWREV_8101E, RE_8169, RE_F_PCIE, "8101E" }, 206 { 0, 0, 0, NULL } 207 }; 208 209 static int re_probe(device_t); 210 static int re_attach(device_t); 211 static int re_detach(device_t); 212 213 static int re_encap(struct re_softc *, struct mbuf **, int *, int *); 214 215 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int); 216 static void re_dma_map_desc(void *, bus_dma_segment_t *, int, 217 bus_size_t, int); 218 static int re_allocmem(device_t, struct re_softc *); 219 static int re_newbuf(struct re_softc *, int, struct mbuf *); 220 static int re_rx_list_init(struct re_softc *); 221 static int re_tx_list_init(struct re_softc *); 222 static void re_rxeof(struct re_softc *); 223 static void re_txeof(struct re_softc *); 224 static void re_intr(void *); 225 static void re_tick(void *); 226 static void re_tick_serialized(void *); 227 static void re_start(struct ifnet *); 228 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 229 static void re_init(void *); 230 static void re_stop(struct re_softc *); 231 static void re_watchdog(struct ifnet *); 232 static int re_suspend(device_t); 233 static int re_resume(device_t); 234 static void re_shutdown(device_t); 235 static int re_ifmedia_upd(struct ifnet *); 236 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 237 238 static void re_eeprom_putbyte(struct re_softc *, int); 239 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *); 240 static void re_read_eeprom(struct re_softc *, caddr_t, int, int); 241 static int re_gmii_readreg(device_t, int, int); 242 static int re_gmii_writereg(device_t, int, int, int); 243 244 static int re_miibus_readreg(device_t, int, int); 245 static int re_miibus_writereg(device_t, int, int, int); 246 static void re_miibus_statchg(device_t); 247 248 static void re_setmulti(struct re_softc *); 249 static void re_reset(struct re_softc *); 250 251 #ifdef RE_DIAG 252 static int re_diag(struct re_softc *); 253 #endif 254 255 #ifdef DEVICE_POLLING 256 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 257 #endif 258 259 static int re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS); 260 261 static device_method_t re_methods[] = { 262 /* Device interface */ 263 DEVMETHOD(device_probe, re_probe), 264 DEVMETHOD(device_attach, re_attach), 265 DEVMETHOD(device_detach, re_detach), 266 DEVMETHOD(device_suspend, re_suspend), 267 DEVMETHOD(device_resume, re_resume), 268 DEVMETHOD(device_shutdown, re_shutdown), 269 270 /* bus interface */ 271 DEVMETHOD(bus_print_child, bus_generic_print_child), 272 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 273 274 /* MII interface */ 275 DEVMETHOD(miibus_readreg, re_miibus_readreg), 276 DEVMETHOD(miibus_writereg, re_miibus_writereg), 277 DEVMETHOD(miibus_statchg, re_miibus_statchg), 278 279 { 0, 0 } 280 }; 281 282 static driver_t re_driver = { 283 "re", 284 re_methods, 285 sizeof(struct re_softc) 286 }; 287 288 static devclass_t re_devclass; 289 290 DECLARE_DUMMY_MODULE(if_re); 291 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0); 292 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0); 293 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 294 295 #define EE_SET(x) \ 296 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x)) 297 298 #define EE_CLR(x) \ 299 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x)) 300 301 /* 302 * Send a read command and address to the EEPROM, check for ACK. 303 */ 304 static void 305 re_eeprom_putbyte(struct re_softc *sc, int addr) 306 { 307 int d, i; 308 309 d = addr | (RE_9346_READ << sc->re_eewidth); 310 311 /* 312 * Feed in each bit and strobe the clock. 313 */ 314 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) { 315 if (d & i) 316 EE_SET(RE_EE_DATAIN); 317 else 318 EE_CLR(RE_EE_DATAIN); 319 DELAY(100); 320 EE_SET(RE_EE_CLK); 321 DELAY(150); 322 EE_CLR(RE_EE_CLK); 323 DELAY(100); 324 } 325 } 326 327 /* 328 * Read a word of data stored in the EEPROM at address 'addr.' 329 */ 330 static void 331 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest) 332 { 333 int i; 334 uint16_t word = 0; 335 336 /* 337 * Send address of word we want to read. 338 */ 339 re_eeprom_putbyte(sc, addr); 340 341 /* 342 * Start reading bits from EEPROM. 343 */ 344 for (i = 0x8000; i != 0; i >>= 1) { 345 EE_SET(RE_EE_CLK); 346 DELAY(100); 347 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT) 348 word |= i; 349 EE_CLR(RE_EE_CLK); 350 DELAY(100); 351 } 352 353 *dest = word; 354 } 355 356 /* 357 * Read a sequence of words from the EEPROM. 358 */ 359 static void 360 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt) 361 { 362 int i; 363 uint16_t word = 0, *ptr; 364 365 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 366 DELAY(100); 367 368 for (i = 0; i < cnt; i++) { 369 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL); 370 re_eeprom_getword(sc, off + i, &word); 371 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL); 372 ptr = (uint16_t *)(dest + (i * 2)); 373 *ptr = word; 374 } 375 376 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 377 } 378 379 static int 380 re_gmii_readreg(device_t dev, int phy, int reg) 381 { 382 struct re_softc *sc = device_get_softc(dev); 383 u_int32_t rval; 384 int i; 385 386 if (phy != 1) 387 return(0); 388 389 /* Let the rgephy driver read the GMEDIASTAT register */ 390 391 if (reg == RE_GMEDIASTAT) 392 return(CSR_READ_1(sc, RE_GMEDIASTAT)); 393 394 CSR_WRITE_4(sc, RE_PHYAR, reg << 16); 395 DELAY(1000); 396 397 for (i = 0; i < RE_TIMEOUT; i++) { 398 rval = CSR_READ_4(sc, RE_PHYAR); 399 if (rval & RE_PHYAR_BUSY) 400 break; 401 DELAY(100); 402 } 403 404 if (i == RE_TIMEOUT) { 405 device_printf(dev, "PHY read failed\n"); 406 return(0); 407 } 408 409 return(rval & RE_PHYAR_PHYDATA); 410 } 411 412 static int 413 re_gmii_writereg(device_t dev, int phy, int reg, int data) 414 { 415 struct re_softc *sc = device_get_softc(dev); 416 uint32_t rval; 417 int i; 418 419 CSR_WRITE_4(sc, RE_PHYAR, 420 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY); 421 DELAY(1000); 422 423 for (i = 0; i < RE_TIMEOUT; i++) { 424 rval = CSR_READ_4(sc, RE_PHYAR); 425 if ((rval & RE_PHYAR_BUSY) == 0) 426 break; 427 DELAY(100); 428 } 429 430 if (i == RE_TIMEOUT) 431 device_printf(dev, "PHY write failed\n"); 432 433 return(0); 434 } 435 436 static int 437 re_miibus_readreg(device_t dev, int phy, int reg) 438 { 439 struct re_softc *sc = device_get_softc(dev); 440 uint16_t rval = 0; 441 uint16_t re8139_reg = 0; 442 443 if (sc->re_type == RE_8169) { 444 rval = re_gmii_readreg(dev, phy, reg); 445 return(rval); 446 } 447 448 /* Pretend the internal PHY is only at address 0 */ 449 if (phy) 450 return(0); 451 452 switch(reg) { 453 case MII_BMCR: 454 re8139_reg = RE_BMCR; 455 break; 456 case MII_BMSR: 457 re8139_reg = RE_BMSR; 458 break; 459 case MII_ANAR: 460 re8139_reg = RE_ANAR; 461 break; 462 case MII_ANER: 463 re8139_reg = RE_ANER; 464 break; 465 case MII_ANLPAR: 466 re8139_reg = RE_LPAR; 467 break; 468 case MII_PHYIDR1: 469 case MII_PHYIDR2: 470 return(0); 471 /* 472 * Allow the rlphy driver to read the media status 473 * register. If we have a link partner which does not 474 * support NWAY, this is the register which will tell 475 * us the results of parallel detection. 476 */ 477 case RE_MEDIASTAT: 478 return(CSR_READ_1(sc, RE_MEDIASTAT)); 479 default: 480 device_printf(dev, "bad phy register\n"); 481 return(0); 482 } 483 rval = CSR_READ_2(sc, re8139_reg); 484 if (sc->re_type == RE_8139CPLUS && re8139_reg == RE_BMCR) { 485 /* 8139C+ has different bit layout. */ 486 rval &= ~(BMCR_LOOP | BMCR_ISO); 487 } 488 return(rval); 489 } 490 491 static int 492 re_miibus_writereg(device_t dev, int phy, int reg, int data) 493 { 494 struct re_softc *sc= device_get_softc(dev); 495 u_int16_t re8139_reg = 0; 496 497 if (sc->re_type == RE_8169) 498 return(re_gmii_writereg(dev, phy, reg, data)); 499 500 /* Pretend the internal PHY is only at address 0 */ 501 if (phy) 502 return(0); 503 504 switch(reg) { 505 case MII_BMCR: 506 re8139_reg = RE_BMCR; 507 if (sc->re_type == RE_8139CPLUS) { 508 /* 8139C+ has different bit layout. */ 509 data &= ~(BMCR_LOOP | BMCR_ISO); 510 } 511 break; 512 case MII_BMSR: 513 re8139_reg = RE_BMSR; 514 break; 515 case MII_ANAR: 516 re8139_reg = RE_ANAR; 517 break; 518 case MII_ANER: 519 re8139_reg = RE_ANER; 520 break; 521 case MII_ANLPAR: 522 re8139_reg = RE_LPAR; 523 break; 524 case MII_PHYIDR1: 525 case MII_PHYIDR2: 526 return(0); 527 default: 528 device_printf(dev, "bad phy register\n"); 529 return(0); 530 } 531 CSR_WRITE_2(sc, re8139_reg, data); 532 return(0); 533 } 534 535 static void 536 re_miibus_statchg(device_t dev) 537 { 538 } 539 540 /* 541 * Program the 64-bit multicast hash filter. 542 */ 543 static void 544 re_setmulti(struct re_softc *sc) 545 { 546 struct ifnet *ifp = &sc->arpcom.ac_if; 547 int h = 0; 548 uint32_t hashes[2] = { 0, 0 }; 549 struct ifmultiaddr *ifma; 550 uint32_t rxfilt; 551 int mcnt = 0; 552 553 rxfilt = CSR_READ_4(sc, RE_RXCFG); 554 555 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 556 rxfilt |= RE_RXCFG_RX_MULTI; 557 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 558 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF); 559 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF); 560 return; 561 } 562 563 /* first, zot all the existing hash bits */ 564 CSR_WRITE_4(sc, RE_MAR0, 0); 565 CSR_WRITE_4(sc, RE_MAR4, 0); 566 567 /* now program new ones */ 568 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 569 if (ifma->ifma_addr->sa_family != AF_LINK) 570 continue; 571 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 572 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 573 if (h < 32) 574 hashes[0] |= (1 << h); 575 else 576 hashes[1] |= (1 << (h - 32)); 577 mcnt++; 578 } 579 580 if (mcnt) 581 rxfilt |= RE_RXCFG_RX_MULTI; 582 else 583 rxfilt &= ~RE_RXCFG_RX_MULTI; 584 585 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 586 587 /* 588 * For some unfathomable reason, RealTek decided to reverse 589 * the order of the multicast hash registers in the PCI Express 590 * parts. This means we have to write the hash pattern in reverse 591 * order for those devices. 592 */ 593 if (sc->re_flags & RE_F_PCIE) { 594 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[0])); 595 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[1])); 596 } else { 597 CSR_WRITE_4(sc, RE_MAR0, hashes[0]); 598 CSR_WRITE_4(sc, RE_MAR4, hashes[1]); 599 } 600 } 601 602 static void 603 re_reset(struct re_softc *sc) 604 { 605 int i; 606 607 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET); 608 609 for (i = 0; i < RE_TIMEOUT; i++) { 610 DELAY(10); 611 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0) 612 break; 613 } 614 if (i == RE_TIMEOUT) 615 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 616 617 CSR_WRITE_1(sc, 0x82, 1); 618 } 619 620 #ifdef RE_DIAG 621 /* 622 * The following routine is designed to test for a defect on some 623 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 624 * lines connected to the bus, however for a 32-bit only card, they 625 * should be pulled high. The result of this defect is that the 626 * NIC will not work right if you plug it into a 64-bit slot: DMA 627 * operations will be done with 64-bit transfers, which will fail 628 * because the 64-bit data lines aren't connected. 629 * 630 * There's no way to work around this (short of talking a soldering 631 * iron to the board), however we can detect it. The method we use 632 * here is to put the NIC into digital loopback mode, set the receiver 633 * to promiscuous mode, and then try to send a frame. We then compare 634 * the frame data we sent to what was received. If the data matches, 635 * then the NIC is working correctly, otherwise we know the user has 636 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 637 * slot. In the latter case, there's no way the NIC can work correctly, 638 * so we print out a message on the console and abort the device attach. 639 */ 640 641 static int 642 re_diag(struct re_softc *sc) 643 { 644 struct ifnet *ifp = &sc->arpcom.ac_if; 645 struct mbuf *m0; 646 struct ether_header *eh; 647 struct re_desc *cur_rx; 648 uint16_t status; 649 uint32_t rxstat; 650 int total_len, i, error = 0, phyaddr; 651 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 652 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 653 654 /* Allocate a single mbuf */ 655 656 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 657 if (m0 == NULL) 658 return(ENOBUFS); 659 660 /* 661 * Initialize the NIC in test mode. This sets the chip up 662 * so that it can send and receive frames, but performs the 663 * following special functions: 664 * - Puts receiver in promiscuous mode 665 * - Enables digital loopback mode 666 * - Leaves interrupts turned off 667 */ 668 669 ifp->if_flags |= IFF_PROMISC; 670 sc->re_testmode = 1; 671 re_reset(sc); 672 re_init(sc); 673 sc->re_link = 1; 674 if (sc->re_type == RE_8169) 675 phyaddr = 1; 676 else 677 phyaddr = 0; 678 679 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET); 680 for (i = 0; i < RE_TIMEOUT; i++) { 681 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR); 682 if (!(status & BMCR_RESET)) 683 break; 684 } 685 686 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP); 687 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG); 688 689 DELAY(100000); 690 691 /* Put some data in the mbuf */ 692 693 eh = mtod(m0, struct ether_header *); 694 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN); 695 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN); 696 eh->ether_type = htons(ETHERTYPE_IP); 697 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 698 699 /* 700 * Queue the packet, start transmission. 701 * Note: ifq_handoff() ultimately calls re_start() for us. 702 */ 703 704 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 705 error = ifq_handoff(ifp, m0, NULL); 706 if (error) { 707 m0 = NULL; 708 goto done; 709 } 710 m0 = NULL; 711 712 /* Wait for it to propagate through the chip */ 713 714 DELAY(100000); 715 for (i = 0; i < RE_TIMEOUT; i++) { 716 status = CSR_READ_2(sc, RE_ISR); 717 CSR_WRITE_2(sc, RE_ISR, status); 718 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) == 719 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) 720 break; 721 DELAY(10); 722 } 723 724 if (i == RE_TIMEOUT) { 725 if_printf(ifp, "diagnostic failed to receive packet " 726 "in loopback mode\n"); 727 error = EIO; 728 goto done; 729 } 730 731 /* 732 * The packet should have been dumped into the first 733 * entry in the RX DMA ring. Grab it from there. 734 */ 735 736 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 737 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 738 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0], 739 BUS_DMASYNC_POSTWRITE); 740 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]); 741 742 m0 = sc->re_ldata.re_rx_mbuf[0]; 743 sc->re_ldata.re_rx_mbuf[0] = NULL; 744 eh = mtod(m0, struct ether_header *); 745 746 cur_rx = &sc->re_ldata.re_rx_list[0]; 747 total_len = RE_RXBYTES(cur_rx); 748 rxstat = le32toh(cur_rx->re_cmdstat); 749 750 if (total_len != ETHER_MIN_LEN) { 751 if_printf(ifp, "diagnostic failed, received short packet\n"); 752 error = EIO; 753 goto done; 754 } 755 756 /* Test that the received packet data matches what we sent. */ 757 758 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) || 759 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) || 760 be16toh(eh->ether_type) != ETHERTYPE_IP) { 761 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 762 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n", 763 dst, ":", src, ":", ETHERTYPE_IP); 764 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n", 765 eh->ether_dhost, ":", eh->ether_shost, ":", 766 ntohs(eh->ether_type)); 767 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 768 "into a 64-bit PCI slot.\n"); 769 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 770 "for proper operation.\n"); 771 if_printf(ifp, "Read the re(4) man page for more details.\n"); 772 error = EIO; 773 } 774 775 done: 776 /* Turn interface off, release resources */ 777 778 sc->re_testmode = 0; 779 sc->re_link = 0; 780 ifp->if_flags &= ~IFF_PROMISC; 781 re_stop(sc); 782 if (m0 != NULL) 783 m_freem(m0); 784 785 return (error); 786 } 787 #endif /* RE_DIAG */ 788 789 /* 790 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 791 * IDs against our list and return a device name if we find a match. 792 */ 793 static int 794 re_probe(device_t dev) 795 { 796 const struct re_type *t; 797 struct re_softc *sc; 798 int rid; 799 uint32_t hwrev; 800 uint16_t vendor, product; 801 802 t = re_devs; 803 804 vendor = pci_get_vendor(dev); 805 product = pci_get_device(dev); 806 807 /* 808 * Only attach to rev.3 of the Linksys EG1032 adapter. 809 * Rev.2 is supported by sk(4). 810 */ 811 if (vendor == PCI_VENDOR_LINKSYS && 812 product == PCI_PRODUCT_LINKSYS_EG1032 && 813 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3) 814 return ENXIO; 815 816 for (t = re_devs; t->re_name != NULL; t++) { 817 if (product == t->re_did && vendor == t->re_vid) 818 break; 819 } 820 821 /* 822 * Check if we found a RealTek device. 823 */ 824 if (t->re_name == NULL) 825 return(ENXIO); 826 827 /* 828 * Temporarily map the I/O space so we can read the chip ID register. 829 */ 830 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO); 831 rid = RE_PCI_LOIO; 832 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 833 RF_ACTIVE); 834 if (sc->re_res == NULL) { 835 device_printf(dev, "couldn't map ports/memory\n"); 836 kfree(sc, M_TEMP); 837 return(ENXIO); 838 } 839 840 sc->re_btag = rman_get_bustag(sc->re_res); 841 sc->re_bhandle = rman_get_bushandle(sc->re_res); 842 843 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV; 844 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res); 845 kfree(sc, M_TEMP); 846 847 /* 848 * and continue matching for the specific chip... 849 */ 850 for (; t->re_name != NULL; t++) { 851 if (product == t->re_did && vendor == t->re_vid && 852 t->re_basetype == hwrev) { 853 device_set_desc(dev, t->re_name); 854 return(0); 855 } 856 } 857 return(ENXIO); 858 } 859 860 /* 861 * This routine takes the segment list provided as the result of 862 * a bus_dma_map_load() operation and assigns the addresses/lengths 863 * to RealTek DMA descriptors. This can be called either by the RX 864 * code or the TX code. In the RX case, we'll probably wind up mapping 865 * at most one segment. For the TX case, there could be any number of 866 * segments since TX packets may span multiple mbufs. In either case, 867 * if the number of segments is larger than the re_maxsegs limit 868 * specified by the caller, we abort the mapping operation. Sadly, 869 * whoever designed the buffer mapping API did not provide a way to 870 * return an error from here, so we have to fake it a bit. 871 */ 872 873 static void 874 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, 875 bus_size_t mapsize, int error) 876 { 877 struct re_dmaload_arg *ctx; 878 struct re_desc *d = NULL; 879 int i = 0, idx; 880 uint32_t cmdstat; 881 882 if (error) 883 return; 884 885 ctx = arg; 886 887 /* Signal error to caller if there's too many segments */ 888 if (nseg > ctx->re_maxsegs) { 889 ctx->re_maxsegs = 0; 890 return; 891 } 892 893 /* 894 * Map the segment array into descriptors. Note that we set the 895 * start-of-frame and end-of-frame markers for either TX or RX, but 896 * they really only have meaning in the TX case. (In the RX case, 897 * it's the chip that tells us where packets begin and end.) 898 * We also keep track of the end of the ring and set the 899 * end-of-ring bits as needed, and we set the ownership bits 900 * in all except the very first descriptor. (The caller will 901 * set this descriptor later when it start transmission or 902 * reception.) 903 */ 904 idx = ctx->re_idx; 905 for (;;) { 906 d = &ctx->re_ring[idx]; 907 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) { 908 ctx->re_maxsegs = 0; 909 return; 910 } 911 cmdstat = segs[i].ds_len; 912 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr)); 913 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr)); 914 if (i == 0) 915 cmdstat |= RE_TDESC_CMD_SOF; 916 else 917 cmdstat |= RE_TDESC_CMD_OWN; 918 if (idx == (RE_RX_DESC_CNT - 1)) 919 cmdstat |= RE_TDESC_CMD_EOR; 920 d->re_cmdstat = htole32(cmdstat | ctx->re_flags); 921 i++; 922 if (i == nseg) 923 break; 924 RE_DESC_INC(idx); 925 } 926 927 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF); 928 ctx->re_maxsegs = nseg; 929 ctx->re_idx = idx; 930 } 931 932 /* 933 * Map a single buffer address. 934 */ 935 936 static void 937 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 938 { 939 uint32_t *addr; 940 941 if (error) 942 return; 943 944 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 945 addr = arg; 946 *addr = segs->ds_addr; 947 } 948 949 static int 950 re_allocmem(device_t dev, struct re_softc *sc) 951 { 952 int error, i, nseg; 953 954 /* 955 * Allocate map for RX mbufs. 956 */ 957 nseg = 32; 958 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0, 959 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 960 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 961 &sc->re_ldata.re_mtag); 962 if (error) { 963 device_printf(dev, "could not allocate dma tag\n"); 964 return(error); 965 } 966 967 /* 968 * Allocate map for TX descriptor list. 969 */ 970 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN, 971 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 972 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 973 &sc->re_ldata.re_tx_list_tag); 974 if (error) { 975 device_printf(dev, "could not allocate dma tag\n"); 976 return(error); 977 } 978 979 /* Allocate DMA'able memory for the TX ring */ 980 981 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag, 982 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO, 983 &sc->re_ldata.re_tx_list_map); 984 if (error) { 985 device_printf(dev, "could not allocate TX ring\n"); 986 return(error); 987 } 988 989 /* Load the map for the TX ring. */ 990 991 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag, 992 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 993 RE_TX_LIST_SZ, re_dma_map_addr, 994 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT); 995 if (error) { 996 device_printf(dev, "could not get addres of TX ring\n"); 997 return(error); 998 } 999 1000 /* Create DMA maps for TX buffers */ 1001 1002 for (i = 0; i < RE_TX_DESC_CNT; i++) { 1003 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, 1004 &sc->re_ldata.re_tx_dmamap[i]); 1005 if (error) { 1006 device_printf(dev, "can't create DMA map for TX\n"); 1007 return(error); 1008 } 1009 } 1010 1011 /* 1012 * Allocate map for RX descriptor list. 1013 */ 1014 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN, 1015 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1016 NULL, RE_RX_LIST_SZ, 1, RE_RX_LIST_SZ, BUS_DMA_ALLOCNOW, 1017 &sc->re_ldata.re_rx_list_tag); 1018 if (error) { 1019 device_printf(dev, "could not allocate dma tag\n"); 1020 return(error); 1021 } 1022 1023 /* Allocate DMA'able memory for the RX ring */ 1024 1025 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag, 1026 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO, 1027 &sc->re_ldata.re_rx_list_map); 1028 if (error) { 1029 device_printf(dev, "could not allocate RX ring\n"); 1030 return(error); 1031 } 1032 1033 /* Load the map for the RX ring. */ 1034 1035 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag, 1036 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 1037 RE_RX_LIST_SZ, re_dma_map_addr, 1038 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT); 1039 if (error) { 1040 device_printf(dev, "could not get address of RX ring\n"); 1041 return(error); 1042 } 1043 1044 /* Create DMA maps for RX buffers */ 1045 1046 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1047 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, 1048 &sc->re_ldata.re_rx_dmamap[i]); 1049 if (error) { 1050 device_printf(dev, "can't create DMA map for RX\n"); 1051 return(ENOMEM); 1052 } 1053 } 1054 1055 return(0); 1056 } 1057 1058 /* 1059 * Attach the interface. Allocate softc structures, do ifmedia 1060 * setup and ethernet/BPF attach. 1061 */ 1062 static int 1063 re_attach(device_t dev) 1064 { 1065 struct re_softc *sc = device_get_softc(dev); 1066 struct ifnet *ifp; 1067 const struct re_hwrev *hw_rev; 1068 uint8_t eaddr[ETHER_ADDR_LEN]; 1069 uint16_t as[ETHER_ADDR_LEN / 2]; 1070 uint16_t re_did = 0; 1071 uint32_t hwrev; 1072 int error = 0, rid, i; 1073 1074 callout_init(&sc->re_timer); 1075 #ifdef RE_DIAG 1076 sc->re_dev = dev; 1077 #endif 1078 1079 RE_ENABLE_TX_MODERATION(sc); 1080 1081 sysctl_ctx_init(&sc->re_sysctl_ctx); 1082 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx, 1083 SYSCTL_STATIC_CHILDREN(_hw), 1084 OID_AUTO, 1085 device_get_nameunit(dev), 1086 CTLFLAG_RD, 0, ""); 1087 if (sc->re_sysctl_tree == NULL) { 1088 device_printf(dev, "can't add sysctl node\n"); 1089 error = ENXIO; 1090 goto fail; 1091 } 1092 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1093 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1094 OID_AUTO, "tx_moderation", 1095 CTLTYPE_INT | CTLFLAG_RW, 1096 sc, 0, re_sysctl_tx_moderation, "I", 1097 "Enable/Disable TX moderation"); 1098 1099 #ifndef BURN_BRIDGES 1100 /* 1101 * Handle power management nonsense. 1102 */ 1103 1104 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1105 uint32_t membase, irq; 1106 1107 /* Save important PCI config data. */ 1108 membase = pci_read_config(dev, RE_PCI_LOMEM, 4); 1109 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1110 1111 /* Reset the power state. */ 1112 device_printf(dev, "chip is in D%d power mode " 1113 "-- setting to D0\n", pci_get_powerstate(dev)); 1114 1115 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1116 1117 /* Restore PCI config data. */ 1118 pci_write_config(dev, RE_PCI_LOMEM, membase, 4); 1119 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1120 } 1121 #endif 1122 /* 1123 * Map control/status registers. 1124 */ 1125 pci_enable_busmaster(dev); 1126 1127 rid = RE_PCI_LOIO; 1128 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1129 RF_ACTIVE); 1130 1131 if (sc->re_res == NULL) { 1132 device_printf(dev, "couldn't map ports\n"); 1133 error = ENXIO; 1134 goto fail; 1135 } 1136 1137 sc->re_btag = rman_get_bustag(sc->re_res); 1138 sc->re_bhandle = rman_get_bushandle(sc->re_res); 1139 1140 /* Allocate interrupt */ 1141 rid = 0; 1142 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1143 RF_SHAREABLE | RF_ACTIVE); 1144 1145 if (sc->re_irq == NULL) { 1146 device_printf(dev, "couldn't map interrupt\n"); 1147 error = ENXIO; 1148 goto fail; 1149 } 1150 1151 /* Reset the adapter. */ 1152 re_reset(sc); 1153 1154 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV; 1155 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) { 1156 if (hw_rev->re_rev == hwrev) { 1157 sc->re_type = hw_rev->re_type; 1158 sc->re_flags = hw_rev->re_flags; 1159 break; 1160 } 1161 } 1162 1163 sc->re_eewidth = 6; 1164 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1165 if (re_did != 0x8129) 1166 sc->re_eewidth = 8; 1167 1168 /* 1169 * Get station address from the EEPROM. 1170 */ 1171 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3); 1172 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1173 as[i] = le16toh(as[i]); 1174 bcopy(as, eaddr, sizeof(eaddr)); 1175 1176 if (sc->re_type == RE_8169) { 1177 /* Set RX length mask */ 1178 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 1179 sc->re_txstart = RE_GTXSTART; 1180 } else { 1181 /* Set RX length mask */ 1182 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 1183 sc->re_txstart = RE_TXSTART; 1184 } 1185 1186 /* 1187 * Allocate the parent bus DMA tag appropriate for PCI. 1188 */ 1189 #define RE_NSEG_NEW 32 1190 error = bus_dma_tag_create(NULL, /* parent */ 1191 1, 0, /* alignment, boundary */ 1192 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1193 BUS_SPACE_MAXADDR, /* highaddr */ 1194 NULL, NULL, /* filter, filterarg */ 1195 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */ 1196 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1197 BUS_DMA_ALLOCNOW, /* flags */ 1198 &sc->re_parent_tag); 1199 if (error) 1200 goto fail; 1201 1202 error = re_allocmem(dev, sc); 1203 1204 if (error) 1205 goto fail; 1206 1207 /* Do MII setup */ 1208 if (mii_phy_probe(dev, &sc->re_miibus, 1209 re_ifmedia_upd, re_ifmedia_sts)) { 1210 device_printf(dev, "MII without any phy!\n"); 1211 error = ENXIO; 1212 goto fail; 1213 } 1214 1215 ifp = &sc->arpcom.ac_if; 1216 ifp->if_softc = sc; 1217 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1218 ifp->if_mtu = ETHERMTU; 1219 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1220 ifp->if_ioctl = re_ioctl; 1221 ifp->if_capabilities = IFCAP_VLAN_MTU; 1222 ifp->if_start = re_start; 1223 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1224 #ifdef DEVICE_POLLING 1225 ifp->if_poll = re_poll; 1226 #endif 1227 ifp->if_watchdog = re_watchdog; 1228 ifp->if_init = re_init; 1229 if (sc->re_type == RE_8169) 1230 ifp->if_baudrate = 1000000000; 1231 else 1232 ifp->if_baudrate = 100000000; 1233 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN); 1234 ifq_set_ready(&ifp->if_snd); 1235 1236 #ifdef RE_DISABLE_HWCSUM 1237 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1238 ifp->if_hwassist = 0; 1239 #else 1240 ifp->if_capenable = ifp->if_capabilities; 1241 ifp->if_hwassist = RE_CSUM_FEATURES; 1242 #endif /* RE_DISABLE_HWCSUM */ 1243 1244 /* 1245 * Call MI attach routine. 1246 */ 1247 ether_ifattach(ifp, eaddr, NULL); 1248 1249 #ifdef RE_DIAG 1250 /* 1251 * Perform hardware diagnostic on the original RTL8169. 1252 * Some 32-bit cards were incorrectly wired and would 1253 * malfunction if plugged into a 64-bit slot. 1254 */ 1255 if (hwrev == RE_HWREV_8169) { 1256 lwkt_serialize_enter(ifp->if_serializer); 1257 error = re_diag(sc); 1258 lwkt_serialize_exit(ifp->if_serializer); 1259 1260 if (error) { 1261 device_printf(dev, "hardware diagnostic failure\n"); 1262 ether_ifdetach(ifp); 1263 goto fail; 1264 } 1265 } 1266 #endif /* RE_DIAG */ 1267 1268 /* Hook interrupt last to avoid having to lock softc */ 1269 error = bus_setup_intr(dev, sc->re_irq, INTR_NETSAFE, re_intr, sc, 1270 &sc->re_intrhand, ifp->if_serializer); 1271 1272 if (error) { 1273 device_printf(dev, "couldn't set up irq\n"); 1274 ether_ifdetach(ifp); 1275 goto fail; 1276 } 1277 1278 fail: 1279 if (error) 1280 re_detach(dev); 1281 1282 return (error); 1283 } 1284 1285 /* 1286 * Shutdown hardware and free up resources. This can be called any 1287 * time after the mutex has been initialized. It is called in both 1288 * the error case in attach and the normal detach case so it needs 1289 * to be careful about only freeing resources that have actually been 1290 * allocated. 1291 */ 1292 static int 1293 re_detach(device_t dev) 1294 { 1295 struct re_softc *sc = device_get_softc(dev); 1296 struct ifnet *ifp = &sc->arpcom.ac_if; 1297 int i; 1298 1299 /* These should only be active if attach succeeded */ 1300 if (device_is_attached(dev)) { 1301 lwkt_serialize_enter(ifp->if_serializer); 1302 re_stop(sc); 1303 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand); 1304 lwkt_serialize_exit(ifp->if_serializer); 1305 1306 ether_ifdetach(ifp); 1307 } 1308 if (sc->re_miibus) 1309 device_delete_child(dev, sc->re_miibus); 1310 bus_generic_detach(dev); 1311 1312 if (sc->re_irq) 1313 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq); 1314 if (sc->re_res) { 1315 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, 1316 sc->re_res); 1317 } 1318 1319 /* Unload and free the RX DMA ring memory and map */ 1320 1321 if (sc->re_ldata.re_rx_list_tag) { 1322 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag, 1323 sc->re_ldata.re_rx_list_map); 1324 bus_dmamem_free(sc->re_ldata.re_rx_list_tag, 1325 sc->re_ldata.re_rx_list, 1326 sc->re_ldata.re_rx_list_map); 1327 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1328 } 1329 1330 /* Unload and free the TX DMA ring memory and map */ 1331 1332 if (sc->re_ldata.re_tx_list_tag) { 1333 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag, 1334 sc->re_ldata.re_tx_list_map); 1335 bus_dmamem_free(sc->re_ldata.re_tx_list_tag, 1336 sc->re_ldata.re_tx_list, 1337 sc->re_ldata.re_tx_list_map); 1338 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1339 } 1340 1341 /* Destroy all the RX and TX buffer maps */ 1342 1343 if (sc->re_ldata.re_mtag) { 1344 for (i = 0; i < RE_TX_DESC_CNT; i++) 1345 bus_dmamap_destroy(sc->re_ldata.re_mtag, 1346 sc->re_ldata.re_tx_dmamap[i]); 1347 for (i = 0; i < RE_RX_DESC_CNT; i++) 1348 bus_dmamap_destroy(sc->re_ldata.re_mtag, 1349 sc->re_ldata.re_rx_dmamap[i]); 1350 bus_dma_tag_destroy(sc->re_ldata.re_mtag); 1351 } 1352 1353 /* Unload and free the stats buffer and map */ 1354 1355 if (sc->re_ldata.re_stag) { 1356 bus_dmamap_unload(sc->re_ldata.re_stag, 1357 sc->re_ldata.re_rx_list_map); 1358 bus_dmamem_free(sc->re_ldata.re_stag, 1359 sc->re_ldata.re_stats, 1360 sc->re_ldata.re_smap); 1361 bus_dma_tag_destroy(sc->re_ldata.re_stag); 1362 } 1363 1364 if (sc->re_parent_tag) 1365 bus_dma_tag_destroy(sc->re_parent_tag); 1366 1367 return(0); 1368 } 1369 1370 static int 1371 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m) 1372 { 1373 struct re_dmaload_arg arg; 1374 struct mbuf *n = NULL; 1375 int error; 1376 1377 if (m == NULL) { 1378 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1379 if (n == NULL) 1380 return(ENOBUFS); 1381 m = n; 1382 } else 1383 m->m_data = m->m_ext.ext_buf; 1384 1385 m->m_len = m->m_pkthdr.len = MCLBYTES; 1386 1387 /* 1388 * NOTE: 1389 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer 1390 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1391 */ 1392 1393 arg.sc = sc; 1394 arg.re_idx = idx; 1395 arg.re_maxsegs = 1; 1396 arg.re_flags = 0; 1397 arg.re_ring = sc->re_ldata.re_rx_list; 1398 1399 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, 1400 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc, 1401 &arg, BUS_DMA_NOWAIT); 1402 if (error || arg.re_maxsegs != 1) { 1403 if (n != NULL) 1404 m_freem(n); 1405 return (ENOMEM); 1406 } 1407 1408 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN); 1409 sc->re_ldata.re_rx_mbuf[idx] = m; 1410 1411 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx], 1412 BUS_DMASYNC_PREREAD); 1413 1414 return(0); 1415 } 1416 1417 static int 1418 re_tx_list_init(struct re_softc *sc) 1419 { 1420 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ); 1421 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *)); 1422 1423 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1424 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE); 1425 sc->re_ldata.re_tx_prodidx = 0; 1426 sc->re_ldata.re_tx_considx = 0; 1427 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT; 1428 1429 return(0); 1430 } 1431 1432 static int 1433 re_rx_list_init(struct re_softc *sc) 1434 { 1435 int i, error; 1436 1437 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ); 1438 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *)); 1439 1440 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1441 error = re_newbuf(sc, i, NULL); 1442 if (error) 1443 return(error); 1444 } 1445 1446 /* Flush the RX descriptors */ 1447 1448 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1449 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE); 1450 1451 sc->re_ldata.re_rx_prodidx = 0; 1452 sc->re_head = sc->re_tail = NULL; 1453 1454 return(0); 1455 } 1456 1457 /* 1458 * RX handler for C+ and 8169. For the gigE chips, we support 1459 * the reception of jumbo frames that have been fragmented 1460 * across multiple 2K mbuf cluster buffers. 1461 */ 1462 static void 1463 re_rxeof(struct re_softc *sc) 1464 { 1465 struct ifnet *ifp = &sc->arpcom.ac_if; 1466 struct mbuf *m; 1467 struct re_desc *cur_rx; 1468 uint32_t rxstat, rxvlan; 1469 int i, total_len; 1470 1471 /* Invalidate the descriptor memory */ 1472 1473 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1474 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); 1475 1476 for (i = sc->re_ldata.re_rx_prodidx; 1477 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) { 1478 cur_rx = &sc->re_ldata.re_rx_list[i]; 1479 m = sc->re_ldata.re_rx_mbuf[i]; 1480 total_len = RE_RXBYTES(cur_rx); 1481 rxstat = le32toh(cur_rx->re_cmdstat); 1482 rxvlan = le32toh(cur_rx->re_vlanctl); 1483 1484 /* Invalidate the RX mbuf and unload its map */ 1485 1486 bus_dmamap_sync(sc->re_ldata.re_mtag, 1487 sc->re_ldata.re_rx_dmamap[i], 1488 BUS_DMASYNC_POSTWRITE); 1489 bus_dmamap_unload(sc->re_ldata.re_mtag, 1490 sc->re_ldata.re_rx_dmamap[i]); 1491 1492 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1493 m->m_len = MCLBYTES - ETHER_ALIGN; 1494 if (sc->re_head == NULL) { 1495 sc->re_head = sc->re_tail = m; 1496 } else { 1497 sc->re_tail->m_next = m; 1498 sc->re_tail = m; 1499 } 1500 re_newbuf(sc, i, NULL); 1501 continue; 1502 } 1503 1504 /* 1505 * NOTE: for the 8139C+, the frame length field 1506 * is always 12 bits in size, but for the gigE chips, 1507 * it is 13 bits (since the max RX frame length is 16K). 1508 * Unfortunately, all 32 bits in the status word 1509 * were already used, so to make room for the extra 1510 * length bit, RealTek took out the 'frame alignment 1511 * error' bit and shifted the other status bits 1512 * over one slot. The OWN, EOR, FS and LS bits are 1513 * still in the same places. We have already extracted 1514 * the frame length and checked the OWN bit, so rather 1515 * than using an alternate bit mapping, we shift the 1516 * status bits one space to the right so we can evaluate 1517 * them using the 8169 status as though it was in the 1518 * same format as that of the 8139C+. 1519 */ 1520 if (sc->re_type == RE_8169) 1521 rxstat >>= 1; 1522 1523 if (rxstat & RE_RDESC_STAT_RXERRSUM) { 1524 ifp->if_ierrors++; 1525 /* 1526 * If this is part of a multi-fragment packet, 1527 * discard all the pieces. 1528 */ 1529 if (sc->re_head != NULL) { 1530 m_freem(sc->re_head); 1531 sc->re_head = sc->re_tail = NULL; 1532 } 1533 re_newbuf(sc, i, m); 1534 continue; 1535 } 1536 1537 /* 1538 * If allocating a replacement mbuf fails, 1539 * reload the current one. 1540 */ 1541 1542 if (re_newbuf(sc, i, NULL)) { 1543 ifp->if_ierrors++; 1544 if (sc->re_head != NULL) { 1545 m_freem(sc->re_head); 1546 sc->re_head = sc->re_tail = NULL; 1547 } 1548 re_newbuf(sc, i, m); 1549 continue; 1550 } 1551 1552 if (sc->re_head != NULL) { 1553 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN); 1554 /* 1555 * Special case: if there's 4 bytes or less 1556 * in this buffer, the mbuf can be discarded: 1557 * the last 4 bytes is the CRC, which we don't 1558 * care about anyway. 1559 */ 1560 if (m->m_len <= ETHER_CRC_LEN) { 1561 sc->re_tail->m_len -= 1562 (ETHER_CRC_LEN - m->m_len); 1563 m_freem(m); 1564 } else { 1565 m->m_len -= ETHER_CRC_LEN; 1566 sc->re_tail->m_next = m; 1567 } 1568 m = sc->re_head; 1569 sc->re_head = sc->re_tail = NULL; 1570 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1571 } else 1572 m->m_pkthdr.len = m->m_len = 1573 (total_len - ETHER_CRC_LEN); 1574 1575 ifp->if_ipackets++; 1576 m->m_pkthdr.rcvif = ifp; 1577 1578 /* Do RX checksumming if enabled */ 1579 1580 if (ifp->if_capenable & IFCAP_RXCSUM) { 1581 1582 /* Check IP header checksum */ 1583 if (rxstat & RE_RDESC_STAT_PROTOID) 1584 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1585 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0) 1586 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1587 1588 /* Check TCP/UDP checksum */ 1589 if ((RE_TCPPKT(rxstat) && 1590 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) || 1591 (RE_UDPPKT(rxstat) && 1592 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) { 1593 m->m_pkthdr.csum_flags |= 1594 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 1595 CSUM_FRAG_NOT_CHECKED; 1596 m->m_pkthdr.csum_data = 0xffff; 1597 } 1598 } 1599 1600 if (rxvlan & RE_RDESC_VLANCTL_TAG) { 1601 VLAN_INPUT_TAG(m, 1602 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA))); 1603 } else { 1604 ifp->if_input(ifp, m); 1605 } 1606 } 1607 1608 /* Flush the RX DMA ring */ 1609 1610 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, 1611 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE); 1612 1613 sc->re_ldata.re_rx_prodidx = i; 1614 } 1615 1616 static void 1617 re_txeof(struct re_softc *sc) 1618 { 1619 struct ifnet *ifp = &sc->arpcom.ac_if; 1620 uint32_t txstat; 1621 int idx; 1622 1623 /* Invalidate the TX descriptor list */ 1624 1625 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 1626 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_POSTREAD); 1627 1628 for (idx = sc->re_ldata.re_tx_considx; 1629 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT; RE_DESC_INC(idx)) { 1630 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat); 1631 if (txstat & RE_TDESC_CMD_OWN) 1632 break; 1633 1634 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0; 1635 1636 /* 1637 * We only stash mbufs in the last descriptor 1638 * in a fragment chain, which also happens to 1639 * be the only place where the TX status bits 1640 * are valid. 1641 */ 1642 if (txstat & RE_TDESC_CMD_EOF) { 1643 m_freem(sc->re_ldata.re_tx_mbuf[idx]); 1644 sc->re_ldata.re_tx_mbuf[idx] = NULL; 1645 bus_dmamap_unload(sc->re_ldata.re_mtag, 1646 sc->re_ldata.re_tx_dmamap[idx]); 1647 if (txstat & (RE_TDESC_STAT_EXCESSCOL| 1648 RE_TDESC_STAT_COLCNT)) 1649 ifp->if_collisions++; 1650 if (txstat & RE_TDESC_STAT_TXERRSUM) 1651 ifp->if_oerrors++; 1652 else 1653 ifp->if_opackets++; 1654 } 1655 sc->re_ldata.re_tx_free++; 1656 } 1657 1658 /* No changes made to the TX ring, so no flush needed */ 1659 if (sc->re_ldata.re_tx_free) { 1660 sc->re_ldata.re_tx_considx = idx; 1661 ifp->if_flags &= ~IFF_OACTIVE; 1662 ifp->if_timer = 0; 1663 } 1664 1665 /* 1666 * Some chips will ignore a second TX request issued while an 1667 * existing transmission is in progress. If the transmitter goes 1668 * idle but there are still packets waiting to be sent, we need 1669 * to restart the channel here to flush them out. This only seems 1670 * to be required with the PCIe devices. 1671 */ 1672 if (sc->re_ldata.re_tx_free < RE_TX_DESC_CNT) 1673 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 1674 1675 /* 1676 * If not all descriptors have been released reaped yet, 1677 * reload the timer so that we will eventually get another 1678 * interrupt that will cause us to re-enter this routine. 1679 * This is done in case the transmitter has gone idle. 1680 */ 1681 if (RE_TX_MODERATION_IS_ENABLED(sc) && 1682 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT) 1683 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 1684 } 1685 1686 static void 1687 re_tick(void *xsc) 1688 { 1689 struct re_softc *sc = xsc; 1690 1691 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1692 re_tick_serialized(xsc); 1693 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1694 } 1695 1696 static void 1697 re_tick_serialized(void *xsc) 1698 { 1699 struct re_softc *sc = xsc; 1700 struct ifnet *ifp = &sc->arpcom.ac_if; 1701 struct mii_data *mii; 1702 1703 mii = device_get_softc(sc->re_miibus); 1704 mii_tick(mii); 1705 if (sc->re_link) { 1706 if (!(mii->mii_media_status & IFM_ACTIVE)) 1707 sc->re_link = 0; 1708 } else { 1709 if (mii->mii_media_status & IFM_ACTIVE && 1710 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1711 sc->re_link = 1; 1712 if (!ifq_is_empty(&ifp->if_snd)) 1713 ifp->if_start(ifp); 1714 } 1715 } 1716 1717 callout_reset(&sc->re_timer, hz, re_tick, sc); 1718 } 1719 1720 #ifdef DEVICE_POLLING 1721 1722 static void 1723 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1724 { 1725 struct re_softc *sc = ifp->if_softc; 1726 1727 switch(cmd) { 1728 case POLL_REGISTER: 1729 /* disable interrupts */ 1730 CSR_WRITE_2(sc, RE_IMR, 0x0000); 1731 break; 1732 case POLL_DEREGISTER: 1733 /* enable interrupts */ 1734 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 1735 break; 1736 default: 1737 sc->rxcycles = count; 1738 re_rxeof(sc); 1739 re_txeof(sc); 1740 1741 if (!ifq_is_empty(&ifp->if_snd)) 1742 (*ifp->if_start)(ifp); 1743 1744 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1745 uint16_t status; 1746 1747 status = CSR_READ_2(sc, RE_ISR); 1748 if (status == 0xffff) 1749 return; 1750 if (status) 1751 CSR_WRITE_2(sc, RE_ISR, status); 1752 1753 /* 1754 * XXX check behaviour on receiver stalls. 1755 */ 1756 1757 if (status & RE_ISR_SYSTEM_ERR) { 1758 re_reset(sc); 1759 re_init(sc); 1760 } 1761 } 1762 break; 1763 } 1764 } 1765 #endif /* DEVICE_POLLING */ 1766 1767 static void 1768 re_intr(void *arg) 1769 { 1770 struct re_softc *sc = arg; 1771 struct ifnet *ifp = &sc->arpcom.ac_if; 1772 uint16_t status; 1773 1774 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0) 1775 return; 1776 1777 for (;;) { 1778 status = CSR_READ_2(sc, RE_ISR); 1779 /* If the card has gone away the read returns 0xffff. */ 1780 if (status == 0xffff) 1781 break; 1782 if (status) 1783 CSR_WRITE_2(sc, RE_ISR, status); 1784 1785 if ((status & sc->re_intrs) == 0) 1786 break; 1787 1788 if (status & (RE_ISR_RX_OK | RE_ISR_RX_ERR | RE_ISR_FIFO_OFLOW)) 1789 re_rxeof(sc); 1790 1791 if ((status & sc->re_tx_ack) || 1792 (status & RE_ISR_TX_ERR) || 1793 (status & RE_ISR_TX_DESC_UNAVAIL)) 1794 re_txeof(sc); 1795 1796 if (status & RE_ISR_SYSTEM_ERR) { 1797 re_reset(sc); 1798 re_init(sc); 1799 } 1800 1801 if (status & RE_ISR_LINKCHG) { 1802 callout_stop(&sc->re_timer); 1803 re_tick_serialized(sc); 1804 } 1805 } 1806 1807 if (!ifq_is_empty(&ifp->if_snd)) 1808 (*ifp->if_start)(ifp); 1809 } 1810 1811 static int 1812 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx, int *called_defrag) 1813 { 1814 struct ifnet *ifp = &sc->arpcom.ac_if; 1815 struct mbuf *m, *m_new = NULL; 1816 struct re_dmaload_arg arg; 1817 bus_dmamap_t map; 1818 int error; 1819 1820 *called_defrag = 0; 1821 if (sc->re_ldata.re_tx_free <= 4) 1822 return(EFBIG); 1823 1824 m = *m_head; 1825 1826 /* 1827 * Set up checksum offload. Note: checksum offload bits must 1828 * appear in all descriptors of a multi-descriptor transmit 1829 * attempt. (This is according to testing done with an 8169 1830 * chip. I'm not sure if this is a requirement or a bug.) 1831 */ 1832 1833 arg.re_flags = 0; 1834 1835 if (m->m_pkthdr.csum_flags & CSUM_IP) 1836 arg.re_flags |= RE_TDESC_CMD_IPCSUM; 1837 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1838 arg.re_flags |= RE_TDESC_CMD_TCPCSUM; 1839 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1840 arg.re_flags |= RE_TDESC_CMD_UDPCSUM; 1841 1842 arg.sc = sc; 1843 arg.re_idx = *idx; 1844 arg.re_maxsegs = sc->re_ldata.re_tx_free; 1845 if (arg.re_maxsegs > 4) 1846 arg.re_maxsegs -= 4; 1847 arg.re_ring = sc->re_ldata.re_tx_list; 1848 1849 map = sc->re_ldata.re_tx_dmamap[*idx]; 1850 1851 /* 1852 * With some of the RealTek chips, using the checksum offload 1853 * support in conjunction with the autopadding feature results 1854 * in the transmission of corrupt frames. For example, if we 1855 * need to send a really small IP fragment that's less than 60 1856 * bytes in size, and IP header checksumming is enabled, the 1857 * resulting ethernet frame that appears on the wire will 1858 * have garbled payload. To work around this, if TX checksum 1859 * offload is enabled, we always manually pad short frames out 1860 * to the minimum ethernet frame size. We do this by pretending 1861 * the mbuf chain has too many fragments so the coalescing code 1862 * below can assemble the packet into a single buffer that's 1863 * padded out to the mininum frame size. 1864 * 1865 * Note: this appears unnecessary for TCP, and doing it for TCP 1866 * with PCIe adapters seems to result in bad checksums. 1867 */ 1868 if (arg.re_flags && !(arg.re_flags & RE_TDESC_CMD_TCPCSUM) && 1869 m->m_pkthdr.len < RE_MIN_FRAMELEN) { 1870 error = EFBIG; 1871 } else { 1872 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, 1873 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1874 } 1875 1876 if (error && error != EFBIG) { 1877 if_printf(ifp, "can't map mbuf (error %d)\n", error); 1878 return(ENOBUFS); 1879 } 1880 1881 /* Too many segments to map, coalesce into a single mbuf */ 1882 1883 if (error || arg.re_maxsegs == 0) { 1884 m_new = m_defrag_nofree(m, MB_DONTWAIT); 1885 if (m_new == NULL) { 1886 return(1); 1887 } else { 1888 m = m_new; 1889 *m_head = m; 1890 } 1891 1892 /* 1893 * Manually pad short frames, and zero the pad space 1894 * to avoid leaking data. 1895 */ 1896 if (m_new->m_pkthdr.len < RE_MIN_FRAMELEN) { 1897 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, 1898 RE_MIN_FRAMELEN - m_new->m_pkthdr.len); 1899 m_new->m_pkthdr.len += RE_MIN_FRAMELEN - 1900 m_new->m_pkthdr.len; 1901 m_new->m_len = m_new->m_pkthdr.len; 1902 } 1903 1904 *called_defrag = 1; 1905 arg.sc = sc; 1906 arg.re_idx = *idx; 1907 arg.re_maxsegs = sc->re_ldata.re_tx_free; 1908 arg.re_ring = sc->re_ldata.re_tx_list; 1909 1910 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, 1911 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1912 if (error) { 1913 m_freem(m); 1914 if_printf(ifp, "can't map mbuf (error %d)\n", error); 1915 return(EFBIG); 1916 } 1917 } 1918 1919 /* 1920 * Insure that the map for this transmission 1921 * is placed at the array index of the last descriptor 1922 * in this chain. 1923 */ 1924 sc->re_ldata.re_tx_dmamap[*idx] = 1925 sc->re_ldata.re_tx_dmamap[arg.re_idx]; 1926 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map; 1927 1928 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m; 1929 sc->re_ldata.re_tx_free -= arg.re_maxsegs; 1930 1931 /* 1932 * Set up hardware VLAN tagging. Note: vlan tag info must 1933 * appear in the first descriptor of a multi-descriptor 1934 * transmission attempt. 1935 */ 1936 1937 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1938 m->m_pkthdr.rcvif != NULL && 1939 m->m_pkthdr.rcvif->if_type == IFT_L2VLAN) { 1940 struct ifvlan *ifv; 1941 ifv = m->m_pkthdr.rcvif->if_softc; 1942 if (ifv != NULL) 1943 sc->re_ldata.re_tx_list[*idx].re_vlanctl = 1944 htole32(htobe16(ifv->ifv_tag) | RE_TDESC_VLANCTL_TAG); 1945 } 1946 1947 /* Transfer ownership of packet to the chip. */ 1948 1949 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |= 1950 htole32(RE_TDESC_CMD_OWN); 1951 if (*idx != arg.re_idx) 1952 sc->re_ldata.re_tx_list[*idx].re_cmdstat |= 1953 htole32(RE_TDESC_CMD_OWN); 1954 1955 RE_DESC_INC(arg.re_idx); 1956 *idx = arg.re_idx; 1957 1958 return(0); 1959 } 1960 1961 /* 1962 * Main transmit routine for C+ and gigE NICs. 1963 */ 1964 1965 static void 1966 re_start(struct ifnet *ifp) 1967 { 1968 struct re_softc *sc = ifp->if_softc; 1969 struct mbuf *m_head; 1970 struct mbuf *m_head2; 1971 int called_defrag, idx, need_trans; 1972 1973 if (!sc->re_link || (ifp->if_flags & IFF_OACTIVE)) 1974 return; 1975 1976 idx = sc->re_ldata.re_tx_prodidx; 1977 1978 need_trans = 0; 1979 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) { 1980 m_head = ifq_poll(&ifp->if_snd); 1981 if (m_head == NULL) 1982 break; 1983 m_head2 = m_head; 1984 if (re_encap(sc, &m_head2, &idx, &called_defrag)) { 1985 /* 1986 * If we could not encapsulate the defragged packet, 1987 * the returned m_head2 is garbage and we must dequeue 1988 * and throw away the original packet. 1989 */ 1990 if (called_defrag) { 1991 ifq_dequeue(&ifp->if_snd, m_head); 1992 m_freem(m_head); 1993 } 1994 ifp->if_flags |= IFF_OACTIVE; 1995 break; 1996 } 1997 1998 /* 1999 * Clean out the packet we encapsulated. If we defragged 2000 * the packet the m_head2 is the one that got encapsulated 2001 * and the original must be thrown away. Otherwise m_head2 2002 * *IS* the original. 2003 */ 2004 ifq_dequeue(&ifp->if_snd, m_head); 2005 if (called_defrag) 2006 m_freem(m_head); 2007 need_trans = 1; 2008 2009 /* 2010 * If there's a BPF listener, bounce a copy of this frame 2011 * to him. 2012 */ 2013 BPF_MTAP(ifp, m_head2); 2014 } 2015 2016 if (!need_trans) { 2017 if (RE_TX_MODERATION_IS_ENABLED(sc) && 2018 sc->re_ldata.re_tx_free != RE_TX_DESC_CNT) 2019 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 2020 return; 2021 } 2022 2023 /* Flush the TX descriptors */ 2024 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, 2025 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE); 2026 2027 sc->re_ldata.re_tx_prodidx = idx; 2028 2029 /* 2030 * RealTek put the TX poll request register in a different 2031 * location on the 8169 gigE chip. I don't know why. 2032 */ 2033 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2034 2035 if (RE_TX_MODERATION_IS_ENABLED(sc)) { 2036 /* 2037 * Use the countdown timer for interrupt moderation. 2038 * 'TX done' interrupts are disabled. Instead, we reset the 2039 * countdown timer, which will begin counting until it hits 2040 * the value in the TIMERINT register, and then trigger an 2041 * interrupt. Each time we write to the TIMERCNT register, 2042 * the timer count is reset to 0. 2043 */ 2044 CSR_WRITE_4(sc, RE_TIMERCNT, 1); 2045 } 2046 2047 /* 2048 * Set a timeout in case the chip goes out to lunch. 2049 */ 2050 ifp->if_timer = 5; 2051 } 2052 2053 static void 2054 re_init(void *xsc) 2055 { 2056 struct re_softc *sc = xsc; 2057 struct ifnet *ifp = &sc->arpcom.ac_if; 2058 struct mii_data *mii; 2059 uint32_t rxcfg = 0; 2060 2061 mii = device_get_softc(sc->re_miibus); 2062 2063 /* 2064 * Cancel pending I/O and free all RX/TX buffers. 2065 */ 2066 re_stop(sc); 2067 2068 /* 2069 * Enable C+ RX and TX mode, as well as VLAN stripping and 2070 * RX checksum offload. We must configure the C+ register 2071 * before all others. 2072 */ 2073 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB | 2074 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP | 2075 (ifp->if_capenable & IFCAP_RXCSUM ? 2076 RE_CPLUSCMD_RXCSUM_ENB : 0)); 2077 2078 /* 2079 * Init our MAC address. Even though the chipset 2080 * documentation doesn't mention it, we need to enter "Config 2081 * register write enable" mode to modify the ID registers. 2082 */ 2083 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG); 2084 CSR_WRITE_4(sc, RE_IDR0, 2085 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0]))); 2086 CSR_WRITE_2(sc, RE_IDR4, 2087 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4]))); 2088 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 2089 2090 /* 2091 * For C+ mode, initialize the RX descriptors and mbufs. 2092 */ 2093 re_rx_list_init(sc); 2094 re_tx_list_init(sc); 2095 2096 /* 2097 * Load the addresses of the RX and TX lists into the chip. 2098 */ 2099 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI, 2100 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr)); 2101 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO, 2102 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr)); 2103 2104 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI, 2105 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr)); 2106 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO, 2107 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr)); 2108 2109 /* 2110 * Enable transmit and receive. 2111 */ 2112 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2113 2114 /* 2115 * Set the initial TX and RX configuration. 2116 */ 2117 if (sc->re_testmode) { 2118 if (sc->re_type == RE_8169) 2119 CSR_WRITE_4(sc, RE_TXCFG, 2120 RE_TXCFG_CONFIG | RE_LOOPTEST_ON); 2121 else 2122 CSR_WRITE_4(sc, RE_TXCFG, 2123 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS); 2124 } else 2125 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG); 2126 2127 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16); 2128 2129 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG); 2130 2131 /* Set the individual bit to receive frames for this host only. */ 2132 rxcfg = CSR_READ_4(sc, RE_RXCFG); 2133 rxcfg |= RE_RXCFG_RX_INDIV; 2134 2135 /* If we want promiscuous mode, set the allframes bit. */ 2136 if (ifp->if_flags & IFF_PROMISC) { 2137 rxcfg |= RE_RXCFG_RX_ALLPHYS; 2138 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 2139 } else { 2140 rxcfg &= ~RE_RXCFG_RX_ALLPHYS; 2141 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 2142 } 2143 2144 /* 2145 * Set capture broadcast bit to capture broadcast frames. 2146 */ 2147 if (ifp->if_flags & IFF_BROADCAST) { 2148 rxcfg |= RE_RXCFG_RX_BROAD; 2149 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 2150 } else { 2151 rxcfg &= ~RE_RXCFG_RX_BROAD; 2152 CSR_WRITE_4(sc, RE_RXCFG, rxcfg); 2153 } 2154 2155 /* 2156 * Program the multicast filter, if necessary. 2157 */ 2158 re_setmulti(sc); 2159 2160 #ifdef DEVICE_POLLING 2161 /* 2162 * Disable interrupts if we are polling. 2163 */ 2164 if (ifp->if_flags & IFF_POLLING) 2165 CSR_WRITE_2(sc, RE_IMR, 0); 2166 else /* otherwise ... */ 2167 #endif /* DEVICE_POLLING */ 2168 /* 2169 * Enable interrupts. 2170 */ 2171 if (sc->re_testmode) 2172 CSR_WRITE_2(sc, RE_IMR, 0); 2173 else 2174 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 2175 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs); 2176 2177 /* Set initial TX threshold */ 2178 sc->re_txthresh = RE_TX_THRESH_INIT; 2179 2180 /* Start RX/TX process. */ 2181 if (sc->re_flags & RE_F_HASMPC) 2182 CSR_WRITE_4(sc, RE_MISSEDPKT, 0); 2183 #ifdef notdef 2184 /* Enable receiver and transmitter. */ 2185 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2186 #endif 2187 2188 if (RE_TX_MODERATION_IS_ENABLED(sc)) { 2189 /* 2190 * Initialize the timer interrupt register so that 2191 * a timer interrupt will be generated once the timer 2192 * reaches a certain number of ticks. The timer is 2193 * reloaded on each transmit. This gives us TX interrupt 2194 * moderation, which dramatically improves TX frame rate. 2195 */ 2196 if (sc->re_type == RE_8169) 2197 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800); 2198 else 2199 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); 2200 } 2201 2202 /* 2203 * For 8169 gigE NICs, set the max allowed RX packet 2204 * size so we can receive jumbo frames. 2205 */ 2206 if (sc->re_type == RE_8169) 2207 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383); 2208 2209 if (sc->re_testmode) { 2210 return; 2211 } 2212 2213 mii_mediachg(mii); 2214 2215 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX); 2216 2217 ifp->if_flags |= IFF_RUNNING; 2218 ifp->if_flags &= ~IFF_OACTIVE; 2219 2220 sc->re_link = 0; 2221 callout_reset(&sc->re_timer, hz, re_tick, sc); 2222 } 2223 2224 /* 2225 * Set media options. 2226 */ 2227 static int 2228 re_ifmedia_upd(struct ifnet *ifp) 2229 { 2230 struct re_softc *sc = ifp->if_softc; 2231 struct mii_data *mii; 2232 2233 mii = device_get_softc(sc->re_miibus); 2234 mii_mediachg(mii); 2235 2236 return(0); 2237 } 2238 2239 /* 2240 * Report current media status. 2241 */ 2242 static void 2243 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2244 { 2245 struct re_softc *sc = ifp->if_softc; 2246 struct mii_data *mii; 2247 2248 mii = device_get_softc(sc->re_miibus); 2249 2250 mii_pollstat(mii); 2251 ifmr->ifm_active = mii->mii_media_active; 2252 ifmr->ifm_status = mii->mii_media_status; 2253 } 2254 2255 static int 2256 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2257 { 2258 struct re_softc *sc = ifp->if_softc; 2259 struct ifreq *ifr = (struct ifreq *) data; 2260 struct mii_data *mii; 2261 int error = 0; 2262 2263 switch(command) { 2264 case SIOCSIFMTU: 2265 if (ifr->ifr_mtu > RE_JUMBO_MTU) 2266 error = EINVAL; 2267 ifp->if_mtu = ifr->ifr_mtu; 2268 break; 2269 case SIOCSIFFLAGS: 2270 if (ifp->if_flags & IFF_UP) 2271 re_init(sc); 2272 else if (ifp->if_flags & IFF_RUNNING) 2273 re_stop(sc); 2274 break; 2275 case SIOCADDMULTI: 2276 case SIOCDELMULTI: 2277 re_setmulti(sc); 2278 error = 0; 2279 break; 2280 case SIOCGIFMEDIA: 2281 case SIOCSIFMEDIA: 2282 mii = device_get_softc(sc->re_miibus); 2283 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2284 break; 2285 case SIOCSIFCAP: 2286 ifp->if_capenable &= ~(IFCAP_HWCSUM); 2287 ifp->if_capenable |= 2288 ifr->ifr_reqcap & (IFCAP_HWCSUM); 2289 if (ifp->if_capenable & IFCAP_TXCSUM) 2290 ifp->if_hwassist = RE_CSUM_FEATURES; 2291 else 2292 ifp->if_hwassist = 0; 2293 if (ifp->if_flags & IFF_RUNNING) 2294 re_init(sc); 2295 break; 2296 default: 2297 error = ether_ioctl(ifp, command, data); 2298 break; 2299 } 2300 return(error); 2301 } 2302 2303 static void 2304 re_watchdog(struct ifnet *ifp) 2305 { 2306 struct re_softc *sc = ifp->if_softc; 2307 2308 if_printf(ifp, "watchdog timeout\n"); 2309 2310 ifp->if_oerrors++; 2311 2312 re_txeof(sc); 2313 re_rxeof(sc); 2314 2315 re_init(sc); 2316 2317 if (!ifq_is_empty(&ifp->if_snd)) 2318 ifp->if_start(ifp); 2319 } 2320 2321 /* 2322 * Stop the adapter and free any mbufs allocated to the 2323 * RX and TX lists. 2324 */ 2325 static void 2326 re_stop(struct re_softc *sc) 2327 { 2328 struct ifnet *ifp = &sc->arpcom.ac_if; 2329 int i; 2330 2331 ifp->if_timer = 0; 2332 callout_stop(&sc->re_timer); 2333 2334 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2335 2336 CSR_WRITE_1(sc, RE_COMMAND, 0x00); 2337 CSR_WRITE_2(sc, RE_IMR, 0x0000); 2338 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 2339 2340 if (sc->re_head != NULL) { 2341 m_freem(sc->re_head); 2342 sc->re_head = sc->re_tail = NULL; 2343 } 2344 2345 /* Free the TX list buffers. */ 2346 for (i = 0; i < RE_TX_DESC_CNT; i++) { 2347 if (sc->re_ldata.re_tx_mbuf[i] != NULL) { 2348 bus_dmamap_unload(sc->re_ldata.re_mtag, 2349 sc->re_ldata.re_tx_dmamap[i]); 2350 m_freem(sc->re_ldata.re_tx_mbuf[i]); 2351 sc->re_ldata.re_tx_mbuf[i] = NULL; 2352 } 2353 } 2354 2355 /* Free the RX list buffers. */ 2356 for (i = 0; i < RE_RX_DESC_CNT; i++) { 2357 if (sc->re_ldata.re_rx_mbuf[i] != NULL) { 2358 bus_dmamap_unload(sc->re_ldata.re_mtag, 2359 sc->re_ldata.re_rx_dmamap[i]); 2360 m_freem(sc->re_ldata.re_rx_mbuf[i]); 2361 sc->re_ldata.re_rx_mbuf[i] = NULL; 2362 } 2363 } 2364 } 2365 2366 /* 2367 * Device suspend routine. Stop the interface and save some PCI 2368 * settings in case the BIOS doesn't restore them properly on 2369 * resume. 2370 */ 2371 static int 2372 re_suspend(device_t dev) 2373 { 2374 #ifndef BURN_BRIDGES 2375 int i; 2376 #endif 2377 struct re_softc *sc = device_get_softc(dev); 2378 2379 re_stop(sc); 2380 2381 #ifndef BURN_BRIDGES 2382 for (i = 0; i < 5; i++) 2383 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2384 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2385 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2386 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2387 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2388 #endif 2389 2390 sc->suspended = 1; 2391 2392 return (0); 2393 } 2394 2395 /* 2396 * Device resume routine. Restore some PCI settings in case the BIOS 2397 * doesn't, re-enable busmastering, and restart the interface if 2398 * appropriate. 2399 */ 2400 static int 2401 re_resume(device_t dev) 2402 { 2403 struct re_softc *sc = device_get_softc(dev); 2404 struct ifnet *ifp = &sc->arpcom.ac_if; 2405 #ifndef BURN_BRIDGES 2406 int i; 2407 #endif 2408 2409 #ifndef BURN_BRIDGES 2410 /* better way to do this? */ 2411 for (i = 0; i < 5; i++) 2412 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2413 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2414 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2415 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2416 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2417 2418 /* reenable busmastering */ 2419 pci_enable_busmaster(dev); 2420 pci_enable_io(dev, SYS_RES_IOPORT); 2421 #endif 2422 2423 /* reinitialize interface if necessary */ 2424 if (ifp->if_flags & IFF_UP) 2425 re_init(sc); 2426 2427 sc->suspended = 0; 2428 2429 return (0); 2430 } 2431 2432 /* 2433 * Stop all chip I/O so that the kernel's probe routines don't 2434 * get confused by errant DMAs when rebooting. 2435 */ 2436 static void 2437 re_shutdown(device_t dev) 2438 { 2439 struct re_softc *sc = device_get_softc(dev); 2440 struct ifnet *ifp = &sc->arpcom.ac_if; 2441 2442 lwkt_serialize_enter(ifp->if_serializer); 2443 re_stop(sc); 2444 lwkt_serialize_exit(ifp->if_serializer); 2445 } 2446 2447 static int 2448 re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS) 2449 { 2450 struct re_softc *sc = arg1; 2451 struct ifnet *ifp = &sc->arpcom.ac_if; 2452 int error = 0, mod, mod_old; 2453 2454 lwkt_serialize_enter(ifp->if_serializer); 2455 2456 mod_old = mod = RE_TX_MODERATION_IS_ENABLED(sc); 2457 2458 error = sysctl_handle_int(oidp, &mod, 0, req); 2459 if (error || req->newptr == NULL || mod == mod_old) 2460 goto back; 2461 if (mod != 0 && mod != 1) { 2462 error = EINVAL; 2463 goto back; 2464 } 2465 2466 if (mod) 2467 RE_ENABLE_TX_MODERATION(sc); 2468 else 2469 RE_DISABLE_TX_MODERATION(sc); 2470 2471 if ((ifp->if_flags & (IFF_RUNNING | IFF_UP)) == (IFF_RUNNING | IFF_UP)) 2472 re_init(sc); 2473 back: 2474 lwkt_serialize_exit(ifp->if_serializer); 2475 return error; 2476 } 2477