1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.42 2004/05/24 19:39:23 jhb Exp $ 36 */ 37 38 #define RE_RX_DESC_CNT_8139CP 64 39 #define RE_TX_DESC_CNT_8139CP 64 40 41 #define RE_RX_DESC_CNT_DEF 256 42 #define RE_TX_DESC_CNT_DEF 256 43 #define RE_RX_DESC_CNT_MAX 1024 44 #define RE_TX_DESC_CNT_MAX 1024 45 46 #define RE_RX_LIST_SZ(sc) ((sc)->re_rx_desc_cnt * sizeof(struct re_desc)) 47 #define RE_TX_LIST_SZ(sc) ((sc)->re_tx_desc_cnt * sizeof(struct re_desc)) 48 #define RE_RING_ALIGN 256 49 #define RE_IFQ_MAXLEN 512 50 #define RE_MAXSEGS 16 51 #define RE_TXDESC_SPARE 5 52 #define RE_JBUF_COUNT(sc) (((sc)->re_rx_desc_cnt * 3) / 2) 53 54 #define RE_RXDESC_INC(sc, x) (x = (x + 1) % (sc)->re_rx_desc_cnt) 55 #define RE_TXDESC_INC(sc, x) (x = (x + 1) % (sc)->re_tx_desc_cnt) 56 #define RE_OWN(x) (le32toh((x)->re_cmdstat) & RE_RDESC_STAT_OWN) 57 #define RE_RXBYTES(x) (le32toh((x)->re_cmdstat) & sc->re_rxlenmask) 58 #define RE_PKTSZ(x) ((x)/* >> 3*/) 59 60 #define RE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 61 #define RE_ADDR_HI(y) ((uint64_t) (y) >> 32) 62 63 #define RE_MTU_6K (6 * 1024) 64 #define RE_MTU_9K (9 * 1024) 65 66 #define RE_ETHER_EXTRA (ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN) 67 #define RE_FRAMELEN(mtu) ((mtu) + RE_ETHER_EXTRA) 68 69 #define RE_FRAMELEN_6K RE_FRAMELEN(RE_MTU_6K) 70 #define RE_FRAMELEN_9K RE_FRAMELEN(RE_MTU_9K) 71 #define RE_FRAMELEN_MAX RE_FRAMELEN_9K 72 73 #define RE_RXBUF_ALIGN 8 74 #define RE_JBUF_SIZE roundup2(RE_FRAMELEN_MAX, RE_RXBUF_ALIGN) 75 76 #define RE_TIMEOUT 1000 77 #define RE_PHY_TIMEOUT 2000 78 79 struct re_hwrev { 80 uint32_t re_hwrev; 81 int re_maxmtu; 82 uint32_t re_caps; /* see RE_C_ */ 83 }; 84 85 struct re_softc; 86 struct re_jbuf { 87 struct re_softc *re_sc; 88 int re_inuse; 89 int re_slot; 90 caddr_t re_buf; 91 bus_addr_t re_paddr; 92 SLIST_ENTRY(re_jbuf) re_link; 93 }; 94 95 struct re_list_data { 96 struct mbuf **re_tx_mbuf; 97 struct mbuf **re_rx_mbuf; 98 bus_addr_t *re_rx_paddr; 99 int re_tx_prodidx; 100 int re_rx_prodidx; 101 int re_tx_considx; 102 int re_tx_free; 103 bus_dmamap_t *re_tx_dmamap; 104 bus_dmamap_t *re_rx_dmamap; 105 bus_dmamap_t re_rx_spare; 106 bus_dma_tag_t re_rx_mtag; /* RX mbuf mapping tag */ 107 bus_dma_tag_t re_tx_mtag; /* TX mbuf mapping tag */ 108 bus_dma_tag_t re_stag; /* stats mapping tag */ 109 bus_dmamap_t re_smap; /* stats map */ 110 struct re_stats *re_stats; 111 bus_addr_t re_stats_addr; 112 bus_dma_tag_t re_rx_list_tag; 113 bus_dmamap_t re_rx_list_map; 114 struct re_desc *re_rx_list; 115 bus_addr_t re_rx_list_addr; 116 bus_dma_tag_t re_tx_list_tag; 117 bus_dmamap_t re_tx_list_map; 118 struct re_desc *re_tx_list; 119 bus_addr_t re_tx_list_addr; 120 121 bus_dma_tag_t re_jpool_tag; 122 bus_dmamap_t re_jpool_map; 123 caddr_t re_jpool; 124 struct re_jbuf *re_jbuf; 125 struct lwkt_serialize re_jbuf_serializer; 126 SLIST_HEAD(, re_jbuf) re_jbuf_free; 127 }; 128 129 struct re_softc { 130 struct arpcom arpcom; /* interface info */ 131 device_t re_dev; 132 bus_space_handle_t re_bhandle; /* bus space handle */ 133 bus_space_tag_t re_btag; /* bus space tag */ 134 int re_res_rid; 135 int re_res_type; 136 struct resource *re_res; 137 struct resource *re_irq; 138 void *re_intrhand; 139 device_t re_miibus; 140 bus_dma_tag_t re_parent_tag; 141 bus_dma_tag_t re_tag; 142 uint32_t re_hwrev; 143 struct ifpoll_compat re_npoll; 144 struct re_list_data re_ldata; 145 struct callout re_timer; 146 struct mbuf *re_head; 147 struct mbuf *re_tail; 148 uint32_t re_caps; /* see RE_C_ */ 149 uint32_t re_rxlenmask; 150 int re_txstart; 151 int re_eewidth; 152 int re_ee_eaddr; 153 int re_maxmtu; 154 int re_rx_desc_cnt; 155 int re_tx_desc_cnt; 156 int re_bus_speed; 157 int rxcycles; 158 int re_rxbuf_size; 159 int (*re_newbuf)(struct re_softc *, int, int); 160 int re_irq_type; 161 int re_irq_rid; 162 163 uint32_t re_flags; /* see RE_F_ */ 164 int re_if_flags; /* saved ifnet.if_flags */ 165 166 u_long re_hwassist; 167 uint16_t re_intrs; 168 uint16_t re_tx_ack; 169 uint16_t re_rx_ack; 170 int re_tx_time; 171 int re_rx_time; 172 int re_sim_time; 173 int re_imtype; /* see RE_IMTYPE_ */ 174 175 uint32_t saved_maps[5]; /* pci data */ 176 uint32_t saved_biosaddr; 177 uint8_t saved_intline; 178 uint8_t saved_cachelnsz; 179 uint8_t saved_lattimer; 180 }; 181 182 #define RE_C_PCIE 0x1 /* PCI-E */ 183 #define RE_C_PCI64 0x2 /* PCI64 */ 184 #define RE_C_HWIM 0x4 /* hardware interrupt moderation */ 185 #define RE_C_HWCSUM 0x8 /* hardware csum offload */ 186 #define RE_C_PHYPMCH 0x10 /* XXX PHY needs power change? */ 187 #define RE_C_8139CP 0x20 /* is 8139C+ */ 188 #define RE_C_MAC2 0x40 /* MAC style 2 */ 189 #define RE_C_PHYPMGT 0x80 /* PHY supports power mgmt */ 190 #define RE_C_8169 0x100 /* is 8110/8169 */ 191 #define RE_C_AUTOPAD 0x200 /* hardware auto-pad short frames */ 192 #define RE_C_CONTIGRX 0x400 /* need contig buf to RX jumbo frames */ 193 #define RE_C_STOP_RXTX 0x800 /* could stop RX/TX engine */ 194 #define RE_C_FASTE 0x1000 /* 10/100 only NIC */ 195 #define RE_C_EE_EADDR 0x2000 /* ethernet address in EEPROM */ 196 197 #define RE_IS_8139CP(sc) ((sc)->re_caps & RE_C_8139CP) 198 #define RE_IS_8169(sc) ((sc)->re_caps & RE_C_8169) 199 200 /* Interrupt moderation types */ 201 #define RE_IMTYPE_NONE 0 202 #define RE_IMTYPE_SIM 1 /* simulated */ 203 #define RE_IMTYPE_HW 2 /* hardware based */ 204 205 #define RE_F_TIMER_INTR 0x1 206 #define RE_F_USE_JPOOL 0x2 207 #define RE_F_DROP_RXFRAG 0x4 208 #define RE_F_LINKED 0x8 209 #define RE_F_SUSPENDED 0x10 210 #define RE_F_TESTMODE 0x20 211 212 /* 213 * register space access macros 214 */ 215 #define CSR_WRITE_STREAM_4(sc, reg, val) \ 216 bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val) 217 #define CSR_WRITE_4(sc, reg, val) \ 218 bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val) 219 #define CSR_WRITE_2(sc, reg, val) \ 220 bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val) 221 #define CSR_WRITE_1(sc, reg, val) \ 222 bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val) 223 224 #define CSR_READ_4(sc, reg) \ 225 bus_space_read_4(sc->re_btag, sc->re_bhandle, reg) 226 #define CSR_READ_2(sc, reg) \ 227 bus_space_read_2(sc->re_btag, sc->re_bhandle, reg) 228 #define CSR_READ_1(sc, reg) \ 229 bus_space_read_1(sc->re_btag, sc->re_bhandle, reg) 230 231 #define CSR_SETBIT_1(sc, reg, val) \ 232 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (val)) 233 #define CSR_CLRBIT_1(sc, reg, val) \ 234 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(val)) 235