1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.42 2004/05/24 19:39:23 jhb Exp $ 36 * $DragonFly: src/sys/dev/netif/re/if_revar.h,v 1.3 2007/01/15 12:53:26 sephe Exp $ 37 */ 38 39 struct re_chain_data { 40 uint16_t cur_rx; 41 caddr_t re_rx_buf; 42 caddr_t re_rx_buf_ptr; 43 bus_dmamap_t re_rx_dmamap; 44 45 struct mbuf *re_tx_chain[RE_TX_LIST_CNT]; 46 bus_dmamap_t re_tx_dmamap[RE_TX_LIST_CNT]; 47 uint8_t last_tx; 48 uint8_t cur_tx; 49 }; 50 51 #define RE_INC(x) (x = (x + 1) % RE_TX_LIST_CNT) 52 #define RE_CUR_TXADDR(x) ((x->re_cdata.cur_tx * 4) + RE_TXADDR0) 53 #define RE_CUR_TXSTAT(x) ((x->re_cdata.cur_tx * 4) + RE_TXSTAT0) 54 #define RE_CUR_TXMBUF(x) (x->re_cdata.re_tx_chain[x->re_cdata.cur_tx]) 55 #define RE_CUR_DMAMAP(x) (x->re_cdata.re_tx_dmamap[x->re_cdata.cur_tx]) 56 #define RE_LAST_TXADDR(x) ((x->re_cdata.last_tx * 4) + RE_TXADDR0) 57 #define RE_LAST_TXSTAT(x) ((x->re_cdata.last_tx * 4) + RE_TXSTAT0) 58 #define RE_LAST_TXMBUF(x) (x->re_cdata.re_tx_chain[x->re_cdata.last_tx]) 59 #define RE_LAST_DMAMAP(x) (x->re_cdata.re_tx_dmamap[x->re_cdata.last_tx]) 60 61 struct re_type { 62 uint16_t re_vid; 63 uint16_t re_did; 64 int re_basetype; 65 const char *re_name; 66 }; 67 68 struct re_hwrev { 69 uint32_t re_rev; 70 int re_type; /* RE_{8139CPLUS,8169} */ 71 uint32_t re_flags; /* see RE_F_ */ 72 const char *re_desc; 73 }; 74 75 #define RE_8139CPLUS 3 76 #define RE_8169 4 77 78 struct re_softc; 79 80 struct re_dmaload_arg { 81 struct re_softc *sc; 82 int re_idx; 83 int re_maxsegs; 84 uint32_t re_flags; 85 struct re_desc *re_ring; 86 }; 87 88 struct re_list_data { 89 struct mbuf *re_tx_mbuf[RE_TX_DESC_CNT]; 90 struct mbuf *re_rx_mbuf[RE_TX_DESC_CNT]; 91 int re_tx_prodidx; 92 int re_rx_prodidx; 93 int re_tx_considx; 94 int re_tx_free; 95 bus_dmamap_t re_tx_dmamap[RE_TX_DESC_CNT]; 96 bus_dmamap_t re_rx_dmamap[RE_RX_DESC_CNT]; 97 bus_dma_tag_t re_mtag; /* mbuf mapping tag */ 98 bus_dma_tag_t re_stag; /* stats mapping tag */ 99 bus_dmamap_t re_smap; /* stats map */ 100 struct re_stats *re_stats; 101 bus_addr_t re_stats_addr; 102 bus_dma_tag_t re_rx_list_tag; 103 bus_dmamap_t re_rx_list_map; 104 struct re_desc *re_rx_list; 105 bus_addr_t re_rx_list_addr; 106 bus_dma_tag_t re_tx_list_tag; 107 bus_dmamap_t re_tx_list_map; 108 struct re_desc *re_tx_list; 109 bus_addr_t re_tx_list_addr; 110 }; 111 112 struct re_softc { 113 struct arpcom arpcom; /* interface info */ 114 #ifdef RE_DIAG 115 device_t re_dev; 116 #endif 117 bus_space_handle_t re_bhandle; /* bus space handle */ 118 bus_space_tag_t re_btag; /* bus space tag */ 119 struct resource *re_res; 120 struct resource *re_irq; 121 void *re_intrhand; 122 device_t re_miibus; 123 bus_dma_tag_t re_parent_tag; 124 bus_dma_tag_t re_tag; 125 uint8_t re_type; 126 int re_eecmd_read; 127 uint8_t re_stats_no_timeout; 128 int re_txthresh; 129 struct re_chain_data re_cdata; 130 struct re_list_data re_ldata; 131 struct callout re_timer; 132 struct mbuf *re_head; 133 struct mbuf *re_tail; 134 uint32_t re_flags; /* see RE_F_ */ 135 uint32_t re_rxlenmask; 136 int re_txstart; 137 int re_testmode; 138 int suspended; /* 0 = normal 1 = suspended */ 139 int re_link; 140 int re_eewidth; 141 #ifdef DEVICE_POLLING 142 int rxcycles; 143 #endif 144 145 struct sysctl_ctx_list re_sysctl_ctx; 146 struct sysctl_oid *re_sysctl_tree; 147 uint16_t re_intrs; 148 uint16_t re_tx_ack; 149 150 #ifndef BURN_BRIDGES 151 uint32_t saved_maps[5]; /* pci data */ 152 uint32_t saved_biosaddr; 153 uint8_t saved_intline; 154 uint8_t saved_cachelnsz; 155 uint8_t saved_lattimer; 156 #endif 157 }; 158 159 #define RE_F_HASMPC 0x1 160 #define RE_F_PCIE 0x2 161 162 #define RE_TX_MODERATION_IS_ENABLED(sc) \ 163 ((sc)->re_tx_ack == RE_ISR_TIMEOUT_EXPIRED) 164 165 #define RE_DISABLE_TX_MODERATION(sc) do { \ 166 (sc)->re_tx_ack = RE_ISR_TX_OK; \ 167 (sc)->re_intrs = RE_INTRS | RE_ISR_TX_OK; \ 168 } while (0) 169 170 #define RE_ENABLE_TX_MODERATION(sc) do { \ 171 (sc)->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED; \ 172 (sc)->re_intrs = RE_INTRS; \ 173 } while (0) 174 175 /* 176 * register space access macros 177 */ 178 #define CSR_WRITE_STREAM_4(sc, reg, val) \ 179 bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val) 180 #define CSR_WRITE_4(sc, reg, val) \ 181 bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val) 182 #define CSR_WRITE_2(sc, reg, val) \ 183 bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val) 184 #define CSR_WRITE_1(sc, reg, val) \ 185 bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val) 186 187 #define CSR_READ_4(sc, reg) \ 188 bus_space_read_4(sc->re_btag, sc->re_bhandle, reg) 189 #define CSR_READ_2(sc, reg) \ 190 bus_space_read_2(sc->re_btag, sc->re_bhandle, reg) 191 #define CSR_READ_1(sc, reg) \ 192 bus_space_read_1(sc->re_btag, sc->re_bhandle, reg) 193 194 #define CSR_SETBIT_1(sc, reg, val) \ 195 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (val)) 196 #define CSR_CLRBIT_1(sc, reg, val) \ 197 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(val)) 198