1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/dev/re/if_rereg.h,v 1.14.2.1 2001/07/19 18:33:07 wpaul Exp $ 33 */ 34 35 #ifndef __DragonFly__ 36 /*#define VERSION(_MainVer,_MinorVer) ((_MainVer)*10+(_MinorVer))*/ 37 /*#define OS_VER VERSION(5,1)*/ 38 #if __FreeBSD_version < 500000 39 #define VERSION(_MainVer,_MinorVer) ((_MainVer)*100000+(_MinorVer)*10000) 40 #else 41 #define VERSION(_MainVer,_MinorVer) ((_MainVer)*100000+(_MinorVer)*1000) 42 #endif 43 #define OS_VER __FreeBSD_version 44 45 #ifndef M_DONTWAIT 46 #define M_DONTWAIT M_NOWAIT 47 #endif 48 49 #if OS_VER>=VERSION(4,0) 50 #define RE_USE_NEW_CALLOUT_FUN 1 51 #endif 52 #endif /* !__DragonFly__ */ 53 54 55 /* 56 * RealTek RTL8110S/SB/SC register offsets 57 */ 58 59 #define RE_TPPOLL 0x0038 /* transmit priority polling */ 60 61 /* 62 * RealTek RTL8110S/SB/SC register contents 63 */ 64 65 /* Transmit Priority Polling --- 0x40 */ 66 #define RE_HPQ 0x80 /* high priority queue polling */ 67 #define RE_NPQ 0x40 /* normal priority queue polling */ 68 #define RE_FSWInt 0x01 /* Forced Software Interrupt */ 69 #define RE_NPQ_8125 0x01 70 71 72 /* 73 * RealTek 8129/8139 register offsets 74 */ 75 76 #define RE_IDR0 0x0000 /* ID register 0 (station addr) */ 77 #define RE_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 78 #define RE_IDR2 0x0002 79 #define RE_IDR3 0x0003 80 #define RE_IDR4 0x0004 81 #define RE_IDR5 0x0005 82 /* 0006-0007 reserved */ 83 #define RE_MAR0 0x0008 /* Multicast hash table */ 84 #define RE_MAR1 0x0009 85 #define RE_MAR2 0x000A 86 #define RE_MAR3 0x000B 87 #define RE_MAR4 0x000C 88 #define RE_MAR5 0x000D 89 #define RE_MAR6 0x000E 90 #define RE_MAR7 0x000F 91 92 #define RE_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 93 #define RE_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 94 #define RE_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 95 #define RE_CUSTOM_LED 0x0018 96 #define RE_TXSTAT3 0x001C /* status of TX descriptor 3 */ 97 98 #define RE_TXADDR0 0x0020 /* address of TX descriptor 0 */ 99 #define RE_TXADDR1 0x0024 /* address of TX descriptor 1 */ 100 #define RE_TXADDR2 0x0028 /* address of TX descriptor 2 */ 101 #define RE_TXADDR3 0x002C /* address of TX descriptor 3 */ 102 103 #define RE_RXADDR 0x0030 /* RX ring start address */ 104 #define RE_COMMAND 0x0037 /* command register */ 105 #define RE_CURRXADDR 0x0038 /* current address of packet read */ 106 #define RE_CURRXBUF 0x003A /* current RX buffer address */ 107 #define RE_IMR 0x003C /* interrupt mask register */ 108 #define RE_ISR 0x003E /* interrupt status register */ 109 #define RE_TXCFG 0x0040 /* transmit config */ 110 #define RE_RXCFG 0x0044 /* receive config */ 111 #define RE_TIMERCNT 0x0048 /* timer count register */ 112 #define RE_MISSEDPKT 0x004C /* missed packet counter */ 113 #define RE_EECMD 0x0050 /* EEPROM command register */ 114 #define RE_CFG0 0x0051 /* config register #0 */ 115 #define RE_CFG1 0x0052 /* config register #1 */ 116 #define RE_CFG2 0x0053 /* config register #2 */ 117 #define RE_CFG3 0x0054 /* config register #3 */ 118 #define RE_CFG4 0x0055 /* config register #4 */ 119 #define RE_CFG5 0x0056 /* config register #5 */ 120 /* 0053-0057 reserved */ 121 #define RE_TDFNR 0x0057 /* Tx descriptor fetch number */ 122 #define RE_MEDIASTAT 0x0058 /* media status register (8139) */ 123 #define RE_TIMERINT 0x0058 /* timer interrupt register */ 124 /* 0059-005A reserved */ 125 #define RE_MII 0x005A /* 8129 chip only */ 126 #define RE_HALTCLK 0x005B 127 #define RE_MULTIINTR 0x005C /* multiple interrupt */ 128 #define RE_PCIREV 0x005E /* PCI revision value */ 129 /* 005F reserved */ 130 #define RE_PHYAR 0x0060 /* PHY register access */ 131 #define RE_CSIDR 0x0064 132 #define RE_CSIAR 0x0068 133 #define RE_PHY_STATUS 0x006C /* PHY status */ 134 #define RE_MACDBG 0x006D 135 #define RE_PMCH 0x006F /* 8 bits */ 136 #define RE_ERIDR 0x0070 137 #define RE_ERIAR 0x0074 138 #define RE_EPHY_RXER_NUM 0x007C 139 #define RE_EPHYAR 0x0080 140 #define RE_MCUACCESS 0x00B0 141 #define RE_OCPDR 0x00B0 142 #define RE_OCPAR 0x00B4 143 #define RE_SecMAC0 0x00B4 144 #define RE_SecMAC4 0x00B8 145 #define RE_PHYOCPACCESS 0x00B8 146 #define RE_DBG_reg 0x00D1 147 #define RE_TwiCmdReg 0x00D2 148 #define RE_MCU_CMD 0x00D3 149 #define RE_RxMaxSize 0x00DA 150 #define RE_EFUSEAR 0x00DC 151 #define RE_CPlusCmd 0x00E0 152 #define RE_IntrMitigate 0x00E2 153 #define RE_MTPS 0x00EC 154 #define RE_CMAC_IBCR0 0x00F8 155 #define RE_CMAC_IBCR2 0x00F9 156 #define RE_CMAC_IBIMR0 0x00FA 157 #define RE_CMAC_IBISR0 0x00FB 158 /* 8125 */ 159 #define RE_IMR0_8125 0x38 160 #define RE_ISR0_8125 0x3C 161 #define RE_TPPOLL_8125 0x90 162 #define RE_BACKUP_ADDR0_8125 0x19E0 163 #define RE_BACKUP_ADDR4_8125 0X19E4 164 #define RE_EEE_TXIDLE_TIMER_8125 0x6048 165 166 /* ERI access */ 167 #define ERIAR_Flag 0x80000000 168 #define ERIAR_Write 0x80000000 169 #define ERIAR_Read 0x00000000 170 #define ERIAR_Addr_Align 4 /* ERI access register address must be 4 byte alignment */ 171 #define ERIAR_ExGMAC 0 172 #define ERIAR_MSIX 1 173 #define ERIAR_ASF 2 174 #define ERIAR_Type_shift 16 175 #define ERIAR_ByteEn 0x0f 176 #define ERIAR_ByteEn_shift 12 177 #define ERIAR_OOB 2 178 179 180 181 182 183 /* Direct PHY access registers only available on 8139 */ 184 #define RE_BMCR 0x0062 /* PHY basic mode control */ 185 #define RE_BMSR 0x0064 /* PHY basic mode status */ 186 #define RE_ANAR 0x0066 /* PHY autoneg advert */ 187 #define RE_LPAR 0x0068 /* PHY link partner ability */ 188 #define RE_ANER 0x006A /* PHY autoneg expansion */ 189 190 #define RE_DISCCNT 0x006C /* disconnect counter */ 191 #define RE_FALSECAR 0x006E /* false carrier counter */ 192 #define RE_NWAYTST 0x0070 /* NWAY test register */ 193 #define RE_RX_ER 0x0072 /* RX_ER counter */ 194 #define RE_CSCFG 0x0074 /* CS configuration register */ 195 #define RE_LDPS 0x0082 /* Link Down Power Saving */ 196 #define RE_CPCR 0x00E0 197 #define RE_IM 0x00E2 198 199 200 /* 201 * TX config register bits 202 */ 203 #define RE_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 204 #define RE_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 205 #define RE_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 206 #define RE_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 207 #define RE_TXCFG_IFG 0x03000000 /* interframe gap */ 208 209 #define RE_TXDMA_16BYTES 0x00000000 210 #define RE_TXDMA_32BYTES 0x00000100 211 #define RE_TXDMA_64BYTES 0x00000200 212 #define RE_TXDMA_128BYTES 0x00000300 213 #define RE_TXDMA_256BYTES 0x00000400 214 #define RE_TXDMA_512BYTES 0x00000500 215 #define RE_TXDMA_1024BYTES 0x00000600 216 #define RE_TXDMA_2048BYTES 0x00000700 217 218 /* 219 * Transmit descriptor status register bits. 220 */ 221 #define RE_TXSTAT_LENMASK 0x00001FFF 222 #define RE_TXSTAT_OWN 0x00002000 223 #define RE_TXSTAT_TX_UNDERRUN 0x00004000 224 #define RE_TXSTAT_TX_OK 0x00008000 225 #define RE_TXSTAT_COLLCNT 0x0F000000 226 #define RE_TXSTAT_CARR_HBEAT 0x10000000 227 #define RE_TXSTAT_OUTOFWIN 0x20000000 228 #define RE_TXSTAT_TXABRT 0x40000000 229 #define RE_TXSTAT_CARRLOSS 0x80000000 230 231 /* 232 * Interrupt status register bits. 233 */ 234 #define RE_ISR_RX_OK 0x0001 235 #define RE_ISR_RX_ERR 0x0002 236 #define RE_ISR_TX_OK 0x0004 237 #define RE_ISR_TX_ERR 0x0008 238 #define RE_ISR_RX_OVERRUN 0x0010 239 #define RE_ISR_PKT_UNDERRUN 0x0020 240 #define RE_ISR_LINKCHG 0x0020 241 #define RE_ISR_FIFO_OFLOW 0x0040 242 #define RE_ISR_TDU 0x0080 243 #define RE_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 244 #define RE_ISR_SYSTEM_ERR 0x8000 245 246 /* 247 #define RE_INTRS \ 248 (RE_ISR_TX_OK|RE_ISR_RX_OK|RE_ISR_RX_ERR|RE_ISR_TX_ERR| \ 249 RE_ISR_RX_OVERRUN|RE_ISR_PKT_UNDERRUN|RE_ISR_FIFO_OFLOW| \ 250 RE_ISR_PCS_TIMEOUT|RE_ISR_SYSTEM_ERR) 251 */ 252 253 #define RE_INTRS \ 254 (RE_ISR_TX_OK|RE_ISR_RX_OK|RE_ISR_RX_ERR|RE_ISR_TX_ERR| \ 255 RE_ISR_RX_OVERRUN|RE_ISR_PKT_UNDERRUN|RE_ISR_TDU| \ 256 RE_ISR_PCS_TIMEOUT|RE_ISR_SYSTEM_ERR) 257 258 /* 259 * Media status register. (8139 only) 260 */ 261 #define RE_MEDIASTAT_RXPAUSE 0x01 262 #define RE_MEDIASTAT_TXPAUSE 0x02 263 #define RE_MEDIASTAT_LINK 0x04 264 #define RE_MEDIASTAT_SPEED10 0x08 265 #define RE_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 266 #define RE_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 267 268 /* 269 * Receive config register. 270 */ 271 #define RE_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 272 #define RE_RXCFG_RX_INDIV 0x00000002 /* match filter */ 273 #define RE_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 274 #define RE_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 275 #define RE_RXCFG_RX_RUNT 0x00000010 276 #define RE_RXCFG_RX_ERRPKT 0x00000020 277 #define RE_RXCFG_RX_9356SEL 0x00000040 278 #define RE_RXCFG_WRAP 0x00000080 279 #define RE_RXCFG_MAXDMA 0x00000700 280 #define RE_RXCFG_BUFSZ 0x00001800 281 282 #define RE_RXDMA_16BYTES 0x00000000 283 #define RE_RXDMA_32BYTES 0x00000100 284 #define RE_RXDMA_64BYTES 0x00000200 285 #define RE_RXDMA_128BYTES 0x00000300 286 #define RE_RXDMA_256BYTES 0x00000400 287 #define RE_RXDMA_512BYTES 0x00000500 288 #define RE_RXDMA_1024BYTES 0x00000600 289 #define RE_RXDMA_UNLIMITED 0x00000700 290 291 #define RE_RXBUF_8 0x00000000 292 #define RE_RXBUF_16 0x00000800 293 #define RE_RXBUF_32 0x00001000 294 #define RE_RXBUF_64 0x00001800 295 296 #define RE_RXRESVERED 0x0000E000 297 298 /* 299 * Bits in RX status header (included with RX'ed packet 300 * in ring buffer). 301 */ 302 #define RE_RXSTAT_RXOK 0x00000001 303 #define RE_RXSTAT_ALIGNERR 0x00000002 304 #define RE_RXSTAT_CRCERR 0x00000004 305 #define RE_RXSTAT_GIANT 0x00000008 306 #define RE_RXSTAT_RUNT 0x00000010 307 #define RE_RXSTAT_BADSYM 0x00000020 308 #define RE_RXSTAT_BROAD 0x00002000 309 #define RE_RXSTAT_INDIV 0x00004000 310 #define RE_RXSTAT_MULTI 0x00008000 311 #define RE_RXSTAT_LENMASK 0xFFFF0000 312 313 #define RE_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 314 /* 315 * Command register. 316 */ 317 #define RE_CMD_EMPTY_RXBUF 0x0001 318 #define RE_CMD_TX_ENB 0x0004 319 #define RE_CMD_RX_ENB 0x0008 320 #define RE_CMD_RESET 0x0010 321 322 /* 323 * EEPROM control register 324 */ 325 #define RE_EE_DATAOUT 0x01 /* Data out */ 326 #define RE_EE_DATAIN 0x02 /* Data in */ 327 #define RE_EE_CLK 0x04 /* clock */ 328 #define RE_EE_SEL 0x08 /* chip select */ 329 #define RE_EE_MODE (0x40|0x80) 330 331 #define RE_EEMODE_OFF 0x00 332 #define RE_EEMODE_AUTOLOAD 0x40 333 #define RE_EEMODE_PROGRAM 0x80 334 #define RE_EEMODE_WRITECFG (0x80|0x40) 335 336 /* 9346 EEPROM commands */ 337 #define RE_EECMD_WRITE 0x140 338 #define RE_EECMD_READ 0x180 339 #define RE_EECMD_ERASE 0x1c0 340 341 #define RE_EE_ID 0x00 342 #define RE_EE_PCI_VID 0x01 343 #define RE_EE_PCI_DID 0x02 344 /* Location of station address inside EEPROM */ 345 #define RE_EE_EADDR 0x07 346 347 /* 348 * MII register (8129 only) 349 */ 350 #define RE_MII_CLK 0x01 351 #define RE_MII_DATAIN 0x02 352 #define RE_MII_DATAOUT 0x04 353 #define RE_MII_DIR 0x80 /* 0 == input, 1 == output */ 354 355 /* 356 * Config 0 register 357 */ 358 #define RE_CFG0_ROM0 0x01 359 #define RE_CFG0_ROM1 0x02 360 #define RE_CFG0_ROM2 0x04 361 #define RE_CFG0_PL0 0x08 362 #define RE_CFG0_PL1 0x10 363 #define RE_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 364 #define RE_CFG0_PCS 0x40 365 #define RE_CFG0_SCR 0x80 366 367 /* 368 * Config 1 register 369 */ 370 #define RE_CFG1_PME 0x01 371 #define RE_CFG1_IOMAP 0x04 372 #define RE_CFG1_MEMMAP 0x08 373 #define RE_CFG1_RSVD 0x10 374 #define RE_CFG1_LED0 0x40 375 #define RE_CFG1_LED1 0x80 376 377 /* 378 * Config 3 register 379 */ 380 #define RL_CFG3_GRANTSEL 0x80 381 #define RL_CFG3_WOL_MAGIC 0x20 382 #define RL_CFG3_WOL_LINK 0x10 383 #define RL_CFG3_JUMBO_EN0 0x04 /* RTL8168C or later. */ 384 #define RL_CFG3_FAST_B2B 0x01 385 386 /* 387 * Config 4 register 388 */ 389 #define RL_CFG4_LWPTN 0x04 390 #define RL_CFG4_LWPME 0x10 391 #define RL_CFG4_JUMBO_EN1 0x02 /* RTL8168C or later. */ 392 #define RL_CFG4_CUSTOMIZED_LED 0x40 393 394 /* 395 * Config 5 register 396 */ 397 #define RL_CFG5_WOL_BCAST 0x40 398 #define RL_CFG5_WOL_MCAST 0x20 399 #define RL_CFG5_WOL_UCAST 0x10 400 #define RL_CFG5_WOL_LANWAKE 0x02 401 #define RL_CFG5_PME_STS 0x01 402 403 /* 404 * PHY Status register 405 */ 406 #define RL_PHY_STATUS_500MF 0x80000 407 #define RL_PHY_STATUS_2500MF 0x400 408 #define RL_PHY_STATUS_1250MF 0x200 409 #define RL_PHY_STATUS_CABLE_PLUG 0x80 410 #define RL_PHY_STATUS_TX_FLOW_CTRL 0x40 411 #define RL_PHY_STATUS_RX_FLOW_CTRL 0x20 412 #define RL_PHY_STATUS_1000MF 0x10 413 #define RL_PHY_STATUS_100M 0x08 414 #define RL_PHY_STATUS_10M 0x04 415 #define RL_PHY_STATUS_LINK_STS 0x02 416 #define RL_PHY_STATUS_FULL_DUP 0x01 417 418 /* OCP GPHY access */ 419 #define OCPDR_Write 0x80000000 420 #define OCPDR_Read 0x00000000 421 #define OCPDR_Reg_Mask 0xFF 422 #define OCPDR_Data_Mask 0xFFFF 423 #define OCPDR_GPHY_Reg_shift 16 424 #define OCPAR_Flag 0x80000000 425 #define OCPAR_GPHY_Write 0x8000F060 426 #define OCPAR_GPHY_Read 0x0000F060 427 #define OCPR_Write 0x80000000 428 #define OCPR_Read 0x00000000 429 #define OCPR_Addr_Reg_shift 16 430 #define OCPR_Flag 0x80000000 431 #define OCP_STD_PHY_BASE_PAGE 0x0A40 432 433 /* MCU Command */ 434 #define RE_NOW_IS_OOB (1 << 7) 435 #define RE_TXFIFO_EMPTY (1 << 5) 436 #define RE_RXFIFO_EMPTY (1 << 4) 437 438 /* OOB Command */ 439 #define OOB_CMD_RESET 0x00 440 #define OOB_CMD_DRIVER_START 0x05 441 #define OOB_CMD_DRIVER_STOP 0x06 442 #define OOB_CMD_SET_IPMAC 0x41 443 444 /* Ethernet PHY MDI Mode */ 445 #define RE_ETH_PHY_FORCE_MDI 0 446 #define RE_ETH_PHY_FORCE_MDIX 1 447 #define RE_ETH_PHY_AUTO_MDI_MDIX 2 448 449 /* 450 * The RealTek doesn't use a fragment-based descriptor mechanism. 451 * Instead, there are only four register sets, each or which represents 452 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 453 * packet buffer (32-bit aligned!) and we place the buffer addresses in 454 * the registers so the chip knows where they are. 455 * 456 * We can sort of kludge together the same kind of buffer management 457 * used in previous drivers, but we have to do buffer copies almost all 458 * the time, so it doesn't really buy us much. 459 * 460 * For reception, there's just one large buffer where the chip stores 461 * all received packets. 462 */ 463 #ifndef __NO_STRICT_ALIGNMENT 464 #define RE_FIXUP_RX 1 465 #endif 466 467 468 #define RE_RX_BUF_SZ RE_RXBUF_64 469 #define RE_RXBUFLEN (1 << ((RE_RX_BUF_SZ >> 11) + 13)) 470 #define RE_TX_LIST_CNT 4 /* C mode Tx buffer number */ 471 #define RE_TX_BUF_NUM 256 /* Tx buffer number */ 472 #define RE_RX_BUF_NUM 256 /* Rx buffer number */ 473 #define RE_BUF_SIZE 9216 /* Buffer size of descriptor buffer */ 474 #define RE_MIN_FRAMELEN 60 475 #define RE_TXREV(x) ((x) << 11) 476 #define RE_RX_RESVERED RE_RXRESVERED 477 #define RE_RX_MAXDMA RE_RXDMA_UNLIMITED 478 #define RE_TX_MAXDMA RE_TXDMA_2048BYTES 479 #define RE_NTXSEGS 32 480 481 #define RE_TXCFG_CONFIG 0x03000780 //(RE_TXCFG_IFG|RE_TX_MAXDMA) 482 483 #define RE_DESC_ALIGN 256 /* descriptor alignment */ 484 #define RE_RX_BUFFER_ALIGN 8 /* descriptor alignment */ 485 486 #ifdef RE_FIXUP_RX 487 #define RE_ETHER_ALIGN RE_RX_BUFFER_ALIGN 488 #else 489 #define RE_ETHER_ALIGN 0 490 #endif 491 492 #ifdef __DragonFly__ 493 #ifndef ETHER_VLAN_ENCAP_LEN 494 #define ETHER_VLAN_ENCAP_LEN EVL_ENCAPLEN 495 #endif 496 #endif 497 #define Jumbo_Frame_2k ((2 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 498 #define Jumbo_Frame_3k ((3 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 499 #define Jumbo_Frame_4k ((4 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 500 #define Jumbo_Frame_5k ((5 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 501 #define Jumbo_Frame_6k ((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 502 #define Jumbo_Frame_7k ((7 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 503 #define Jumbo_Frame_8k ((8 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 504 #define Jumbo_Frame_9k ((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 505 506 #ifndef __DragonFly__ 507 struct re_chain_data { 508 u_int16_t cur_rx; 509 caddr_t re_rx_buf; 510 caddr_t re_rx_buf_ptr; 511 512 struct mbuf *re_tx_chain[RE_TX_LIST_CNT]; 513 u_int8_t last_tx; /* Previous Tx OK */ 514 u_int8_t cur_tx; /* Next to TX */ 515 }; 516 517 //+++ From FreeBSD 9.0 +++ 518 519 #define RL_MSI_MESSAGES 1 520 521 #define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 522 #define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 523 /* 524 * RX/TX descriptor definition. When large send mode is enabled, the 525 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 526 * the checksum offload bits are disabled. The structure layout is 527 * the same for RX and TX descriptors 528 */ 529 530 #define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 531 #define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 532 #define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 533 #define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 534 #define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 535 #define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 536 #define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 537 #define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 538 #define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 539 #define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 540 #define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 541 542 #define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 543 #define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 544 /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 545 #define RL_TDESC_CMD_UDPCSUMV2 0x80000000 546 #define RL_TDESC_CMD_TCPCSUMV2 0x40000000 547 #define RL_TDESC_CMD_IPCSUMV2 0x20000000 548 #define RL_TDESC_CMD_MSSVALV2 0x1FFC0000 549 #define RL_TDESC_CMD_MSSVALV2_SHIFT 18 550 551 #define RL_TDESC_CMD_BUFLEN 0x0000FFFF 552 553 /* 554 * Error bits are valid only on the last descriptor of a frame 555 * (i.e. RL_TDESC_CMD_EOF == 1) 556 */ 557 558 #define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 559 #define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 560 #define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 561 #define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 562 #define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 563 #define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 564 #define RL_TDESC_STAT_OWN 0x80000000 565 566 /* 567 * RX descriptor cmd/vlan definitions 568 */ 569 570 #define RL_RDESC_CMD_EOR 0x40000000 571 #define RL_RDESC_CMD_OWN 0x80000000 572 #define RL_RDESC_CMD_BUFLEN 0x00003FFF 573 574 #define RL_RDESC_STAT_OWN 0x80000000 575 #define RL_RDESC_STAT_EOR 0x40000000 576 #define RL_RDESC_STAT_SOF 0x20000000 577 #define RL_RDESC_STAT_EOF 0x10000000 578 #define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 579 #define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 580 #define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 581 #define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 582 #define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 583 #define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 584 #define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 585 #define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 586 #define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 587 #define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 588 #define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 589 #define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 590 #define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 591 #define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 592 #define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 593 #define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 594 #define RL_RDESC_STAT_GFRAGLEN RL_RDESC_CMD_BUFLEN /* RX'ed frame/frag len */ 595 #define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 596 RL_RDESC_STAT_CRCERR) 597 598 #define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 599 (rl_vlandata valid)*/ 600 #define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 601 /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 602 #define RL_RDESC_IPV6 0x80000000 603 #define RL_RDESC_IPV4 0x40000000 604 605 #define RL_PROTOID_NONIP 0x00000000 606 #define RL_PROTOID_TCPIP 0x00010000 607 #define RL_PROTOID_UDPIP 0x00020000 608 #define RL_PROTOID_IP 0x00030000 609 #define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 610 RL_PROTOID_TCPIP) 611 #define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 612 RL_PROTOID_UDPIP) 613 614 //--- From FreeBSD 9.0--- 615 616 617 union RxDesc { 618 u_int32_t ul[4]; 619 struct { 620 #if defined(_LITTLE_ENDIAN) 621 u_int32_t Frame_Length:14; 622 u_int32_t TCPF:1; 623 u_int32_t UDPF:1; 624 u_int32_t IPF:1; 625 u_int32_t TCPT:1; 626 u_int32_t UDPT:1; 627 u_int32_t CRC:1; 628 u_int32_t RUNT:1; 629 u_int32_t RES:1; 630 u_int32_t RWT:1; 631 u_int32_t RESV:2; 632 u_int32_t BAR:1; 633 u_int32_t PAM:1; 634 u_int32_t MAR:1; 635 u_int32_t LS:1; 636 u_int32_t FS:1; 637 u_int32_t EOR:1; 638 u_int32_t OWN:1; 639 640 u_int32_t VLAN_TAG:16; 641 u_int32_t TAVA:1; 642 u_int32_t RESV1:15; 643 #elif defined(_BIG_ENDIAN) 644 u_int32_t OWN:1; 645 u_int32_t EOR:1; 646 u_int32_t FS:1; 647 u_int32_t LS:1; 648 u_int32_t MAR:1; 649 u_int32_t PAM:1; 650 u_int32_t BAR:1; 651 u_int32_t RESV:2; 652 u_int32_t RWT:1; 653 u_int32_t RES:1; 654 u_int32_t RUNT:1; 655 u_int32_t CRC:1; 656 u_int32_t UDPT:1; 657 u_int32_t TCPT:1; 658 u_int32_t IPF:1; 659 u_int32_t UDPF:1; 660 u_int32_t TCPF:1; 661 u_int32_t Frame_Length:14; 662 663 u_int32_t RESV1:15; 664 u_int32_t TAVA:1; 665 u_int32_t VLAN_TAG:16; 666 #else 667 #error "what endian is this machine?" 668 #endif 669 u_int32_t RxBuffL; 670 u_int32_t RxBuffH; 671 } so0; /* symbol owner=0 */ 672 }; 673 674 union TxDesc { 675 u_int32_t ul[4]; 676 struct { 677 #if defined(_LITTLE_ENDIAN) 678 u_int32_t Frame_Length:16; 679 u_int32_t TCPCS:1; 680 u_int32_t UDPCS:1; 681 u_int32_t IPCS:1; 682 u_int32_t SCRC:1; 683 u_int32_t RESV:6; 684 u_int32_t TDMA:1; 685 u_int32_t LGSEN:1; 686 u_int32_t LS:1; 687 u_int32_t FS:1; 688 u_int32_t EOR:1; 689 u_int32_t OWN:1; 690 691 u_int32_t VLAN_TAG:16; 692 u_int32_t TAGC0:1; 693 u_int32_t TAGC1:1; 694 u_int32_t RESV1:14; 695 #elif defined(_BIG_ENDIAN) 696 u_int32_t OWN:1; 697 u_int32_t EOR:1; 698 u_int32_t FS:1; 699 u_int32_t LS:1; 700 u_int32_t LGSEN:1; 701 u_int32_t TDMA:1; 702 u_int32_t RESV:6; 703 u_int32_t SCRC:1; 704 u_int32_t IPCS:1; 705 u_int32_t UDPCS:1; 706 u_int32_t TCPCS:1; 707 u_int32_t Frame_Length:16; 708 709 u_int32_t RESV1:14; 710 u_int32_t TAGC1:1; 711 u_int32_t TAGC0:1; 712 u_int32_t VLAN_TAG:16; 713 #else 714 #error "what endian is this machine?" 715 #endif 716 u_int32_t TxBuffL; 717 u_int32_t TxBuffH; 718 } so1; /* symbol owner=1 */ 719 }; 720 721 struct re_descriptor { 722 u_int8_t rx_cur_index; 723 u_int8_t rx_last_index; 724 union RxDesc *rx_desc; /* 8 bits alignment */ 725 struct mbuf *rx_buf[RE_RX_BUF_NUM]; 726 727 u_int8_t tx_cur_index; 728 u_int8_t tx_last_index; 729 union TxDesc *tx_desc; /* 8 bits alignment */ 730 struct mbuf *tx_buf[RE_TX_BUF_NUM]; 731 bus_dma_tag_t rx_desc_tag; 732 bus_dmamap_t rx_desc_dmamap; 733 bus_dma_tag_t re_rx_mtag; /* mbuf RX mapping tag */ 734 bus_dmamap_t re_rx_dmamap[RE_RX_BUF_NUM]; 735 736 bus_dma_tag_t tx_desc_tag; 737 bus_dmamap_t tx_desc_dmamap; 738 bus_dma_tag_t re_tx_mtag; /* mbuf TX mapping tag */ 739 bus_dmamap_t re_tx_dmamap[RE_TX_BUF_NUM]; 740 }; 741 742 #define RE_INC(x) (x = (x + 1) % RE_TX_LIST_CNT) 743 #define RE_CUR_TXADDR(x) ((x->re_cdata.cur_tx * 4) + RE_TXADDR0) 744 #define RE_CUR_TXSTAT(x) ((x->re_cdata.cur_tx * 4) + RE_TXSTAT0) 745 #define RE_CUR_TXMBUF(x) (x->re_cdata.re_tx_chain[x->re_cdata.cur_tx]) 746 #define RE_LAST_TXADDR(x) ((x->re_cdata.last_tx * 4) + RE_TXADDR0) 747 #define RE_LAST_TXSTAT(x) ((x->re_cdata.last_tx * 4) + RE_TXSTAT0) 748 #define RE_LAST_TXMBUF(x) (x->re_cdata.re_tx_chain[x->re_cdata.last_tx]) 749 750 struct re_type { 751 u_int16_t re_vid; 752 u_int16_t re_did; 753 char *re_name; 754 }; 755 756 struct re_mii_frame { 757 u_int8_t mii_stdelim; 758 u_int8_t mii_opcode; 759 u_int8_t mii_phyaddr; 760 u_int8_t mii_regaddr; 761 u_int8_t mii_turnaround; 762 u_int16_t mii_data; 763 }; 764 #endif /* !__DragonFly__ */ 765 766 /* 767 * MII constants 768 */ 769 #define RE_MII_STARTDELIM 0x01 770 #define RE_MII_READOP 0x02 771 #define RE_MII_WRITEOP 0x01 772 #define RE_MII_TURNAROUND 0x02 773 #define RL_TDESC_VLANCTL_TAG 0x00020000 774 #define RL_RDESC_VLANCTL_TAG 0x00010000 775 #define RL_RDESC_VLANCTL_DATA 0x0000FFFF 776 #define RL_CPLUSCMD_VLANSTRIP 0x0040 777 #define RL_FLAG_MSI 0x00000001 778 #define RL_FLAG_PHYWAKE_PM 0x00000004 779 #define RL_FLAG_DESCV2 0x00000040 780 #define RL_FLAG_MSIX 0x00000800 781 #define RL_FLAG_MAGIC_PACKET_V2 0x20000000 782 #define RL_FLAG_PCIE 0x40000000 783 #define RL_FLAG_MAGIC_PACKET_V3 0x80000000 784 785 #define RL_ProtoIP ((1<<17)|(1<<18)) 786 //#define RL_ProtoIP ((1<<16)|(1<<17)) 787 #define RL_TCPT (1<<17) 788 #define RL_UDPT (1<<18) 789 #define RL_IPF (1<<16) 790 #define RL_UDPF (1<<15) 791 #define RL_TCPF (1<<14) 792 #define RL_V4F (1<<30) 793 794 #define RL_IPV4CS (1<<29) 795 #define RL_TCPCS (1<<30) 796 #define RL_UDPCS (1<<31) 797 #define RL_IPV4CS1 (1<<18) 798 #define RL_TCPCS1 (1<<16) 799 #define RL_UDPCS1 (1<<17) 800 801 #define RL_RxChkSum (1<<5) 802 803 enum { 804 EFUSE_NOT_SUPPORT = 0, 805 EFUSE_SUPPORT_V1, 806 EFUSE_SUPPORT_V2, 807 EFUSE_SUPPORT_V3, 808 EFUSE_SUPPORT_V4, 809 }; 810 811 enum { 812 MACFG_3 = 3, 813 MACFG_4, 814 MACFG_5, 815 MACFG_6, 816 817 MACFG_11 = 11, 818 MACFG_12, 819 MACFG_13, 820 MACFG_14, 821 MACFG_15, 822 MACFG_16, 823 MACFG_17, 824 MACFG_18, 825 MACFG_19, 826 827 MACFG_21 = 21, 828 MACFG_22, 829 MACFG_23, 830 MACFG_24, 831 MACFG_25, 832 MACFG_26, 833 MACFG_27, 834 MACFG_28, 835 836 MACFG_31 = 31, 837 MACFG_32, 838 MACFG_33, 839 840 MACFG_36 = 36, 841 MACFG_37, 842 MACFG_38, 843 MACFG_39, 844 845 MACFG_41 = 41, 846 MACFG_42, 847 MACFG_43, 848 849 MACFG_50 = 50, 850 MACFG_51, 851 MACFG_52, 852 MACFG_53, 853 MACFG_54, 854 MACFG_55, 855 MACFG_56, 856 MACFG_57, 857 MACFG_58, 858 MACFG_59, 859 MACFG_60, 860 MACFG_61, 861 MACFG_62, 862 MACFG_63, 863 MACFG_64, 864 MACFG_65, 865 MACFG_66, 866 MACFG_67, 867 MACFG_68, 868 MACFG_69, 869 MACFG_70, 870 MACFG_71, 871 MACFG_72, 872 873 MACFG_80 = 80, 874 MACFG_81, 875 MACFG_82, 876 MACFG_83, 877 878 MACFG_FF = 0xFF 879 }; 880 881 //#define MAC_STYLE_1 1 /* RTL8110S/SB/SC, RTL8111B and RTL8101E */ 882 //#define MAC_STYLE_2 2 /* RTL8111C/CP/D and RTL8102E */ 883 884 #ifndef __DragonFly__ 885 struct re_softc { 886 #if OS_VER<VERSION(6,0) 887 struct arpcom arpcom; /* interface info */ 888 #else 889 struct ifnet *re_ifp; 890 #endif 891 892 bus_space_handle_t re_bhandle; /* bus space handle */ 893 bus_space_tag_t re_btag; /* bus space tag */ 894 struct resource *re_res; 895 int re_res_id; 896 int re_res_type; 897 struct resource *re_res_pba; 898 struct resource *re_irq; 899 void *re_intrhand; 900 struct ifmedia media; /* used to instead of MII */ 901 902 /* Variable for 8169 family */ 903 u_int8_t re_8169_MacVersion; 904 u_int8_t re_8169_PhyVersion; 905 906 u_int8_t rx_fifo_overflow; 907 u_int8_t driver_detach; 908 909 u_int8_t re_unit; /* interface number */ 910 u_int8_t re_type; 911 u_int8_t re_stats_no_timeout; 912 u_int8_t re_revid; 913 u_int16_t re_vendor_id; 914 u_int16_t re_device_id; 915 u_int16_t re_subvendor_id; 916 u_int16_t re_subdevice_id; 917 918 struct re_chain_data re_cdata; /* Tx buffer chain, Used only in ~C+ mode */ 919 struct re_descriptor re_desc; /* Descriptor, Used only in C+ mode */ 920 #ifdef RE_USE_NEW_CALLOUT_FUN 921 struct callout re_stat_ch; 922 #else 923 struct callout_handle re_stat_ch; 924 #endif 925 u_int8_t re_link_chg_det; 926 struct mtx mtx; 927 bus_dma_tag_t re_parent_tag; 928 device_t dev; 929 int re_expcap; 930 int max_jumbo_frame_size; 931 int re_rx_mbuf_sz; 932 int re_rx_desc_buf_sz; 933 int re_if_flags; 934 int re_tx_cstag; 935 int re_rx_cstag; 936 int suspended; /* 0 = normal 1 = suspended */ 937 938 u_int8_t RequireAdcBiasPatch; 939 u_int16_t AdcBiasPatchIoffset; 940 941 u_int8_t RequireAdjustUpsTxLinkPulseTiming; 942 u_int16_t SwrCnt1msIni; 943 944 u_int8_t RequiredSecLanDonglePatch; 945 946 u_int8_t RequirePhyMdiSwapPatch; 947 948 u_int8_t re_efuse_ver; 949 950 u_int16_t re_sw_ram_code_ver; 951 u_int16_t re_hw_ram_code_ver; 952 #if OS_VER>=VERSION(7,0) 953 struct task re_inttask; 954 #endif 955 u_int16_t cur_page; 956 957 u_int16_t phy_reg_anlpar; 958 959 u_int8_t re_hw_enable_msi_msix; 960 961 u_int8_t re_coalesce_tx_pkt; 962 963 u_int8_t link_state; 964 965 u_int8_t prohibit_access_reg; 966 967 u_int8_t re_hw_supp_now_is_oob_ver; 968 969 u_int8_t hw_hw_supp_serdes_phy_ver; 970 971 u_int8_t HwSuppDashVer; 972 u_int8_t re_dash; 973 bus_space_handle_t re_mapped_cmac_handle; /* bus space tag */ 974 bus_space_tag_t re_mapped_cmac_tag; /* bus space tag */ 975 bus_space_handle_t re_cmac_handle; /* bus space handle */ 976 bus_space_tag_t re_cmac_tag; /* bus space tag */ 977 u_int8_t HwPkgDet; 978 979 u_int32_t HwFiberModeVer; 980 u_int32_t HwFiberStat; 981 982 int (*ifmedia_upd)(struct ifnet *); 983 void (*ifmedia_sts)(struct ifnet *, struct ifmediareq *); 984 #if OS_VER < VERSION(7,0) 985 void (*intr)(void *); 986 #else 987 int (*intr)(void *); 988 #endif //OS_VER < VERSION(7,0) 989 void (*int_task)(void *, int); 990 void (*hw_start_unlock)(struct re_softc *); 991 }; 992 #endif /* !__DragonFly__ */ 993 994 enum bits { 995 BIT_0 = (1 << 0), 996 BIT_1 = (1 << 1), 997 BIT_2 = (1 << 2), 998 BIT_3 = (1 << 3), 999 BIT_4 = (1 << 4), 1000 BIT_5 = (1 << 5), 1001 BIT_6 = (1 << 6), 1002 BIT_7 = (1 << 7), 1003 BIT_8 = (1 << 8), 1004 BIT_9 = (1 << 9), 1005 BIT_10 = (1 << 10), 1006 BIT_11 = (1 << 11), 1007 BIT_12 = (1 << 12), 1008 BIT_13 = (1 << 13), 1009 BIT_14 = (1 << 14), 1010 BIT_15 = (1 << 15), 1011 BIT_16 = (1 << 16), 1012 BIT_17 = (1 << 17), 1013 BIT_18 = (1 << 18), 1014 BIT_19 = (1 << 19), 1015 BIT_20 = (1 << 20), 1016 BIT_21 = (1 << 21), 1017 BIT_22 = (1 << 22), 1018 BIT_23 = (1 << 23), 1019 BIT_24 = (1 << 24), 1020 BIT_25 = (1 << 25), 1021 BIT_26 = (1 << 26), 1022 BIT_27 = (1 << 27), 1023 BIT_28 = (1 << 28), 1024 BIT_29 = (1 << 29), 1025 BIT_30 = (1 << 30), 1026 BIT_31 = (1 << 31) 1027 }; 1028 1029 #ifndef __DragonFly__ 1030 #define RE_LOCK(_sc) mtx_lock(&(_sc)->mtx) 1031 #define RE_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 1032 #define RE_LOCK_INIT(_sc,_name) mtx_init(&(_sc)->mtx,_name,MTX_NETWORK_LOCK,MTX_DEF) 1033 #define RE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) 1034 #define RE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx,MA_OWNED) 1035 1036 /* 1037 * register space access macros 1038 */ 1039 #if OS_VER>VERSION(5,9) 1040 #define CSR_WRITE_STREAM_4(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val)) 1041 #define CSR_WRITE_STREAM_2(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_stream_2(sc->re_btag, sc->re_bhandle, reg, val)) 1042 #endif 1043 #define CSR_WRITE_4(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val)) 1044 #define CSR_WRITE_2(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val)) 1045 #define CSR_WRITE_1(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val)) 1046 1047 #define CSR_READ_4(sc, reg) ((sc->prohibit_access_reg)?0xFFFFFFFF:bus_space_read_4(sc->re_btag, sc->re_bhandle, reg)) 1048 #define CSR_READ_2(sc, reg) ((sc->prohibit_access_reg)?0xFFFF:bus_space_read_2(sc->re_btag, sc->re_bhandle, reg)) 1049 #define CSR_READ_1(sc, reg) ((sc->prohibit_access_reg)?0xFF:bus_space_read_1(sc->re_btag, sc->re_bhandle, reg)) 1050 1051 /* cmac write/read MMIO register */ 1052 #define RE_CMAC_WRITE_1(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_1(sc->re_cmac_tag, sc->re_cmac_handle, reg, val)) 1053 #define RE_CMAC_WRITE_2(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_2(sc->re_cmac_tag, sc->re_cmac_handle, reg, val)) 1054 #define RE_CMAC_WRITE_4(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_4(sc->re_cmac_tag, sc->re_cmac_handle, reg, val)) 1055 #define RE_CMAC_READ_1(sc, reg) ((sc->prohibit_access_reg)?0xFF:bus_space_read_1(sc->re_cmac_tag, sc->re_cmac_handle, reg)) 1056 #define RE_CMAC_READ_2(sc, reg) ((sc->prohibit_access_reg)?0xFFFF:bus_space_read_2(sc->re_cmac_tag, sc->re_cmac_handle, reg)) 1057 #define RE_CMAC_READ_4(sc, reg) (sc->prohibit_access_reg)?0xFFFFFFFF:bus_space_read_4(sc->re_cmac_tag, sc->re_cmac_handle, reg)) 1058 #endif /* !__DragonFly__ */ 1059 1060 #define RE_TIMEOUT 1000 1061 1062 /* 1063 * General constants that are fun to know. 1064 * 1065 * RealTek PCI vendor ID 1066 */ 1067 #define RT_VENDORID 0x10EC 1068 1069 /* 1070 * RealTek chip device IDs. 1071 */ 1072 #define RT_DEVICEID_8129 0x8129 1073 #define RT_DEVICEID_8139 0x8139 1074 #define RT_DEVICEID_8169 0x8169 /* For RTL8169 */ 1075 #define RT_DEVICEID_8169SC 0x8167 /* For RTL8169SC */ 1076 #define RT_DEVICEID_8168 0x8168 /* For RTL8168B */ 1077 #define RT_DEVICEID_8161 0x8161 /* For RTL8168 Series add-on card */ 1078 #define RT_DEVICEID_8136 0x8136 /* For RTL8101E */ 1079 #define RT_DEVICEID_8125 0x8125 /* For RTL8125 */ 1080 #define RT_DEVICEID_2600 0x2600 /* For E2600 Killer Ethernet */ 1081 1082 /* 1083 * Accton PCI vendor ID 1084 */ 1085 #define ACCTON_VENDORID 0x1113 1086 1087 /* 1088 * Accton MPX 5030/5038 device ID. 1089 */ 1090 #define ACCTON_DEVICEID_5030 0x1211 1091 1092 /* 1093 * Delta Electronics Vendor ID. 1094 */ 1095 #define DELTA_VENDORID 0x1500 1096 1097 /* 1098 * Delta device IDs. 1099 */ 1100 #define DELTA_DEVICEID_8139 0x1360 1101 1102 /* 1103 * Addtron vendor ID. 1104 */ 1105 #define ADDTRON_VENDORID 0x4033 1106 1107 /* 1108 * Addtron device IDs. 1109 */ 1110 #define ADDTRON_DEVICEID_8139 0x1360 1111 1112 /* 1113 * D-Link vendor ID. 1114 */ 1115 #define DLINK_VENDORID 0x1186 1116 1117 /* 1118 * D-Link DFE-530TX+ device ID 1119 */ 1120 #define DLINK_DEVICEID_530TXPLUS 0x1300 1121 1122 /* 1123 * PCI low memory base and low I/O base register, and 1124 * other PCI registers. 1125 */ 1126 1127 #define RE_PCI_VENDOR_ID 0x00 1128 #define RE_PCI_DEVICE_ID 0x02 1129 #define RE_PCI_COMMAND 0x04 1130 #define RE_PCI_STATUS 0x06 1131 #define RE_PCI_REVISION_ID 0x08 /* 8 bits */ 1132 #define RE_PCI_CLASSCODE 0x09 1133 #define RE_PCI_LATENCY_TIMER 0x0D 1134 #define RE_PCI_HEADER_TYPE 0x0E 1135 #define RE_PCI_BIOSROM 0x30 1136 #define RE_PCI_INTLINE 0x3C 1137 #define RE_PCI_INTPIN 0x3D 1138 #define RE_PCI_MINGNT 0x3E 1139 #define RE_PCI_MINLAT 0x0F 1140 #define RE_PCI_RESETOPT 0x48 1141 #define RE_PCI_EEPROM_DATA 0x4C 1142 1143 #define RE_PCI_CAPID 0x50 /* 8 bits */ 1144 #define RE_PCI_NEXTPTR 0x51 /* 8 bits */ 1145 #define RE_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 1146 #define RE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 1147 1148 #define RE_PSTATE_MASK 0x0003 1149 #define RE_PSTATE_D0 0x0000 1150 #define RE_PSTATE_D1 0x0002 1151 #define RE_PSTATE_D2 0x0002 1152 #define RE_PSTATE_D3 0x0003 1153 #define RE_PME_EN 0x0010 1154 #define RE_PME_STATUS 0x8000 1155 1156 #define RE_WOL_LINK_SPEED_10M_FIRST ( 0 ) 1157 #define RE_WOL_LINK_SPEED_100M_FIRST ( 1 ) 1158 1159 #define RTK_ADVERTISE_2500FULL 0x80 1160 1161 //Ram Code Version 1162 #define NIC_RAMCODE_VERSION_8168E (0x0057) 1163 #define NIC_RAMCODE_VERSION_8168EVL (0x0055) 1164 #define NIC_RAMCODE_VERSION_8168F (0x0052) 1165 #define NIC_RAMCODE_VERSION_8411 (0x0044) 1166 #define NIC_RAMCODE_VERSION_8168G (0x0042) 1167 #define NIC_RAMCODE_VERSION_8168GU (0x0001) 1168 #define NIC_RAMCODE_VERSION_8168EP (0x0019) 1169 #define NIC_RAMCODE_VERSION_8411B (0x0012) 1170 #define NIC_RAMCODE_VERSION_8168H (0x0018) 1171 #define NIC_RAMCODE_VERSION_8168FP (0x0003) 1172 #define NIC_RAMCODE_VERSION_8125A_REV_A (0x0B11) 1173 #define NIC_RAMCODE_VERSION_8125A_REV_B (0x0B33) 1174 #define NIC_RAMCODE_VERSION_8125B_REV_A (0x0B17) 1175 #define NIC_RAMCODE_VERSION_8125B_REV_B (0x0B36) 1176 1177 #ifdef __alpha__ 1178 #undef vtophys 1179 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1180 #endif 1181 1182 #ifndef TRUE 1183 #define TRUE 1 1184 #endif 1185 #ifndef FALSE 1186 #define FALSE 0 1187 #endif 1188 1189 #define PHYAR_Flag 0x80000000 1190 #define RE_CPlusMode 0x20 /* In Revision ID */ 1191 1192 /* interrupt service routine loop time*/ 1193 /* the minimum value is 1 */ 1194 #define INTR_MAX_LOOP 1 1195 1196 #define RE_REGS_SIZE (256) 1197 1198 #define RTL8168FP_OOBMAC_BASE 0xBAF70000 1199 #define HW_DASH_SUPPORT_DASH(_M) ((_M)->HwSuppDashVer > 0 ) 1200 #define HW_DASH_SUPPORT_TYPE_1(_M) ((_M)->HwSuppDashVer == 1 ) 1201 #define HW_DASH_SUPPORT_TYPE_2(_M) ((_M)->HwSuppDashVer == 2 ) 1202 #define HW_DASH_SUPPORT_TYPE_3(_M) ((_M)->HwSuppDashVer == 3 ) 1203 1204 #define HW_SUPP_SERDES_PHY(_M) ((_M)->hw_hw_supp_serdes_phy_ver > 0) 1205 1206 /*#define RE_DBG*/ 1207 1208 #ifdef RE_DBG 1209 #define DBGPRINT(_unit, _msg) printf ("re%d: %s\n", _unit,_msg) 1210 #define DBGPRINT1(_unit, _msg, _para1) \ 1211 { \ 1212 char buf[100]; \ 1213 sprintf(buf,_msg,_para1); \ 1214 printf ("re%d: %s\n", _unit,buf); \ 1215 } 1216 #else 1217 #define DBGPRINT(_unit, _msg) 1218 #define DBGPRINT1(_unit, _msg, _para1) 1219 #endif 1220 1221 #ifndef __DragonFly__ 1222 #if OS_VER<VERSION(4,9) 1223 #define IFM_1000_T IFM_1000_TX 1224 #elif OS_VER<VERSION(6,0) 1225 #define RE_GET_IFNET(SC) &SC->arpcom.ac_if 1226 #define if_drv_flags if_flags 1227 #define IFF_DRV_RUNNING IFF_RUNNING 1228 #define IFF_DRV_OACTIVE IFF_OACTIVE 1229 #else 1230 #define RE_GET_IFNET(SC) SC->re_ifp 1231 #endif 1232 1233 #if OS_VER>=VERSION(10,0) 1234 #define IF_ADDR_LOCK IF_ADDR_WLOCK 1235 #define IF_ADDR_UNLOCK IF_ADDR_WUNLOCK 1236 #endif 1237 1238 #if OS_VER>=VERSION(7,4) 1239 #if OS_VER>=VERSION(9,2) 1240 #define RE_PCIEM_LINK_CAP_ASPM PCIEM_LINK_CAP_ASPM 1241 #define RE_PCIER_LINK_CTL PCIER_LINK_CTL 1242 #define RE_PCIER_LINK_CAP PCIER_LINK_CAP 1243 #else //OS_VER>=VERSION(9,2) 1244 #define RE_PCIEM_LINK_CAP_ASPM PCIM_LINK_CAP_ASPM 1245 #define RE_PCIER_LINK_CTL PCIR_EXPRESS_LINK_CTL 1246 #define RE_PCIER_LINK_CAP PCIR_EXPRESS_LINK_CAP 1247 #endif 1248 #endif //OS_VER>=VERSION(7,4) 1249 1250 #ifndef IFM_2500_X 1251 #define IFM_2500_X IFM_X(63) 1252 #endif 1253 1254 #endif /* !__DragonFly__ */ 1255 1256 #ifndef ARRAY_SIZE 1257 #define ARRAY_SIZE(_a) (sizeof((_a)) / sizeof((_a)[0])) 1258 #endif 1259