1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $ 33 */ 34 35 /* 36 * RealTek 8129/8139 PCI NIC driver 37 * 38 * Supports several extremely cheap PCI 10/100 adapters based on 39 * the RealTek chipset. Datasheets can be obtained from 40 * www.realtek.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86 #include "opt_polling.h" 87 88 #include <sys/param.h> 89 #include <sys/endian.h> 90 #include <sys/systm.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/module.h> 96 #include <sys/socket.h> 97 #include <sys/serialize.h> 98 #include <sys/bus.h> 99 #include <sys/rman.h> 100 #include <sys/thread2.h> 101 #include <sys/interrupt.h> 102 103 #include <net/if.h> 104 #include <net/ifq_var.h> 105 #include <net/if_arp.h> 106 #include <net/ethernet.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 110 #include <net/bpf.h> 111 112 #include <dev/netif/mii_layer/mii.h> 113 #include <dev/netif/mii_layer/miivar.h> 114 115 #include <bus/pci/pcidevs.h> 116 #include <bus/pci/pcireg.h> 117 #include <bus/pci/pcivar.h> 118 119 /* "controller miibus0" required. See GENERIC if you get errors here. */ 120 #include "miibus_if.h" 121 122 /* 123 * Default to using PIO access for this driver. On SMP systems, 124 * there appear to be problems with memory mapped mode: it looks like 125 * doing too many memory mapped access back to back in rapid succession 126 * can hang the bus. I'm inclined to blame this on crummy design/construction 127 * on the part of RealTek. Memory mapped mode does appear to work on 128 * uniprocessor systems though. 129 */ 130 #define RL_USEIOSPACE 131 132 #include <dev/netif/rl/if_rlreg.h> 133 134 /* 135 * Various supported device vendors/types and their names. 136 */ 137 static struct rl_type { 138 uint16_t rl_vid; 139 uint16_t rl_did; 140 const char *rl_name; 141 } rl_devs[] = { 142 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8129, 143 "RealTek 8129 10/100BaseTX" }, 144 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, 145 "RealTek 8139 10/100BaseTX" }, 146 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139B, 147 "RealTek 8139 10/100BaseTX CardBus" }, 148 { PCI_VENDOR_ACCTON, PCI_PRODUCT_ACCTON_MPX5030, 149 "Accton MPX 5030/5038 10/100BaseTX" }, 150 { PCI_VENDOR_DELTA, PCI_PRODUCT_DELTA_8139, 151 "Delta Electronics 8139 10/100BaseTX" }, 152 { PCI_VENDOR_ADDTRON, PCI_PRODUCT_ADDTRON_8139, 153 "Addtron Technology 8139 10/100BaseTX" }, 154 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE530TXPLUS, 155 "D-Link DFE-530TX+ 10/100BaseTX" }, 156 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE690TXD, 157 "D-Link DFE-690TX 10/100BaseTX" }, 158 { PCI_VENDOR_NORTEL, PCI_PRODUCT_NORTEL_BAYSTACK_21, 159 "Nortel Networks 10/100BaseTX" }, 160 { PCI_VENDOR_PEPPERCON, PCI_PRODUCT_PEPPERCON_ROLF, 161 "Peppercon AG ROL/F" }, 162 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CB_TXD, 163 "Corega FEther CB-TXD" }, 164 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_2CB_TXD, 165 "Corega FEtherII CB-TXD" }, 166 { PCI_VENDOR_PLANEX, PCI_PRODUCT_PLANEX_FNW_3800_TX, 167 "Planex FNW-3800-TX" }, 168 { 0, 0, NULL } 169 }; 170 171 static int rl_probe(device_t); 172 static int rl_attach(device_t); 173 static int rl_detach(device_t); 174 175 static int rl_encap(struct rl_softc *, struct mbuf * ); 176 177 static void rl_rxeof(struct rl_softc *); 178 static void rl_txeof(struct rl_softc *); 179 static void rl_intr(void *); 180 static void rl_tick(void *); 181 static void rl_start(struct ifnet *); 182 static int rl_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 183 static void rl_init(void *); 184 static void rl_stop (struct rl_softc *); 185 static void rl_watchdog(struct ifnet *); 186 static int rl_suspend(device_t); 187 static int rl_resume(device_t); 188 static void rl_shutdown(device_t); 189 static int rl_ifmedia_upd(struct ifnet *); 190 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 191 192 static void rl_eeprom_putbyte(struct rl_softc *, int); 193 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *); 194 static void rl_read_eeprom(struct rl_softc *, caddr_t, int, int, int); 195 static void rl_mii_sync(struct rl_softc *); 196 static void rl_mii_send(struct rl_softc *, uint32_t, int); 197 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *); 198 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *); 199 200 static int rl_miibus_readreg(device_t, int, int); 201 static int rl_miibus_writereg(device_t, int, int, int); 202 static void rl_miibus_statchg(device_t); 203 204 static void rl_setmulti(struct rl_softc *); 205 static void rl_reset(struct rl_softc *); 206 static void rl_list_tx_init(struct rl_softc *); 207 208 #ifdef DEVICE_POLLING 209 static poll_handler_t rl_poll; 210 #endif 211 212 static int rl_dma_alloc(struct rl_softc *); 213 static void rl_dma_free(struct rl_softc *); 214 215 #ifdef RL_USEIOSPACE 216 #define RL_RES SYS_RES_IOPORT 217 #define RL_RID RL_PCI_LOIO 218 #else 219 #define RL_RES SYS_RES_MEMORY 220 #define RL_RID RL_PCI_LOMEM 221 #endif 222 223 static device_method_t rl_methods[] = { 224 /* Device interface */ 225 DEVMETHOD(device_probe, rl_probe), 226 DEVMETHOD(device_attach, rl_attach), 227 DEVMETHOD(device_detach, rl_detach), 228 DEVMETHOD(device_suspend, rl_suspend), 229 DEVMETHOD(device_resume, rl_resume), 230 DEVMETHOD(device_shutdown, rl_shutdown), 231 232 /* bus interface */ 233 DEVMETHOD(bus_print_child, bus_generic_print_child), 234 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 235 236 /* MII interface */ 237 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 238 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 239 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 240 241 { 0, 0 } 242 }; 243 244 static DEFINE_CLASS_0(rl, rl_driver, rl_methods, sizeof(struct rl_softc)); 245 static devclass_t rl_devclass; 246 247 DECLARE_DUMMY_MODULE(if_rl); 248 DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, NULL, NULL); 249 DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, NULL, NULL); 250 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, NULL, NULL); 251 MODULE_DEPEND(if_rl, miibus, 1, 1, 1); 252 253 #define EE_SET(x) \ 254 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) | (x)) 255 256 #define EE_CLR(x) \ 257 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) & ~(x)) 258 259 /* 260 * Send a read command and address to the EEPROM, check for ACK. 261 */ 262 static void 263 rl_eeprom_putbyte(struct rl_softc *sc, int addr) 264 { 265 int d, i; 266 267 d = addr | sc->rl_eecmd_read; 268 269 /* 270 * Feed in each bit and strobe the clock. 271 */ 272 for (i = 0x400; i; i >>= 1) { 273 if (d & i) 274 EE_SET(RL_EE_DATAIN); 275 else 276 EE_CLR(RL_EE_DATAIN); 277 DELAY(100); 278 EE_SET(RL_EE_CLK); 279 DELAY(150); 280 EE_CLR(RL_EE_CLK); 281 DELAY(100); 282 } 283 } 284 285 /* 286 * Read a word of data stored in the EEPROM at address 'addr.' 287 */ 288 static void 289 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest) 290 { 291 int i; 292 uint16_t word = 0; 293 294 /* Enter EEPROM access mode. */ 295 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 296 297 /* 298 * Send address of word we want to read. 299 */ 300 rl_eeprom_putbyte(sc, addr); 301 302 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 303 304 /* 305 * Start reading bits from EEPROM. 306 */ 307 for (i = 0x8000; i; i >>= 1) { 308 EE_SET(RL_EE_CLK); 309 DELAY(100); 310 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 311 word |= i; 312 EE_CLR(RL_EE_CLK); 313 DELAY(100); 314 } 315 316 /* Turn off EEPROM access mode. */ 317 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 318 319 *dest = word; 320 } 321 322 /* 323 * Read a sequence of words from the EEPROM. 324 */ 325 static void 326 rl_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt, int swap) 327 { 328 int i; 329 u_int16_t word = 0, *ptr; 330 331 for (i = 0; i < cnt; i++) { 332 rl_eeprom_getword(sc, off + i, &word); 333 ptr = (u_int16_t *)(dest + (i * 2)); 334 if (swap) 335 *ptr = ntohs(word); 336 else 337 *ptr = word; 338 } 339 } 340 341 342 /* 343 * MII access routines are provided for the 8129, which 344 * doesn't have a built-in PHY. For the 8139, we fake things 345 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 346 * direct access PHY registers. 347 */ 348 #define MII_SET(x) \ 349 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) | x) 350 351 #define MII_CLR(x) \ 352 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) & ~x) 353 354 /* 355 * Sync the PHYs by setting data bit and strobing the clock 32 times. 356 */ 357 static void 358 rl_mii_sync(struct rl_softc *sc) 359 { 360 int i; 361 362 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 363 364 for (i = 0; i < 32; i++) { 365 MII_SET(RL_MII_CLK); 366 DELAY(1); 367 MII_CLR(RL_MII_CLK); 368 DELAY(1); 369 } 370 } 371 372 /* 373 * Clock a series of bits through the MII. 374 */ 375 static void 376 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt) 377 { 378 int i; 379 380 MII_CLR(RL_MII_CLK); 381 382 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 383 if (bits & i) 384 MII_SET(RL_MII_DATAOUT); 385 else 386 MII_CLR(RL_MII_DATAOUT); 387 DELAY(1); 388 MII_CLR(RL_MII_CLK); 389 DELAY(1); 390 MII_SET(RL_MII_CLK); 391 } 392 } 393 394 /* 395 * Read an PHY register through the MII. 396 */ 397 static int 398 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame) 399 { 400 int ack, i; 401 402 /* 403 * Set up frame for RX. 404 */ 405 frame->mii_stdelim = RL_MII_STARTDELIM; 406 frame->mii_opcode = RL_MII_READOP; 407 frame->mii_turnaround = 0; 408 frame->mii_data = 0; 409 410 CSR_WRITE_2(sc, RL_MII, 0); 411 412 /* 413 * Turn on data xmit. 414 */ 415 MII_SET(RL_MII_DIR); 416 417 rl_mii_sync(sc); 418 419 /* 420 * Send command/address info. 421 */ 422 rl_mii_send(sc, frame->mii_stdelim, 2); 423 rl_mii_send(sc, frame->mii_opcode, 2); 424 rl_mii_send(sc, frame->mii_phyaddr, 5); 425 rl_mii_send(sc, frame->mii_regaddr, 5); 426 427 /* Idle bit */ 428 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 429 DELAY(1); 430 MII_SET(RL_MII_CLK); 431 DELAY(1); 432 433 /* Turn off xmit. */ 434 MII_CLR(RL_MII_DIR); 435 436 /* Check for ack */ 437 MII_CLR(RL_MII_CLK); 438 DELAY(1); 439 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 440 MII_SET(RL_MII_CLK); 441 DELAY(1); 442 443 /* 444 * Now try reading data bits. If the ack failed, we still 445 * need to clock through 16 cycles to keep the PHY(s) in sync. 446 */ 447 if (ack) { 448 for(i = 0; i < 16; i++) { 449 MII_CLR(RL_MII_CLK); 450 DELAY(1); 451 MII_SET(RL_MII_CLK); 452 DELAY(1); 453 } 454 } else { 455 for (i = 0x8000; i; i >>= 1) { 456 MII_CLR(RL_MII_CLK); 457 DELAY(1); 458 if (!ack) { 459 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 460 frame->mii_data |= i; 461 DELAY(1); 462 } 463 MII_SET(RL_MII_CLK); 464 DELAY(1); 465 } 466 } 467 468 MII_CLR(RL_MII_CLK); 469 DELAY(1); 470 MII_SET(RL_MII_CLK); 471 DELAY(1); 472 473 return(ack ? 1 : 0); 474 } 475 476 /* 477 * Write to a PHY register through the MII. 478 */ 479 static int 480 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame) 481 { 482 /* 483 * Set up frame for TX. 484 */ 485 frame->mii_stdelim = RL_MII_STARTDELIM; 486 frame->mii_opcode = RL_MII_WRITEOP; 487 frame->mii_turnaround = RL_MII_TURNAROUND; 488 489 /* 490 * Turn on data output. 491 */ 492 MII_SET(RL_MII_DIR); 493 494 rl_mii_sync(sc); 495 496 rl_mii_send(sc, frame->mii_stdelim, 2); 497 rl_mii_send(sc, frame->mii_opcode, 2); 498 rl_mii_send(sc, frame->mii_phyaddr, 5); 499 rl_mii_send(sc, frame->mii_regaddr, 5); 500 rl_mii_send(sc, frame->mii_turnaround, 2); 501 rl_mii_send(sc, frame->mii_data, 16); 502 503 /* Idle bit. */ 504 MII_SET(RL_MII_CLK); 505 DELAY(1); 506 MII_CLR(RL_MII_CLK); 507 DELAY(1); 508 509 /* 510 * Turn off xmit. 511 */ 512 MII_CLR(RL_MII_DIR); 513 514 return(0); 515 } 516 517 static int 518 rl_miibus_readreg(device_t dev, int phy, int reg) 519 { 520 struct rl_softc *sc; 521 struct rl_mii_frame frame; 522 uint16_t rval = 0; 523 uint16_t rl8139_reg = 0; 524 525 sc = device_get_softc(dev); 526 527 if (sc->rl_type == RL_8139) { 528 /* Pretend the internal PHY is only at address 0 */ 529 if (phy) 530 return(0); 531 switch (reg) { 532 case MII_BMCR: 533 rl8139_reg = RL_BMCR; 534 break; 535 case MII_BMSR: 536 rl8139_reg = RL_BMSR; 537 break; 538 case MII_ANAR: 539 rl8139_reg = RL_ANAR; 540 break; 541 case MII_ANER: 542 rl8139_reg = RL_ANER; 543 break; 544 case MII_ANLPAR: 545 rl8139_reg = RL_LPAR; 546 break; 547 case MII_PHYIDR1: 548 case MII_PHYIDR2: 549 return(0); 550 break; 551 /* 552 * Allow the rlphy driver to read the media status 553 * register. If we have a link partner which does not 554 * support NWAY, this is the register which will tell 555 * us the results of parallel detection. 556 */ 557 case RL_MEDIASTAT: 558 rval = CSR_READ_1(sc, RL_MEDIASTAT); 559 return(rval); 560 default: 561 device_printf(dev, "bad phy register\n"); 562 return(0); 563 } 564 rval = CSR_READ_2(sc, rl8139_reg); 565 return(rval); 566 } 567 568 bzero(&frame, sizeof(frame)); 569 570 frame.mii_phyaddr = phy; 571 frame.mii_regaddr = reg; 572 rl_mii_readreg(sc, &frame); 573 574 return(frame.mii_data); 575 } 576 577 static int 578 rl_miibus_writereg(device_t dev, int phy, int reg, int data) 579 { 580 struct rl_softc *sc; 581 struct rl_mii_frame frame; 582 u_int16_t rl8139_reg = 0; 583 584 sc = device_get_softc(dev); 585 586 if (sc->rl_type == RL_8139) { 587 /* Pretend the internal PHY is only at address 0 */ 588 if (phy) 589 return(0); 590 switch (reg) { 591 case MII_BMCR: 592 rl8139_reg = RL_BMCR; 593 break; 594 case MII_BMSR: 595 rl8139_reg = RL_BMSR; 596 break; 597 case MII_ANAR: 598 rl8139_reg = RL_ANAR; 599 break; 600 case MII_ANER: 601 rl8139_reg = RL_ANER; 602 break; 603 case MII_ANLPAR: 604 rl8139_reg = RL_LPAR; 605 break; 606 case MII_PHYIDR1: 607 case MII_PHYIDR2: 608 return(0); 609 default: 610 device_printf(dev, "bad phy register\n"); 611 return(0); 612 } 613 CSR_WRITE_2(sc, rl8139_reg, data); 614 return(0); 615 } 616 617 bzero(&frame, sizeof(frame)); 618 619 frame.mii_phyaddr = phy; 620 frame.mii_regaddr = reg; 621 frame.mii_data = data; 622 623 rl_mii_writereg(sc, &frame); 624 625 return(0); 626 } 627 628 static void 629 rl_miibus_statchg(device_t dev) 630 { 631 } 632 633 /* 634 * Program the 64-bit multicast hash filter. 635 */ 636 static void 637 rl_setmulti(struct rl_softc *sc) 638 { 639 struct ifnet *ifp; 640 int h = 0; 641 uint32_t hashes[2] = { 0, 0 }; 642 struct ifmultiaddr *ifma; 643 uint32_t rxfilt; 644 int mcnt = 0; 645 646 ifp = &sc->arpcom.ac_if; 647 648 rxfilt = CSR_READ_4(sc, RL_RXCFG); 649 650 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 651 rxfilt |= RL_RXCFG_RX_MULTI; 652 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 653 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 654 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 655 return; 656 } 657 658 /* first, zot all the existing hash bits */ 659 CSR_WRITE_4(sc, RL_MAR0, 0); 660 CSR_WRITE_4(sc, RL_MAR4, 0); 661 662 /* now program new ones */ 663 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 664 if (ifma->ifma_addr->sa_family != AF_LINK) 665 continue; 666 h = ether_crc32_be( 667 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 668 ETHER_ADDR_LEN) >> 26; 669 if (h < 32) 670 hashes[0] |= (1 << h); 671 else 672 hashes[1] |= (1 << (h - 32)); 673 mcnt++; 674 } 675 676 if (mcnt) 677 rxfilt |= RL_RXCFG_RX_MULTI; 678 else 679 rxfilt &= ~RL_RXCFG_RX_MULTI; 680 681 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 682 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 683 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 684 } 685 686 static void 687 rl_reset(struct rl_softc *sc) 688 { 689 int i; 690 691 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 692 693 for (i = 0; i < RL_TIMEOUT; i++) { 694 DELAY(10); 695 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 696 break; 697 } 698 if (i == RL_TIMEOUT) 699 device_printf(sc->rl_dev, "reset never completed!\n"); 700 } 701 702 /* 703 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 704 * IDs against our list and return a device name if we find a match. 705 * 706 * Return with a value < 0 to give re(4) a change to attach. 707 */ 708 static int 709 rl_probe(device_t dev) 710 { 711 struct rl_type *t; 712 uint16_t product = pci_get_device(dev); 713 uint16_t vendor = pci_get_vendor(dev); 714 715 for (t = rl_devs; t->rl_name != NULL; t++) { 716 if (vendor == t->rl_vid && product == t->rl_did) { 717 device_set_desc(dev, t->rl_name); 718 return(-100); 719 } 720 } 721 722 return(ENXIO); 723 } 724 725 /* 726 * Attach the interface. Allocate softc structures, do ifmedia 727 * setup and ethernet/BPF attach. 728 */ 729 static int 730 rl_attach(device_t dev) 731 { 732 uint8_t eaddr[ETHER_ADDR_LEN]; 733 uint16_t as[3]; 734 struct rl_softc *sc; 735 struct ifnet *ifp; 736 uint16_t rl_did = 0; 737 int error = 0, rid, i; 738 739 sc = device_get_softc(dev); 740 sc->rl_dev = dev; 741 742 /* 743 * Handle power management nonsense. 744 */ 745 746 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 747 uint32_t iobase, membase, irq; 748 749 /* Save important PCI config data. */ 750 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 751 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 752 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 753 754 /* Reset the power state. */ 755 device_printf(dev, "chip is in D%d power mode " 756 "-- setting to D0\n", pci_get_powerstate(dev)); 757 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 758 759 /* Restore PCI config data. */ 760 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 761 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 762 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 763 } 764 765 pci_enable_busmaster(dev); 766 767 rid = RL_RID; 768 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE); 769 770 if (sc->rl_res == NULL) { 771 device_printf(dev, "couldn't map ports/memory\n"); 772 error = ENXIO; 773 goto fail; 774 } 775 776 sc->rl_btag = rman_get_bustag(sc->rl_res); 777 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 778 779 rid = 0; 780 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 781 RF_SHAREABLE | RF_ACTIVE); 782 783 if (sc->rl_irq == NULL) { 784 device_printf(dev, "couldn't map interrupt\n"); 785 error = ENXIO; 786 goto fail; 787 } 788 789 callout_init(&sc->rl_stat_timer); 790 791 /* Reset the adapter. */ 792 rl_reset(sc); 793 794 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 795 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0); 796 if (rl_did != 0x8129) 797 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 798 799 /* 800 * Get station address from the EEPROM. 801 */ 802 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 803 for (i = 0; i < 3; i++) { 804 eaddr[(i * 2) + 0] = as[i] & 0xff; 805 eaddr[(i * 2) + 1] = as[i] >> 8; 806 } 807 808 /* 809 * Now read the exact device type from the EEPROM to find 810 * out if it's an 8129 or 8139. 811 */ 812 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 813 814 if (rl_did == PCI_PRODUCT_REALTEK_RT8139 || 815 rl_did == PCI_PRODUCT_ACCTON_MPX5030 || 816 rl_did == PCI_PRODUCT_DELTA_8139 || 817 rl_did == PCI_PRODUCT_ADDTRON_8139 || 818 rl_did == PCI_PRODUCT_DLINK_DFE530TXPLUS || 819 rl_did == PCI_PRODUCT_REALTEK_RT8139B || 820 rl_did == PCI_PRODUCT_DLINK_DFE690TXD || 821 rl_did == PCI_PRODUCT_COREGA_CB_TXD || 822 rl_did == PCI_PRODUCT_COREGA_2CB_TXD || 823 rl_did == PCI_PRODUCT_PLANEX_FNW_3800_TX) { 824 sc->rl_type = RL_8139; 825 } else if (rl_did == PCI_PRODUCT_REALTEK_RT8129) { 826 sc->rl_type = RL_8129; 827 } else { 828 device_printf(dev, "unknown device ID: %x\n", rl_did); 829 sc->rl_type = RL_8139; 830 /* 831 * Read RL_IDR register to get ethernet address as accessing 832 * EEPROM may not extract correct address. 833 */ 834 for (i = 0; i < ETHER_ADDR_LEN; i++) 835 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 836 } 837 838 error = rl_dma_alloc(sc); 839 if (error) 840 goto fail; 841 842 /* Do MII setup */ 843 if (mii_phy_probe(dev, &sc->rl_miibus, rl_ifmedia_upd, 844 rl_ifmedia_sts)) { 845 device_printf(dev, "MII without any phy!\n"); 846 error = ENXIO; 847 goto fail; 848 } 849 850 ifp = &sc->arpcom.ac_if; 851 ifp->if_softc = sc; 852 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 853 ifp->if_mtu = ETHERMTU; 854 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 855 ifp->if_ioctl = rl_ioctl; 856 ifp->if_start = rl_start; 857 ifp->if_watchdog = rl_watchdog; 858 ifp->if_init = rl_init; 859 ifp->if_baudrate = 10000000; 860 ifp->if_capabilities = IFCAP_VLAN_MTU; 861 #ifdef DEVICE_POLLING 862 ifp->if_poll = rl_poll; 863 #endif 864 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 865 ifq_set_ready(&ifp->if_snd); 866 867 /* 868 * Call MI attach routine. 869 */ 870 ether_ifattach(ifp, eaddr, NULL); 871 872 error = bus_setup_intr(dev, sc->rl_irq, INTR_MPSAFE, rl_intr, 873 sc, &sc->rl_intrhand, ifp->if_serializer); 874 875 if (error) { 876 device_printf(dev, "couldn't set up irq\n"); 877 ether_ifdetach(ifp); 878 goto fail; 879 } 880 881 ifp->if_cpuid = rman_get_cpuid(sc->rl_irq); 882 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 883 884 return(0); 885 886 fail: 887 rl_detach(dev); 888 return(error); 889 } 890 891 static int 892 rl_detach(device_t dev) 893 { 894 struct rl_softc *sc; 895 struct ifnet *ifp; 896 897 sc = device_get_softc(dev); 898 ifp = &sc->arpcom.ac_if; 899 900 if (device_is_attached(dev)) { 901 lwkt_serialize_enter(ifp->if_serializer); 902 rl_stop(sc); 903 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 904 lwkt_serialize_exit(ifp->if_serializer); 905 906 ether_ifdetach(ifp); 907 } 908 909 if (sc->rl_miibus) 910 device_delete_child(dev, sc->rl_miibus); 911 bus_generic_detach(dev); 912 913 if (sc->rl_irq) 914 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 915 if (sc->rl_res) 916 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 917 918 rl_dma_free(sc); 919 920 return(0); 921 } 922 923 /* 924 * Initialize the transmit descriptors. 925 */ 926 static void 927 rl_list_tx_init(struct rl_softc *sc) 928 { 929 struct rl_chain_data *cd; 930 int i; 931 932 cd = &sc->rl_cdata; 933 for (i = 0; i < RL_TX_LIST_CNT; i++) { 934 cd->rl_tx_chain[i] = NULL; 935 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 936 0x0000000); 937 } 938 939 sc->rl_cdata.cur_tx = 0; 940 sc->rl_cdata.last_tx = 0; 941 } 942 943 /* 944 * A frame has been uploaded: pass the resulting mbuf chain up to 945 * the higher level protocols. 946 * 947 * You know there's something wrong with a PCI bus-master chip design 948 * when you have to use m_devget(). 949 * 950 * The receive operation is badly documented in the datasheet, so I'll 951 * attempt to document it here. The driver provides a buffer area and 952 * places its base address in the RX buffer start address register. 953 * The chip then begins copying frames into the RX buffer. Each frame 954 * is preceded by a 32-bit RX status word which specifies the length 955 * of the frame and certain other status bits. Each frame (starting with 956 * the status word) is also 32-bit aligned. The frame length is in the 957 * first 16 bits of the status word; the lower 15 bits correspond with 958 * the 'rx status register' mentioned in the datasheet. 959 * 960 * Note: to make the Alpha happy, the frame payload needs to be aligned 961 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 962 * the ring buffer starting at an address two bytes before the actual 963 * data location. We can then shave off the first two bytes using m_adj(). 964 * The reason we do this is because m_devget() doesn't let us specify an 965 * offset into the mbuf storage space, so we have to artificially create 966 * one. The ring is allocated in such a way that there are a few unused 967 * bytes of space preceecing it so that it will be safe for us to do the 968 * 2-byte backstep even if reading from the ring at offset 0. 969 */ 970 static void 971 rl_rxeof(struct rl_softc *sc) 972 { 973 struct mbuf *m; 974 struct ifnet *ifp; 975 int total_len = 0; 976 uint32_t rxstat; 977 caddr_t rxbufpos; 978 int wrap = 0; 979 uint16_t cur_rx, limit, max_bytes, rx_bytes = 0; 980 981 ifp = &sc->arpcom.ac_if; 982 983 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 984 985 /* Do not try to read past this point. */ 986 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 987 988 if (limit < cur_rx) 989 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 990 else 991 max_bytes = limit - cur_rx; 992 993 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 994 #ifdef DEVICE_POLLING 995 if (ifp->if_flags & IFF_POLLING) { 996 if (sc->rxcycles <= 0) 997 break; 998 sc->rxcycles--; 999 } 1000 #endif /* DEVICE_POLLING */ 1001 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1002 rxstat = le32toh(*(uint32_t *)rxbufpos); 1003 1004 /* 1005 * Here's a totally undocumented fact for you. When the 1006 * RealTek chip is in the process of copying a packet into 1007 * RAM for you, the length will be 0xfff0. If you spot a 1008 * packet header with this value, you need to stop. The 1009 * datasheet makes absolutely no mention of this and 1010 * RealTek should be shot for this. 1011 */ 1012 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1013 break; 1014 1015 if ((rxstat & RL_RXSTAT_RXOK) == 0) { 1016 ifp->if_ierrors++; 1017 rl_init(sc); 1018 return; 1019 } 1020 1021 /* No errors; receive the packet. */ 1022 total_len = rxstat >> 16; 1023 rx_bytes += total_len + 4; 1024 1025 /* 1026 * XXX The RealTek chip includes the CRC with every 1027 * received frame, and there's no way to turn this 1028 * behavior off (at least, I can't find anything in 1029 * the manual that explains how to do it) so we have 1030 * to trim off the CRC manually. 1031 */ 1032 total_len -= ETHER_CRC_LEN; 1033 1034 /* 1035 * Avoid trying to read more bytes than we know 1036 * the chip has prepared for us. 1037 */ 1038 if (rx_bytes > max_bytes) 1039 break; 1040 1041 rxbufpos = sc->rl_cdata.rl_rx_buf + 1042 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN); 1043 1044 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1045 rxbufpos = sc->rl_cdata.rl_rx_buf; 1046 1047 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1048 1049 if (total_len > wrap) { 1050 /* 1051 * Fool m_devget() into thinking we want to copy 1052 * the whole buffer so we don't end up fragmenting 1053 * the data. 1054 */ 1055 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1056 wrap + RL_ETHER_ALIGN, 0, ifp, NULL); 1057 if (m == NULL) { 1058 ifp->if_ierrors++; 1059 } else { 1060 m_adj(m, RL_ETHER_ALIGN); 1061 m_copyback(m, wrap, total_len - wrap, 1062 sc->rl_cdata.rl_rx_buf); 1063 } 1064 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1065 } else { 1066 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1067 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1068 if (m == NULL) { 1069 ifp->if_ierrors++; 1070 } else 1071 m_adj(m, RL_ETHER_ALIGN); 1072 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1073 } 1074 1075 /* 1076 * Round up to 32-bit boundary. 1077 */ 1078 cur_rx = (cur_rx + 3) & ~3; 1079 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1080 1081 if (m == NULL) 1082 continue; 1083 1084 ifp->if_ipackets++; 1085 1086 ifp->if_input(ifp, m); 1087 } 1088 } 1089 1090 /* 1091 * A frame was downloaded to the chip. It's safe for us to clean up 1092 * the list buffers. 1093 */ 1094 static void 1095 rl_txeof(struct rl_softc *sc) 1096 { 1097 struct ifnet *ifp; 1098 uint32_t txstat; 1099 1100 ifp = &sc->arpcom.ac_if; 1101 1102 /* 1103 * Go through our tx list and free mbufs for those 1104 * frames that have been uploaded. 1105 */ 1106 do { 1107 if (RL_LAST_TXMBUF(sc) == NULL) 1108 break; 1109 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1110 if ((txstat & (RL_TXSTAT_TX_OK | RL_TXSTAT_TX_UNDERRUN | 1111 RL_TXSTAT_TXABRT)) == 0) 1112 break; 1113 1114 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1115 1116 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc)); 1117 m_freem(RL_LAST_TXMBUF(sc)); 1118 RL_LAST_TXMBUF(sc) = NULL; 1119 RL_INC(sc->rl_cdata.last_tx); 1120 1121 if (txstat & RL_TXSTAT_TX_UNDERRUN) { 1122 sc->rl_txthresh += 32; 1123 if (sc->rl_txthresh > RL_TX_THRESH_MAX) 1124 sc->rl_txthresh = RL_TX_THRESH_MAX; 1125 } 1126 1127 if (txstat & RL_TXSTAT_TX_OK) { 1128 ifp->if_opackets++; 1129 } else { 1130 ifp->if_oerrors++; 1131 if (txstat & (RL_TXSTAT_TXABRT | RL_TXSTAT_OUTOFWIN)) 1132 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1133 } 1134 ifp->if_flags &= ~IFF_OACTIVE; 1135 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1136 1137 if (RL_LAST_TXMBUF(sc) == NULL) 1138 ifp->if_timer = 0; 1139 else if (ifp->if_timer == 0) 1140 ifp->if_timer = 5; 1141 } 1142 1143 static void 1144 rl_tick(void *xsc) 1145 { 1146 struct rl_softc *sc = xsc; 1147 struct mii_data *mii; 1148 1149 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1150 1151 mii = device_get_softc(sc->rl_miibus); 1152 mii_tick(mii); 1153 1154 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc); 1155 1156 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1157 } 1158 1159 #ifdef DEVICE_POLLING 1160 1161 static void 1162 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1163 { 1164 struct rl_softc *sc = ifp->if_softc; 1165 1166 switch(cmd) { 1167 case POLL_REGISTER: 1168 /* disable interrupts */ 1169 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1170 break; 1171 case POLL_DEREGISTER: 1172 /* enable interrupts */ 1173 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1174 break; 1175 default: 1176 sc->rxcycles = count; 1177 rl_rxeof(sc); 1178 rl_txeof(sc); 1179 if (!ifq_is_empty(&ifp->if_snd)) 1180 if_devstart(ifp); 1181 1182 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1183 uint16_t status; 1184 1185 status = CSR_READ_2(sc, RL_ISR); 1186 if (status == 0xffff) 1187 return; 1188 if (status) 1189 CSR_WRITE_2(sc, RL_ISR, status); 1190 1191 /* 1192 * XXX check behaviour on receiver stalls. 1193 */ 1194 1195 if (status & RL_ISR_SYSTEM_ERR) { 1196 rl_reset(sc); 1197 rl_init(sc); 1198 } 1199 } 1200 break; 1201 } 1202 } 1203 #endif /* DEVICE_POLLING */ 1204 1205 static void 1206 rl_intr(void *arg) 1207 { 1208 struct rl_softc *sc; 1209 struct ifnet *ifp; 1210 uint16_t status; 1211 1212 sc = arg; 1213 1214 if (sc->suspended) 1215 return; 1216 1217 ifp = &sc->arpcom.ac_if; 1218 1219 for (;;) { 1220 status = CSR_READ_2(sc, RL_ISR); 1221 /* If the card has gone away, the read returns 0xffff. */ 1222 if (status == 0xffff) 1223 break; 1224 1225 if (status != 0) 1226 CSR_WRITE_2(sc, RL_ISR, status); 1227 1228 if ((status & RL_INTRS) == 0) 1229 break; 1230 1231 if (status & RL_ISR_RX_OK) 1232 rl_rxeof(sc); 1233 1234 if (status & RL_ISR_RX_ERR) 1235 rl_rxeof(sc); 1236 1237 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1238 rl_txeof(sc); 1239 1240 if (status & RL_ISR_SYSTEM_ERR) { 1241 rl_reset(sc); 1242 rl_init(sc); 1243 } 1244 1245 } 1246 1247 if (!ifq_is_empty(&ifp->if_snd)) 1248 if_devstart(ifp); 1249 } 1250 1251 /* 1252 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1253 * pointers to the fragment pointers. 1254 */ 1255 static int 1256 rl_encap(struct rl_softc *sc, struct mbuf *m_head) 1257 { 1258 struct mbuf *m_new = NULL; 1259 bus_dma_segment_t seg; 1260 int nseg, error; 1261 1262 /* 1263 * The RealTek is brain damaged and wants longword-aligned 1264 * TX buffers, plus we can only have one fragment buffer 1265 * per packet. We have to copy pretty much all the time. 1266 */ 1267 m_new = m_defrag(m_head, MB_DONTWAIT); 1268 if (m_new == NULL) { 1269 m_freem(m_head); 1270 return ENOBUFS; 1271 } 1272 m_head = m_new; 1273 1274 /* Pad frames to at least 60 bytes. */ 1275 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1276 error = m_devpad(m_head, RL_MIN_FRAMELEN); 1277 if (error) { 1278 m_freem(m_head); 1279 return error; 1280 } 1281 } 1282 1283 /* Extract physical address. */ 1284 error = bus_dmamap_load_mbuf_segment(sc->rl_cdata.rl_tx_tag, 1285 RL_CUR_DMAMAP(sc), m_head, 1286 &seg, 1, &nseg, BUS_DMA_NOWAIT); 1287 if (error) { 1288 m_freem(m_head); 1289 return error; 1290 } 1291 1292 /* Sync the loaded TX buffer. */ 1293 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc), 1294 BUS_DMASYNC_PREWRITE); 1295 1296 /* Transmit */ 1297 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), seg.ds_addr); 1298 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1299 RL_TXTHRESH(sc->rl_txthresh) | seg.ds_len); 1300 1301 RL_CUR_TXMBUF(sc) = m_head; 1302 return 0; 1303 } 1304 1305 /* 1306 * Main transmit routine. 1307 */ 1308 1309 static void 1310 rl_start(struct ifnet *ifp) 1311 { 1312 struct rl_softc *sc = ifp->if_softc; 1313 struct mbuf *m_head = NULL; 1314 1315 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 1316 return; 1317 1318 while (RL_CUR_TXMBUF(sc) == NULL) { 1319 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1320 if (m_head == NULL) 1321 break; 1322 1323 if (rl_encap(sc, m_head)) 1324 continue; 1325 1326 /* 1327 * If there's a BPF listener, bounce a copy of this frame 1328 * to him. 1329 */ 1330 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1331 1332 RL_INC(sc->rl_cdata.cur_tx); 1333 1334 /* 1335 * Set a timeout in case the chip goes out to lunch. 1336 */ 1337 ifp->if_timer = 5; 1338 } 1339 1340 /* 1341 * We broke out of the loop because all our TX slots are 1342 * full. Mark the NIC as busy until it drains some of the 1343 * packets from the queue. 1344 */ 1345 if (RL_CUR_TXMBUF(sc) != NULL) 1346 ifp->if_flags |= IFF_OACTIVE; 1347 } 1348 1349 static void 1350 rl_init(void *xsc) 1351 { 1352 struct rl_softc *sc = xsc; 1353 struct ifnet *ifp = &sc->arpcom.ac_if; 1354 struct mii_data *mii; 1355 uint32_t rxcfg = 0; 1356 1357 mii = device_get_softc(sc->rl_miibus); 1358 1359 /* 1360 * Cancel pending I/O and free all RX/TX buffers. 1361 */ 1362 rl_stop(sc); 1363 1364 /* 1365 * Init our MAC address. Even though the chipset documentation 1366 * doesn't mention it, we need to enter "Config register write enable" 1367 * mode to modify the ID registers. 1368 */ 1369 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1370 CSR_WRITE_STREAM_4(sc, RL_IDR0, 1371 *(uint32_t *)(&sc->arpcom.ac_enaddr[0])); 1372 CSR_WRITE_STREAM_4(sc, RL_IDR4, 1373 *(uint32_t *)(&sc->arpcom.ac_enaddr[4])); 1374 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1375 1376 /* Init the RX buffer pointer register. */ 1377 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr); 1378 1379 /* Init TX descriptors. */ 1380 rl_list_tx_init(sc); 1381 1382 /* 1383 * Enable transmit and receive. 1384 */ 1385 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1386 1387 /* 1388 * Set the initial TX and RX configuration. 1389 */ 1390 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1391 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1392 1393 /* Set the individual bit to receive frames for this host only. */ 1394 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1395 rxcfg |= RL_RXCFG_RX_INDIV; 1396 1397 /* If we want promiscuous mode, set the allframes bit. */ 1398 if (ifp->if_flags & IFF_PROMISC) { 1399 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1400 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1401 } else { 1402 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1403 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1404 } 1405 1406 /* 1407 * Set capture broadcast bit to capture broadcast frames. 1408 */ 1409 if (ifp->if_flags & IFF_BROADCAST) { 1410 rxcfg |= RL_RXCFG_RX_BROAD; 1411 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1412 } else { 1413 rxcfg &= ~RL_RXCFG_RX_BROAD; 1414 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1415 } 1416 1417 /* 1418 * Program the multicast filter, if necessary. 1419 */ 1420 rl_setmulti(sc); 1421 1422 #ifdef DEVICE_POLLING 1423 /* 1424 * Only enable interrupts if we are polling, keep them off otherwise. 1425 */ 1426 if (ifp->if_flags & IFF_POLLING) 1427 CSR_WRITE_2(sc, RL_IMR, 0); 1428 else 1429 #endif /* DEVICE_POLLING */ 1430 /* 1431 * Enable interrupts. 1432 */ 1433 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1434 1435 /* Set initial TX threshold */ 1436 sc->rl_txthresh = RL_TX_THRESH_INIT; 1437 1438 /* Start RX/TX process. */ 1439 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1440 1441 /* Enable receiver and transmitter. */ 1442 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1443 1444 mii_mediachg(mii); 1445 1446 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1447 1448 ifp->if_flags |= IFF_RUNNING; 1449 ifp->if_flags &= ~IFF_OACTIVE; 1450 1451 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc); 1452 } 1453 1454 /* 1455 * Set media options. 1456 */ 1457 static int 1458 rl_ifmedia_upd(struct ifnet *ifp) 1459 { 1460 struct rl_softc *sc; 1461 struct mii_data *mii; 1462 1463 sc = ifp->if_softc; 1464 mii = device_get_softc(sc->rl_miibus); 1465 mii_mediachg(mii); 1466 1467 return(0); 1468 } 1469 1470 /* 1471 * Report current media status. 1472 */ 1473 static void 1474 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1475 { 1476 struct rl_softc *sc = ifp->if_softc; 1477 struct mii_data *mii = device_get_softc(sc->rl_miibus); 1478 1479 mii_pollstat(mii); 1480 ifmr->ifm_active = mii->mii_media_active; 1481 ifmr->ifm_status = mii->mii_media_status; 1482 } 1483 1484 static int 1485 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1486 { 1487 struct rl_softc *sc = ifp->if_softc; 1488 struct ifreq *ifr = (struct ifreq *) data; 1489 struct mii_data *mii; 1490 int error = 0; 1491 1492 switch (command) { 1493 case SIOCSIFFLAGS: 1494 if (ifp->if_flags & IFF_UP) { 1495 rl_init(sc); 1496 } else { 1497 if (ifp->if_flags & IFF_RUNNING) 1498 rl_stop(sc); 1499 } 1500 error = 0; 1501 break; 1502 case SIOCADDMULTI: 1503 case SIOCDELMULTI: 1504 rl_setmulti(sc); 1505 error = 0; 1506 break; 1507 case SIOCGIFMEDIA: 1508 case SIOCSIFMEDIA: 1509 mii = device_get_softc(sc->rl_miibus); 1510 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1511 break; 1512 case SIOCSIFCAP: 1513 break; 1514 default: 1515 error = ether_ioctl(ifp, command, data); 1516 break; 1517 } 1518 1519 return(error); 1520 } 1521 1522 static void 1523 rl_watchdog(struct ifnet *ifp) 1524 { 1525 struct rl_softc *sc = ifp->if_softc; 1526 1527 device_printf(sc->rl_dev, "watchdog timeout\n"); 1528 1529 ifp->if_oerrors++; 1530 1531 rl_txeof(sc); 1532 rl_rxeof(sc); 1533 rl_init(sc); 1534 } 1535 1536 /* 1537 * Stop the adapter and free any mbufs allocated to the 1538 * RX and TX lists. 1539 */ 1540 static void 1541 rl_stop(struct rl_softc *sc) 1542 { 1543 struct ifnet *ifp = &sc->arpcom.ac_if; 1544 int i; 1545 1546 ifp->if_timer = 0; 1547 1548 callout_stop(&sc->rl_stat_timer); 1549 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1550 1551 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1552 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1553 1554 /* 1555 * Free the TX list buffers. 1556 */ 1557 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1558 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1559 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, 1560 sc->rl_cdata.rl_tx_dmamap[i]); 1561 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1562 sc->rl_cdata.rl_tx_chain[i] = NULL; 1563 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 1564 0x0000000); 1565 } 1566 } 1567 } 1568 1569 /* 1570 * Stop all chip I/O so that the kernel's probe routines don't 1571 * get confused by errant DMAs when rebooting. 1572 */ 1573 static void 1574 rl_shutdown(device_t dev) 1575 { 1576 struct rl_softc *sc; 1577 1578 sc = device_get_softc(dev); 1579 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1580 rl_stop(sc); 1581 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1582 } 1583 1584 /* 1585 * Device suspend routine. Stop the interface and save some PCI 1586 * settings in case the BIOS doesn't restore them properly on 1587 * resume. 1588 */ 1589 static int 1590 rl_suspend(device_t dev) 1591 { 1592 struct rl_softc *sc = device_get_softc(dev); 1593 int i; 1594 1595 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1596 rl_stop(sc); 1597 1598 for (i = 0; i < 5; i++) 1599 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1600 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1601 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1602 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1603 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1604 1605 sc->suspended = 1; 1606 1607 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1608 return (0); 1609 } 1610 1611 /* 1612 * Device resume routine. Restore some PCI settings in case the BIOS 1613 * doesn't, re-enable busmastering, and restart the interface if 1614 * appropriate. 1615 */ 1616 static int 1617 rl_resume(device_t dev) 1618 { 1619 struct rl_softc *sc = device_get_softc(dev); 1620 struct ifnet *ifp = &sc->arpcom.ac_if; 1621 int i; 1622 1623 lwkt_serialize_enter(ifp->if_serializer); 1624 1625 /* better way to do this? */ 1626 for (i = 0; i < 5; i++) 1627 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 1628 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1629 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1630 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1631 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1632 1633 /* reenable busmastering */ 1634 pci_enable_busmaster(dev); 1635 pci_enable_io(dev, RL_RES); 1636 1637 /* reinitialize interface if necessary */ 1638 if (ifp->if_flags & IFF_UP) 1639 rl_init(sc); 1640 1641 sc->suspended = 0; 1642 lwkt_serialize_exit(ifp->if_serializer); 1643 return (0); 1644 } 1645 1646 static int 1647 rl_dma_alloc(struct rl_softc *sc) 1648 { 1649 bus_dmamem_t dmem; 1650 int error, i; 1651 1652 error = bus_dma_tag_create(NULL, /* parent */ 1653 1, 0, /* alignment, boundary */ 1654 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1655 BUS_SPACE_MAXADDR, /* highaddr */ 1656 NULL, NULL, /* filter, filterarg */ 1657 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 1658 0, /* nsegments */ 1659 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1660 0, /* flags */ 1661 &sc->rl_parent_tag); 1662 if (error) { 1663 device_printf(sc->rl_dev, "can't create parent tag\n"); 1664 return error; 1665 } 1666 1667 /* Allocate a chunk of coherent memory for RX */ 1668 error = bus_dmamem_coherent(sc->rl_parent_tag, 1, 0, 1669 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1670 RL_RXBUFLEN + 1518, BUS_DMA_WAITOK, &dmem); 1671 if (error) 1672 return error; 1673 1674 sc->rl_cdata.rl_rx_tag = dmem.dmem_tag; 1675 sc->rl_cdata.rl_rx_dmamap = dmem.dmem_map; 1676 sc->rl_cdata.rl_rx_buf_ptr = dmem.dmem_addr; 1677 1678 /* NOTE: Apply same adjustment to vaddr and paddr */ 1679 sc->rl_cdata.rl_rx_buf = sc->rl_cdata.rl_rx_buf_ptr + sizeof(uint64_t); 1680 sc->rl_cdata.rl_rx_buf_paddr = dmem.dmem_busaddr + sizeof(uint64_t); 1681 1682 /* 1683 * Allocate TX mbuf's DMA tag and maps 1684 */ 1685 error = bus_dma_tag_create(sc->rl_parent_tag,/* parent */ 1686 RL_TXBUF_ALIGN, 0, /* alignment, boundary */ 1687 BUS_SPACE_MAXADDR, /* lowaddr */ 1688 BUS_SPACE_MAXADDR, /* highaddr */ 1689 NULL, NULL, /* filter, filterarg */ 1690 MCLBYTES, /* maxsize */ 1691 1, /* nsegments */ 1692 MCLBYTES, /* maxsegsize */ 1693 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | 1694 BUS_DMA_ALIGNED, /* flags */ 1695 &sc->rl_cdata.rl_tx_tag); 1696 if (error) { 1697 device_printf(sc->rl_dev, "can't create TX mbuf tag\n"); 1698 return error; 1699 } 1700 1701 for (i = 0; i < RL_TX_LIST_CNT; ++i) { 1702 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 1703 BUS_DMA_WAITOK, &sc->rl_cdata.rl_tx_dmamap[i]); 1704 if (error) { 1705 int j; 1706 1707 for (j = 0; j < i; ++j) { 1708 bus_dmamap_destroy(sc->rl_cdata.rl_tx_tag, 1709 sc->rl_cdata.rl_tx_dmamap[j]); 1710 } 1711 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag); 1712 sc->rl_cdata.rl_tx_tag = NULL; 1713 1714 device_printf(sc->rl_dev, "can't create TX mbuf map\n"); 1715 return error; 1716 } 1717 } 1718 return 0; 1719 } 1720 1721 static void 1722 rl_dma_free(struct rl_softc *sc) 1723 { 1724 if (sc->rl_cdata.rl_tx_tag != NULL) { 1725 int i; 1726 1727 for (i = 0; i < RL_TX_LIST_CNT; ++i) { 1728 bus_dmamap_destroy(sc->rl_cdata.rl_tx_tag, 1729 sc->rl_cdata.rl_tx_dmamap[i]); 1730 } 1731 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag); 1732 } 1733 1734 if (sc->rl_cdata.rl_rx_tag != NULL) { 1735 bus_dmamap_unload(sc->rl_cdata.rl_rx_tag, 1736 sc->rl_cdata.rl_rx_dmamap); 1737 /* NOTE: Use rl_rx_buf_ptr here */ 1738 bus_dmamem_free(sc->rl_cdata.rl_rx_tag, 1739 sc->rl_cdata.rl_rx_buf_ptr, 1740 sc->rl_cdata.rl_rx_dmamap); 1741 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag); 1742 } 1743 1744 if (sc->rl_parent_tag) 1745 bus_dma_tag_destroy(sc->rl_parent_tag); 1746 } 1747