1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/rl/if_rl.c,v 1.32 2006/08/06 12:49:06 swildner Exp $ 34 */ 35 36 /* 37 * RealTek 8129/8139 PCI NIC driver 38 * 39 * Supports several extremely cheap PCI 10/100 adapters based on 40 * the RealTek chipset. Datasheets can be obtained from 41 * www.realtek.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 50 * probably the worst PCI ethernet controller ever made, with the possible 51 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 52 * DMA, but it has a terrible interface that nullifies any performance 53 * gains that bus-master DMA usually offers. 54 * 55 * For transmission, the chip offers a series of four TX descriptor 56 * registers. Each transmit frame must be in a contiguous buffer, aligned 57 * on a longword (32-bit) boundary. This means we almost always have to 58 * do mbuf copies in order to transmit a frame, except in the unlikely 59 * case where a) the packet fits into a single mbuf, and b) the packet 60 * is 32-bit aligned within the mbuf's data area. The presence of only 61 * four descriptor registers means that we can never have more than four 62 * packets queued for transmission at any one time. 63 * 64 * Reception is not much better. The driver has to allocate a single large 65 * buffer area (up to 64K in size) into which the chip will DMA received 66 * frames. Because we don't know where within this region received packets 67 * will begin or end, we have no choice but to copy data from the buffer 68 * area into mbufs in order to pass the packets up to the higher protocol 69 * levels. 70 * 71 * It's impossible given this rotten design to really achieve decent 72 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 73 * some equally overmuscled CPU to drive it. 74 * 75 * On the bright side, the 8139 does have a built-in PHY, although 76 * rather than using an MDIO serial interface like most other NICs, the 77 * PHY registers are directly accessible through the 8139's register 78 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 79 * filter. 80 * 81 * The 8129 chip is an older version of the 8139 that uses an external PHY 82 * chip. The 8129 has a serial MDIO interface for accessing the MII where 83 * the 8139 lets you directly access the on-board PHY registers. We need 84 * to select which interface to use depending on the chip type. 85 */ 86 87 #include "opt_polling.h" 88 89 #include <sys/param.h> 90 #include <sys/endian.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/module.h> 97 #include <sys/socket.h> 98 #include <sys/serialize.h> 99 #include <sys/thread2.h> 100 101 #include <net/if.h> 102 #include <net/ifq_var.h> 103 #include <net/if_arp.h> 104 #include <net/ethernet.h> 105 #include <net/if_dl.h> 106 #include <net/if_media.h> 107 108 #include <net/bpf.h> 109 110 #include <machine/bus_pio.h> 111 #include <machine/bus_memio.h> 112 #include <machine/bus.h> 113 #include <machine/resource.h> 114 #include <sys/bus.h> 115 #include <sys/rman.h> 116 117 #include <dev/netif/mii_layer/mii.h> 118 #include <dev/netif/mii_layer/miivar.h> 119 120 #include <bus/pci/pcidevs.h> 121 #include <bus/pci/pcireg.h> 122 #include <bus/pci/pcivar.h> 123 124 /* "controller miibus0" required. See GENERIC if you get errors here. */ 125 #include "miibus_if.h" 126 127 /* 128 * Default to using PIO access for this driver. On SMP systems, 129 * there appear to be problems with memory mapped mode: it looks like 130 * doing too many memory mapped access back to back in rapid succession 131 * can hang the bus. I'm inclined to blame this on crummy design/construction 132 * on the part of RealTek. Memory mapped mode does appear to work on 133 * uniprocessor systems though. 134 */ 135 #define RL_USEIOSPACE 136 137 #include <dev/netif/rl/if_rlreg.h> 138 139 /* 140 * Various supported device vendors/types and their names. 141 */ 142 static struct rl_type { 143 uint16_t rl_vid; 144 uint16_t rl_did; 145 const char *rl_name; 146 } rl_devs[] = { 147 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8129, 148 "RealTek 8129 10/100BaseTX" }, 149 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, 150 "RealTek 8139 10/100BaseTX" }, 151 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139B, 152 "RealTek 8139 10/100BaseTX CardBus" }, 153 { PCI_VENDOR_ACCTON, PCI_PRODUCT_ACCTON_MPX5030, 154 "Accton MPX 5030/5038 10/100BaseTX" }, 155 { PCI_VENDOR_DELTA, PCI_PRODUCT_DELTA_8139, 156 "Delta Electronics 8139 10/100BaseTX" }, 157 { PCI_VENDOR_ADDTRON, PCI_PRODUCT_ADDTRON_8139, 158 "Addtron Technolgy 8139 10/100BaseTX" }, 159 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE530TXPLUS, 160 "D-Link DFE-530TX+ 10/100BaseTX" }, 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE690TXD, 162 "D-Link DFE-690TX 10/100BaseTX" }, 163 { PCI_VENDOR_NORTEL, PCI_PRODUCT_NORTEL_BAYSTACK_21, 164 "Nortel Networks 10/100BaseTX" }, 165 { PCI_VENDOR_PEPPERCON, PCI_PRODUCT_PEPPERCON_ROLF, 166 "Peppercon AG ROL/F" }, 167 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CB_TXD, 168 "Corega FEther CB-TXD" }, 169 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_2CB_TXD, 170 "Corega FEtherII CB-TXD" }, 171 { PCI_VENDOR_PLANEX, PCI_PRODUCT_PLANEX_FNW_3800_TX, 172 "Planex FNW-3800-TX" }, 173 { 0, 0, NULL } 174 }; 175 176 static int rl_probe(device_t); 177 static int rl_attach(device_t); 178 static int rl_detach(device_t); 179 180 static int rl_encap(struct rl_softc *, struct mbuf * ); 181 182 static void rl_rxeof(struct rl_softc *); 183 static void rl_txeof(struct rl_softc *); 184 static void rl_intr(void *); 185 static void rl_tick(void *); 186 static void rl_start(struct ifnet *); 187 static int rl_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 188 static void rl_init(void *); 189 static void rl_stop (struct rl_softc *); 190 static void rl_watchdog(struct ifnet *); 191 static int rl_suspend(device_t); 192 static int rl_resume(device_t); 193 static void rl_shutdown(device_t); 194 static int rl_ifmedia_upd(struct ifnet *); 195 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 196 197 static void rl_eeprom_putbyte(struct rl_softc *, int); 198 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *); 199 static void rl_read_eeprom(struct rl_softc *, caddr_t, int, int, int); 200 static void rl_mii_sync(struct rl_softc *); 201 static void rl_mii_send(struct rl_softc *, uint32_t, int); 202 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *); 203 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *); 204 205 static int rl_miibus_readreg(device_t, int, int); 206 static int rl_miibus_writereg(device_t, int, int, int); 207 static void rl_miibus_statchg(device_t); 208 209 static void rl_setmulti(struct rl_softc *); 210 static void rl_reset(struct rl_softc *); 211 static void rl_list_tx_init(struct rl_softc *); 212 213 static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int); 214 static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int); 215 #ifdef DEVICE_POLLING 216 static poll_handler_t rl_poll; 217 #endif 218 219 #ifdef RL_USEIOSPACE 220 #define RL_RES SYS_RES_IOPORT 221 #define RL_RID RL_PCI_LOIO 222 #else 223 #define RL_RES SYS_RES_MEMORY 224 #define RL_RID RL_PCI_LOMEM 225 #endif 226 227 static device_method_t rl_methods[] = { 228 /* Device interface */ 229 DEVMETHOD(device_probe, rl_probe), 230 DEVMETHOD(device_attach, rl_attach), 231 DEVMETHOD(device_detach, rl_detach), 232 DEVMETHOD(device_suspend, rl_suspend), 233 DEVMETHOD(device_resume, rl_resume), 234 DEVMETHOD(device_shutdown, rl_shutdown), 235 236 /* bus interface */ 237 DEVMETHOD(bus_print_child, bus_generic_print_child), 238 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 239 240 /* MII interface */ 241 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 242 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 243 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 244 245 { 0, 0 } 246 }; 247 248 static DEFINE_CLASS_0(rl, rl_driver, rl_methods, sizeof(struct rl_softc)); 249 static devclass_t rl_devclass; 250 251 DECLARE_DUMMY_MODULE(if_rl); 252 DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 253 DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 254 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 255 MODULE_DEPEND(if_rl, miibus, 1, 1, 1); 256 257 #define EE_SET(x) \ 258 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) | (x)) 259 260 #define EE_CLR(x) \ 261 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) & ~(x)) 262 263 static void 264 rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) 265 { 266 struct rl_softc *sc = arg; 267 268 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 269 } 270 271 static void 272 rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) 273 { 274 struct rl_softc *sc = arg; 275 276 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 277 } 278 279 /* 280 * Send a read command and address to the EEPROM, check for ACK. 281 */ 282 static void 283 rl_eeprom_putbyte(struct rl_softc *sc, int addr) 284 { 285 int d, i; 286 287 d = addr | sc->rl_eecmd_read; 288 289 /* 290 * Feed in each bit and strobe the clock. 291 */ 292 for (i = 0x400; i; i >>= 1) { 293 if (d & i) 294 EE_SET(RL_EE_DATAIN); 295 else 296 EE_CLR(RL_EE_DATAIN); 297 DELAY(100); 298 EE_SET(RL_EE_CLK); 299 DELAY(150); 300 EE_CLR(RL_EE_CLK); 301 DELAY(100); 302 } 303 } 304 305 /* 306 * Read a word of data stored in the EEPROM at address 'addr.' 307 */ 308 static void 309 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest) 310 { 311 int i; 312 uint16_t word = 0; 313 314 /* Enter EEPROM access mode. */ 315 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 316 317 /* 318 * Send address of word we want to read. 319 */ 320 rl_eeprom_putbyte(sc, addr); 321 322 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 323 324 /* 325 * Start reading bits from EEPROM. 326 */ 327 for (i = 0x8000; i; i >>= 1) { 328 EE_SET(RL_EE_CLK); 329 DELAY(100); 330 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 331 word |= i; 332 EE_CLR(RL_EE_CLK); 333 DELAY(100); 334 } 335 336 /* Turn off EEPROM access mode. */ 337 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 338 339 *dest = word; 340 } 341 342 /* 343 * Read a sequence of words from the EEPROM. 344 */ 345 static void 346 rl_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt, int swap) 347 { 348 int i; 349 u_int16_t word = 0, *ptr; 350 351 for (i = 0; i < cnt; i++) { 352 rl_eeprom_getword(sc, off + i, &word); 353 ptr = (u_int16_t *)(dest + (i * 2)); 354 if (swap) 355 *ptr = ntohs(word); 356 else 357 *ptr = word; 358 } 359 } 360 361 362 /* 363 * MII access routines are provided for the 8129, which 364 * doesn't have a built-in PHY. For the 8139, we fake things 365 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 366 * direct access PHY registers. 367 */ 368 #define MII_SET(x) \ 369 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) | x) 370 371 #define MII_CLR(x) \ 372 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) & ~x) 373 374 /* 375 * Sync the PHYs by setting data bit and strobing the clock 32 times. 376 */ 377 static void 378 rl_mii_sync(struct rl_softc *sc) 379 { 380 int i; 381 382 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 383 384 for (i = 0; i < 32; i++) { 385 MII_SET(RL_MII_CLK); 386 DELAY(1); 387 MII_CLR(RL_MII_CLK); 388 DELAY(1); 389 } 390 } 391 392 /* 393 * Clock a series of bits through the MII. 394 */ 395 static void 396 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt) 397 { 398 int i; 399 400 MII_CLR(RL_MII_CLK); 401 402 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 403 if (bits & i) 404 MII_SET(RL_MII_DATAOUT); 405 else 406 MII_CLR(RL_MII_DATAOUT); 407 DELAY(1); 408 MII_CLR(RL_MII_CLK); 409 DELAY(1); 410 MII_SET(RL_MII_CLK); 411 } 412 } 413 414 /* 415 * Read an PHY register through the MII. 416 */ 417 static int 418 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame) 419 { 420 int ack, i; 421 422 /* 423 * Set up frame for RX. 424 */ 425 frame->mii_stdelim = RL_MII_STARTDELIM; 426 frame->mii_opcode = RL_MII_READOP; 427 frame->mii_turnaround = 0; 428 frame->mii_data = 0; 429 430 CSR_WRITE_2(sc, RL_MII, 0); 431 432 /* 433 * Turn on data xmit. 434 */ 435 MII_SET(RL_MII_DIR); 436 437 rl_mii_sync(sc); 438 439 /* 440 * Send command/address info. 441 */ 442 rl_mii_send(sc, frame->mii_stdelim, 2); 443 rl_mii_send(sc, frame->mii_opcode, 2); 444 rl_mii_send(sc, frame->mii_phyaddr, 5); 445 rl_mii_send(sc, frame->mii_regaddr, 5); 446 447 /* Idle bit */ 448 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 449 DELAY(1); 450 MII_SET(RL_MII_CLK); 451 DELAY(1); 452 453 /* Turn off xmit. */ 454 MII_CLR(RL_MII_DIR); 455 456 /* Check for ack */ 457 MII_CLR(RL_MII_CLK); 458 DELAY(1); 459 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 460 MII_SET(RL_MII_CLK); 461 DELAY(1); 462 463 /* 464 * Now try reading data bits. If the ack failed, we still 465 * need to clock through 16 cycles to keep the PHY(s) in sync. 466 */ 467 if (ack) { 468 for(i = 0; i < 16; i++) { 469 MII_CLR(RL_MII_CLK); 470 DELAY(1); 471 MII_SET(RL_MII_CLK); 472 DELAY(1); 473 } 474 } else { 475 for (i = 0x8000; i; i >>= 1) { 476 MII_CLR(RL_MII_CLK); 477 DELAY(1); 478 if (!ack) { 479 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 480 frame->mii_data |= i; 481 DELAY(1); 482 } 483 MII_SET(RL_MII_CLK); 484 DELAY(1); 485 } 486 } 487 488 MII_CLR(RL_MII_CLK); 489 DELAY(1); 490 MII_SET(RL_MII_CLK); 491 DELAY(1); 492 493 return(ack ? 1 : 0); 494 } 495 496 /* 497 * Write to a PHY register through the MII. 498 */ 499 static int 500 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame) 501 { 502 /* 503 * Set up frame for TX. 504 */ 505 frame->mii_stdelim = RL_MII_STARTDELIM; 506 frame->mii_opcode = RL_MII_WRITEOP; 507 frame->mii_turnaround = RL_MII_TURNAROUND; 508 509 /* 510 * Turn on data output. 511 */ 512 MII_SET(RL_MII_DIR); 513 514 rl_mii_sync(sc); 515 516 rl_mii_send(sc, frame->mii_stdelim, 2); 517 rl_mii_send(sc, frame->mii_opcode, 2); 518 rl_mii_send(sc, frame->mii_phyaddr, 5); 519 rl_mii_send(sc, frame->mii_regaddr, 5); 520 rl_mii_send(sc, frame->mii_turnaround, 2); 521 rl_mii_send(sc, frame->mii_data, 16); 522 523 /* Idle bit. */ 524 MII_SET(RL_MII_CLK); 525 DELAY(1); 526 MII_CLR(RL_MII_CLK); 527 DELAY(1); 528 529 /* 530 * Turn off xmit. 531 */ 532 MII_CLR(RL_MII_DIR); 533 534 return(0); 535 } 536 537 static int 538 rl_miibus_readreg(device_t dev, int phy, int reg) 539 { 540 struct rl_softc *sc; 541 struct rl_mii_frame frame; 542 uint16_t rval = 0; 543 uint16_t rl8139_reg = 0; 544 545 sc = device_get_softc(dev); 546 547 if (sc->rl_type == RL_8139) { 548 /* Pretend the internal PHY is only at address 0 */ 549 if (phy) 550 return(0); 551 switch (reg) { 552 case MII_BMCR: 553 rl8139_reg = RL_BMCR; 554 break; 555 case MII_BMSR: 556 rl8139_reg = RL_BMSR; 557 break; 558 case MII_ANAR: 559 rl8139_reg = RL_ANAR; 560 break; 561 case MII_ANER: 562 rl8139_reg = RL_ANER; 563 break; 564 case MII_ANLPAR: 565 rl8139_reg = RL_LPAR; 566 break; 567 case MII_PHYIDR1: 568 case MII_PHYIDR2: 569 return(0); 570 break; 571 /* 572 * Allow the rlphy driver to read the media status 573 * register. If we have a link partner which does not 574 * support NWAY, this is the register which will tell 575 * us the results of parallel detection. 576 */ 577 case RL_MEDIASTAT: 578 rval = CSR_READ_1(sc, RL_MEDIASTAT); 579 return(rval); 580 default: 581 device_printf(dev, "bad phy register\n"); 582 return(0); 583 } 584 rval = CSR_READ_2(sc, rl8139_reg); 585 return(rval); 586 } 587 588 bzero(&frame, sizeof(frame)); 589 590 frame.mii_phyaddr = phy; 591 frame.mii_regaddr = reg; 592 rl_mii_readreg(sc, &frame); 593 594 return(frame.mii_data); 595 } 596 597 static int 598 rl_miibus_writereg(device_t dev, int phy, int reg, int data) 599 { 600 struct rl_softc *sc; 601 struct rl_mii_frame frame; 602 u_int16_t rl8139_reg = 0; 603 604 sc = device_get_softc(dev); 605 606 if (sc->rl_type == RL_8139) { 607 /* Pretend the internal PHY is only at address 0 */ 608 if (phy) 609 return(0); 610 switch (reg) { 611 case MII_BMCR: 612 rl8139_reg = RL_BMCR; 613 break; 614 case MII_BMSR: 615 rl8139_reg = RL_BMSR; 616 break; 617 case MII_ANAR: 618 rl8139_reg = RL_ANAR; 619 break; 620 case MII_ANER: 621 rl8139_reg = RL_ANER; 622 break; 623 case MII_ANLPAR: 624 rl8139_reg = RL_LPAR; 625 break; 626 case MII_PHYIDR1: 627 case MII_PHYIDR2: 628 return(0); 629 default: 630 device_printf(dev, "bad phy register\n"); 631 return(0); 632 } 633 CSR_WRITE_2(sc, rl8139_reg, data); 634 return(0); 635 } 636 637 bzero(&frame, sizeof(frame)); 638 639 frame.mii_phyaddr = phy; 640 frame.mii_regaddr = reg; 641 frame.mii_data = data; 642 643 rl_mii_writereg(sc, &frame); 644 645 return(0); 646 } 647 648 static void 649 rl_miibus_statchg(device_t dev) 650 { 651 } 652 653 /* 654 * Program the 64-bit multicast hash filter. 655 */ 656 static void 657 rl_setmulti(struct rl_softc *sc) 658 { 659 struct ifnet *ifp; 660 int h = 0; 661 uint32_t hashes[2] = { 0, 0 }; 662 struct ifmultiaddr *ifma; 663 uint32_t rxfilt; 664 int mcnt = 0; 665 666 ifp = &sc->arpcom.ac_if; 667 668 rxfilt = CSR_READ_4(sc, RL_RXCFG); 669 670 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 671 rxfilt |= RL_RXCFG_RX_MULTI; 672 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 673 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 674 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 675 return; 676 } 677 678 /* first, zot all the existing hash bits */ 679 CSR_WRITE_4(sc, RL_MAR0, 0); 680 CSR_WRITE_4(sc, RL_MAR4, 0); 681 682 /* now program new ones */ 683 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 684 if (ifma->ifma_addr->sa_family != AF_LINK) 685 continue; 686 h = ether_crc32_be( 687 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 688 ETHER_ADDR_LEN) >> 26; 689 if (h < 32) 690 hashes[0] |= (1 << h); 691 else 692 hashes[1] |= (1 << (h - 32)); 693 mcnt++; 694 } 695 696 if (mcnt) 697 rxfilt |= RL_RXCFG_RX_MULTI; 698 else 699 rxfilt &= ~RL_RXCFG_RX_MULTI; 700 701 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 702 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 703 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 704 } 705 706 static void 707 rl_reset(struct rl_softc *sc) 708 { 709 int i; 710 711 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 712 713 for (i = 0; i < RL_TIMEOUT; i++) { 714 DELAY(10); 715 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 716 break; 717 } 718 if (i == RL_TIMEOUT) 719 device_printf(sc->rl_dev, "reset never completed!\n"); 720 } 721 722 /* 723 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 724 * IDs against our list and return a device name if we find a match. 725 * 726 * Return with a value < 0 to give re(4) a change to attach. 727 */ 728 static int 729 rl_probe(device_t dev) 730 { 731 struct rl_type *t; 732 uint16_t product = pci_get_device(dev); 733 uint16_t vendor = pci_get_vendor(dev); 734 735 for (t = rl_devs; t->rl_name != NULL; t++) { 736 if (vendor == t->rl_vid && product == t->rl_did) { 737 device_set_desc(dev, t->rl_name); 738 return(-100); 739 } 740 } 741 742 return(ENXIO); 743 } 744 745 /* 746 * Attach the interface. Allocate softc structures, do ifmedia 747 * setup and ethernet/BPF attach. 748 */ 749 static int 750 rl_attach(device_t dev) 751 { 752 uint8_t eaddr[ETHER_ADDR_LEN]; 753 uint16_t as[3]; 754 struct rl_softc *sc; 755 struct ifnet *ifp; 756 uint16_t rl_did = 0; 757 int error = 0, rid, i; 758 759 sc = device_get_softc(dev); 760 sc->rl_dev = dev; 761 762 /* 763 * Handle power management nonsense. 764 */ 765 766 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 767 uint32_t iobase, membase, irq; 768 769 /* Save important PCI config data. */ 770 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 771 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 772 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 773 774 /* Reset the power state. */ 775 device_printf(dev, "chip is is in D%d power mode " 776 "-- setting to D0\n", pci_get_powerstate(dev)); 777 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 778 779 /* Restore PCI config data. */ 780 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 781 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 782 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 783 } 784 785 pci_enable_busmaster(dev); 786 787 rid = RL_RID; 788 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE); 789 790 if (sc->rl_res == NULL) { 791 device_printf(dev, "couldn't map ports/memory\n"); 792 error = ENXIO; 793 goto fail; 794 } 795 796 sc->rl_btag = rman_get_bustag(sc->rl_res); 797 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 798 799 rid = 0; 800 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 801 RF_SHAREABLE | RF_ACTIVE); 802 803 if (sc->rl_irq == NULL) { 804 device_printf(dev, "couldn't map interrupt\n"); 805 error = ENXIO; 806 goto fail; 807 } 808 809 callout_init(&sc->rl_stat_timer); 810 811 /* Reset the adapter. */ 812 rl_reset(sc); 813 814 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 815 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0); 816 if (rl_did != 0x8129) 817 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 818 819 /* 820 * Get station address from the EEPROM. 821 */ 822 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 823 for (i = 0; i < 3; i++) { 824 eaddr[(i * 2) + 0] = as[i] & 0xff; 825 eaddr[(i * 2) + 1] = as[i] >> 8; 826 } 827 828 /* 829 * Now read the exact device type from the EEPROM to find 830 * out if it's an 8129 or 8139. 831 */ 832 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 833 834 if (rl_did == PCI_PRODUCT_REALTEK_RT8139 || 835 rl_did == PCI_PRODUCT_ACCTON_MPX5030 || 836 rl_did == PCI_PRODUCT_DELTA_8139 || 837 rl_did == PCI_PRODUCT_ADDTRON_8139 || 838 rl_did == PCI_PRODUCT_DLINK_DFE530TXPLUS || 839 rl_did == PCI_PRODUCT_REALTEK_RT8139B || 840 rl_did == PCI_PRODUCT_DLINK_DFE690TXD || 841 rl_did == PCI_PRODUCT_COREGA_CB_TXD || 842 rl_did == PCI_PRODUCT_COREGA_2CB_TXD || 843 rl_did == PCI_PRODUCT_PLANEX_FNW_3800_TX) 844 sc->rl_type = RL_8139; 845 else if (rl_did == PCI_PRODUCT_REALTEK_RT8129) 846 sc->rl_type = RL_8129; 847 else { 848 device_printf(dev, "unknown device ID: %x\n", rl_did); 849 error = ENXIO; 850 goto fail; 851 } 852 853 #define RL_NSEG_NEW 32 854 error = bus_dma_tag_create(NULL, /* parent */ 855 1, 0, /* alignment, boundary */ 856 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 857 BUS_SPACE_MAXADDR, /* highaddr */ 858 NULL, NULL, /* filter, filterarg */ 859 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 860 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 861 BUS_DMA_ALLOCNOW, /* flags */ 862 &sc->rl_parent_tag); 863 864 if (error) { 865 device_printf(dev, "can't create parent tag\n"); 866 goto fail; 867 } 868 869 /* 870 * Now allocate a tag for the DMA descriptor lists. 871 * All of our lists are allocated as a contiguous block 872 * of memory. 873 */ 874 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 875 1, 0, /* alignment, boundary */ 876 BUS_SPACE_MAXADDR, /* lowaddr */ 877 BUS_SPACE_MAXADDR, /* highaddr */ 878 NULL, NULL, /* filter, filterarg */ 879 RL_RXBUFLEN + 1518, 1, /* maxsize, nsegments */ 880 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 881 0, /* flags */ 882 &sc->rl_tag); 883 884 if (error) { 885 device_printf(dev, "can't create RX tag\n"); 886 goto fail; 887 } 888 889 /* 890 * Now allocate a chunk of DMA-able memory based on the tag 891 * we just created. 892 */ 893 error = bus_dmamem_alloc(sc->rl_tag, (void **)&sc->rl_cdata.rl_rx_buf, 894 BUS_DMA_WAITOK, &sc->rl_cdata.rl_rx_dmamap); 895 896 if (error) { 897 device_printf(dev, "can't allocate RX memory!\n"); 898 error = ENXIO; 899 goto fail; 900 } 901 902 /* Leave a few bytes before the start of the RX ring buffer. */ 903 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 904 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 905 906 /* Do MII setup */ 907 if (mii_phy_probe(dev, &sc->rl_miibus, rl_ifmedia_upd, 908 rl_ifmedia_sts)) { 909 device_printf(dev, "MII without any phy!\n"); 910 error = ENXIO; 911 goto fail; 912 } 913 914 ifp = &sc->arpcom.ac_if; 915 ifp->if_softc = sc; 916 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 917 ifp->if_mtu = ETHERMTU; 918 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 919 ifp->if_ioctl = rl_ioctl; 920 ifp->if_start = rl_start; 921 ifp->if_watchdog = rl_watchdog; 922 ifp->if_init = rl_init; 923 ifp->if_baudrate = 10000000; 924 ifp->if_capabilities = IFCAP_VLAN_MTU; 925 #ifdef DEVICE_POLLING 926 ifp->if_poll = rl_poll; 927 #endif 928 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 929 ifq_set_ready(&ifp->if_snd); 930 931 /* 932 * Call MI attach routine. 933 */ 934 ether_ifattach(ifp, eaddr, NULL); 935 936 error = bus_setup_intr(dev, sc->rl_irq, INTR_NETSAFE, rl_intr, 937 sc, &sc->rl_intrhand, ifp->if_serializer); 938 939 if (error) { 940 device_printf(dev, "couldn't set up irq\n"); 941 ether_ifdetach(ifp); 942 goto fail; 943 } 944 945 return(0); 946 947 fail: 948 rl_detach(dev); 949 return(error); 950 } 951 952 static int 953 rl_detach(device_t dev) 954 { 955 struct rl_softc *sc; 956 struct ifnet *ifp; 957 958 sc = device_get_softc(dev); 959 ifp = &sc->arpcom.ac_if; 960 961 if (device_is_attached(dev)) { 962 lwkt_serialize_enter(ifp->if_serializer); 963 rl_stop(sc); 964 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 965 lwkt_serialize_exit(ifp->if_serializer); 966 967 ether_ifdetach(ifp); 968 } 969 970 if (sc->rl_miibus) 971 device_delete_child(dev, sc->rl_miibus); 972 bus_generic_detach(dev); 973 974 if (sc->rl_irq) 975 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 976 if (sc->rl_res) 977 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 978 979 if (sc->rl_cdata.rl_rx_buf) { 980 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 981 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 982 sc->rl_cdata.rl_rx_dmamap); 983 } 984 if (sc->rl_tag) 985 bus_dma_tag_destroy(sc->rl_tag); 986 if (sc->rl_parent_tag) 987 bus_dma_tag_destroy(sc->rl_parent_tag); 988 989 return(0); 990 } 991 992 /* 993 * Initialize the transmit descriptors. 994 */ 995 static void 996 rl_list_tx_init(struct rl_softc *sc) 997 { 998 struct rl_chain_data *cd; 999 int i; 1000 1001 cd = &sc->rl_cdata; 1002 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1003 cd->rl_tx_chain[i] = NULL; 1004 CSR_WRITE_4(sc, 1005 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000); 1006 } 1007 1008 sc->rl_cdata.cur_tx = 0; 1009 sc->rl_cdata.last_tx = 0; 1010 } 1011 1012 /* 1013 * A frame has been uploaded: pass the resulting mbuf chain up to 1014 * the higher level protocols. 1015 * 1016 * You know there's something wrong with a PCI bus-master chip design 1017 * when you have to use m_devget(). 1018 * 1019 * The receive operation is badly documented in the datasheet, so I'll 1020 * attempt to document it here. The driver provides a buffer area and 1021 * places its base address in the RX buffer start address register. 1022 * The chip then begins copying frames into the RX buffer. Each frame 1023 * is preceded by a 32-bit RX status word which specifies the length 1024 * of the frame and certain other status bits. Each frame (starting with 1025 * the status word) is also 32-bit aligned. The frame length is in the 1026 * first 16 bits of the status word; the lower 15 bits correspond with 1027 * the 'rx status register' mentioned in the datasheet. 1028 * 1029 * Note: to make the Alpha happy, the frame payload needs to be aligned 1030 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 1031 * the ring buffer starting at an address two bytes before the actual 1032 * data location. We can then shave off the first two bytes using m_adj(). 1033 * The reason we do this is because m_devget() doesn't let us specify an 1034 * offset into the mbuf storage space, so we have to artificially create 1035 * one. The ring is allocated in such a way that there are a few unused 1036 * bytes of space preceecing it so that it will be safe for us to do the 1037 * 2-byte backstep even if reading from the ring at offset 0. 1038 */ 1039 static void 1040 rl_rxeof(struct rl_softc *sc) 1041 { 1042 struct mbuf *m; 1043 struct ifnet *ifp; 1044 int total_len = 0; 1045 uint32_t rxstat; 1046 caddr_t rxbufpos; 1047 int wrap = 0; 1048 uint16_t cur_rx, limit, max_bytes, rx_bytes = 0; 1049 1050 ifp = &sc->arpcom.ac_if; 1051 1052 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1053 BUS_DMASYNC_POSTREAD); 1054 1055 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1056 1057 /* Do not try to read past this point. */ 1058 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1059 1060 if (limit < cur_rx) 1061 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1062 else 1063 max_bytes = limit - cur_rx; 1064 1065 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1066 #ifdef DEVICE_POLLING 1067 if (ifp->if_flags & IFF_POLLING) { 1068 if (sc->rxcycles <= 0) 1069 break; 1070 sc->rxcycles--; 1071 } 1072 #endif /* DEVICE_POLLING */ 1073 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1074 rxstat = le32toh(*(uint32_t *)rxbufpos); 1075 1076 /* 1077 * Here's a totally undocumented fact for you. When the 1078 * RealTek chip is in the process of copying a packet into 1079 * RAM for you, the length will be 0xfff0. If you spot a 1080 * packet header with this value, you need to stop. The 1081 * datasheet makes absolutely no mention of this and 1082 * RealTek should be shot for this. 1083 */ 1084 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1085 break; 1086 1087 if ((rxstat & RL_RXSTAT_RXOK) == 0) { 1088 ifp->if_ierrors++; 1089 rl_init(sc); 1090 return; 1091 } 1092 1093 /* No errors; receive the packet. */ 1094 total_len = rxstat >> 16; 1095 rx_bytes += total_len + 4; 1096 1097 /* 1098 * XXX The RealTek chip includes the CRC with every 1099 * received frame, and there's no way to turn this 1100 * behavior off (at least, I can't find anything in 1101 * the manual that explains how to do it) so we have 1102 * to trim off the CRC manually. 1103 */ 1104 total_len -= ETHER_CRC_LEN; 1105 1106 /* 1107 * Avoid trying to read more bytes than we know 1108 * the chip has prepared for us. 1109 */ 1110 if (rx_bytes > max_bytes) 1111 break; 1112 1113 rxbufpos = sc->rl_cdata.rl_rx_buf + 1114 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN); 1115 1116 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1117 rxbufpos = sc->rl_cdata.rl_rx_buf; 1118 1119 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1120 1121 if (total_len > wrap) { 1122 /* 1123 * Fool m_devget() into thinking we want to copy 1124 * the whole buffer so we don't end up fragmenting 1125 * the data. 1126 */ 1127 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1128 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1129 if (m == NULL) { 1130 ifp->if_ierrors++; 1131 } else { 1132 m_adj(m, RL_ETHER_ALIGN); 1133 m_copyback(m, wrap, total_len - wrap, 1134 sc->rl_cdata.rl_rx_buf); 1135 } 1136 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1137 } else { 1138 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1139 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1140 if (m == NULL) { 1141 ifp->if_ierrors++; 1142 } else 1143 m_adj(m, RL_ETHER_ALIGN); 1144 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1145 } 1146 1147 /* 1148 * Round up to 32-bit boundary. 1149 */ 1150 cur_rx = (cur_rx + 3) & ~3; 1151 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1152 1153 if (m == NULL) 1154 continue; 1155 1156 ifp->if_ipackets++; 1157 1158 ifp->if_input(ifp, m); 1159 } 1160 } 1161 1162 /* 1163 * A frame was downloaded to the chip. It's safe for us to clean up 1164 * the list buffers. 1165 */ 1166 static void 1167 rl_txeof(struct rl_softc *sc) 1168 { 1169 struct ifnet *ifp; 1170 uint32_t txstat; 1171 1172 ifp = &sc->arpcom.ac_if; 1173 1174 /* 1175 * Go through our tx list and free mbufs for those 1176 * frames that have been uploaded. 1177 */ 1178 do { 1179 if (RL_LAST_TXMBUF(sc) == NULL) 1180 break; 1181 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1182 if ((txstat & (RL_TXSTAT_TX_OK | RL_TXSTAT_TX_UNDERRUN | 1183 RL_TXSTAT_TXABRT)) == 0) 1184 break; 1185 1186 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1187 1188 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1189 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1190 m_freem(RL_LAST_TXMBUF(sc)); 1191 RL_LAST_TXMBUF(sc) = NULL; 1192 RL_INC(sc->rl_cdata.last_tx); 1193 1194 if (txstat & RL_TXSTAT_TX_UNDERRUN) { 1195 sc->rl_txthresh += 32; 1196 if (sc->rl_txthresh > RL_TX_THRESH_MAX) 1197 sc->rl_txthresh = RL_TX_THRESH_MAX; 1198 } 1199 1200 if (txstat & RL_TXSTAT_TX_OK) { 1201 ifp->if_opackets++; 1202 } else { 1203 ifp->if_oerrors++; 1204 if (txstat & (RL_TXSTAT_TXABRT | RL_TXSTAT_OUTOFWIN)) 1205 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1206 } 1207 ifp->if_flags &= ~IFF_OACTIVE; 1208 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1209 1210 if (RL_LAST_TXMBUF(sc) == NULL) 1211 ifp->if_timer = 0; 1212 else if (ifp->if_timer == 0) 1213 ifp->if_timer = 5; 1214 } 1215 1216 static void 1217 rl_tick(void *xsc) 1218 { 1219 struct rl_softc *sc = xsc; 1220 struct mii_data *mii; 1221 1222 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1223 1224 mii = device_get_softc(sc->rl_miibus); 1225 mii_tick(mii); 1226 1227 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc); 1228 1229 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1230 } 1231 1232 #ifdef DEVICE_POLLING 1233 1234 static void 1235 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1236 { 1237 struct rl_softc *sc = ifp->if_softc; 1238 1239 switch(cmd) { 1240 case POLL_REGISTER: 1241 /* disable interrupts */ 1242 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1243 break; 1244 case POLL_DEREGISTER: 1245 /* enable interrupts */ 1246 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1247 break; 1248 default: 1249 sc->rxcycles = count; 1250 rl_rxeof(sc); 1251 rl_txeof(sc); 1252 if (!ifq_is_empty(&ifp->if_snd)) 1253 rl_start(ifp); 1254 1255 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1256 uint16_t status; 1257 1258 status = CSR_READ_2(sc, RL_ISR); 1259 if (status == 0xffff) 1260 return; 1261 if (status) 1262 CSR_WRITE_2(sc, RL_ISR, status); 1263 1264 /* 1265 * XXX check behaviour on receiver stalls. 1266 */ 1267 1268 if (status & RL_ISR_SYSTEM_ERR) { 1269 rl_reset(sc); 1270 rl_init(sc); 1271 } 1272 } 1273 break; 1274 } 1275 } 1276 #endif /* DEVICE_POLLING */ 1277 1278 static void 1279 rl_intr(void *arg) 1280 { 1281 struct rl_softc *sc; 1282 struct ifnet *ifp; 1283 uint16_t status; 1284 1285 sc = arg; 1286 1287 if (sc->suspended) 1288 return; 1289 1290 ifp = &sc->arpcom.ac_if; 1291 1292 for (;;) { 1293 status = CSR_READ_2(sc, RL_ISR); 1294 /* If the card has gone away, the read returns 0xffff. */ 1295 if (status == 0xffff) 1296 break; 1297 1298 if (status != 0) 1299 CSR_WRITE_2(sc, RL_ISR, status); 1300 1301 if ((status & RL_INTRS) == 0) 1302 break; 1303 1304 if (status & RL_ISR_RX_OK) 1305 rl_rxeof(sc); 1306 1307 if (status & RL_ISR_RX_ERR) 1308 rl_rxeof(sc); 1309 1310 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1311 rl_txeof(sc); 1312 1313 if (status & RL_ISR_SYSTEM_ERR) { 1314 rl_reset(sc); 1315 rl_init(sc); 1316 } 1317 1318 } 1319 1320 if (!ifq_is_empty(&ifp->if_snd)) 1321 rl_start(ifp); 1322 } 1323 1324 /* 1325 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1326 * pointers to the fragment pointers. 1327 */ 1328 static int 1329 rl_encap(struct rl_softc *sc, struct mbuf *m_head) 1330 { 1331 struct mbuf *m_new = NULL; 1332 1333 /* 1334 * The RealTek is brain damaged and wants longword-aligned 1335 * TX buffers, plus we can only have one fragment buffer 1336 * per packet. We have to copy pretty much all the time. 1337 */ 1338 m_new = m_defrag(m_head, MB_DONTWAIT); 1339 1340 if (m_new == NULL) { 1341 m_freem(m_head); 1342 return(1); 1343 } 1344 m_head = m_new; 1345 1346 /* Pad frames to at least 60 bytes. */ 1347 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1348 /* 1349 * Make security concious people happy: zero out the 1350 * bytes in the pad area, since we don't know what 1351 * this mbuf cluster buffer's previous user might 1352 * have left in it. 1353 */ 1354 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1355 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1356 m_head->m_pkthdr.len += 1357 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1358 m_head->m_len = m_head->m_pkthdr.len; 1359 } 1360 1361 RL_CUR_TXMBUF(sc) = m_head; 1362 1363 return(0); 1364 } 1365 1366 /* 1367 * Main transmit routine. 1368 */ 1369 1370 static void 1371 rl_start(struct ifnet *ifp) 1372 { 1373 struct rl_softc *sc; 1374 struct mbuf *m_head = NULL; 1375 1376 sc = ifp->if_softc; 1377 1378 while(RL_CUR_TXMBUF(sc) == NULL) { 1379 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1380 if (m_head == NULL) 1381 break; 1382 1383 if (rl_encap(sc, m_head)) 1384 break; 1385 1386 /* 1387 * If there's a BPF listener, bounce a copy of this frame 1388 * to him. 1389 */ 1390 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1391 1392 /* 1393 * Transmit the frame. 1394 */ 1395 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1396 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1397 mtod(RL_CUR_TXMBUF(sc), void *), 1398 RL_CUR_TXMBUF(sc)->m_pkthdr.len, 1399 rl_dma_map_txbuf, sc, 0); 1400 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1401 BUS_DMASYNC_PREREAD); 1402 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1403 RL_TXTHRESH(sc->rl_txthresh) | 1404 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1405 1406 RL_INC(sc->rl_cdata.cur_tx); 1407 1408 /* 1409 * Set a timeout in case the chip goes out to lunch. 1410 */ 1411 ifp->if_timer = 5; 1412 } 1413 1414 /* 1415 * We broke out of the loop because all our TX slots are 1416 * full. Mark the NIC as busy until it drains some of the 1417 * packets from the queue. 1418 */ 1419 if (RL_CUR_TXMBUF(sc) != NULL) 1420 ifp->if_flags |= IFF_OACTIVE; 1421 } 1422 1423 static void 1424 rl_init(void *xsc) 1425 { 1426 struct rl_softc *sc = xsc; 1427 struct ifnet *ifp = &sc->arpcom.ac_if; 1428 struct mii_data *mii; 1429 uint32_t rxcfg = 0; 1430 1431 mii = device_get_softc(sc->rl_miibus); 1432 1433 /* 1434 * Cancel pending I/O and free all RX/TX buffers. 1435 */ 1436 rl_stop(sc); 1437 1438 /* 1439 * Init our MAC address. Even though the chipset documentation 1440 * doesn't mention it, we need to enter "Config register write enable" 1441 * mode to modify the ID registers. 1442 */ 1443 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1444 CSR_WRITE_STREAM_4(sc, RL_IDR0, 1445 *(uint32_t *)(&sc->arpcom.ac_enaddr[0])); 1446 CSR_WRITE_STREAM_4(sc, RL_IDR4, 1447 *(uint32_t *)(&sc->arpcom.ac_enaddr[4])); 1448 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1449 1450 /* Init the RX buffer pointer register. */ 1451 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1452 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, 1453 sc, 0); 1454 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1455 BUS_DMASYNC_PREWRITE); 1456 1457 /* Init TX descriptors. */ 1458 rl_list_tx_init(sc); 1459 1460 /* 1461 * Enable transmit and receive. 1462 */ 1463 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1464 1465 /* 1466 * Set the initial TX and RX configuration. 1467 */ 1468 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1469 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1470 1471 /* Set the individual bit to receive frames for this host only. */ 1472 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1473 rxcfg |= RL_RXCFG_RX_INDIV; 1474 1475 /* If we want promiscuous mode, set the allframes bit. */ 1476 if (ifp->if_flags & IFF_PROMISC) { 1477 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1478 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1479 } else { 1480 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1481 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1482 } 1483 1484 /* 1485 * Set capture broadcast bit to capture broadcast frames. 1486 */ 1487 if (ifp->if_flags & IFF_BROADCAST) { 1488 rxcfg |= RL_RXCFG_RX_BROAD; 1489 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1490 } else { 1491 rxcfg &= ~RL_RXCFG_RX_BROAD; 1492 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1493 } 1494 1495 /* 1496 * Program the multicast filter, if necessary. 1497 */ 1498 rl_setmulti(sc); 1499 1500 #ifdef DEVICE_POLLING 1501 /* 1502 * Only enable interrupts if we are polling, keep them off otherwise. 1503 */ 1504 if (ifp->if_flags & IFF_POLLING) 1505 CSR_WRITE_2(sc, RL_IMR, 0); 1506 else 1507 #endif /* DEVICE_POLLING */ 1508 /* 1509 * Enable interrupts. 1510 */ 1511 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1512 1513 /* Set initial TX threshold */ 1514 sc->rl_txthresh = RL_TX_THRESH_INIT; 1515 1516 /* Start RX/TX process. */ 1517 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1518 1519 /* Enable receiver and transmitter. */ 1520 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1521 1522 mii_mediachg(mii); 1523 1524 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1525 1526 ifp->if_flags |= IFF_RUNNING; 1527 ifp->if_flags &= ~IFF_OACTIVE; 1528 1529 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc); 1530 } 1531 1532 /* 1533 * Set media options. 1534 */ 1535 static int 1536 rl_ifmedia_upd(struct ifnet *ifp) 1537 { 1538 struct rl_softc *sc; 1539 struct mii_data *mii; 1540 1541 sc = ifp->if_softc; 1542 mii = device_get_softc(sc->rl_miibus); 1543 mii_mediachg(mii); 1544 1545 return(0); 1546 } 1547 1548 /* 1549 * Report current media status. 1550 */ 1551 static void 1552 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1553 { 1554 struct rl_softc *sc = ifp->if_softc; 1555 struct mii_data *mii = device_get_softc(sc->rl_miibus); 1556 1557 mii_pollstat(mii); 1558 ifmr->ifm_active = mii->mii_media_active; 1559 ifmr->ifm_status = mii->mii_media_status; 1560 } 1561 1562 static int 1563 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1564 { 1565 struct rl_softc *sc = ifp->if_softc; 1566 struct ifreq *ifr = (struct ifreq *) data; 1567 struct mii_data *mii; 1568 int error = 0; 1569 1570 switch (command) { 1571 case SIOCSIFFLAGS: 1572 if (ifp->if_flags & IFF_UP) { 1573 rl_init(sc); 1574 } else { 1575 if (ifp->if_flags & IFF_RUNNING) 1576 rl_stop(sc); 1577 } 1578 error = 0; 1579 break; 1580 case SIOCADDMULTI: 1581 case SIOCDELMULTI: 1582 rl_setmulti(sc); 1583 error = 0; 1584 break; 1585 case SIOCGIFMEDIA: 1586 case SIOCSIFMEDIA: 1587 mii = device_get_softc(sc->rl_miibus); 1588 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1589 break; 1590 case SIOCSIFCAP: 1591 break; 1592 default: 1593 error = ether_ioctl(ifp, command, data); 1594 break; 1595 } 1596 1597 return(error); 1598 } 1599 1600 static void 1601 rl_watchdog(struct ifnet *ifp) 1602 { 1603 struct rl_softc *sc = ifp->if_softc; 1604 1605 device_printf(sc->rl_dev, "watchdog timeout\n"); 1606 1607 lwkt_serialize_enter(ifp->if_serializer); 1608 1609 ifp->if_oerrors++; 1610 1611 rl_txeof(sc); 1612 rl_rxeof(sc); 1613 rl_init(sc); 1614 1615 lwkt_serialize_exit(ifp->if_serializer); 1616 } 1617 1618 /* 1619 * Stop the adapter and free any mbufs allocated to the 1620 * RX and TX lists. 1621 */ 1622 static void 1623 rl_stop(struct rl_softc *sc) 1624 { 1625 struct ifnet *ifp = &sc->arpcom.ac_if; 1626 int i; 1627 1628 ifp->if_timer = 0; 1629 1630 callout_stop(&sc->rl_stat_timer); 1631 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1632 1633 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1634 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1635 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1636 1637 /* 1638 * Free the TX list buffers. 1639 */ 1640 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1641 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1642 bus_dmamap_unload(sc->rl_tag, 1643 sc->rl_cdata.rl_tx_dmamap[i]); 1644 bus_dmamap_destroy(sc->rl_tag, 1645 sc->rl_cdata.rl_tx_dmamap[i]); 1646 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1647 sc->rl_cdata.rl_tx_chain[i] = NULL; 1648 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 1649 0x0000000); 1650 } 1651 } 1652 } 1653 1654 /* 1655 * Stop all chip I/O so that the kernel's probe routines don't 1656 * get confused by errant DMAs when rebooting. 1657 */ 1658 static void 1659 rl_shutdown(device_t dev) 1660 { 1661 struct rl_softc *sc; 1662 1663 sc = device_get_softc(dev); 1664 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1665 rl_stop(sc); 1666 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1667 } 1668 1669 /* 1670 * Device suspend routine. Stop the interface and save some PCI 1671 * settings in case the BIOS doesn't restore them properly on 1672 * resume. 1673 */ 1674 static int 1675 rl_suspend(device_t dev) 1676 { 1677 struct rl_softc *sc = device_get_softc(dev); 1678 int i; 1679 1680 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1681 rl_stop(sc); 1682 1683 for (i = 0; i < 5; i++) 1684 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1685 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1686 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1687 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1688 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1689 1690 sc->suspended = 1; 1691 1692 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1693 return (0); 1694 } 1695 1696 /* 1697 * Device resume routine. Restore some PCI settings in case the BIOS 1698 * doesn't, re-enable busmastering, and restart the interface if 1699 * appropriate. 1700 */ 1701 static int 1702 rl_resume(device_t dev) 1703 { 1704 struct rl_softc *sc = device_get_softc(dev); 1705 struct ifnet *ifp = &sc->arpcom.ac_if; 1706 int i; 1707 1708 lwkt_serialize_enter(ifp->if_serializer); 1709 1710 /* better way to do this? */ 1711 for (i = 0; i < 5; i++) 1712 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 1713 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1714 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1715 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1716 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1717 1718 /* reenable busmastering */ 1719 pci_enable_busmaster(dev); 1720 pci_enable_io(dev, RL_RES); 1721 1722 /* reinitialize interface if necessary */ 1723 if (ifp->if_flags & IFF_UP) 1724 rl_init(sc); 1725 1726 sc->suspended = 0; 1727 lwkt_serialize_exit(ifp->if_serializer); 1728 return (0); 1729 } 1730