1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/rl/if_rl.c,v 1.25 2005/06/14 14:19:22 joerg Exp $ 34 */ 35 36 /* 37 * RealTek 8129/8139 PCI NIC driver 38 * 39 * Supports several extremely cheap PCI 10/100 adapters based on 40 * the RealTek chipset. Datasheets can be obtained from 41 * www.realtek.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 50 * probably the worst PCI ethernet controller ever made, with the possible 51 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 52 * DMA, but it has a terrible interface that nullifies any performance 53 * gains that bus-master DMA usually offers. 54 * 55 * For transmission, the chip offers a series of four TX descriptor 56 * registers. Each transmit frame must be in a contiguous buffer, aligned 57 * on a longword (32-bit) boundary. This means we almost always have to 58 * do mbuf copies in order to transmit a frame, except in the unlikely 59 * case where a) the packet fits into a single mbuf, and b) the packet 60 * is 32-bit aligned within the mbuf's data area. The presence of only 61 * four descriptor registers means that we can never have more than four 62 * packets queued for transmission at any one time. 63 * 64 * Reception is not much better. The driver has to allocate a single large 65 * buffer area (up to 64K in size) into which the chip will DMA received 66 * frames. Because we don't know where within this region received packets 67 * will begin or end, we have no choice but to copy data from the buffer 68 * area into mbufs in order to pass the packets up to the higher protocol 69 * levels. 70 * 71 * It's impossible given this rotten design to really achieve decent 72 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 73 * some equally overmuscled CPU to drive it. 74 * 75 * On the bright side, the 8139 does have a built-in PHY, although 76 * rather than using an MDIO serial interface like most other NICs, the 77 * PHY registers are directly accessible through the 8139's register 78 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 79 * filter. 80 * 81 * The 8129 chip is an older version of the 8139 that uses an external PHY 82 * chip. The 8129 has a serial MDIO interface for accessing the MII where 83 * the 8139 lets you directly access the on-board PHY registers. We need 84 * to select which interface to use depending on the chip type. 85 */ 86 87 #include <sys/param.h> 88 #include <sys/endian.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/module.h> 95 #include <sys/socket.h> 96 #include <sys/thread2.h> 97 98 #include <net/if.h> 99 #include <net/ifq_var.h> 100 #include <net/if_arp.h> 101 #include <net/ethernet.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 105 #include <net/bpf.h> 106 107 #include <machine/bus_pio.h> 108 #include <machine/bus_memio.h> 109 #include <machine/bus.h> 110 #include <machine/resource.h> 111 #include <sys/bus.h> 112 #include <sys/rman.h> 113 114 #include <dev/netif/mii_layer/mii.h> 115 #include <dev/netif/mii_layer/miivar.h> 116 117 #include <bus/pci/pcireg.h> 118 #include <bus/pci/pcivar.h> 119 120 /* "controller miibus0" required. See GENERIC if you get errors here. */ 121 #include "miibus_if.h" 122 123 /* 124 * Default to using PIO access for this driver. On SMP systems, 125 * there appear to be problems with memory mapped mode: it looks like 126 * doing too many memory mapped access back to back in rapid succession 127 * can hang the bus. I'm inclined to blame this on crummy design/construction 128 * on the part of RealTek. Memory mapped mode does appear to work on 129 * uniprocessor systems though. 130 */ 131 #define RL_USEIOSPACE 132 133 #include <dev/netif/rl/if_rlreg.h> 134 135 /* 136 * Various supported device vendors/types and their names. 137 */ 138 static struct rl_type { 139 uint16_t rl_vid; 140 uint16_t rl_did; 141 const char *rl_name; 142 } rl_devs[] = { 143 { RT_VENDORID, RT_DEVICEID_8129, 144 "RealTek 8129 10/100BaseTX" }, 145 { RT_VENDORID, RT_DEVICEID_8139, 146 "RealTek 8139 10/100BaseTX" }, 147 { RT_VENDORID, RT_DEVICEID_8138, 148 "RealTek 8139 10/100BaseTX CardBus" }, 149 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 150 "Accton MPX 5030/5038 10/100BaseTX" }, 151 { DELTA_VENDORID, DELTA_DEVICEID_8139, 152 "Delta Electronics 8139 10/100BaseTX" }, 153 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 154 "Addtron Technolgy 8139 10/100BaseTX" }, 155 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 156 "D-Link DFE-530TX+ 10/100BaseTX" }, 157 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, 158 "D-Link DFE-690TX 10/100BaseTX" }, 159 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 160 "Nortel Networks 10/100BaseTX" }, 161 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, 162 "Peppercon AG ROL/F" }, 163 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, 164 "Corega FEther CB-TXD" }, 165 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, 166 "Corega FEtherII CB-TXD" }, 167 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, 168 "Planex FNW-3800-TX" }, 169 { 0, 0, NULL } 170 }; 171 172 static int rl_probe(device_t); 173 static int rl_attach(device_t); 174 static int rl_detach(device_t); 175 176 static int rl_encap(struct rl_softc *, struct mbuf * ); 177 178 static void rl_rxeof(struct rl_softc *); 179 static void rl_txeof(struct rl_softc *); 180 static void rl_intr(void *); 181 static void rl_tick(void *); 182 static void rl_start(struct ifnet *); 183 static int rl_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 184 static void rl_init(void *); 185 static void rl_stop (struct rl_softc *); 186 static void rl_watchdog(struct ifnet *); 187 static int rl_suspend(device_t); 188 static int rl_resume(device_t); 189 static void rl_shutdown(device_t); 190 static int rl_ifmedia_upd(struct ifnet *); 191 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 192 193 static void rl_eeprom_putbyte(struct rl_softc *, int); 194 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *); 195 static void rl_read_eeprom(struct rl_softc *, caddr_t, int, int, int); 196 static void rl_mii_sync(struct rl_softc *); 197 static void rl_mii_send(struct rl_softc *, uint32_t, int); 198 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *); 199 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *); 200 201 static int rl_miibus_readreg(device_t, int, int); 202 static int rl_miibus_writereg(device_t, int, int, int); 203 static void rl_miibus_statchg(device_t); 204 205 static void rl_setmulti(struct rl_softc *); 206 static void rl_reset(struct rl_softc *); 207 static void rl_list_tx_init(struct rl_softc *); 208 209 static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int); 210 static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int); 211 #ifdef DEVICE_POLLING 212 static poll_handler_t rl_poll; 213 #endif 214 215 #ifdef RL_USEIOSPACE 216 #define RL_RES SYS_RES_IOPORT 217 #define RL_RID RL_PCI_LOIO 218 #else 219 #define RL_RES SYS_RES_MEMORY 220 #define RL_RID RL_PCI_LOMEM 221 #endif 222 223 static device_method_t rl_methods[] = { 224 /* Device interface */ 225 DEVMETHOD(device_probe, rl_probe), 226 DEVMETHOD(device_attach, rl_attach), 227 DEVMETHOD(device_detach, rl_detach), 228 DEVMETHOD(device_suspend, rl_suspend), 229 DEVMETHOD(device_resume, rl_resume), 230 DEVMETHOD(device_shutdown, rl_shutdown), 231 232 /* bus interface */ 233 DEVMETHOD(bus_print_child, bus_generic_print_child), 234 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 235 236 /* MII interface */ 237 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 238 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 239 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 240 241 { 0, 0 } 242 }; 243 244 static DEFINE_CLASS_0(rl, rl_driver, rl_methods, sizeof(struct rl_softc)); 245 static devclass_t rl_devclass; 246 247 DECLARE_DUMMY_MODULE(if_rl); 248 DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 249 DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 250 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 251 MODULE_DEPEND(if_rl, miibus, 1, 1, 1); 252 253 #define EE_SET(x) \ 254 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) | (x)) 255 256 #define EE_CLR(x) \ 257 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) & ~(x)) 258 259 static void 260 rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) 261 { 262 struct rl_softc *sc = arg; 263 264 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 265 } 266 267 static void 268 rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) 269 { 270 struct rl_softc *sc = arg; 271 272 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 273 } 274 275 /* 276 * Send a read command and address to the EEPROM, check for ACK. 277 */ 278 static void 279 rl_eeprom_putbyte(struct rl_softc *sc, int addr) 280 { 281 int d, i; 282 283 d = addr | sc->rl_eecmd_read; 284 285 /* 286 * Feed in each bit and strobe the clock. 287 */ 288 for (i = 0x400; i; i >>= 1) { 289 if (d & i) 290 EE_SET(RL_EE_DATAIN); 291 else 292 EE_CLR(RL_EE_DATAIN); 293 DELAY(100); 294 EE_SET(RL_EE_CLK); 295 DELAY(150); 296 EE_CLR(RL_EE_CLK); 297 DELAY(100); 298 } 299 } 300 301 /* 302 * Read a word of data stored in the EEPROM at address 'addr.' 303 */ 304 static void 305 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest) 306 { 307 int i; 308 uint16_t word = 0; 309 310 /* Enter EEPROM access mode. */ 311 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 312 313 /* 314 * Send address of word we want to read. 315 */ 316 rl_eeprom_putbyte(sc, addr); 317 318 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 319 320 /* 321 * Start reading bits from EEPROM. 322 */ 323 for (i = 0x8000; i; i >>= 1) { 324 EE_SET(RL_EE_CLK); 325 DELAY(100); 326 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 327 word |= i; 328 EE_CLR(RL_EE_CLK); 329 DELAY(100); 330 } 331 332 /* Turn off EEPROM access mode. */ 333 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 334 335 *dest = word; 336 } 337 338 /* 339 * Read a sequence of words from the EEPROM. 340 */ 341 static void 342 rl_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt, int swap) 343 { 344 int i; 345 u_int16_t word = 0, *ptr; 346 347 for (i = 0; i < cnt; i++) { 348 rl_eeprom_getword(sc, off + i, &word); 349 ptr = (u_int16_t *)(dest + (i * 2)); 350 if (swap) 351 *ptr = ntohs(word); 352 else 353 *ptr = word; 354 } 355 } 356 357 358 /* 359 * MII access routines are provided for the 8129, which 360 * doesn't have a built-in PHY. For the 8139, we fake things 361 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 362 * direct access PHY registers. 363 */ 364 #define MII_SET(x) \ 365 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) | x) 366 367 #define MII_CLR(x) \ 368 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) & ~x) 369 370 /* 371 * Sync the PHYs by setting data bit and strobing the clock 32 times. 372 */ 373 static void 374 rl_mii_sync(struct rl_softc *sc) 375 { 376 int i; 377 378 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 379 380 for (i = 0; i < 32; i++) { 381 MII_SET(RL_MII_CLK); 382 DELAY(1); 383 MII_CLR(RL_MII_CLK); 384 DELAY(1); 385 } 386 } 387 388 /* 389 * Clock a series of bits through the MII. 390 */ 391 static void 392 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt) 393 { 394 int i; 395 396 MII_CLR(RL_MII_CLK); 397 398 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 399 if (bits & i) 400 MII_SET(RL_MII_DATAOUT); 401 else 402 MII_CLR(RL_MII_DATAOUT); 403 DELAY(1); 404 MII_CLR(RL_MII_CLK); 405 DELAY(1); 406 MII_SET(RL_MII_CLK); 407 } 408 } 409 410 /* 411 * Read an PHY register through the MII. 412 */ 413 static int 414 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame) 415 { 416 int ack, i; 417 418 crit_enter(); 419 420 /* 421 * Set up frame for RX. 422 */ 423 frame->mii_stdelim = RL_MII_STARTDELIM; 424 frame->mii_opcode = RL_MII_READOP; 425 frame->mii_turnaround = 0; 426 frame->mii_data = 0; 427 428 CSR_WRITE_2(sc, RL_MII, 0); 429 430 /* 431 * Turn on data xmit. 432 */ 433 MII_SET(RL_MII_DIR); 434 435 rl_mii_sync(sc); 436 437 /* 438 * Send command/address info. 439 */ 440 rl_mii_send(sc, frame->mii_stdelim, 2); 441 rl_mii_send(sc, frame->mii_opcode, 2); 442 rl_mii_send(sc, frame->mii_phyaddr, 5); 443 rl_mii_send(sc, frame->mii_regaddr, 5); 444 445 /* Idle bit */ 446 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 447 DELAY(1); 448 MII_SET(RL_MII_CLK); 449 DELAY(1); 450 451 /* Turn off xmit. */ 452 MII_CLR(RL_MII_DIR); 453 454 /* Check for ack */ 455 MII_CLR(RL_MII_CLK); 456 DELAY(1); 457 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 458 MII_SET(RL_MII_CLK); 459 DELAY(1); 460 461 /* 462 * Now try reading data bits. If the ack failed, we still 463 * need to clock through 16 cycles to keep the PHY(s) in sync. 464 */ 465 if (ack) { 466 for(i = 0; i < 16; i++) { 467 MII_CLR(RL_MII_CLK); 468 DELAY(1); 469 MII_SET(RL_MII_CLK); 470 DELAY(1); 471 } 472 } else { 473 for (i = 0x8000; i; i >>= 1) { 474 MII_CLR(RL_MII_CLK); 475 DELAY(1); 476 if (!ack) { 477 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 478 frame->mii_data |= i; 479 DELAY(1); 480 } 481 MII_SET(RL_MII_CLK); 482 DELAY(1); 483 } 484 } 485 486 MII_CLR(RL_MII_CLK); 487 DELAY(1); 488 MII_SET(RL_MII_CLK); 489 DELAY(1); 490 491 crit_exit(); 492 493 return(ack ? 1 : 0); 494 } 495 496 /* 497 * Write to a PHY register through the MII. 498 */ 499 static int 500 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame) 501 { 502 crit_enter(); 503 504 /* 505 * Set up frame for TX. 506 */ 507 frame->mii_stdelim = RL_MII_STARTDELIM; 508 frame->mii_opcode = RL_MII_WRITEOP; 509 frame->mii_turnaround = RL_MII_TURNAROUND; 510 511 /* 512 * Turn on data output. 513 */ 514 MII_SET(RL_MII_DIR); 515 516 rl_mii_sync(sc); 517 518 rl_mii_send(sc, frame->mii_stdelim, 2); 519 rl_mii_send(sc, frame->mii_opcode, 2); 520 rl_mii_send(sc, frame->mii_phyaddr, 5); 521 rl_mii_send(sc, frame->mii_regaddr, 5); 522 rl_mii_send(sc, frame->mii_turnaround, 2); 523 rl_mii_send(sc, frame->mii_data, 16); 524 525 /* Idle bit. */ 526 MII_SET(RL_MII_CLK); 527 DELAY(1); 528 MII_CLR(RL_MII_CLK); 529 DELAY(1); 530 531 /* 532 * Turn off xmit. 533 */ 534 MII_CLR(RL_MII_DIR); 535 536 crit_exit(); 537 538 return(0); 539 } 540 541 static int 542 rl_miibus_readreg(device_t dev, int phy, int reg) 543 { 544 struct rl_softc *sc; 545 struct rl_mii_frame frame; 546 uint16_t rval = 0; 547 uint16_t rl8139_reg = 0; 548 549 sc = device_get_softc(dev); 550 551 if (sc->rl_type == RL_8139) { 552 /* Pretend the internal PHY is only at address 0 */ 553 if (phy) 554 return(0); 555 switch (reg) { 556 case MII_BMCR: 557 rl8139_reg = RL_BMCR; 558 break; 559 case MII_BMSR: 560 rl8139_reg = RL_BMSR; 561 break; 562 case MII_ANAR: 563 rl8139_reg = RL_ANAR; 564 break; 565 case MII_ANER: 566 rl8139_reg = RL_ANER; 567 break; 568 case MII_ANLPAR: 569 rl8139_reg = RL_LPAR; 570 break; 571 case MII_PHYIDR1: 572 case MII_PHYIDR2: 573 return(0); 574 break; 575 /* 576 * Allow the rlphy driver to read the media status 577 * register. If we have a link partner which does not 578 * support NWAY, this is the register which will tell 579 * us the results of parallel detection. 580 */ 581 case RL_MEDIASTAT: 582 rval = CSR_READ_1(sc, RL_MEDIASTAT); 583 return(rval); 584 default: 585 device_printf(dev, "bad phy register\n"); 586 return(0); 587 } 588 rval = CSR_READ_2(sc, rl8139_reg); 589 return(rval); 590 } 591 592 bzero(&frame, sizeof(frame)); 593 594 frame.mii_phyaddr = phy; 595 frame.mii_regaddr = reg; 596 rl_mii_readreg(sc, &frame); 597 598 return(frame.mii_data); 599 } 600 601 static int 602 rl_miibus_writereg(device_t dev, int phy, int reg, int data) 603 { 604 struct rl_softc *sc; 605 struct rl_mii_frame frame; 606 u_int16_t rl8139_reg = 0; 607 608 sc = device_get_softc(dev); 609 610 if (sc->rl_type == RL_8139) { 611 /* Pretend the internal PHY is only at address 0 */ 612 if (phy) 613 return(0); 614 switch (reg) { 615 case MII_BMCR: 616 rl8139_reg = RL_BMCR; 617 break; 618 case MII_BMSR: 619 rl8139_reg = RL_BMSR; 620 break; 621 case MII_ANAR: 622 rl8139_reg = RL_ANAR; 623 break; 624 case MII_ANER: 625 rl8139_reg = RL_ANER; 626 break; 627 case MII_ANLPAR: 628 rl8139_reg = RL_LPAR; 629 break; 630 case MII_PHYIDR1: 631 case MII_PHYIDR2: 632 return(0); 633 default: 634 device_printf(dev, "bad phy register\n"); 635 return(0); 636 } 637 CSR_WRITE_2(sc, rl8139_reg, data); 638 return(0); 639 } 640 641 bzero(&frame, sizeof(frame)); 642 643 frame.mii_phyaddr = phy; 644 frame.mii_regaddr = reg; 645 frame.mii_data = data; 646 647 rl_mii_writereg(sc, &frame); 648 649 return(0); 650 } 651 652 static void 653 rl_miibus_statchg(device_t dev) 654 { 655 } 656 657 /* 658 * Program the 64-bit multicast hash filter. 659 */ 660 static void 661 rl_setmulti(struct rl_softc *sc) 662 { 663 struct ifnet *ifp; 664 int h = 0; 665 uint32_t hashes[2] = { 0, 0 }; 666 struct ifmultiaddr *ifma; 667 uint32_t rxfilt; 668 int mcnt = 0; 669 670 ifp = &sc->arpcom.ac_if; 671 672 rxfilt = CSR_READ_4(sc, RL_RXCFG); 673 674 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 675 rxfilt |= RL_RXCFG_RX_MULTI; 676 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 677 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 678 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 679 return; 680 } 681 682 /* first, zot all the existing hash bits */ 683 CSR_WRITE_4(sc, RL_MAR0, 0); 684 CSR_WRITE_4(sc, RL_MAR4, 0); 685 686 /* now program new ones */ 687 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 688 if (ifma->ifma_addr->sa_family != AF_LINK) 689 continue; 690 h = ether_crc32_be( 691 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 692 ETHER_ADDR_LEN) >> 26; 693 if (h < 32) 694 hashes[0] |= (1 << h); 695 else 696 hashes[1] |= (1 << (h - 32)); 697 mcnt++; 698 } 699 700 if (mcnt) 701 rxfilt |= RL_RXCFG_RX_MULTI; 702 else 703 rxfilt &= ~RL_RXCFG_RX_MULTI; 704 705 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 706 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 707 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 708 } 709 710 static void 711 rl_reset(struct rl_softc *sc) 712 { 713 int i; 714 715 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 716 717 for (i = 0; i < RL_TIMEOUT; i++) { 718 DELAY(10); 719 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 720 break; 721 } 722 if (i == RL_TIMEOUT) 723 device_printf(sc->rl_dev, "reset never completed!\n"); 724 } 725 726 /* 727 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 728 * IDs against our list and return a device name if we find a match. 729 * 730 * Return with a value < 0 to give re(4) a change to attach. 731 */ 732 static int 733 rl_probe(device_t dev) 734 { 735 struct rl_type *t; 736 uint16_t product = pci_get_device(dev); 737 uint16_t vendor = pci_get_vendor(dev); 738 739 for (t = rl_devs; t->rl_name != NULL; t++) { 740 if (vendor == t->rl_vid && product == t->rl_did) { 741 device_set_desc(dev, t->rl_name); 742 return(-100); 743 } 744 } 745 746 return(ENXIO); 747 } 748 749 /* 750 * Attach the interface. Allocate softc structures, do ifmedia 751 * setup and ethernet/BPF attach. 752 */ 753 static int 754 rl_attach(device_t dev) 755 { 756 uint8_t eaddr[ETHER_ADDR_LEN]; 757 uint16_t as[3]; 758 struct rl_softc *sc; 759 struct ifnet *ifp; 760 uint16_t rl_did = 0; 761 int error = 0, rid, i; 762 763 sc = device_get_softc(dev); 764 sc->rl_dev = dev; 765 766 /* 767 * Handle power management nonsense. 768 */ 769 770 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 771 uint32_t iobase, membase, irq; 772 773 /* Save important PCI config data. */ 774 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 775 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 776 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 777 778 /* Reset the power state. */ 779 device_printf(dev, "chip is is in D%d power mode " 780 "-- setting to D0\n", pci_get_powerstate(dev)); 781 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 782 783 /* Restore PCI config data. */ 784 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 785 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 786 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 787 } 788 789 pci_enable_busmaster(dev); 790 791 rid = RL_RID; 792 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE); 793 794 if (sc->rl_res == NULL) { 795 device_printf(dev, "couldn't map ports/memory\n"); 796 error = ENXIO; 797 goto fail; 798 } 799 800 sc->rl_btag = rman_get_bustag(sc->rl_res); 801 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 802 803 rid = 0; 804 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 805 RF_SHAREABLE | RF_ACTIVE); 806 807 if (sc->rl_irq == NULL) { 808 device_printf(dev, "couldn't map interrupt\n"); 809 error = ENXIO; 810 goto fail; 811 } 812 813 callout_init(&sc->rl_stat_timer); 814 815 /* Reset the adapter. */ 816 rl_reset(sc); 817 818 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 819 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0); 820 if (rl_did != 0x8129) 821 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 822 823 /* 824 * Get station address from the EEPROM. 825 */ 826 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 827 for (i = 0; i < 3; i++) { 828 eaddr[(i * 2) + 0] = as[i] & 0xff; 829 eaddr[(i * 2) + 1] = as[i] >> 8; 830 } 831 832 /* 833 * Now read the exact device type from the EEPROM to find 834 * out if it's an 8129 or 8139. 835 */ 836 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 837 838 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 839 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 840 rl_did == DLINK_DEVICEID_530TXPLUS || rl_did == RT_DEVICEID_8138 || 841 rl_did == DLINK_DEVICEID_690TXD || 842 rl_did == COREGA_DEVICEID_FETHERCBTXD || 843 rl_did == COREGA_DEVICEID_FETHERIICBTXD || 844 rl_did == PLANEX_DEVICEID_FNW3800TX) 845 sc->rl_type = RL_8139; 846 else if (rl_did == RT_DEVICEID_8129) 847 sc->rl_type = RL_8129; 848 else { 849 device_printf(dev, "unknown device ID: %x\n", rl_did); 850 error = ENXIO; 851 goto fail; 852 } 853 854 #define RL_NSEG_NEW 32 855 error = bus_dma_tag_create(NULL, /* parent */ 856 1, 0, /* alignment, boundary */ 857 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 858 BUS_SPACE_MAXADDR, /* highaddr */ 859 NULL, NULL, /* filter, filterarg */ 860 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 861 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 862 BUS_DMA_ALLOCNOW, /* flags */ 863 &sc->rl_parent_tag); 864 865 if (error) { 866 device_printf(dev, "can't create parent tag\n"); 867 goto fail; 868 } 869 870 /* 871 * Now allocate a tag for the DMA descriptor lists. 872 * All of our lists are allocated as a contiguous block 873 * of memory. 874 */ 875 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 876 1, 0, /* alignment, boundary */ 877 BUS_SPACE_MAXADDR, /* lowaddr */ 878 BUS_SPACE_MAXADDR, /* highaddr */ 879 NULL, NULL, /* filter, filterarg */ 880 RL_RXBUFLEN + 1518, 1, /* maxsize, nsegments */ 881 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 882 0, /* flags */ 883 &sc->rl_tag); 884 885 if (error) { 886 device_printf(dev, "can't create RX tag\n"); 887 goto fail; 888 } 889 890 /* 891 * Now allocate a chunk of DMA-able memory based on the tag 892 * we just created. 893 */ 894 error = bus_dmamem_alloc(sc->rl_tag, (void **)&sc->rl_cdata.rl_rx_buf, 895 BUS_DMA_WAITOK, &sc->rl_cdata.rl_rx_dmamap); 896 897 if (error) { 898 device_printf(dev, "can't allocate RX memory!\n"); 899 error = ENXIO; 900 goto fail; 901 } 902 903 /* Leave a few bytes before the start of the RX ring buffer. */ 904 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 905 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 906 907 /* Do MII setup */ 908 if (mii_phy_probe(dev, &sc->rl_miibus, rl_ifmedia_upd, 909 rl_ifmedia_sts)) { 910 device_printf(dev, "MII without any phy!\n"); 911 error = ENXIO; 912 goto fail; 913 } 914 915 ifp = &sc->arpcom.ac_if; 916 ifp->if_softc = sc; 917 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 918 ifp->if_mtu = ETHERMTU; 919 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 920 ifp->if_ioctl = rl_ioctl; 921 ifp->if_start = rl_start; 922 ifp->if_watchdog = rl_watchdog; 923 ifp->if_init = rl_init; 924 ifp->if_baudrate = 10000000; 925 ifp->if_capabilities = IFCAP_VLAN_MTU; 926 #ifdef DEVICE_POLLING 927 ifp->if_poll = rl_poll; 928 #endif 929 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 930 ifq_set_ready(&ifp->if_snd); 931 932 /* 933 * Call MI attach routine. 934 */ 935 ether_ifattach(ifp, eaddr); 936 937 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, rl_intr, 938 sc, &sc->rl_intrhand, NULL); 939 940 if (error) { 941 device_printf(dev, "couldn't set up irq\n"); 942 ether_ifdetach(ifp); 943 goto fail; 944 } 945 946 return(0); 947 948 fail: 949 rl_detach(dev); 950 return(error); 951 } 952 953 static int 954 rl_detach(device_t dev) 955 { 956 struct rl_softc *sc; 957 struct ifnet *ifp; 958 959 sc = device_get_softc(dev); 960 ifp = &sc->arpcom.ac_if; 961 962 crit_enter(); 963 964 if (device_is_attached(dev)) { 965 rl_stop(sc); 966 ether_ifdetach(ifp); 967 } 968 969 if (sc->rl_miibus) 970 device_delete_child(dev, sc->rl_miibus); 971 bus_generic_detach(dev); 972 973 if (sc->rl_intrhand) 974 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 975 976 crit_exit(); 977 978 if (sc->rl_irq) 979 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 980 if (sc->rl_res) 981 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 982 983 if (sc->rl_cdata.rl_rx_buf) { 984 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 985 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 986 sc->rl_cdata.rl_rx_dmamap); 987 } 988 if (sc->rl_tag) 989 bus_dma_tag_destroy(sc->rl_tag); 990 if (sc->rl_parent_tag) 991 bus_dma_tag_destroy(sc->rl_parent_tag); 992 993 return(0); 994 } 995 996 /* 997 * Initialize the transmit descriptors. 998 */ 999 static void 1000 rl_list_tx_init(struct rl_softc *sc) 1001 { 1002 struct rl_chain_data *cd; 1003 int i; 1004 1005 cd = &sc->rl_cdata; 1006 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1007 cd->rl_tx_chain[i] = NULL; 1008 CSR_WRITE_4(sc, 1009 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000); 1010 } 1011 1012 sc->rl_cdata.cur_tx = 0; 1013 sc->rl_cdata.last_tx = 0; 1014 } 1015 1016 /* 1017 * A frame has been uploaded: pass the resulting mbuf chain up to 1018 * the higher level protocols. 1019 * 1020 * You know there's something wrong with a PCI bus-master chip design 1021 * when you have to use m_devget(). 1022 * 1023 * The receive operation is badly documented in the datasheet, so I'll 1024 * attempt to document it here. The driver provides a buffer area and 1025 * places its base address in the RX buffer start address register. 1026 * The chip then begins copying frames into the RX buffer. Each frame 1027 * is preceded by a 32-bit RX status word which specifies the length 1028 * of the frame and certain other status bits. Each frame (starting with 1029 * the status word) is also 32-bit aligned. The frame length is in the 1030 * first 16 bits of the status word; the lower 15 bits correspond with 1031 * the 'rx status register' mentioned in the datasheet. 1032 * 1033 * Note: to make the Alpha happy, the frame payload needs to be aligned 1034 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 1035 * the ring buffer starting at an address two bytes before the actual 1036 * data location. We can then shave off the first two bytes using m_adj(). 1037 * The reason we do this is because m_devget() doesn't let us specify an 1038 * offset into the mbuf storage space, so we have to artificially create 1039 * one. The ring is allocated in such a way that there are a few unused 1040 * bytes of space preceecing it so that it will be safe for us to do the 1041 * 2-byte backstep even if reading from the ring at offset 0. 1042 */ 1043 static void 1044 rl_rxeof(struct rl_softc *sc) 1045 { 1046 struct mbuf *m; 1047 struct ifnet *ifp; 1048 int total_len = 0; 1049 uint32_t rxstat; 1050 caddr_t rxbufpos; 1051 int wrap = 0; 1052 uint16_t cur_rx, limit, max_bytes, rx_bytes = 0; 1053 1054 ifp = &sc->arpcom.ac_if; 1055 1056 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1057 BUS_DMASYNC_POSTREAD); 1058 1059 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1060 1061 /* Do not try to read past this point. */ 1062 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1063 1064 if (limit < cur_rx) 1065 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1066 else 1067 max_bytes = limit - cur_rx; 1068 1069 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1070 #ifdef DEVICE_POLLING 1071 if (ifp->if_flags & IFF_POLLING) { 1072 if (sc->rxcycles <= 0) 1073 break; 1074 sc->rxcycles--; 1075 } 1076 #endif /* DEVICE_POLLING */ 1077 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1078 rxstat = le32toh(*(uint32_t *)rxbufpos); 1079 1080 /* 1081 * Here's a totally undocumented fact for you. When the 1082 * RealTek chip is in the process of copying a packet into 1083 * RAM for you, the length will be 0xfff0. If you spot a 1084 * packet header with this value, you need to stop. The 1085 * datasheet makes absolutely no mention of this and 1086 * RealTek should be shot for this. 1087 */ 1088 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1089 break; 1090 1091 if ((rxstat & RL_RXSTAT_RXOK) == 0) { 1092 ifp->if_ierrors++; 1093 rl_init(sc); 1094 return; 1095 } 1096 1097 /* No errors; receive the packet. */ 1098 total_len = rxstat >> 16; 1099 rx_bytes += total_len + 4; 1100 1101 /* 1102 * XXX The RealTek chip includes the CRC with every 1103 * received frame, and there's no way to turn this 1104 * behavior off (at least, I can't find anything in 1105 * the manual that explains how to do it) so we have 1106 * to trim off the CRC manually. 1107 */ 1108 total_len -= ETHER_CRC_LEN; 1109 1110 /* 1111 * Avoid trying to read more bytes than we know 1112 * the chip has prepared for us. 1113 */ 1114 if (rx_bytes > max_bytes) 1115 break; 1116 1117 rxbufpos = sc->rl_cdata.rl_rx_buf + 1118 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN); 1119 1120 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1121 rxbufpos = sc->rl_cdata.rl_rx_buf; 1122 1123 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1124 1125 if (total_len > wrap) { 1126 /* 1127 * Fool m_devget() into thinking we want to copy 1128 * the whole buffer so we don't end up fragmenting 1129 * the data. 1130 */ 1131 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1132 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1133 if (m == NULL) { 1134 ifp->if_ierrors++; 1135 } else { 1136 m_adj(m, RL_ETHER_ALIGN); 1137 m_copyback(m, wrap, total_len - wrap, 1138 sc->rl_cdata.rl_rx_buf); 1139 } 1140 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1141 } else { 1142 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1143 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1144 if (m == NULL) { 1145 ifp->if_ierrors++; 1146 } else 1147 m_adj(m, RL_ETHER_ALIGN); 1148 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1149 } 1150 1151 /* 1152 * Round up to 32-bit boundary. 1153 */ 1154 cur_rx = (cur_rx + 3) & ~3; 1155 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1156 1157 if (m == NULL) 1158 continue; 1159 1160 ifp->if_ipackets++; 1161 1162 (*ifp->if_input)(ifp, m); 1163 } 1164 } 1165 1166 /* 1167 * A frame was downloaded to the chip. It's safe for us to clean up 1168 * the list buffers. 1169 */ 1170 static void 1171 rl_txeof(struct rl_softc *sc) 1172 { 1173 struct ifnet *ifp; 1174 uint32_t txstat; 1175 1176 ifp = &sc->arpcom.ac_if; 1177 1178 /* 1179 * Go through our tx list and free mbufs for those 1180 * frames that have been uploaded. 1181 */ 1182 do { 1183 if (RL_LAST_TXMBUF(sc) == NULL) 1184 break; 1185 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1186 if ((txstat & (RL_TXSTAT_TX_OK | RL_TXSTAT_TX_UNDERRUN | 1187 RL_TXSTAT_TXABRT)) == 0) 1188 break; 1189 1190 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1191 1192 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1193 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1194 m_freem(RL_LAST_TXMBUF(sc)); 1195 RL_LAST_TXMBUF(sc) = NULL; 1196 RL_INC(sc->rl_cdata.last_tx); 1197 1198 if (txstat & RL_TXSTAT_TX_UNDERRUN) { 1199 sc->rl_txthresh += 32; 1200 if (sc->rl_txthresh > RL_TX_THRESH_MAX) 1201 sc->rl_txthresh = RL_TX_THRESH_MAX; 1202 } 1203 1204 if (txstat & RL_TXSTAT_TX_OK) { 1205 ifp->if_opackets++; 1206 } else { 1207 ifp->if_oerrors++; 1208 if (txstat & (RL_TXSTAT_TXABRT | RL_TXSTAT_OUTOFWIN)) 1209 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1210 } 1211 ifp->if_flags &= ~IFF_OACTIVE; 1212 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1213 1214 if (RL_LAST_TXMBUF(sc) == NULL) 1215 ifp->if_timer = 0; 1216 else if (ifp->if_timer == 0) 1217 ifp->if_timer = 5; 1218 } 1219 1220 static void 1221 rl_tick(void *xsc) 1222 { 1223 struct rl_softc *sc = xsc; 1224 struct mii_data *mii; 1225 1226 crit_enter(); 1227 1228 mii = device_get_softc(sc->rl_miibus); 1229 mii_tick(mii); 1230 1231 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc); 1232 1233 crit_exit(); 1234 } 1235 1236 #ifdef DEVICE_POLLING 1237 1238 static void 1239 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1240 { 1241 struct rl_softc *sc = ifp->if_softc; 1242 1243 switch(cmd) { 1244 case POLL_REGISTER: 1245 /* disable interrupts */ 1246 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1247 break; 1248 case POLL_DEREGISTER: 1249 /* enable interrupts */ 1250 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1251 break; 1252 default: 1253 sc->rxcycles = count; 1254 rl_rxeof(sc); 1255 rl_txeof(sc); 1256 if (!ifq_is_empty(&ifp->if_snd)) 1257 rl_start(ifp); 1258 1259 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1260 uint16_t status; 1261 1262 status = CSR_READ_2(sc, RL_ISR); 1263 if (status == 0xffff) 1264 return; 1265 if (status) 1266 CSR_WRITE_2(sc, RL_ISR, status); 1267 1268 /* 1269 * XXX check behaviour on receiver stalls. 1270 */ 1271 1272 if (status & RL_ISR_SYSTEM_ERR) { 1273 rl_reset(sc); 1274 rl_init(sc); 1275 } 1276 } 1277 break; 1278 } 1279 } 1280 #endif /* DEVICE_POLLING */ 1281 1282 static void 1283 rl_intr(void *arg) 1284 { 1285 struct rl_softc *sc; 1286 struct ifnet *ifp; 1287 uint16_t status; 1288 1289 sc = arg; 1290 1291 if (sc->suspended) 1292 return; 1293 1294 ifp = &sc->arpcom.ac_if; 1295 1296 for (;;) { 1297 status = CSR_READ_2(sc, RL_ISR); 1298 /* If the card has gone away, the read returns 0xffff. */ 1299 if (status == 0xffff) 1300 break; 1301 1302 if (status != 0) 1303 CSR_WRITE_2(sc, RL_ISR, status); 1304 1305 if ((status & RL_INTRS) == 0) 1306 break; 1307 1308 if (status & RL_ISR_RX_OK) 1309 rl_rxeof(sc); 1310 1311 if (status & RL_ISR_RX_ERR) 1312 rl_rxeof(sc); 1313 1314 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1315 rl_txeof(sc); 1316 1317 if (status & RL_ISR_SYSTEM_ERR) { 1318 rl_reset(sc); 1319 rl_init(sc); 1320 } 1321 1322 } 1323 1324 if (!ifq_is_empty(&ifp->if_snd)) 1325 rl_start(ifp); 1326 } 1327 1328 /* 1329 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1330 * pointers to the fragment pointers. 1331 */ 1332 static int 1333 rl_encap(struct rl_softc *sc, struct mbuf *m_head) 1334 { 1335 struct mbuf *m_new = NULL; 1336 1337 /* 1338 * The RealTek is brain damaged and wants longword-aligned 1339 * TX buffers, plus we can only have one fragment buffer 1340 * per packet. We have to copy pretty much all the time. 1341 */ 1342 m_new = m_defrag(m_head, MB_DONTWAIT); 1343 1344 if (m_new == NULL) { 1345 m_freem(m_head); 1346 return(1); 1347 } 1348 m_head = m_new; 1349 1350 /* Pad frames to at least 60 bytes. */ 1351 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1352 /* 1353 * Make security concious people happy: zero out the 1354 * bytes in the pad area, since we don't know what 1355 * this mbuf cluster buffer's previous user might 1356 * have left in it. 1357 */ 1358 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1359 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1360 m_head->m_pkthdr.len += 1361 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1362 m_head->m_len = m_head->m_pkthdr.len; 1363 } 1364 1365 RL_CUR_TXMBUF(sc) = m_head; 1366 1367 return(0); 1368 } 1369 1370 /* 1371 * Main transmit routine. 1372 */ 1373 1374 static void 1375 rl_start(struct ifnet *ifp) 1376 { 1377 struct rl_softc *sc; 1378 struct mbuf *m_head = NULL; 1379 1380 sc = ifp->if_softc; 1381 1382 while(RL_CUR_TXMBUF(sc) == NULL) { 1383 m_head = ifq_dequeue(&ifp->if_snd); 1384 if (m_head == NULL) 1385 break; 1386 1387 if (rl_encap(sc, m_head)) 1388 break; 1389 1390 /* 1391 * If there's a BPF listener, bounce a copy of this frame 1392 * to him. 1393 */ 1394 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1395 1396 /* 1397 * Transmit the frame. 1398 */ 1399 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1400 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1401 mtod(RL_CUR_TXMBUF(sc), void *), 1402 RL_CUR_TXMBUF(sc)->m_pkthdr.len, 1403 rl_dma_map_txbuf, sc, 0); 1404 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1405 BUS_DMASYNC_PREREAD); 1406 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1407 RL_TXTHRESH(sc->rl_txthresh) | 1408 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1409 1410 RL_INC(sc->rl_cdata.cur_tx); 1411 1412 /* 1413 * Set a timeout in case the chip goes out to lunch. 1414 */ 1415 ifp->if_timer = 5; 1416 } 1417 1418 /* 1419 * We broke out of the loop because all our TX slots are 1420 * full. Mark the NIC as busy until it drains some of the 1421 * packets from the queue. 1422 */ 1423 if (RL_CUR_TXMBUF(sc) != NULL) 1424 ifp->if_flags |= IFF_OACTIVE; 1425 } 1426 1427 static void 1428 rl_init(void *xsc) 1429 { 1430 struct rl_softc *sc = xsc; 1431 struct ifnet *ifp = &sc->arpcom.ac_if; 1432 struct mii_data *mii; 1433 uint32_t rxcfg = 0; 1434 1435 crit_enter(); 1436 1437 mii = device_get_softc(sc->rl_miibus); 1438 1439 /* 1440 * Cancel pending I/O and free all RX/TX buffers. 1441 */ 1442 rl_stop(sc); 1443 1444 /* 1445 * Init our MAC address. Even though the chipset documentation 1446 * doesn't mention it, we need to enter "Config register write enable" 1447 * mode to modify the ID registers. 1448 */ 1449 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1450 CSR_WRITE_STREAM_4(sc, RL_IDR0, 1451 *(uint32_t *)(&sc->arpcom.ac_enaddr[0])); 1452 CSR_WRITE_STREAM_4(sc, RL_IDR4, 1453 *(uint32_t *)(&sc->arpcom.ac_enaddr[4])); 1454 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1455 1456 /* Init the RX buffer pointer register. */ 1457 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1458 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, 1459 sc, 0); 1460 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1461 BUS_DMASYNC_PREWRITE); 1462 1463 /* Init TX descriptors. */ 1464 rl_list_tx_init(sc); 1465 1466 /* 1467 * Enable transmit and receive. 1468 */ 1469 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1470 1471 /* 1472 * Set the initial TX and RX configuration. 1473 */ 1474 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1475 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1476 1477 /* Set the individual bit to receive frames for this host only. */ 1478 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1479 rxcfg |= RL_RXCFG_RX_INDIV; 1480 1481 /* If we want promiscuous mode, set the allframes bit. */ 1482 if (ifp->if_flags & IFF_PROMISC) { 1483 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1484 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1485 } else { 1486 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1487 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1488 } 1489 1490 /* 1491 * Set capture broadcast bit to capture broadcast frames. 1492 */ 1493 if (ifp->if_flags & IFF_BROADCAST) { 1494 rxcfg |= RL_RXCFG_RX_BROAD; 1495 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1496 } else { 1497 rxcfg &= ~RL_RXCFG_RX_BROAD; 1498 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1499 } 1500 1501 /* 1502 * Program the multicast filter, if necessary. 1503 */ 1504 rl_setmulti(sc); 1505 1506 #ifdef DEVICE_POLLING 1507 /* 1508 * Only enable interrupts if we are polling, keep them off otherwise. 1509 */ 1510 if (ifp->if_flags & IFF_POLLING) 1511 CSR_WRITE_2(sc, RL_IMR, 0); 1512 else 1513 #endif /* DEVICE_POLLING */ 1514 /* 1515 * Enable interrupts. 1516 */ 1517 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1518 1519 /* Set initial TX threshold */ 1520 sc->rl_txthresh = RL_TX_THRESH_INIT; 1521 1522 /* Start RX/TX process. */ 1523 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1524 1525 /* Enable receiver and transmitter. */ 1526 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1527 1528 mii_mediachg(mii); 1529 1530 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1531 1532 ifp->if_flags |= IFF_RUNNING; 1533 ifp->if_flags &= ~IFF_OACTIVE; 1534 1535 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc); 1536 1537 crit_exit(); 1538 } 1539 1540 /* 1541 * Set media options. 1542 */ 1543 static int 1544 rl_ifmedia_upd(struct ifnet *ifp) 1545 { 1546 struct rl_softc *sc; 1547 struct mii_data *mii; 1548 1549 sc = ifp->if_softc; 1550 mii = device_get_softc(sc->rl_miibus); 1551 mii_mediachg(mii); 1552 1553 return(0); 1554 } 1555 1556 /* 1557 * Report current media status. 1558 */ 1559 static void 1560 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1561 { 1562 struct rl_softc *sc = ifp->if_softc; 1563 struct mii_data *mii = device_get_softc(sc->rl_miibus); 1564 1565 mii_pollstat(mii); 1566 ifmr->ifm_active = mii->mii_media_active; 1567 ifmr->ifm_status = mii->mii_media_status; 1568 } 1569 1570 static int 1571 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1572 { 1573 struct rl_softc *sc = ifp->if_softc; 1574 struct ifreq *ifr = (struct ifreq *) data; 1575 struct mii_data *mii; 1576 int error = 0; 1577 1578 crit_enter(); 1579 1580 switch (command) { 1581 case SIOCSIFFLAGS: 1582 if (ifp->if_flags & IFF_UP) { 1583 rl_init(sc); 1584 } else { 1585 if (ifp->if_flags & IFF_RUNNING) 1586 rl_stop(sc); 1587 } 1588 error = 0; 1589 break; 1590 case SIOCADDMULTI: 1591 case SIOCDELMULTI: 1592 rl_setmulti(sc); 1593 error = 0; 1594 break; 1595 case SIOCGIFMEDIA: 1596 case SIOCSIFMEDIA: 1597 mii = device_get_softc(sc->rl_miibus); 1598 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1599 break; 1600 case SIOCSIFCAP: 1601 break; 1602 default: 1603 error = ether_ioctl(ifp, command, data); 1604 break; 1605 } 1606 1607 crit_exit(); 1608 1609 return(error); 1610 } 1611 1612 static void 1613 rl_watchdog(struct ifnet *ifp) 1614 { 1615 struct rl_softc *sc = ifp->if_softc; 1616 1617 device_printf(sc->rl_dev, "watchdog timeout\n"); 1618 1619 crit_enter(); 1620 1621 ifp->if_oerrors++; 1622 1623 rl_txeof(sc); 1624 rl_rxeof(sc); 1625 rl_init(sc); 1626 1627 crit_exit(); 1628 } 1629 1630 /* 1631 * Stop the adapter and free any mbufs allocated to the 1632 * RX and TX lists. 1633 */ 1634 static void 1635 rl_stop(struct rl_softc *sc) 1636 { 1637 struct ifnet *ifp = &sc->arpcom.ac_if; 1638 int i; 1639 1640 ifp->if_timer = 0; 1641 1642 callout_stop(&sc->rl_stat_timer); 1643 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1644 1645 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1646 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1647 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1648 1649 /* 1650 * Free the TX list buffers. 1651 */ 1652 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1653 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1654 bus_dmamap_unload(sc->rl_tag, 1655 sc->rl_cdata.rl_tx_dmamap[i]); 1656 bus_dmamap_destroy(sc->rl_tag, 1657 sc->rl_cdata.rl_tx_dmamap[i]); 1658 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1659 sc->rl_cdata.rl_tx_chain[i] = NULL; 1660 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 1661 0x0000000); 1662 } 1663 } 1664 } 1665 1666 /* 1667 * Stop all chip I/O so that the kernel's probe routines don't 1668 * get confused by errant DMAs when rebooting. 1669 */ 1670 static void 1671 rl_shutdown(device_t dev) 1672 { 1673 struct rl_softc *sc; 1674 1675 sc = device_get_softc(dev); 1676 1677 rl_stop(sc); 1678 } 1679 1680 /* 1681 * Device suspend routine. Stop the interface and save some PCI 1682 * settings in case the BIOS doesn't restore them properly on 1683 * resume. 1684 */ 1685 static int 1686 rl_suspend(device_t dev) 1687 { 1688 struct rl_softc *sc = device_get_softc(dev); 1689 int i; 1690 1691 rl_stop(sc); 1692 1693 for (i = 0; i < 5; i++) 1694 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1695 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1696 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1697 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1698 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1699 1700 sc->suspended = 1; 1701 1702 return (0); 1703 } 1704 1705 /* 1706 * Device resume routine. Restore some PCI settings in case the BIOS 1707 * doesn't, re-enable busmastering, and restart the interface if 1708 * appropriate. 1709 */ 1710 static int rl_resume(device_t dev) 1711 { 1712 struct rl_softc *sc = device_get_softc(dev); 1713 struct ifnet *ifp = &sc->arpcom.ac_if; 1714 int i; 1715 1716 /* better way to do this? */ 1717 for (i = 0; i < 5; i++) 1718 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 1719 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1720 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1721 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1722 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1723 1724 /* reenable busmastering */ 1725 pci_enable_busmaster(dev); 1726 pci_enable_io(dev, RL_RES); 1727 1728 /* reinitialize interface if necessary */ 1729 if (ifp->if_flags & IFF_UP) 1730 rl_init(sc); 1731 1732 sc->suspended = 0; 1733 1734 return (0); 1735 } 1736