1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/rl/if_rl.c,v 1.38 2008/08/17 04:32:34 sephe Exp $ 34 */ 35 36 /* 37 * RealTek 8129/8139 PCI NIC driver 38 * 39 * Supports several extremely cheap PCI 10/100 adapters based on 40 * the RealTek chipset. Datasheets can be obtained from 41 * www.realtek.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 50 * probably the worst PCI ethernet controller ever made, with the possible 51 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 52 * DMA, but it has a terrible interface that nullifies any performance 53 * gains that bus-master DMA usually offers. 54 * 55 * For transmission, the chip offers a series of four TX descriptor 56 * registers. Each transmit frame must be in a contiguous buffer, aligned 57 * on a longword (32-bit) boundary. This means we almost always have to 58 * do mbuf copies in order to transmit a frame, except in the unlikely 59 * case where a) the packet fits into a single mbuf, and b) the packet 60 * is 32-bit aligned within the mbuf's data area. The presence of only 61 * four descriptor registers means that we can never have more than four 62 * packets queued for transmission at any one time. 63 * 64 * Reception is not much better. The driver has to allocate a single large 65 * buffer area (up to 64K in size) into which the chip will DMA received 66 * frames. Because we don't know where within this region received packets 67 * will begin or end, we have no choice but to copy data from the buffer 68 * area into mbufs in order to pass the packets up to the higher protocol 69 * levels. 70 * 71 * It's impossible given this rotten design to really achieve decent 72 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 73 * some equally overmuscled CPU to drive it. 74 * 75 * On the bright side, the 8139 does have a built-in PHY, although 76 * rather than using an MDIO serial interface like most other NICs, the 77 * PHY registers are directly accessible through the 8139's register 78 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 79 * filter. 80 * 81 * The 8129 chip is an older version of the 8139 that uses an external PHY 82 * chip. The 8129 has a serial MDIO interface for accessing the MII where 83 * the 8139 lets you directly access the on-board PHY registers. We need 84 * to select which interface to use depending on the chip type. 85 */ 86 87 #include "opt_polling.h" 88 89 #include <sys/param.h> 90 #include <sys/endian.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/module.h> 97 #include <sys/socket.h> 98 #include <sys/serialize.h> 99 #include <sys/bus.h> 100 #include <sys/rman.h> 101 #include <sys/thread2.h> 102 #include <sys/interrupt.h> 103 104 #include <net/if.h> 105 #include <net/ifq_var.h> 106 #include <net/if_arp.h> 107 #include <net/ethernet.h> 108 #include <net/if_dl.h> 109 #include <net/if_media.h> 110 111 #include <net/bpf.h> 112 113 #include <dev/netif/mii_layer/mii.h> 114 #include <dev/netif/mii_layer/miivar.h> 115 116 #include <bus/pci/pcidevs.h> 117 #include <bus/pci/pcireg.h> 118 #include <bus/pci/pcivar.h> 119 120 /* "controller miibus0" required. See GENERIC if you get errors here. */ 121 #include "miibus_if.h" 122 123 /* 124 * Default to using PIO access for this driver. On SMP systems, 125 * there appear to be problems with memory mapped mode: it looks like 126 * doing too many memory mapped access back to back in rapid succession 127 * can hang the bus. I'm inclined to blame this on crummy design/construction 128 * on the part of RealTek. Memory mapped mode does appear to work on 129 * uniprocessor systems though. 130 */ 131 #define RL_USEIOSPACE 132 133 #include <dev/netif/rl/if_rlreg.h> 134 135 /* 136 * Various supported device vendors/types and their names. 137 */ 138 static struct rl_type { 139 uint16_t rl_vid; 140 uint16_t rl_did; 141 const char *rl_name; 142 } rl_devs[] = { 143 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8129, 144 "RealTek 8129 10/100BaseTX" }, 145 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, 146 "RealTek 8139 10/100BaseTX" }, 147 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139B, 148 "RealTek 8139 10/100BaseTX CardBus" }, 149 { PCI_VENDOR_ACCTON, PCI_PRODUCT_ACCTON_MPX5030, 150 "Accton MPX 5030/5038 10/100BaseTX" }, 151 { PCI_VENDOR_DELTA, PCI_PRODUCT_DELTA_8139, 152 "Delta Electronics 8139 10/100BaseTX" }, 153 { PCI_VENDOR_ADDTRON, PCI_PRODUCT_ADDTRON_8139, 154 "Addtron Technology 8139 10/100BaseTX" }, 155 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE530TXPLUS, 156 "D-Link DFE-530TX+ 10/100BaseTX" }, 157 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE690TXD, 158 "D-Link DFE-690TX 10/100BaseTX" }, 159 { PCI_VENDOR_NORTEL, PCI_PRODUCT_NORTEL_BAYSTACK_21, 160 "Nortel Networks 10/100BaseTX" }, 161 { PCI_VENDOR_PEPPERCON, PCI_PRODUCT_PEPPERCON_ROLF, 162 "Peppercon AG ROL/F" }, 163 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CB_TXD, 164 "Corega FEther CB-TXD" }, 165 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_2CB_TXD, 166 "Corega FEtherII CB-TXD" }, 167 { PCI_VENDOR_PLANEX, PCI_PRODUCT_PLANEX_FNW_3800_TX, 168 "Planex FNW-3800-TX" }, 169 { 0, 0, NULL } 170 }; 171 172 static int rl_probe(device_t); 173 static int rl_attach(device_t); 174 static int rl_detach(device_t); 175 176 static int rl_encap(struct rl_softc *, struct mbuf * ); 177 178 static void rl_rxeof(struct rl_softc *); 179 static void rl_txeof(struct rl_softc *); 180 static void rl_intr(void *); 181 static void rl_tick(void *); 182 static void rl_start(struct ifnet *); 183 static int rl_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 184 static void rl_init(void *); 185 static void rl_stop (struct rl_softc *); 186 static void rl_watchdog(struct ifnet *); 187 static int rl_suspend(device_t); 188 static int rl_resume(device_t); 189 static void rl_shutdown(device_t); 190 static int rl_ifmedia_upd(struct ifnet *); 191 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 192 193 static void rl_eeprom_putbyte(struct rl_softc *, int); 194 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *); 195 static void rl_read_eeprom(struct rl_softc *, caddr_t, int, int, int); 196 static void rl_mii_sync(struct rl_softc *); 197 static void rl_mii_send(struct rl_softc *, uint32_t, int); 198 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *); 199 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *); 200 201 static int rl_miibus_readreg(device_t, int, int); 202 static int rl_miibus_writereg(device_t, int, int, int); 203 static void rl_miibus_statchg(device_t); 204 205 static void rl_setmulti(struct rl_softc *); 206 static void rl_reset(struct rl_softc *); 207 static void rl_list_tx_init(struct rl_softc *); 208 209 #ifdef DEVICE_POLLING 210 static poll_handler_t rl_poll; 211 #endif 212 213 static int rl_dma_alloc(struct rl_softc *); 214 static void rl_dma_free(struct rl_softc *); 215 216 #ifdef RL_USEIOSPACE 217 #define RL_RES SYS_RES_IOPORT 218 #define RL_RID RL_PCI_LOIO 219 #else 220 #define RL_RES SYS_RES_MEMORY 221 #define RL_RID RL_PCI_LOMEM 222 #endif 223 224 static device_method_t rl_methods[] = { 225 /* Device interface */ 226 DEVMETHOD(device_probe, rl_probe), 227 DEVMETHOD(device_attach, rl_attach), 228 DEVMETHOD(device_detach, rl_detach), 229 DEVMETHOD(device_suspend, rl_suspend), 230 DEVMETHOD(device_resume, rl_resume), 231 DEVMETHOD(device_shutdown, rl_shutdown), 232 233 /* bus interface */ 234 DEVMETHOD(bus_print_child, bus_generic_print_child), 235 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 236 237 /* MII interface */ 238 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 239 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 240 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 241 242 { 0, 0 } 243 }; 244 245 static DEFINE_CLASS_0(rl, rl_driver, rl_methods, sizeof(struct rl_softc)); 246 static devclass_t rl_devclass; 247 248 DECLARE_DUMMY_MODULE(if_rl); 249 DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 250 DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 251 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 252 MODULE_DEPEND(if_rl, miibus, 1, 1, 1); 253 254 #define EE_SET(x) \ 255 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) | (x)) 256 257 #define EE_CLR(x) \ 258 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) & ~(x)) 259 260 /* 261 * Send a read command and address to the EEPROM, check for ACK. 262 */ 263 static void 264 rl_eeprom_putbyte(struct rl_softc *sc, int addr) 265 { 266 int d, i; 267 268 d = addr | sc->rl_eecmd_read; 269 270 /* 271 * Feed in each bit and strobe the clock. 272 */ 273 for (i = 0x400; i; i >>= 1) { 274 if (d & i) 275 EE_SET(RL_EE_DATAIN); 276 else 277 EE_CLR(RL_EE_DATAIN); 278 DELAY(100); 279 EE_SET(RL_EE_CLK); 280 DELAY(150); 281 EE_CLR(RL_EE_CLK); 282 DELAY(100); 283 } 284 } 285 286 /* 287 * Read a word of data stored in the EEPROM at address 'addr.' 288 */ 289 static void 290 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest) 291 { 292 int i; 293 uint16_t word = 0; 294 295 /* Enter EEPROM access mode. */ 296 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 297 298 /* 299 * Send address of word we want to read. 300 */ 301 rl_eeprom_putbyte(sc, addr); 302 303 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 304 305 /* 306 * Start reading bits from EEPROM. 307 */ 308 for (i = 0x8000; i; i >>= 1) { 309 EE_SET(RL_EE_CLK); 310 DELAY(100); 311 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 312 word |= i; 313 EE_CLR(RL_EE_CLK); 314 DELAY(100); 315 } 316 317 /* Turn off EEPROM access mode. */ 318 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 319 320 *dest = word; 321 } 322 323 /* 324 * Read a sequence of words from the EEPROM. 325 */ 326 static void 327 rl_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt, int swap) 328 { 329 int i; 330 u_int16_t word = 0, *ptr; 331 332 for (i = 0; i < cnt; i++) { 333 rl_eeprom_getword(sc, off + i, &word); 334 ptr = (u_int16_t *)(dest + (i * 2)); 335 if (swap) 336 *ptr = ntohs(word); 337 else 338 *ptr = word; 339 } 340 } 341 342 343 /* 344 * MII access routines are provided for the 8129, which 345 * doesn't have a built-in PHY. For the 8139, we fake things 346 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 347 * direct access PHY registers. 348 */ 349 #define MII_SET(x) \ 350 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) | x) 351 352 #define MII_CLR(x) \ 353 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) & ~x) 354 355 /* 356 * Sync the PHYs by setting data bit and strobing the clock 32 times. 357 */ 358 static void 359 rl_mii_sync(struct rl_softc *sc) 360 { 361 int i; 362 363 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 364 365 for (i = 0; i < 32; i++) { 366 MII_SET(RL_MII_CLK); 367 DELAY(1); 368 MII_CLR(RL_MII_CLK); 369 DELAY(1); 370 } 371 } 372 373 /* 374 * Clock a series of bits through the MII. 375 */ 376 static void 377 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt) 378 { 379 int i; 380 381 MII_CLR(RL_MII_CLK); 382 383 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 384 if (bits & i) 385 MII_SET(RL_MII_DATAOUT); 386 else 387 MII_CLR(RL_MII_DATAOUT); 388 DELAY(1); 389 MII_CLR(RL_MII_CLK); 390 DELAY(1); 391 MII_SET(RL_MII_CLK); 392 } 393 } 394 395 /* 396 * Read an PHY register through the MII. 397 */ 398 static int 399 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame) 400 { 401 int ack, i; 402 403 /* 404 * Set up frame for RX. 405 */ 406 frame->mii_stdelim = RL_MII_STARTDELIM; 407 frame->mii_opcode = RL_MII_READOP; 408 frame->mii_turnaround = 0; 409 frame->mii_data = 0; 410 411 CSR_WRITE_2(sc, RL_MII, 0); 412 413 /* 414 * Turn on data xmit. 415 */ 416 MII_SET(RL_MII_DIR); 417 418 rl_mii_sync(sc); 419 420 /* 421 * Send command/address info. 422 */ 423 rl_mii_send(sc, frame->mii_stdelim, 2); 424 rl_mii_send(sc, frame->mii_opcode, 2); 425 rl_mii_send(sc, frame->mii_phyaddr, 5); 426 rl_mii_send(sc, frame->mii_regaddr, 5); 427 428 /* Idle bit */ 429 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 430 DELAY(1); 431 MII_SET(RL_MII_CLK); 432 DELAY(1); 433 434 /* Turn off xmit. */ 435 MII_CLR(RL_MII_DIR); 436 437 /* Check for ack */ 438 MII_CLR(RL_MII_CLK); 439 DELAY(1); 440 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 441 MII_SET(RL_MII_CLK); 442 DELAY(1); 443 444 /* 445 * Now try reading data bits. If the ack failed, we still 446 * need to clock through 16 cycles to keep the PHY(s) in sync. 447 */ 448 if (ack) { 449 for(i = 0; i < 16; i++) { 450 MII_CLR(RL_MII_CLK); 451 DELAY(1); 452 MII_SET(RL_MII_CLK); 453 DELAY(1); 454 } 455 } else { 456 for (i = 0x8000; i; i >>= 1) { 457 MII_CLR(RL_MII_CLK); 458 DELAY(1); 459 if (!ack) { 460 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 461 frame->mii_data |= i; 462 DELAY(1); 463 } 464 MII_SET(RL_MII_CLK); 465 DELAY(1); 466 } 467 } 468 469 MII_CLR(RL_MII_CLK); 470 DELAY(1); 471 MII_SET(RL_MII_CLK); 472 DELAY(1); 473 474 return(ack ? 1 : 0); 475 } 476 477 /* 478 * Write to a PHY register through the MII. 479 */ 480 static int 481 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame) 482 { 483 /* 484 * Set up frame for TX. 485 */ 486 frame->mii_stdelim = RL_MII_STARTDELIM; 487 frame->mii_opcode = RL_MII_WRITEOP; 488 frame->mii_turnaround = RL_MII_TURNAROUND; 489 490 /* 491 * Turn on data output. 492 */ 493 MII_SET(RL_MII_DIR); 494 495 rl_mii_sync(sc); 496 497 rl_mii_send(sc, frame->mii_stdelim, 2); 498 rl_mii_send(sc, frame->mii_opcode, 2); 499 rl_mii_send(sc, frame->mii_phyaddr, 5); 500 rl_mii_send(sc, frame->mii_regaddr, 5); 501 rl_mii_send(sc, frame->mii_turnaround, 2); 502 rl_mii_send(sc, frame->mii_data, 16); 503 504 /* Idle bit. */ 505 MII_SET(RL_MII_CLK); 506 DELAY(1); 507 MII_CLR(RL_MII_CLK); 508 DELAY(1); 509 510 /* 511 * Turn off xmit. 512 */ 513 MII_CLR(RL_MII_DIR); 514 515 return(0); 516 } 517 518 static int 519 rl_miibus_readreg(device_t dev, int phy, int reg) 520 { 521 struct rl_softc *sc; 522 struct rl_mii_frame frame; 523 uint16_t rval = 0; 524 uint16_t rl8139_reg = 0; 525 526 sc = device_get_softc(dev); 527 528 if (sc->rl_type == RL_8139) { 529 /* Pretend the internal PHY is only at address 0 */ 530 if (phy) 531 return(0); 532 switch (reg) { 533 case MII_BMCR: 534 rl8139_reg = RL_BMCR; 535 break; 536 case MII_BMSR: 537 rl8139_reg = RL_BMSR; 538 break; 539 case MII_ANAR: 540 rl8139_reg = RL_ANAR; 541 break; 542 case MII_ANER: 543 rl8139_reg = RL_ANER; 544 break; 545 case MII_ANLPAR: 546 rl8139_reg = RL_LPAR; 547 break; 548 case MII_PHYIDR1: 549 case MII_PHYIDR2: 550 return(0); 551 break; 552 /* 553 * Allow the rlphy driver to read the media status 554 * register. If we have a link partner which does not 555 * support NWAY, this is the register which will tell 556 * us the results of parallel detection. 557 */ 558 case RL_MEDIASTAT: 559 rval = CSR_READ_1(sc, RL_MEDIASTAT); 560 return(rval); 561 default: 562 device_printf(dev, "bad phy register\n"); 563 return(0); 564 } 565 rval = CSR_READ_2(sc, rl8139_reg); 566 return(rval); 567 } 568 569 bzero(&frame, sizeof(frame)); 570 571 frame.mii_phyaddr = phy; 572 frame.mii_regaddr = reg; 573 rl_mii_readreg(sc, &frame); 574 575 return(frame.mii_data); 576 } 577 578 static int 579 rl_miibus_writereg(device_t dev, int phy, int reg, int data) 580 { 581 struct rl_softc *sc; 582 struct rl_mii_frame frame; 583 u_int16_t rl8139_reg = 0; 584 585 sc = device_get_softc(dev); 586 587 if (sc->rl_type == RL_8139) { 588 /* Pretend the internal PHY is only at address 0 */ 589 if (phy) 590 return(0); 591 switch (reg) { 592 case MII_BMCR: 593 rl8139_reg = RL_BMCR; 594 break; 595 case MII_BMSR: 596 rl8139_reg = RL_BMSR; 597 break; 598 case MII_ANAR: 599 rl8139_reg = RL_ANAR; 600 break; 601 case MII_ANER: 602 rl8139_reg = RL_ANER; 603 break; 604 case MII_ANLPAR: 605 rl8139_reg = RL_LPAR; 606 break; 607 case MII_PHYIDR1: 608 case MII_PHYIDR2: 609 return(0); 610 default: 611 device_printf(dev, "bad phy register\n"); 612 return(0); 613 } 614 CSR_WRITE_2(sc, rl8139_reg, data); 615 return(0); 616 } 617 618 bzero(&frame, sizeof(frame)); 619 620 frame.mii_phyaddr = phy; 621 frame.mii_regaddr = reg; 622 frame.mii_data = data; 623 624 rl_mii_writereg(sc, &frame); 625 626 return(0); 627 } 628 629 static void 630 rl_miibus_statchg(device_t dev) 631 { 632 } 633 634 /* 635 * Program the 64-bit multicast hash filter. 636 */ 637 static void 638 rl_setmulti(struct rl_softc *sc) 639 { 640 struct ifnet *ifp; 641 int h = 0; 642 uint32_t hashes[2] = { 0, 0 }; 643 struct ifmultiaddr *ifma; 644 uint32_t rxfilt; 645 int mcnt = 0; 646 647 ifp = &sc->arpcom.ac_if; 648 649 rxfilt = CSR_READ_4(sc, RL_RXCFG); 650 651 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 652 rxfilt |= RL_RXCFG_RX_MULTI; 653 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 654 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 655 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 656 return; 657 } 658 659 /* first, zot all the existing hash bits */ 660 CSR_WRITE_4(sc, RL_MAR0, 0); 661 CSR_WRITE_4(sc, RL_MAR4, 0); 662 663 /* now program new ones */ 664 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 665 if (ifma->ifma_addr->sa_family != AF_LINK) 666 continue; 667 h = ether_crc32_be( 668 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 669 ETHER_ADDR_LEN) >> 26; 670 if (h < 32) 671 hashes[0] |= (1 << h); 672 else 673 hashes[1] |= (1 << (h - 32)); 674 mcnt++; 675 } 676 677 if (mcnt) 678 rxfilt |= RL_RXCFG_RX_MULTI; 679 else 680 rxfilt &= ~RL_RXCFG_RX_MULTI; 681 682 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 683 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 684 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 685 } 686 687 static void 688 rl_reset(struct rl_softc *sc) 689 { 690 int i; 691 692 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 693 694 for (i = 0; i < RL_TIMEOUT; i++) { 695 DELAY(10); 696 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 697 break; 698 } 699 if (i == RL_TIMEOUT) 700 device_printf(sc->rl_dev, "reset never completed!\n"); 701 } 702 703 /* 704 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 705 * IDs against our list and return a device name if we find a match. 706 * 707 * Return with a value < 0 to give re(4) a change to attach. 708 */ 709 static int 710 rl_probe(device_t dev) 711 { 712 struct rl_type *t; 713 uint16_t product = pci_get_device(dev); 714 uint16_t vendor = pci_get_vendor(dev); 715 716 for (t = rl_devs; t->rl_name != NULL; t++) { 717 if (vendor == t->rl_vid && product == t->rl_did) { 718 device_set_desc(dev, t->rl_name); 719 return(-100); 720 } 721 } 722 723 return(ENXIO); 724 } 725 726 /* 727 * Attach the interface. Allocate softc structures, do ifmedia 728 * setup and ethernet/BPF attach. 729 */ 730 static int 731 rl_attach(device_t dev) 732 { 733 uint8_t eaddr[ETHER_ADDR_LEN]; 734 uint16_t as[3]; 735 struct rl_softc *sc; 736 struct ifnet *ifp; 737 uint16_t rl_did = 0; 738 int error = 0, rid, i; 739 740 sc = device_get_softc(dev); 741 sc->rl_dev = dev; 742 743 /* 744 * Handle power management nonsense. 745 */ 746 747 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 748 uint32_t iobase, membase, irq; 749 750 /* Save important PCI config data. */ 751 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 752 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 753 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 754 755 /* Reset the power state. */ 756 device_printf(dev, "chip is in D%d power mode " 757 "-- setting to D0\n", pci_get_powerstate(dev)); 758 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 759 760 /* Restore PCI config data. */ 761 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 762 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 763 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 764 } 765 766 pci_enable_busmaster(dev); 767 768 rid = RL_RID; 769 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE); 770 771 if (sc->rl_res == NULL) { 772 device_printf(dev, "couldn't map ports/memory\n"); 773 error = ENXIO; 774 goto fail; 775 } 776 777 sc->rl_btag = rman_get_bustag(sc->rl_res); 778 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 779 780 rid = 0; 781 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 782 RF_SHAREABLE | RF_ACTIVE); 783 784 if (sc->rl_irq == NULL) { 785 device_printf(dev, "couldn't map interrupt\n"); 786 error = ENXIO; 787 goto fail; 788 } 789 790 callout_init(&sc->rl_stat_timer); 791 792 /* Reset the adapter. */ 793 rl_reset(sc); 794 795 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 796 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0); 797 if (rl_did != 0x8129) 798 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 799 800 /* 801 * Get station address from the EEPROM. 802 */ 803 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 804 for (i = 0; i < 3; i++) { 805 eaddr[(i * 2) + 0] = as[i] & 0xff; 806 eaddr[(i * 2) + 1] = as[i] >> 8; 807 } 808 809 /* 810 * Now read the exact device type from the EEPROM to find 811 * out if it's an 8129 or 8139. 812 */ 813 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 814 815 if (rl_did == PCI_PRODUCT_REALTEK_RT8139 || 816 rl_did == PCI_PRODUCT_ACCTON_MPX5030 || 817 rl_did == PCI_PRODUCT_DELTA_8139 || 818 rl_did == PCI_PRODUCT_ADDTRON_8139 || 819 rl_did == PCI_PRODUCT_DLINK_DFE530TXPLUS || 820 rl_did == PCI_PRODUCT_REALTEK_RT8139B || 821 rl_did == PCI_PRODUCT_DLINK_DFE690TXD || 822 rl_did == PCI_PRODUCT_COREGA_CB_TXD || 823 rl_did == PCI_PRODUCT_COREGA_2CB_TXD || 824 rl_did == PCI_PRODUCT_PLANEX_FNW_3800_TX) { 825 sc->rl_type = RL_8139; 826 } else if (rl_did == PCI_PRODUCT_REALTEK_RT8129) { 827 sc->rl_type = RL_8129; 828 } else { 829 device_printf(dev, "unknown device ID: %x\n", rl_did); 830 sc->rl_type = RL_8139; 831 /* 832 * Read RL_IDR register to get ethernet address as accessing 833 * EEPROM may not extract correct address. 834 */ 835 for (i = 0; i < ETHER_ADDR_LEN; i++) 836 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 837 } 838 839 error = rl_dma_alloc(sc); 840 if (error) 841 goto fail; 842 843 /* Do MII setup */ 844 if (mii_phy_probe(dev, &sc->rl_miibus, rl_ifmedia_upd, 845 rl_ifmedia_sts)) { 846 device_printf(dev, "MII without any phy!\n"); 847 error = ENXIO; 848 goto fail; 849 } 850 851 ifp = &sc->arpcom.ac_if; 852 ifp->if_softc = sc; 853 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 854 ifp->if_mtu = ETHERMTU; 855 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 856 ifp->if_ioctl = rl_ioctl; 857 ifp->if_start = rl_start; 858 ifp->if_watchdog = rl_watchdog; 859 ifp->if_init = rl_init; 860 ifp->if_baudrate = 10000000; 861 ifp->if_capabilities = IFCAP_VLAN_MTU; 862 #ifdef DEVICE_POLLING 863 ifp->if_poll = rl_poll; 864 #endif 865 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 866 ifq_set_ready(&ifp->if_snd); 867 868 /* 869 * Call MI attach routine. 870 */ 871 ether_ifattach(ifp, eaddr, NULL); 872 873 error = bus_setup_intr(dev, sc->rl_irq, INTR_MPSAFE, rl_intr, 874 sc, &sc->rl_intrhand, ifp->if_serializer); 875 876 if (error) { 877 device_printf(dev, "couldn't set up irq\n"); 878 ether_ifdetach(ifp); 879 goto fail; 880 } 881 882 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->rl_irq)); 883 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 884 885 return(0); 886 887 fail: 888 rl_detach(dev); 889 return(error); 890 } 891 892 static int 893 rl_detach(device_t dev) 894 { 895 struct rl_softc *sc; 896 struct ifnet *ifp; 897 898 sc = device_get_softc(dev); 899 ifp = &sc->arpcom.ac_if; 900 901 if (device_is_attached(dev)) { 902 lwkt_serialize_enter(ifp->if_serializer); 903 rl_stop(sc); 904 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 905 lwkt_serialize_exit(ifp->if_serializer); 906 907 ether_ifdetach(ifp); 908 } 909 910 if (sc->rl_miibus) 911 device_delete_child(dev, sc->rl_miibus); 912 bus_generic_detach(dev); 913 914 if (sc->rl_irq) 915 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 916 if (sc->rl_res) 917 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 918 919 rl_dma_free(sc); 920 921 return(0); 922 } 923 924 /* 925 * Initialize the transmit descriptors. 926 */ 927 static void 928 rl_list_tx_init(struct rl_softc *sc) 929 { 930 struct rl_chain_data *cd; 931 int i; 932 933 cd = &sc->rl_cdata; 934 for (i = 0; i < RL_TX_LIST_CNT; i++) { 935 cd->rl_tx_chain[i] = NULL; 936 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 937 0x0000000); 938 } 939 940 sc->rl_cdata.cur_tx = 0; 941 sc->rl_cdata.last_tx = 0; 942 } 943 944 /* 945 * A frame has been uploaded: pass the resulting mbuf chain up to 946 * the higher level protocols. 947 * 948 * You know there's something wrong with a PCI bus-master chip design 949 * when you have to use m_devget(). 950 * 951 * The receive operation is badly documented in the datasheet, so I'll 952 * attempt to document it here. The driver provides a buffer area and 953 * places its base address in the RX buffer start address register. 954 * The chip then begins copying frames into the RX buffer. Each frame 955 * is preceded by a 32-bit RX status word which specifies the length 956 * of the frame and certain other status bits. Each frame (starting with 957 * the status word) is also 32-bit aligned. The frame length is in the 958 * first 16 bits of the status word; the lower 15 bits correspond with 959 * the 'rx status register' mentioned in the datasheet. 960 * 961 * Note: to make the Alpha happy, the frame payload needs to be aligned 962 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 963 * the ring buffer starting at an address two bytes before the actual 964 * data location. We can then shave off the first two bytes using m_adj(). 965 * The reason we do this is because m_devget() doesn't let us specify an 966 * offset into the mbuf storage space, so we have to artificially create 967 * one. The ring is allocated in such a way that there are a few unused 968 * bytes of space preceecing it so that it will be safe for us to do the 969 * 2-byte backstep even if reading from the ring at offset 0. 970 */ 971 static void 972 rl_rxeof(struct rl_softc *sc) 973 { 974 struct mbuf *m; 975 struct ifnet *ifp; 976 int total_len = 0; 977 uint32_t rxstat; 978 caddr_t rxbufpos; 979 int wrap = 0; 980 uint16_t cur_rx, limit, max_bytes, rx_bytes = 0; 981 982 ifp = &sc->arpcom.ac_if; 983 984 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 985 986 /* Do not try to read past this point. */ 987 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 988 989 if (limit < cur_rx) 990 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 991 else 992 max_bytes = limit - cur_rx; 993 994 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 995 #ifdef DEVICE_POLLING 996 if (ifp->if_flags & IFF_POLLING) { 997 if (sc->rxcycles <= 0) 998 break; 999 sc->rxcycles--; 1000 } 1001 #endif /* DEVICE_POLLING */ 1002 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1003 rxstat = le32toh(*(uint32_t *)rxbufpos); 1004 1005 /* 1006 * Here's a totally undocumented fact for you. When the 1007 * RealTek chip is in the process of copying a packet into 1008 * RAM for you, the length will be 0xfff0. If you spot a 1009 * packet header with this value, you need to stop. The 1010 * datasheet makes absolutely no mention of this and 1011 * RealTek should be shot for this. 1012 */ 1013 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1014 break; 1015 1016 if ((rxstat & RL_RXSTAT_RXOK) == 0) { 1017 ifp->if_ierrors++; 1018 rl_init(sc); 1019 return; 1020 } 1021 1022 /* No errors; receive the packet. */ 1023 total_len = rxstat >> 16; 1024 rx_bytes += total_len + 4; 1025 1026 /* 1027 * XXX The RealTek chip includes the CRC with every 1028 * received frame, and there's no way to turn this 1029 * behavior off (at least, I can't find anything in 1030 * the manual that explains how to do it) so we have 1031 * to trim off the CRC manually. 1032 */ 1033 total_len -= ETHER_CRC_LEN; 1034 1035 /* 1036 * Avoid trying to read more bytes than we know 1037 * the chip has prepared for us. 1038 */ 1039 if (rx_bytes > max_bytes) 1040 break; 1041 1042 rxbufpos = sc->rl_cdata.rl_rx_buf + 1043 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN); 1044 1045 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1046 rxbufpos = sc->rl_cdata.rl_rx_buf; 1047 1048 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1049 1050 if (total_len > wrap) { 1051 /* 1052 * Fool m_devget() into thinking we want to copy 1053 * the whole buffer so we don't end up fragmenting 1054 * the data. 1055 */ 1056 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1057 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1058 if (m == NULL) { 1059 ifp->if_ierrors++; 1060 } else { 1061 m_adj(m, RL_ETHER_ALIGN); 1062 m_copyback(m, wrap, total_len - wrap, 1063 sc->rl_cdata.rl_rx_buf); 1064 } 1065 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1066 } else { 1067 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1068 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1069 if (m == NULL) { 1070 ifp->if_ierrors++; 1071 } else 1072 m_adj(m, RL_ETHER_ALIGN); 1073 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1074 } 1075 1076 /* 1077 * Round up to 32-bit boundary. 1078 */ 1079 cur_rx = (cur_rx + 3) & ~3; 1080 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1081 1082 if (m == NULL) 1083 continue; 1084 1085 ifp->if_ipackets++; 1086 1087 ifp->if_input(ifp, m); 1088 } 1089 } 1090 1091 /* 1092 * A frame was downloaded to the chip. It's safe for us to clean up 1093 * the list buffers. 1094 */ 1095 static void 1096 rl_txeof(struct rl_softc *sc) 1097 { 1098 struct ifnet *ifp; 1099 uint32_t txstat; 1100 1101 ifp = &sc->arpcom.ac_if; 1102 1103 /* 1104 * Go through our tx list and free mbufs for those 1105 * frames that have been uploaded. 1106 */ 1107 do { 1108 if (RL_LAST_TXMBUF(sc) == NULL) 1109 break; 1110 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1111 if ((txstat & (RL_TXSTAT_TX_OK | RL_TXSTAT_TX_UNDERRUN | 1112 RL_TXSTAT_TXABRT)) == 0) 1113 break; 1114 1115 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1116 1117 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc)); 1118 m_freem(RL_LAST_TXMBUF(sc)); 1119 RL_LAST_TXMBUF(sc) = NULL; 1120 RL_INC(sc->rl_cdata.last_tx); 1121 1122 if (txstat & RL_TXSTAT_TX_UNDERRUN) { 1123 sc->rl_txthresh += 32; 1124 if (sc->rl_txthresh > RL_TX_THRESH_MAX) 1125 sc->rl_txthresh = RL_TX_THRESH_MAX; 1126 } 1127 1128 if (txstat & RL_TXSTAT_TX_OK) { 1129 ifp->if_opackets++; 1130 } else { 1131 ifp->if_oerrors++; 1132 if (txstat & (RL_TXSTAT_TXABRT | RL_TXSTAT_OUTOFWIN)) 1133 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1134 } 1135 ifp->if_flags &= ~IFF_OACTIVE; 1136 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1137 1138 if (RL_LAST_TXMBUF(sc) == NULL) 1139 ifp->if_timer = 0; 1140 else if (ifp->if_timer == 0) 1141 ifp->if_timer = 5; 1142 } 1143 1144 static void 1145 rl_tick(void *xsc) 1146 { 1147 struct rl_softc *sc = xsc; 1148 struct mii_data *mii; 1149 1150 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1151 1152 mii = device_get_softc(sc->rl_miibus); 1153 mii_tick(mii); 1154 1155 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc); 1156 1157 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1158 } 1159 1160 #ifdef DEVICE_POLLING 1161 1162 static void 1163 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1164 { 1165 struct rl_softc *sc = ifp->if_softc; 1166 1167 switch(cmd) { 1168 case POLL_REGISTER: 1169 /* disable interrupts */ 1170 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1171 break; 1172 case POLL_DEREGISTER: 1173 /* enable interrupts */ 1174 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1175 break; 1176 default: 1177 sc->rxcycles = count; 1178 rl_rxeof(sc); 1179 rl_txeof(sc); 1180 if (!ifq_is_empty(&ifp->if_snd)) 1181 if_devstart(ifp); 1182 1183 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1184 uint16_t status; 1185 1186 status = CSR_READ_2(sc, RL_ISR); 1187 if (status == 0xffff) 1188 return; 1189 if (status) 1190 CSR_WRITE_2(sc, RL_ISR, status); 1191 1192 /* 1193 * XXX check behaviour on receiver stalls. 1194 */ 1195 1196 if (status & RL_ISR_SYSTEM_ERR) { 1197 rl_reset(sc); 1198 rl_init(sc); 1199 } 1200 } 1201 break; 1202 } 1203 } 1204 #endif /* DEVICE_POLLING */ 1205 1206 static void 1207 rl_intr(void *arg) 1208 { 1209 struct rl_softc *sc; 1210 struct ifnet *ifp; 1211 uint16_t status; 1212 1213 sc = arg; 1214 1215 if (sc->suspended) 1216 return; 1217 1218 ifp = &sc->arpcom.ac_if; 1219 1220 for (;;) { 1221 status = CSR_READ_2(sc, RL_ISR); 1222 /* If the card has gone away, the read returns 0xffff. */ 1223 if (status == 0xffff) 1224 break; 1225 1226 if (status != 0) 1227 CSR_WRITE_2(sc, RL_ISR, status); 1228 1229 if ((status & RL_INTRS) == 0) 1230 break; 1231 1232 if (status & RL_ISR_RX_OK) 1233 rl_rxeof(sc); 1234 1235 if (status & RL_ISR_RX_ERR) 1236 rl_rxeof(sc); 1237 1238 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1239 rl_txeof(sc); 1240 1241 if (status & RL_ISR_SYSTEM_ERR) { 1242 rl_reset(sc); 1243 rl_init(sc); 1244 } 1245 1246 } 1247 1248 if (!ifq_is_empty(&ifp->if_snd)) 1249 if_devstart(ifp); 1250 } 1251 1252 /* 1253 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1254 * pointers to the fragment pointers. 1255 */ 1256 static int 1257 rl_encap(struct rl_softc *sc, struct mbuf *m_head) 1258 { 1259 struct mbuf *m_new = NULL; 1260 bus_dma_segment_t seg; 1261 int nseg, error; 1262 1263 /* 1264 * The RealTek is brain damaged and wants longword-aligned 1265 * TX buffers, plus we can only have one fragment buffer 1266 * per packet. We have to copy pretty much all the time. 1267 */ 1268 m_new = m_defrag(m_head, MB_DONTWAIT); 1269 if (m_new == NULL) { 1270 m_freem(m_head); 1271 return ENOBUFS; 1272 } 1273 m_head = m_new; 1274 1275 /* Pad frames to at least 60 bytes. */ 1276 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1277 error = m_devpad(m_head, RL_MIN_FRAMELEN); 1278 if (error) { 1279 m_freem(m_head); 1280 return error; 1281 } 1282 } 1283 1284 /* Extract physical address. */ 1285 error = bus_dmamap_load_mbuf_segment(sc->rl_cdata.rl_tx_tag, 1286 RL_CUR_DMAMAP(sc), m_head, 1287 &seg, 1, &nseg, BUS_DMA_NOWAIT); 1288 if (error) { 1289 m_freem(m_head); 1290 return error; 1291 } 1292 1293 /* Sync the loaded TX buffer. */ 1294 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc), 1295 BUS_DMASYNC_PREWRITE); 1296 1297 /* Transmit */ 1298 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), seg.ds_addr); 1299 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1300 RL_TXTHRESH(sc->rl_txthresh) | seg.ds_len); 1301 1302 RL_CUR_TXMBUF(sc) = m_head; 1303 return 0; 1304 } 1305 1306 /* 1307 * Main transmit routine. 1308 */ 1309 1310 static void 1311 rl_start(struct ifnet *ifp) 1312 { 1313 struct rl_softc *sc = ifp->if_softc; 1314 struct mbuf *m_head = NULL; 1315 1316 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 1317 return; 1318 1319 while (RL_CUR_TXMBUF(sc) == NULL) { 1320 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1321 if (m_head == NULL) 1322 break; 1323 1324 if (rl_encap(sc, m_head)) 1325 continue; 1326 1327 /* 1328 * If there's a BPF listener, bounce a copy of this frame 1329 * to him. 1330 */ 1331 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1332 1333 RL_INC(sc->rl_cdata.cur_tx); 1334 1335 /* 1336 * Set a timeout in case the chip goes out to lunch. 1337 */ 1338 ifp->if_timer = 5; 1339 } 1340 1341 /* 1342 * We broke out of the loop because all our TX slots are 1343 * full. Mark the NIC as busy until it drains some of the 1344 * packets from the queue. 1345 */ 1346 if (RL_CUR_TXMBUF(sc) != NULL) 1347 ifp->if_flags |= IFF_OACTIVE; 1348 } 1349 1350 static void 1351 rl_init(void *xsc) 1352 { 1353 struct rl_softc *sc = xsc; 1354 struct ifnet *ifp = &sc->arpcom.ac_if; 1355 struct mii_data *mii; 1356 uint32_t rxcfg = 0; 1357 1358 mii = device_get_softc(sc->rl_miibus); 1359 1360 /* 1361 * Cancel pending I/O and free all RX/TX buffers. 1362 */ 1363 rl_stop(sc); 1364 1365 /* 1366 * Init our MAC address. Even though the chipset documentation 1367 * doesn't mention it, we need to enter "Config register write enable" 1368 * mode to modify the ID registers. 1369 */ 1370 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1371 CSR_WRITE_STREAM_4(sc, RL_IDR0, 1372 *(uint32_t *)(&sc->arpcom.ac_enaddr[0])); 1373 CSR_WRITE_STREAM_4(sc, RL_IDR4, 1374 *(uint32_t *)(&sc->arpcom.ac_enaddr[4])); 1375 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1376 1377 /* Init the RX buffer pointer register. */ 1378 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr); 1379 1380 /* Init TX descriptors. */ 1381 rl_list_tx_init(sc); 1382 1383 /* 1384 * Enable transmit and receive. 1385 */ 1386 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1387 1388 /* 1389 * Set the initial TX and RX configuration. 1390 */ 1391 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1392 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1393 1394 /* Set the individual bit to receive frames for this host only. */ 1395 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1396 rxcfg |= RL_RXCFG_RX_INDIV; 1397 1398 /* If we want promiscuous mode, set the allframes bit. */ 1399 if (ifp->if_flags & IFF_PROMISC) { 1400 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1401 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1402 } else { 1403 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1404 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1405 } 1406 1407 /* 1408 * Set capture broadcast bit to capture broadcast frames. 1409 */ 1410 if (ifp->if_flags & IFF_BROADCAST) { 1411 rxcfg |= RL_RXCFG_RX_BROAD; 1412 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1413 } else { 1414 rxcfg &= ~RL_RXCFG_RX_BROAD; 1415 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1416 } 1417 1418 /* 1419 * Program the multicast filter, if necessary. 1420 */ 1421 rl_setmulti(sc); 1422 1423 #ifdef DEVICE_POLLING 1424 /* 1425 * Only enable interrupts if we are polling, keep them off otherwise. 1426 */ 1427 if (ifp->if_flags & IFF_POLLING) 1428 CSR_WRITE_2(sc, RL_IMR, 0); 1429 else 1430 #endif /* DEVICE_POLLING */ 1431 /* 1432 * Enable interrupts. 1433 */ 1434 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1435 1436 /* Set initial TX threshold */ 1437 sc->rl_txthresh = RL_TX_THRESH_INIT; 1438 1439 /* Start RX/TX process. */ 1440 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1441 1442 /* Enable receiver and transmitter. */ 1443 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1444 1445 mii_mediachg(mii); 1446 1447 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1448 1449 ifp->if_flags |= IFF_RUNNING; 1450 ifp->if_flags &= ~IFF_OACTIVE; 1451 1452 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc); 1453 } 1454 1455 /* 1456 * Set media options. 1457 */ 1458 static int 1459 rl_ifmedia_upd(struct ifnet *ifp) 1460 { 1461 struct rl_softc *sc; 1462 struct mii_data *mii; 1463 1464 sc = ifp->if_softc; 1465 mii = device_get_softc(sc->rl_miibus); 1466 mii_mediachg(mii); 1467 1468 return(0); 1469 } 1470 1471 /* 1472 * Report current media status. 1473 */ 1474 static void 1475 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1476 { 1477 struct rl_softc *sc = ifp->if_softc; 1478 struct mii_data *mii = device_get_softc(sc->rl_miibus); 1479 1480 mii_pollstat(mii); 1481 ifmr->ifm_active = mii->mii_media_active; 1482 ifmr->ifm_status = mii->mii_media_status; 1483 } 1484 1485 static int 1486 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1487 { 1488 struct rl_softc *sc = ifp->if_softc; 1489 struct ifreq *ifr = (struct ifreq *) data; 1490 struct mii_data *mii; 1491 int error = 0; 1492 1493 switch (command) { 1494 case SIOCSIFFLAGS: 1495 if (ifp->if_flags & IFF_UP) { 1496 rl_init(sc); 1497 } else { 1498 if (ifp->if_flags & IFF_RUNNING) 1499 rl_stop(sc); 1500 } 1501 error = 0; 1502 break; 1503 case SIOCADDMULTI: 1504 case SIOCDELMULTI: 1505 rl_setmulti(sc); 1506 error = 0; 1507 break; 1508 case SIOCGIFMEDIA: 1509 case SIOCSIFMEDIA: 1510 mii = device_get_softc(sc->rl_miibus); 1511 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1512 break; 1513 case SIOCSIFCAP: 1514 break; 1515 default: 1516 error = ether_ioctl(ifp, command, data); 1517 break; 1518 } 1519 1520 return(error); 1521 } 1522 1523 static void 1524 rl_watchdog(struct ifnet *ifp) 1525 { 1526 struct rl_softc *sc = ifp->if_softc; 1527 1528 device_printf(sc->rl_dev, "watchdog timeout\n"); 1529 1530 ifp->if_oerrors++; 1531 1532 rl_txeof(sc); 1533 rl_rxeof(sc); 1534 rl_init(sc); 1535 } 1536 1537 /* 1538 * Stop the adapter and free any mbufs allocated to the 1539 * RX and TX lists. 1540 */ 1541 static void 1542 rl_stop(struct rl_softc *sc) 1543 { 1544 struct ifnet *ifp = &sc->arpcom.ac_if; 1545 int i; 1546 1547 ifp->if_timer = 0; 1548 1549 callout_stop(&sc->rl_stat_timer); 1550 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1551 1552 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1553 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1554 1555 /* 1556 * Free the TX list buffers. 1557 */ 1558 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1559 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1560 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, 1561 sc->rl_cdata.rl_tx_dmamap[i]); 1562 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1563 sc->rl_cdata.rl_tx_chain[i] = NULL; 1564 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 1565 0x0000000); 1566 } 1567 } 1568 } 1569 1570 /* 1571 * Stop all chip I/O so that the kernel's probe routines don't 1572 * get confused by errant DMAs when rebooting. 1573 */ 1574 static void 1575 rl_shutdown(device_t dev) 1576 { 1577 struct rl_softc *sc; 1578 1579 sc = device_get_softc(dev); 1580 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1581 rl_stop(sc); 1582 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1583 } 1584 1585 /* 1586 * Device suspend routine. Stop the interface and save some PCI 1587 * settings in case the BIOS doesn't restore them properly on 1588 * resume. 1589 */ 1590 static int 1591 rl_suspend(device_t dev) 1592 { 1593 struct rl_softc *sc = device_get_softc(dev); 1594 int i; 1595 1596 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1597 rl_stop(sc); 1598 1599 for (i = 0; i < 5; i++) 1600 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1601 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1602 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1603 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1604 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1605 1606 sc->suspended = 1; 1607 1608 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1609 return (0); 1610 } 1611 1612 /* 1613 * Device resume routine. Restore some PCI settings in case the BIOS 1614 * doesn't, re-enable busmastering, and restart the interface if 1615 * appropriate. 1616 */ 1617 static int 1618 rl_resume(device_t dev) 1619 { 1620 struct rl_softc *sc = device_get_softc(dev); 1621 struct ifnet *ifp = &sc->arpcom.ac_if; 1622 int i; 1623 1624 lwkt_serialize_enter(ifp->if_serializer); 1625 1626 /* better way to do this? */ 1627 for (i = 0; i < 5; i++) 1628 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 1629 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1630 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1631 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1632 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1633 1634 /* reenable busmastering */ 1635 pci_enable_busmaster(dev); 1636 pci_enable_io(dev, RL_RES); 1637 1638 /* reinitialize interface if necessary */ 1639 if (ifp->if_flags & IFF_UP) 1640 rl_init(sc); 1641 1642 sc->suspended = 0; 1643 lwkt_serialize_exit(ifp->if_serializer); 1644 return (0); 1645 } 1646 1647 static int 1648 rl_dma_alloc(struct rl_softc *sc) 1649 { 1650 bus_dmamem_t dmem; 1651 int error, i; 1652 1653 error = bus_dma_tag_create(NULL, /* parent */ 1654 1, 0, /* alignment, boundary */ 1655 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1656 BUS_SPACE_MAXADDR, /* highaddr */ 1657 NULL, NULL, /* filter, filterarg */ 1658 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 1659 0, /* nsegments */ 1660 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1661 0, /* flags */ 1662 &sc->rl_parent_tag); 1663 if (error) { 1664 device_printf(sc->rl_dev, "can't create parent tag\n"); 1665 return error; 1666 } 1667 1668 /* Allocate a chunk of coherent memory for RX */ 1669 error = bus_dmamem_coherent(sc->rl_parent_tag, 1, 0, 1670 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1671 RL_RXBUFLEN + 1518, BUS_DMA_WAITOK, &dmem); 1672 if (error) 1673 return error; 1674 1675 sc->rl_cdata.rl_rx_tag = dmem.dmem_tag; 1676 sc->rl_cdata.rl_rx_dmamap = dmem.dmem_map; 1677 sc->rl_cdata.rl_rx_buf_ptr = dmem.dmem_addr; 1678 1679 /* NOTE: Apply same adjustment to vaddr and paddr */ 1680 sc->rl_cdata.rl_rx_buf = sc->rl_cdata.rl_rx_buf_ptr + sizeof(uint64_t); 1681 sc->rl_cdata.rl_rx_buf_paddr = dmem.dmem_busaddr + sizeof(uint64_t); 1682 1683 /* 1684 * Allocate TX mbuf's DMA tag and maps 1685 */ 1686 error = bus_dma_tag_create(sc->rl_parent_tag,/* parent */ 1687 RL_TXBUF_ALIGN, 0, /* alignment, boundary */ 1688 BUS_SPACE_MAXADDR, /* lowaddr */ 1689 BUS_SPACE_MAXADDR, /* highaddr */ 1690 NULL, NULL, /* filter, filterarg */ 1691 MCLBYTES, /* maxsize */ 1692 1, /* nsegments */ 1693 MCLBYTES, /* maxsegsize */ 1694 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | 1695 BUS_DMA_ALIGNED, /* flags */ 1696 &sc->rl_cdata.rl_tx_tag); 1697 if (error) { 1698 device_printf(sc->rl_dev, "can't create TX mbuf tag\n"); 1699 return error; 1700 } 1701 1702 for (i = 0; i < RL_TX_LIST_CNT; ++i) { 1703 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 1704 BUS_DMA_WAITOK, &sc->rl_cdata.rl_tx_dmamap[i]); 1705 if (error) { 1706 int j; 1707 1708 for (j = 0; j < i; ++j) { 1709 bus_dmamap_destroy(sc->rl_cdata.rl_tx_tag, 1710 sc->rl_cdata.rl_tx_dmamap[j]); 1711 } 1712 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag); 1713 sc->rl_cdata.rl_tx_tag = NULL; 1714 1715 device_printf(sc->rl_dev, "can't create TX mbuf map\n"); 1716 return error; 1717 } 1718 } 1719 return 0; 1720 } 1721 1722 static void 1723 rl_dma_free(struct rl_softc *sc) 1724 { 1725 if (sc->rl_cdata.rl_tx_tag != NULL) { 1726 int i; 1727 1728 for (i = 0; i < RL_TX_LIST_CNT; ++i) { 1729 bus_dmamap_destroy(sc->rl_cdata.rl_tx_tag, 1730 sc->rl_cdata.rl_tx_dmamap[i]); 1731 } 1732 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag); 1733 } 1734 1735 if (sc->rl_cdata.rl_rx_tag != NULL) { 1736 bus_dmamap_unload(sc->rl_cdata.rl_rx_tag, 1737 sc->rl_cdata.rl_rx_dmamap); 1738 /* NOTE: Use rl_rx_buf_ptr here */ 1739 bus_dmamem_free(sc->rl_cdata.rl_rx_tag, 1740 sc->rl_cdata.rl_rx_buf_ptr, 1741 sc->rl_cdata.rl_rx_dmamap); 1742 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag); 1743 } 1744 1745 if (sc->rl_parent_tag) 1746 bus_dma_tag_destroy(sc->rl_parent_tag); 1747 } 1748