1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $ 33 * $DragonFly: src/sys/dev/netif/sf/if_sf.c,v 1.3 2003/08/07 21:17:05 dillon Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $ 36 */ 37 38 /* 39 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 40 * Programming manual is available from: 41 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Department of Electical Engineering 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 50 * controller designed with flexibility and reducing CPU load in mind. 51 * The Starfire offers high and low priority buffer queues, a 52 * producer/consumer index mechanism and several different buffer 53 * queue and completion queue descriptor types. Any one of a number 54 * of different driver designs can be used, depending on system and 55 * OS requirements. This driver makes use of type0 transmit frame 56 * descriptors (since BSD fragments packets across an mbuf chain) 57 * and two RX buffer queues prioritized on size (one queue for small 58 * frames that will fit into a single mbuf, another with full size 59 * mbuf clusters for everything else). The producer/consumer indexes 60 * and completion queues are also used. 61 * 62 * One downside to the Starfire has to do with alignment: buffer 63 * queues must be aligned on 256-byte boundaries, and receive buffers 64 * must be aligned on longword boundaries. The receive buffer alignment 65 * causes problems on the Alpha platform, where the packet payload 66 * should be longword aligned. There is no simple way around this. 67 * 68 * For receive filtering, the Starfire offers 16 perfect filter slots 69 * and a 512-bit hash table. 70 * 71 * The Starfire has no internal transceiver, relying instead on an 72 * external MII-based transceiver. Accessing registers on external 73 * PHYs is done through a special register map rather than with the 74 * usual bitbang MDIO method. 75 * 76 * Acesssing the registers on the Starfire is a little tricky. The 77 * Starfire has a 512K internal register space. When programmed for 78 * PCI memory mapped mode, the entire register space can be accessed 79 * directly. However in I/O space mode, only 256 bytes are directly 80 * mapped into PCI I/O space. The other registers can be accessed 81 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 82 * registers inside the 256-byte I/O window. 83 */ 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/socket.h> 92 93 #include <net/if.h> 94 #include <net/if_arp.h> 95 #include <net/ethernet.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 99 #include <net/bpf.h> 100 101 #include <vm/vm.h> /* for vtophys */ 102 #include <vm/pmap.h> /* for vtophys */ 103 #include <machine/clock.h> /* for DELAY */ 104 #include <machine/bus_pio.h> 105 #include <machine/bus_memio.h> 106 #include <machine/bus.h> 107 #include <machine/resource.h> 108 #include <sys/bus.h> 109 #include <sys/rman.h> 110 111 #include "../mii_layer/mii.h" 112 #include "../mii_layer/miivar.h" 113 114 /* "controller miibus0" required. See GENERIC if you get errors here. */ 115 #include "miibus_if.h" 116 117 #include <bus/pci/pcireg.h> 118 #include <bus/pci/pcivar.h> 119 120 #define SF_USEIOSPACE 121 122 #include "if_sfreg.h" 123 124 static struct sf_type sf_devs[] = { 125 { AD_VENDORID, AD_DEVICEID_STARFIRE, 126 "Adaptec AIC-6915 10/100BaseTX" }, 127 { 0, 0, NULL } 128 }; 129 130 static int sf_probe __P((device_t)); 131 static int sf_attach __P((device_t)); 132 static int sf_detach __P((device_t)); 133 static void sf_intr __P((void *)); 134 static void sf_stats_update __P((void *)); 135 static void sf_rxeof __P((struct sf_softc *)); 136 static void sf_txeof __P((struct sf_softc *)); 137 static int sf_encap __P((struct sf_softc *, 138 struct sf_tx_bufdesc_type0 *, 139 struct mbuf *)); 140 static void sf_start __P((struct ifnet *)); 141 static int sf_ioctl __P((struct ifnet *, u_long, caddr_t)); 142 static void sf_init __P((void *)); 143 static void sf_stop __P((struct sf_softc *)); 144 static void sf_watchdog __P((struct ifnet *)); 145 static void sf_shutdown __P((device_t)); 146 static int sf_ifmedia_upd __P((struct ifnet *)); 147 static void sf_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 148 static void sf_reset __P((struct sf_softc *)); 149 static int sf_init_rx_ring __P((struct sf_softc *)); 150 static void sf_init_tx_ring __P((struct sf_softc *)); 151 static int sf_newbuf __P((struct sf_softc *, 152 struct sf_rx_bufdesc_type0 *, 153 struct mbuf *)); 154 static void sf_setmulti __P((struct sf_softc *)); 155 static int sf_setperf __P((struct sf_softc *, int, caddr_t)); 156 static int sf_sethash __P((struct sf_softc *, caddr_t, int)); 157 #ifdef notdef 158 static int sf_setvlan __P((struct sf_softc *, int, u_int32_t)); 159 #endif 160 161 static u_int8_t sf_read_eeprom __P((struct sf_softc *, int)); 162 static u_int32_t sf_calchash __P((caddr_t)); 163 164 static int sf_miibus_readreg __P((device_t, int, int)); 165 static int sf_miibus_writereg __P((device_t, int, int, int)); 166 static void sf_miibus_statchg __P((device_t)); 167 168 static u_int32_t csr_read_4 __P((struct sf_softc *, int)); 169 static void csr_write_4 __P((struct sf_softc *, int, u_int32_t)); 170 static void sf_txthresh_adjust __P((struct sf_softc *)); 171 172 #ifdef SF_USEIOSPACE 173 #define SF_RES SYS_RES_IOPORT 174 #define SF_RID SF_PCI_LOIO 175 #else 176 #define SF_RES SYS_RES_MEMORY 177 #define SF_RID SF_PCI_LOMEM 178 #endif 179 180 static device_method_t sf_methods[] = { 181 /* Device interface */ 182 DEVMETHOD(device_probe, sf_probe), 183 DEVMETHOD(device_attach, sf_attach), 184 DEVMETHOD(device_detach, sf_detach), 185 DEVMETHOD(device_shutdown, sf_shutdown), 186 187 /* bus interface */ 188 DEVMETHOD(bus_print_child, bus_generic_print_child), 189 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 190 191 /* MII interface */ 192 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 193 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 194 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 195 196 { 0, 0 } 197 }; 198 199 static driver_t sf_driver = { 200 "sf", 201 sf_methods, 202 sizeof(struct sf_softc), 203 }; 204 205 static devclass_t sf_devclass; 206 207 DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 208 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 209 210 #define SF_SETBIT(sc, reg, x) \ 211 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 212 213 #define SF_CLRBIT(sc, reg, x) \ 214 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 215 216 static u_int32_t csr_read_4(sc, reg) 217 struct sf_softc *sc; 218 int reg; 219 { 220 u_int32_t val; 221 222 #ifdef SF_USEIOSPACE 223 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 224 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 225 #else 226 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 227 #endif 228 229 return(val); 230 } 231 232 static u_int8_t sf_read_eeprom(sc, reg) 233 struct sf_softc *sc; 234 int reg; 235 { 236 u_int8_t val; 237 238 val = (csr_read_4(sc, SF_EEADDR_BASE + 239 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 240 241 return(val); 242 } 243 244 static void csr_write_4(sc, reg, val) 245 struct sf_softc *sc; 246 int reg; 247 u_int32_t val; 248 { 249 #ifdef SF_USEIOSPACE 250 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 251 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 252 #else 253 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 254 #endif 255 return; 256 } 257 258 static u_int32_t sf_calchash(addr) 259 caddr_t addr; 260 { 261 u_int32_t crc, carry; 262 int i, j; 263 u_int8_t c; 264 265 /* Compute CRC for the address value. */ 266 crc = 0xFFFFFFFF; /* initial value */ 267 268 for (i = 0; i < 6; i++) { 269 c = *(addr + i); 270 for (j = 0; j < 8; j++) { 271 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 272 crc <<= 1; 273 c >>= 1; 274 if (carry) 275 crc = (crc ^ 0x04c11db6) | carry; 276 } 277 } 278 279 /* return the filter bit position */ 280 return(crc >> 23 & 0x1FF); 281 } 282 283 /* 284 * Copy the address 'mac' into the perfect RX filter entry at 285 * offset 'idx.' The perfect filter only has 16 entries so do 286 * some sanity tests. 287 */ 288 static int sf_setperf(sc, idx, mac) 289 struct sf_softc *sc; 290 int idx; 291 caddr_t mac; 292 { 293 u_int16_t *p; 294 295 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 296 return(EINVAL); 297 298 if (mac == NULL) 299 return(EINVAL); 300 301 p = (u_int16_t *)mac; 302 303 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 304 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 305 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 306 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 307 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 308 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 309 310 return(0); 311 } 312 313 /* 314 * Set the bit in the 512-bit hash table that corresponds to the 315 * specified mac address 'mac.' If 'prio' is nonzero, update the 316 * priority hash table instead of the filter hash table. 317 */ 318 static int sf_sethash(sc, mac, prio) 319 struct sf_softc *sc; 320 caddr_t mac; 321 int prio; 322 { 323 u_int32_t h = 0; 324 325 if (mac == NULL) 326 return(EINVAL); 327 328 h = sf_calchash(mac); 329 330 if (prio) { 331 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 332 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 333 } else { 334 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 335 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 336 } 337 338 return(0); 339 } 340 341 #ifdef notdef 342 /* 343 * Set a VLAN tag in the receive filter. 344 */ 345 static int sf_setvlan(sc, idx, vlan) 346 struct sf_softc *sc; 347 int idx; 348 u_int32_t vlan; 349 { 350 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 351 return(EINVAL); 352 353 csr_write_4(sc, SF_RXFILT_HASH_BASE + 354 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 355 356 return(0); 357 } 358 #endif 359 360 static int sf_miibus_readreg(dev, phy, reg) 361 device_t dev; 362 int phy, reg; 363 { 364 struct sf_softc *sc; 365 int i; 366 u_int32_t val = 0; 367 368 sc = device_get_softc(dev); 369 370 for (i = 0; i < SF_TIMEOUT; i++) { 371 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 372 if (val & SF_MII_DATAVALID) 373 break; 374 } 375 376 if (i == SF_TIMEOUT) 377 return(0); 378 379 if ((val & 0x0000FFFF) == 0xFFFF) 380 return(0); 381 382 return(val & 0x0000FFFF); 383 } 384 385 static int sf_miibus_writereg(dev, phy, reg, val) 386 device_t dev; 387 int phy, reg, val; 388 { 389 struct sf_softc *sc; 390 int i; 391 int busy; 392 393 sc = device_get_softc(dev); 394 395 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 396 397 for (i = 0; i < SF_TIMEOUT; i++) { 398 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 399 if (!(busy & SF_MII_BUSY)) 400 break; 401 } 402 403 return(0); 404 } 405 406 static void sf_miibus_statchg(dev) 407 device_t dev; 408 { 409 struct sf_softc *sc; 410 struct mii_data *mii; 411 412 sc = device_get_softc(dev); 413 mii = device_get_softc(sc->sf_miibus); 414 415 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 416 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 417 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 418 } else { 419 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 420 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 421 } 422 423 return; 424 } 425 426 static void sf_setmulti(sc) 427 struct sf_softc *sc; 428 { 429 struct ifnet *ifp; 430 int i; 431 struct ifmultiaddr *ifma; 432 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 433 434 ifp = &sc->arpcom.ac_if; 435 436 /* First zot all the existing filters. */ 437 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 438 sf_setperf(sc, i, (char *)&dummy); 439 for (i = SF_RXFILT_HASH_BASE; 440 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 441 csr_write_4(sc, i, 0); 442 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 443 444 /* Now program new ones. */ 445 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 446 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 447 } else { 448 i = 1; 449 /* First find the tail of the list. */ 450 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 451 ifma = ifma->ifma_link.le_next) { 452 if (ifma->ifma_link.le_next == NULL) 453 break; 454 } 455 /* Now traverse the list backwards. */ 456 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 457 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 458 if (ifma->ifma_addr->sa_family != AF_LINK) 459 continue; 460 /* 461 * Program the first 15 multicast groups 462 * into the perfect filter. For all others, 463 * use the hash table. 464 */ 465 if (i < SF_RXFILT_PERFECT_CNT) { 466 sf_setperf(sc, i, 467 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 468 i++; 469 continue; 470 } 471 472 sf_sethash(sc, 473 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 474 } 475 } 476 477 return; 478 } 479 480 /* 481 * Set media options. 482 */ 483 static int sf_ifmedia_upd(ifp) 484 struct ifnet *ifp; 485 { 486 struct sf_softc *sc; 487 struct mii_data *mii; 488 489 sc = ifp->if_softc; 490 mii = device_get_softc(sc->sf_miibus); 491 sc->sf_link = 0; 492 if (mii->mii_instance) { 493 struct mii_softc *miisc; 494 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 495 miisc = LIST_NEXT(miisc, mii_list)) 496 mii_phy_reset(miisc); 497 } 498 mii_mediachg(mii); 499 500 return(0); 501 } 502 503 /* 504 * Report current media status. 505 */ 506 static void sf_ifmedia_sts(ifp, ifmr) 507 struct ifnet *ifp; 508 struct ifmediareq *ifmr; 509 { 510 struct sf_softc *sc; 511 struct mii_data *mii; 512 513 sc = ifp->if_softc; 514 mii = device_get_softc(sc->sf_miibus); 515 516 mii_pollstat(mii); 517 ifmr->ifm_active = mii->mii_media_active; 518 ifmr->ifm_status = mii->mii_media_status; 519 520 return; 521 } 522 523 static int sf_ioctl(ifp, command, data) 524 struct ifnet *ifp; 525 u_long command; 526 caddr_t data; 527 { 528 struct sf_softc *sc = ifp->if_softc; 529 struct ifreq *ifr = (struct ifreq *) data; 530 struct mii_data *mii; 531 int s, error = 0; 532 533 s = splimp(); 534 535 switch(command) { 536 case SIOCSIFADDR: 537 case SIOCGIFADDR: 538 case SIOCSIFMTU: 539 error = ether_ioctl(ifp, command, data); 540 break; 541 case SIOCSIFFLAGS: 542 if (ifp->if_flags & IFF_UP) { 543 if (ifp->if_flags & IFF_RUNNING && 544 ifp->if_flags & IFF_PROMISC && 545 !(sc->sf_if_flags & IFF_PROMISC)) { 546 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 547 } else if (ifp->if_flags & IFF_RUNNING && 548 !(ifp->if_flags & IFF_PROMISC) && 549 sc->sf_if_flags & IFF_PROMISC) { 550 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 551 } else if (!(ifp->if_flags & IFF_RUNNING)) 552 sf_init(sc); 553 } else { 554 if (ifp->if_flags & IFF_RUNNING) 555 sf_stop(sc); 556 } 557 sc->sf_if_flags = ifp->if_flags; 558 error = 0; 559 break; 560 case SIOCADDMULTI: 561 case SIOCDELMULTI: 562 sf_setmulti(sc); 563 error = 0; 564 break; 565 case SIOCGIFMEDIA: 566 case SIOCSIFMEDIA: 567 mii = device_get_softc(sc->sf_miibus); 568 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 569 break; 570 default: 571 error = EINVAL; 572 break; 573 } 574 575 (void)splx(s); 576 577 return(error); 578 } 579 580 static void sf_reset(sc) 581 struct sf_softc *sc; 582 { 583 register int i; 584 585 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 586 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 587 DELAY(1000); 588 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 589 590 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 591 592 for (i = 0; i < SF_TIMEOUT; i++) { 593 DELAY(10); 594 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 595 break; 596 } 597 598 if (i == SF_TIMEOUT) 599 printf("sf%d: reset never completed!\n", sc->sf_unit); 600 601 /* Wait a little while for the chip to get its brains in order. */ 602 DELAY(1000); 603 return; 604 } 605 606 /* 607 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 608 * IDs against our list and return a device name if we find a match. 609 * We also check the subsystem ID so that we can identify exactly which 610 * NIC has been found, if possible. 611 */ 612 static int sf_probe(dev) 613 device_t dev; 614 { 615 struct sf_type *t; 616 617 t = sf_devs; 618 619 while(t->sf_name != NULL) { 620 if ((pci_get_vendor(dev) == t->sf_vid) && 621 (pci_get_device(dev) == t->sf_did)) { 622 switch((pci_read_config(dev, 623 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 624 case AD_SUBSYSID_62011_REV0: 625 case AD_SUBSYSID_62011_REV1: 626 device_set_desc(dev, 627 "Adaptec ANA-62011 10/100BaseTX"); 628 return(0); 629 break; 630 case AD_SUBSYSID_62022: 631 device_set_desc(dev, 632 "Adaptec ANA-62022 10/100BaseTX"); 633 return(0); 634 break; 635 case AD_SUBSYSID_62044_REV0: 636 case AD_SUBSYSID_62044_REV1: 637 device_set_desc(dev, 638 "Adaptec ANA-62044 10/100BaseTX"); 639 return(0); 640 break; 641 case AD_SUBSYSID_62020: 642 device_set_desc(dev, 643 "Adaptec ANA-62020 10/100BaseFX"); 644 return(0); 645 break; 646 case AD_SUBSYSID_69011: 647 device_set_desc(dev, 648 "Adaptec ANA-69011 10/100BaseTX"); 649 return(0); 650 break; 651 default: 652 device_set_desc(dev, t->sf_name); 653 return(0); 654 break; 655 } 656 } 657 t++; 658 } 659 660 return(ENXIO); 661 } 662 663 /* 664 * Attach the interface. Allocate softc structures, do ifmedia 665 * setup and ethernet/BPF attach. 666 */ 667 static int sf_attach(dev) 668 device_t dev; 669 { 670 int s, i; 671 u_int32_t command; 672 struct sf_softc *sc; 673 struct ifnet *ifp; 674 int unit, rid, error = 0; 675 676 s = splimp(); 677 678 sc = device_get_softc(dev); 679 unit = device_get_unit(dev); 680 bzero(sc, sizeof(struct sf_softc)); 681 682 /* 683 * Handle power management nonsense. 684 */ 685 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 686 if (command == 0x01) { 687 688 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 689 if (command & SF_PSTATE_MASK) { 690 u_int32_t iobase, membase, irq; 691 692 /* Save important PCI config data. */ 693 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 694 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 695 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 696 697 /* Reset the power state. */ 698 printf("sf%d: chip is in D%d power mode " 699 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 700 command &= 0xFFFFFFFC; 701 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 702 703 /* Restore PCI config data. */ 704 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 705 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 706 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 707 } 708 } 709 710 /* 711 * Map control/status registers. 712 */ 713 command = pci_read_config(dev, PCIR_COMMAND, 4); 714 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 715 pci_write_config(dev, PCIR_COMMAND, command, 4); 716 command = pci_read_config(dev, PCIR_COMMAND, 4); 717 718 #ifdef SF_USEIOSPACE 719 if (!(command & PCIM_CMD_PORTEN)) { 720 printf("sf%d: failed to enable I/O ports!\n", unit); 721 error = ENXIO; 722 goto fail; 723 } 724 #else 725 if (!(command & PCIM_CMD_MEMEN)) { 726 printf("sf%d: failed to enable memory mapping!\n", unit); 727 error = ENXIO; 728 goto fail; 729 } 730 #endif 731 732 rid = SF_RID; 733 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 734 0, ~0, 1, RF_ACTIVE); 735 736 if (sc->sf_res == NULL) { 737 printf ("sf%d: couldn't map ports\n", unit); 738 error = ENXIO; 739 goto fail; 740 } 741 742 sc->sf_btag = rman_get_bustag(sc->sf_res); 743 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 744 745 /* Allocate interrupt */ 746 rid = 0; 747 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 748 RF_SHAREABLE | RF_ACTIVE); 749 750 if (sc->sf_irq == NULL) { 751 printf("sf%d: couldn't map interrupt\n", unit); 752 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 753 error = ENXIO; 754 goto fail; 755 } 756 757 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 758 sf_intr, sc, &sc->sf_intrhand); 759 760 if (error) { 761 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 762 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 763 printf("sf%d: couldn't set up irq\n", unit); 764 goto fail; 765 } 766 767 callout_handle_init(&sc->sf_stat_ch); 768 769 /* Reset the adapter. */ 770 sf_reset(sc); 771 772 /* 773 * Get station address from the EEPROM. 774 */ 775 for (i = 0; i < ETHER_ADDR_LEN; i++) 776 sc->arpcom.ac_enaddr[i] = 777 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 778 779 /* 780 * An Adaptec chip was detected. Inform the world. 781 */ 782 printf("sf%d: Ethernet address: %6D\n", unit, 783 sc->arpcom.ac_enaddr, ":"); 784 785 sc->sf_unit = unit; 786 787 /* Allocate the descriptor queues. */ 788 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 789 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 790 791 if (sc->sf_ldata == NULL) { 792 printf("sf%d: no memory for list buffers!\n", unit); 793 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 794 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 795 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 796 error = ENXIO; 797 goto fail; 798 } 799 800 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 801 802 /* Do MII setup. */ 803 if (mii_phy_probe(dev, &sc->sf_miibus, 804 sf_ifmedia_upd, sf_ifmedia_sts)) { 805 printf("sf%d: MII without any phy!\n", sc->sf_unit); 806 contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF); 807 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 808 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 809 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 810 error = ENXIO; 811 goto fail; 812 } 813 814 ifp = &sc->arpcom.ac_if; 815 ifp->if_softc = sc; 816 ifp->if_unit = unit; 817 ifp->if_name = "sf"; 818 ifp->if_mtu = ETHERMTU; 819 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 820 ifp->if_ioctl = sf_ioctl; 821 ifp->if_output = ether_output; 822 ifp->if_start = sf_start; 823 ifp->if_watchdog = sf_watchdog; 824 ifp->if_init = sf_init; 825 ifp->if_baudrate = 10000000; 826 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 827 828 /* 829 * Call MI attach routine. 830 */ 831 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 832 833 fail: 834 splx(s); 835 return(error); 836 } 837 838 static int sf_detach(dev) 839 device_t dev; 840 { 841 struct sf_softc *sc; 842 struct ifnet *ifp; 843 int s; 844 845 s = splimp(); 846 847 sc = device_get_softc(dev); 848 ifp = &sc->arpcom.ac_if; 849 850 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 851 sf_stop(sc); 852 853 bus_generic_detach(dev); 854 device_delete_child(dev, sc->sf_miibus); 855 856 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 857 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 858 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 859 860 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 861 862 splx(s); 863 864 return(0); 865 } 866 867 static int sf_init_rx_ring(sc) 868 struct sf_softc *sc; 869 { 870 struct sf_list_data *ld; 871 int i; 872 873 ld = sc->sf_ldata; 874 875 bzero((char *)ld->sf_rx_dlist_big, 876 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 877 bzero((char *)ld->sf_rx_clist, 878 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 879 880 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 881 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 882 return(ENOBUFS); 883 } 884 885 return(0); 886 } 887 888 static void sf_init_tx_ring(sc) 889 struct sf_softc *sc; 890 { 891 struct sf_list_data *ld; 892 int i; 893 894 ld = sc->sf_ldata; 895 896 bzero((char *)ld->sf_tx_dlist, 897 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 898 bzero((char *)ld->sf_tx_clist, 899 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 900 901 for (i = 0; i < SF_TX_DLIST_CNT; i++) 902 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 903 for (i = 0; i < SF_TX_CLIST_CNT; i++) 904 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 905 906 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 907 sc->sf_tx_cnt = 0; 908 909 return; 910 } 911 912 static int sf_newbuf(sc, c, m) 913 struct sf_softc *sc; 914 struct sf_rx_bufdesc_type0 *c; 915 struct mbuf *m; 916 { 917 struct mbuf *m_new = NULL; 918 919 if (m == NULL) { 920 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 921 if (m_new == NULL) 922 return(ENOBUFS); 923 924 MCLGET(m_new, M_DONTWAIT); 925 if (!(m_new->m_flags & M_EXT)) { 926 m_freem(m_new); 927 return(ENOBUFS); 928 } 929 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 930 } else { 931 m_new = m; 932 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 933 m_new->m_data = m_new->m_ext.ext_buf; 934 } 935 936 m_adj(m_new, sizeof(u_int64_t)); 937 938 c->sf_mbuf = m_new; 939 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 940 c->sf_valid = 1; 941 942 return(0); 943 } 944 945 /* 946 * The starfire is programmed to use 'normal' mode for packet reception, 947 * which means we use the consumer/producer model for both the buffer 948 * descriptor queue and the completion descriptor queue. The only problem 949 * with this is that it involves a lot of register accesses: we have to 950 * read the RX completion consumer and producer indexes and the RX buffer 951 * producer index, plus the RX completion consumer and RX buffer producer 952 * indexes have to be updated. It would have been easier if Adaptec had 953 * put each index in a separate register, especially given that the damn 954 * NIC has a 512K register space. 955 * 956 * In spite of all the lovely features that Adaptec crammed into the 6915, 957 * it is marred by one truly stupid design flaw, which is that receive 958 * buffer addresses must be aligned on a longword boundary. This forces 959 * the packet payload to be unaligned, which is suboptimal on the x86 and 960 * completely unuseable on the Alpha. Our only recourse is to copy received 961 * packets into properly aligned buffers before handing them off. 962 */ 963 964 static void sf_rxeof(sc) 965 struct sf_softc *sc; 966 { 967 struct ether_header *eh; 968 struct mbuf *m; 969 struct ifnet *ifp; 970 struct sf_rx_bufdesc_type0 *desc; 971 struct sf_rx_cmpdesc_type3 *cur_rx; 972 u_int32_t rxcons, rxprod; 973 int cmpprodidx, cmpconsidx, bufprodidx; 974 975 ifp = &sc->arpcom.ac_if; 976 977 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 978 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 979 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 980 cmpconsidx = SF_IDX_LO(rxcons); 981 bufprodidx = SF_IDX_LO(rxprod); 982 983 while (cmpconsidx != cmpprodidx) { 984 struct mbuf *m0; 985 986 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 987 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 988 m = desc->sf_mbuf; 989 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 990 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 991 992 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 993 ifp->if_ierrors++; 994 sf_newbuf(sc, desc, m); 995 continue; 996 } 997 998 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 999 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 1000 sf_newbuf(sc, desc, m); 1001 if (m0 == NULL) { 1002 ifp->if_ierrors++; 1003 continue; 1004 } 1005 m_adj(m0, ETHER_ALIGN); 1006 m = m0; 1007 1008 eh = mtod(m, struct ether_header *); 1009 ifp->if_ipackets++; 1010 1011 /* Remove header from mbuf and pass it on. */ 1012 m_adj(m, sizeof(struct ether_header)); 1013 ether_input(ifp, eh, m); 1014 } 1015 1016 csr_write_4(sc, SF_CQ_CONSIDX, 1017 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1018 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1019 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1020 1021 return; 1022 } 1023 1024 /* 1025 * Read the transmit status from the completion queue and release 1026 * mbufs. Note that the buffer descriptor index in the completion 1027 * descriptor is an offset from the start of the transmit buffer 1028 * descriptor list in bytes. This is important because the manual 1029 * gives the impression that it should match the producer/consumer 1030 * index, which is the offset in 8 byte blocks. 1031 */ 1032 static void sf_txeof(sc) 1033 struct sf_softc *sc; 1034 { 1035 int txcons, cmpprodidx, cmpconsidx; 1036 struct sf_tx_cmpdesc_type1 *cur_cmp; 1037 struct sf_tx_bufdesc_type0 *cur_tx; 1038 struct ifnet *ifp; 1039 1040 ifp = &sc->arpcom.ac_if; 1041 1042 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1043 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1044 cmpconsidx = SF_IDX_HI(txcons); 1045 1046 while (cmpconsidx != cmpprodidx) { 1047 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1048 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1049 1050 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1051 ifp->if_opackets++; 1052 else { 1053 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1054 sf_txthresh_adjust(sc); 1055 ifp->if_oerrors++; 1056 } 1057 1058 sc->sf_tx_cnt--; 1059 if (cur_tx->sf_mbuf != NULL) { 1060 m_freem(cur_tx->sf_mbuf); 1061 cur_tx->sf_mbuf = NULL; 1062 } else 1063 break; 1064 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1065 } 1066 1067 ifp->if_timer = 0; 1068 ifp->if_flags &= ~IFF_OACTIVE; 1069 1070 csr_write_4(sc, SF_CQ_CONSIDX, 1071 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1072 ((cmpconsidx << 16) & 0xFFFF0000)); 1073 1074 return; 1075 } 1076 1077 static void sf_txthresh_adjust(sc) 1078 struct sf_softc *sc; 1079 { 1080 u_int32_t txfctl; 1081 u_int8_t txthresh; 1082 1083 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1084 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1085 if (txthresh < 0xFF) { 1086 txthresh++; 1087 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1088 txfctl |= txthresh; 1089 #ifdef DIAGNOSTIC 1090 printf("sf%d: tx underrun, increasing " 1091 "tx threshold to %d bytes\n", 1092 sc->sf_unit, txthresh * 4); 1093 #endif 1094 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1095 } 1096 1097 return; 1098 } 1099 1100 static void sf_intr(arg) 1101 void *arg; 1102 { 1103 struct sf_softc *sc; 1104 struct ifnet *ifp; 1105 u_int32_t status; 1106 1107 sc = arg; 1108 ifp = &sc->arpcom.ac_if; 1109 1110 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) 1111 return; 1112 1113 /* Disable interrupts. */ 1114 csr_write_4(sc, SF_IMR, 0x00000000); 1115 1116 for (;;) { 1117 status = csr_read_4(sc, SF_ISR); 1118 if (status) 1119 csr_write_4(sc, SF_ISR, status); 1120 1121 if (!(status & SF_INTRS)) 1122 break; 1123 1124 if (status & SF_ISR_RXDQ1_DMADONE) 1125 sf_rxeof(sc); 1126 1127 if (status & SF_ISR_TX_TXDONE || 1128 status & SF_ISR_TX_DMADONE || 1129 status & SF_ISR_TX_QUEUEDONE) 1130 sf_txeof(sc); 1131 1132 if (status & SF_ISR_TX_LOFIFO) 1133 sf_txthresh_adjust(sc); 1134 1135 if (status & SF_ISR_ABNORMALINTR) { 1136 if (status & SF_ISR_STATSOFLOW) { 1137 untimeout(sf_stats_update, sc, 1138 sc->sf_stat_ch); 1139 sf_stats_update(sc); 1140 } else 1141 sf_init(sc); 1142 } 1143 } 1144 1145 /* Re-enable interrupts. */ 1146 csr_write_4(sc, SF_IMR, SF_INTRS); 1147 1148 if (ifp->if_snd.ifq_head != NULL) 1149 sf_start(ifp); 1150 1151 return; 1152 } 1153 1154 static void sf_init(xsc) 1155 void *xsc; 1156 { 1157 struct sf_softc *sc; 1158 struct ifnet *ifp; 1159 struct mii_data *mii; 1160 int i, s; 1161 1162 s = splimp(); 1163 1164 sc = xsc; 1165 ifp = &sc->arpcom.ac_if; 1166 mii = device_get_softc(sc->sf_miibus); 1167 1168 sf_stop(sc); 1169 sf_reset(sc); 1170 1171 /* Init all the receive filter registers */ 1172 for (i = SF_RXFILT_PERFECT_BASE; 1173 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1174 csr_write_4(sc, i, 0); 1175 1176 /* Empty stats counter registers. */ 1177 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1178 csr_write_4(sc, SF_STATS_BASE + 1179 (i + sizeof(u_int32_t)), 0); 1180 1181 /* Init our MAC address */ 1182 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1183 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1184 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1185 1186 if (sf_init_rx_ring(sc) == ENOBUFS) { 1187 printf("sf%d: initialization failed: no " 1188 "memory for rx buffers\n", sc->sf_unit); 1189 (void)splx(s); 1190 return; 1191 } 1192 1193 sf_init_tx_ring(sc); 1194 1195 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1196 1197 /* If we want promiscuous mode, set the allframes bit. */ 1198 if (ifp->if_flags & IFF_PROMISC) { 1199 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1200 } else { 1201 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1202 } 1203 1204 if (ifp->if_flags & IFF_BROADCAST) { 1205 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1206 } else { 1207 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1208 } 1209 1210 /* 1211 * Load the multicast filter. 1212 */ 1213 sf_setmulti(sc); 1214 1215 /* Init the completion queue indexes */ 1216 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1217 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1218 1219 /* Init the RX completion queue */ 1220 csr_write_4(sc, SF_RXCQ_CTL_1, 1221 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1222 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1223 1224 /* Init RX DMA control. */ 1225 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1226 1227 /* Init the RX buffer descriptor queue. */ 1228 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1229 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1230 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1231 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1232 1233 /* Init the TX completion queue */ 1234 csr_write_4(sc, SF_TXCQ_CTL, 1235 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1236 1237 /* Init the TX buffer descriptor queue. */ 1238 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1239 vtophys(sc->sf_ldata->sf_tx_dlist)); 1240 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1241 csr_write_4(sc, SF_TXDQ_CTL, 1242 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1243 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1244 1245 /* Enable autopadding of short TX frames. */ 1246 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1247 1248 /* Enable interrupts. */ 1249 csr_write_4(sc, SF_IMR, SF_INTRS); 1250 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1251 1252 /* Enable the RX and TX engines. */ 1253 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1254 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1255 1256 /*mii_mediachg(mii);*/ 1257 sf_ifmedia_upd(ifp); 1258 1259 ifp->if_flags |= IFF_RUNNING; 1260 ifp->if_flags &= ~IFF_OACTIVE; 1261 1262 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1263 1264 splx(s); 1265 1266 return; 1267 } 1268 1269 static int sf_encap(sc, c, m_head) 1270 struct sf_softc *sc; 1271 struct sf_tx_bufdesc_type0 *c; 1272 struct mbuf *m_head; 1273 { 1274 int frag = 0; 1275 struct sf_frag *f = NULL; 1276 struct mbuf *m; 1277 1278 m = m_head; 1279 1280 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1281 if (m->m_len != 0) { 1282 if (frag == SF_MAXFRAGS) 1283 break; 1284 f = &c->sf_frags[frag]; 1285 if (frag == 0) 1286 f->sf_pktlen = m_head->m_pkthdr.len; 1287 f->sf_fraglen = m->m_len; 1288 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1289 frag++; 1290 } 1291 } 1292 1293 if (m != NULL) { 1294 struct mbuf *m_new = NULL; 1295 1296 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1297 if (m_new == NULL) { 1298 printf("sf%d: no memory for tx list", sc->sf_unit); 1299 return(1); 1300 } 1301 1302 if (m_head->m_pkthdr.len > MHLEN) { 1303 MCLGET(m_new, M_DONTWAIT); 1304 if (!(m_new->m_flags & M_EXT)) { 1305 m_freem(m_new); 1306 printf("sf%d: no memory for tx list", 1307 sc->sf_unit); 1308 return(1); 1309 } 1310 } 1311 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1312 mtod(m_new, caddr_t)); 1313 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1314 m_freem(m_head); 1315 m_head = m_new; 1316 f = &c->sf_frags[0]; 1317 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1318 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1319 frag = 1; 1320 } 1321 1322 c->sf_mbuf = m_head; 1323 c->sf_id = SF_TX_BUFDESC_ID; 1324 c->sf_fragcnt = frag; 1325 c->sf_intr = 1; 1326 c->sf_caltcp = 0; 1327 c->sf_crcen = 1; 1328 1329 return(0); 1330 } 1331 1332 static void sf_start(ifp) 1333 struct ifnet *ifp; 1334 { 1335 struct sf_softc *sc; 1336 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1337 struct mbuf *m_head = NULL; 1338 int i, txprod; 1339 1340 sc = ifp->if_softc; 1341 1342 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) 1343 return; 1344 1345 if (ifp->if_flags & IFF_OACTIVE) 1346 return; 1347 1348 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1349 i = SF_IDX_HI(txprod) >> 4; 1350 1351 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1352 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1353 sf_init(sc); 1354 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1355 i = SF_IDX_HI(txprod) >> 4; 1356 } 1357 1358 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1359 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1360 ifp->if_flags |= IFF_OACTIVE; 1361 cur_tx = NULL; 1362 break; 1363 } 1364 IF_DEQUEUE(&ifp->if_snd, m_head); 1365 if (m_head == NULL) 1366 break; 1367 1368 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1369 if (sf_encap(sc, cur_tx, m_head)) { 1370 IF_PREPEND(&ifp->if_snd, m_head); 1371 ifp->if_flags |= IFF_OACTIVE; 1372 cur_tx = NULL; 1373 break; 1374 } 1375 1376 1377 /* 1378 * If there's a BPF listener, bounce a copy of this frame 1379 * to him. 1380 */ 1381 if (ifp->if_bpf) 1382 bpf_mtap(ifp, m_head); 1383 1384 SF_INC(i, SF_TX_DLIST_CNT); 1385 sc->sf_tx_cnt++; 1386 /* 1387 * Don't get the TX DMA queue get too full. 1388 */ 1389 if (sc->sf_tx_cnt > 64) 1390 break; 1391 } 1392 1393 if (cur_tx == NULL) 1394 return; 1395 1396 /* Transmit */ 1397 csr_write_4(sc, SF_TXDQ_PRODIDX, 1398 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1399 ((i << 20) & 0xFFFF0000)); 1400 1401 ifp->if_timer = 5; 1402 1403 return; 1404 } 1405 1406 static void sf_stop(sc) 1407 struct sf_softc *sc; 1408 { 1409 int i; 1410 struct ifnet *ifp; 1411 1412 ifp = &sc->arpcom.ac_if; 1413 1414 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1415 1416 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1417 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1418 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1419 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1420 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1421 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1422 csr_write_4(sc, SF_TXCQ_CTL, 0); 1423 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1424 csr_write_4(sc, SF_TXDQ_CTL, 0); 1425 sf_reset(sc); 1426 1427 sc->sf_link = 0; 1428 1429 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1430 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1431 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1432 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1433 } 1434 } 1435 1436 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1437 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1438 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1439 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1440 } 1441 } 1442 1443 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1444 1445 return; 1446 } 1447 1448 /* 1449 * Note: it is important that this function not be interrupted. We 1450 * use a two-stage register access scheme: if we are interrupted in 1451 * between setting the indirect address register and reading from the 1452 * indirect data register, the contents of the address register could 1453 * be changed out from under us. 1454 */ 1455 static void sf_stats_update(xsc) 1456 void *xsc; 1457 { 1458 struct sf_softc *sc; 1459 struct ifnet *ifp; 1460 struct mii_data *mii; 1461 struct sf_stats stats; 1462 u_int32_t *ptr; 1463 int i, s; 1464 1465 s = splimp(); 1466 1467 sc = xsc; 1468 ifp = &sc->arpcom.ac_if; 1469 mii = device_get_softc(sc->sf_miibus); 1470 1471 ptr = (u_int32_t *)&stats; 1472 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1473 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1474 (i + sizeof(u_int32_t))); 1475 1476 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1477 csr_write_4(sc, SF_STATS_BASE + 1478 (i + sizeof(u_int32_t)), 0); 1479 1480 ifp->if_collisions += stats.sf_tx_single_colls + 1481 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1482 1483 mii_tick(mii); 1484 if (!sc->sf_link) { 1485 mii_pollstat(mii); 1486 if (mii->mii_media_status & IFM_ACTIVE && 1487 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1488 sc->sf_link++; 1489 if (ifp->if_snd.ifq_head != NULL) 1490 sf_start(ifp); 1491 } 1492 1493 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1494 1495 splx(s); 1496 1497 return; 1498 } 1499 1500 static void sf_watchdog(ifp) 1501 struct ifnet *ifp; 1502 { 1503 struct sf_softc *sc; 1504 1505 sc = ifp->if_softc; 1506 1507 ifp->if_oerrors++; 1508 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1509 1510 sf_stop(sc); 1511 sf_reset(sc); 1512 sf_init(sc); 1513 1514 if (ifp->if_snd.ifq_head != NULL) 1515 sf_start(ifp); 1516 1517 return; 1518 } 1519 1520 static void sf_shutdown(dev) 1521 device_t dev; 1522 { 1523 struct sf_softc *sc; 1524 1525 sc = device_get_softc(dev); 1526 1527 sf_stop(sc); 1528 1529 return; 1530 } 1531