1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $ 33 */ 34 35 /* 36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 37 * Programming manual is available from: 38 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Department of Electical Engineering 42 * Columbia University, New York City 43 */ 44 45 /* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82 #include <sys/param.h> 83 #include <sys/systm.h> 84 #include <sys/sockio.h> 85 #include <sys/mbuf.h> 86 #include <sys/malloc.h> 87 #include <sys/kernel.h> 88 #include <sys/interrupt.h> 89 #include <sys/socket.h> 90 #include <sys/serialize.h> 91 #include <sys/bus.h> 92 #include <sys/rman.h> 93 94 #include <net/if.h> 95 #include <net/ifq_var.h> 96 #include <net/if_arp.h> 97 #include <net/ethernet.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 101 #include <net/bpf.h> 102 103 #include <vm/vm.h> /* for vtophys */ 104 #include <vm/pmap.h> /* for vtophys */ 105 106 #include <machine/clock.h> /* for DELAY */ 107 108 #include "../mii_layer/mii.h" 109 #include "../mii_layer/miivar.h" 110 111 /* "controller miibus0" required. See GENERIC if you get errors here. */ 112 #include "miibus_if.h" 113 114 #include "pcidevs.h" 115 #include <bus/pci/pcireg.h> 116 #include <bus/pci/pcivar.h> 117 118 #define SF_USEIOSPACE 119 120 #include "if_sfreg.h" 121 122 static struct sf_type sf_devs[] = { 123 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC6915, 124 "Adaptec AIC-6915 10/100BaseTX" }, 125 { 0, 0, NULL } 126 }; 127 128 static int sf_probe (device_t); 129 static int sf_attach (device_t); 130 static int sf_detach (device_t); 131 static void sf_intr (void *); 132 static void sf_stats_update (void *); 133 static void sf_rxeof (struct sf_softc *); 134 static void sf_txeof (struct sf_softc *); 135 static int sf_encap (struct sf_softc *, 136 struct sf_tx_bufdesc_type0 *, 137 struct mbuf *); 138 static void sf_start (struct ifnet *, struct ifaltq_subque *); 139 static int sf_ioctl (struct ifnet *, u_long, caddr_t, 140 struct ucred *); 141 static void sf_init (void *); 142 static void sf_stop (struct sf_softc *); 143 static void sf_watchdog (struct ifnet *); 144 static void sf_shutdown (device_t); 145 static int sf_ifmedia_upd (struct ifnet *); 146 static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 147 static void sf_reset (struct sf_softc *); 148 static int sf_init_rx_ring (struct sf_softc *); 149 static void sf_init_tx_ring (struct sf_softc *); 150 static int sf_newbuf (struct sf_softc *, 151 struct sf_rx_bufdesc_type0 *, 152 struct mbuf *); 153 static void sf_setmulti (struct sf_softc *); 154 static int sf_setperf (struct sf_softc *, int, caddr_t); 155 static int sf_sethash (struct sf_softc *, caddr_t, int); 156 #ifdef notdef 157 static int sf_setvlan (struct sf_softc *, int, u_int32_t); 158 #endif 159 160 static u_int8_t sf_read_eeprom (struct sf_softc *, int); 161 static u_int32_t sf_calchash (caddr_t); 162 163 static int sf_miibus_readreg (device_t, int, int); 164 static int sf_miibus_writereg (device_t, int, int, int); 165 static void sf_miibus_statchg (device_t); 166 167 static u_int32_t csr_read_4 (struct sf_softc *, int); 168 static void csr_write_4 (struct sf_softc *, int, u_int32_t); 169 static void sf_txthresh_adjust (struct sf_softc *); 170 171 #ifdef SF_USEIOSPACE 172 #define SF_RES SYS_RES_IOPORT 173 #define SF_RID SF_PCI_LOIO 174 #else 175 #define SF_RES SYS_RES_MEMORY 176 #define SF_RID SF_PCI_LOMEM 177 #endif 178 179 static device_method_t sf_methods[] = { 180 /* Device interface */ 181 DEVMETHOD(device_probe, sf_probe), 182 DEVMETHOD(device_attach, sf_attach), 183 DEVMETHOD(device_detach, sf_detach), 184 DEVMETHOD(device_shutdown, sf_shutdown), 185 186 /* bus interface */ 187 DEVMETHOD(bus_print_child, bus_generic_print_child), 188 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 189 190 /* MII interface */ 191 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 192 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 193 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 194 195 DEVMETHOD_END 196 }; 197 198 static driver_t sf_driver = { 199 "sf", 200 sf_methods, 201 sizeof(struct sf_softc), 202 }; 203 204 static devclass_t sf_devclass; 205 206 DECLARE_DUMMY_MODULE(if_sf); 207 DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, NULL, NULL); 208 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, NULL, NULL); 209 210 #define SF_SETBIT(sc, reg, x) \ 211 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 212 213 #define SF_CLRBIT(sc, reg, x) \ 214 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 215 216 static u_int32_t 217 csr_read_4(struct sf_softc *sc, int reg) 218 { 219 u_int32_t val; 220 221 #ifdef SF_USEIOSPACE 222 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 223 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 224 #else 225 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 226 #endif 227 228 return(val); 229 } 230 231 static u_int8_t 232 sf_read_eeprom(struct sf_softc *sc, int reg) 233 { 234 u_int8_t val; 235 236 val = (csr_read_4(sc, SF_EEADDR_BASE + 237 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 238 239 return(val); 240 } 241 242 static void 243 csr_write_4(struct sf_softc *sc, int reg, u_int32_t val) 244 { 245 #ifdef SF_USEIOSPACE 246 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 247 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 248 #else 249 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 250 #endif 251 return; 252 } 253 254 static u_int32_t 255 sf_calchash(caddr_t addr) 256 { 257 u_int32_t crc, carry; 258 int i, j; 259 u_int8_t c; 260 261 /* Compute CRC for the address value. */ 262 crc = 0xFFFFFFFF; /* initial value */ 263 264 for (i = 0; i < 6; i++) { 265 c = *(addr + i); 266 for (j = 0; j < 8; j++) { 267 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 268 crc <<= 1; 269 c >>= 1; 270 if (carry) 271 crc = (crc ^ 0x04c11db6) | carry; 272 } 273 } 274 275 /* return the filter bit position */ 276 return(crc >> 23 & 0x1FF); 277 } 278 279 /* 280 * Copy the address 'mac' into the perfect RX filter entry at 281 * offset 'idx.' The perfect filter only has 16 entries so do 282 * some sanity tests. 283 */ 284 static int 285 sf_setperf(struct sf_softc *sc, int idx, caddr_t mac) 286 { 287 u_int16_t *p; 288 289 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 290 return(EINVAL); 291 292 if (mac == NULL) 293 return(EINVAL); 294 295 p = (u_int16_t *)mac; 296 297 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 298 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 299 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 300 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 301 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 302 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 303 304 return(0); 305 } 306 307 /* 308 * Set the bit in the 512-bit hash table that corresponds to the 309 * specified mac address 'mac.' If 'prio' is nonzero, update the 310 * priority hash table instead of the filter hash table. 311 */ 312 static int 313 sf_sethash(struct sf_softc *sc, caddr_t mac, int prio) 314 { 315 u_int32_t h = 0; 316 317 if (mac == NULL) 318 return(EINVAL); 319 320 h = sf_calchash(mac); 321 322 if (prio) { 323 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 324 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 325 } else { 326 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 327 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 328 } 329 330 return(0); 331 } 332 333 #ifdef notdef 334 /* 335 * Set a VLAN tag in the receive filter. 336 */ 337 static int 338 sf_setvlan(struct sf_softc *sc, int idx, u_int32_t vlan) 339 { 340 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 341 return(EINVAL); 342 343 csr_write_4(sc, SF_RXFILT_HASH_BASE + 344 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 345 346 return(0); 347 } 348 #endif 349 350 static int 351 sf_miibus_readreg(device_t dev, int phy, int reg) 352 { 353 struct sf_softc *sc; 354 int i; 355 u_int32_t val = 0; 356 357 sc = device_get_softc(dev); 358 359 for (i = 0; i < SF_TIMEOUT; i++) { 360 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 361 if (val & SF_MII_DATAVALID) 362 break; 363 } 364 365 if (i == SF_TIMEOUT) 366 return(0); 367 368 if ((val & 0x0000FFFF) == 0xFFFF) 369 return(0); 370 371 return(val & 0x0000FFFF); 372 } 373 374 static int 375 sf_miibus_writereg(device_t dev, int phy, int reg, int val) 376 { 377 struct sf_softc *sc; 378 int i; 379 int busy; 380 381 sc = device_get_softc(dev); 382 383 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 384 385 for (i = 0; i < SF_TIMEOUT; i++) { 386 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 387 if (!(busy & SF_MII_BUSY)) 388 break; 389 } 390 391 return(0); 392 } 393 394 static void 395 sf_miibus_statchg(device_t dev) 396 { 397 struct sf_softc *sc; 398 struct mii_data *mii; 399 400 sc = device_get_softc(dev); 401 mii = device_get_softc(sc->sf_miibus); 402 403 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 404 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 405 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 406 } else { 407 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 408 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 409 } 410 411 return; 412 } 413 414 static void 415 sf_setmulti(struct sf_softc *sc) 416 { 417 struct ifnet *ifp; 418 int i; 419 struct ifmultiaddr *ifma; 420 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 421 422 ifp = &sc->arpcom.ac_if; 423 424 /* First zot all the existing filters. */ 425 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 426 sf_setperf(sc, i, (char *)&dummy); 427 for (i = SF_RXFILT_HASH_BASE; 428 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 429 csr_write_4(sc, i, 0); 430 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 431 432 /* Now program new ones. */ 433 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 434 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 435 } else { 436 i = 1; 437 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 438 if (ifma->ifma_addr->sa_family != AF_LINK) 439 continue; 440 /* 441 * Program the first 15 multicast groups 442 * into the perfect filter. For all others, 443 * use the hash table. 444 */ 445 if (i < SF_RXFILT_PERFECT_CNT) { 446 sf_setperf(sc, i, 447 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 448 i++; 449 continue; 450 } 451 452 sf_sethash(sc, 453 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 454 } 455 } 456 457 return; 458 } 459 460 /* 461 * Set media options. 462 */ 463 static int 464 sf_ifmedia_upd(struct ifnet *ifp) 465 { 466 struct sf_softc *sc; 467 struct mii_data *mii; 468 469 sc = ifp->if_softc; 470 mii = device_get_softc(sc->sf_miibus); 471 sc->sf_link = 0; 472 if (mii->mii_instance) { 473 struct mii_softc *miisc; 474 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 475 miisc = LIST_NEXT(miisc, mii_list)) 476 mii_phy_reset(miisc); 477 } 478 mii_mediachg(mii); 479 480 return(0); 481 } 482 483 /* 484 * Report current media status. 485 */ 486 static void 487 sf_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 488 { 489 struct sf_softc *sc; 490 struct mii_data *mii; 491 492 sc = ifp->if_softc; 493 mii = device_get_softc(sc->sf_miibus); 494 495 mii_pollstat(mii); 496 ifmr->ifm_active = mii->mii_media_active; 497 ifmr->ifm_status = mii->mii_media_status; 498 499 return; 500 } 501 502 static int 503 sf_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 504 { 505 struct sf_softc *sc = ifp->if_softc; 506 struct ifreq *ifr = (struct ifreq *) data; 507 struct mii_data *mii; 508 int error = 0; 509 510 switch(command) { 511 case SIOCSIFFLAGS: 512 if (ifp->if_flags & IFF_UP) { 513 if (ifp->if_flags & IFF_RUNNING && 514 ifp->if_flags & IFF_PROMISC && 515 !(sc->sf_if_flags & IFF_PROMISC)) { 516 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 517 } else if (ifp->if_flags & IFF_RUNNING && 518 !(ifp->if_flags & IFF_PROMISC) && 519 sc->sf_if_flags & IFF_PROMISC) { 520 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 521 } else if (!(ifp->if_flags & IFF_RUNNING)) 522 sf_init(sc); 523 } else { 524 if (ifp->if_flags & IFF_RUNNING) 525 sf_stop(sc); 526 } 527 sc->sf_if_flags = ifp->if_flags; 528 error = 0; 529 break; 530 case SIOCADDMULTI: 531 case SIOCDELMULTI: 532 sf_setmulti(sc); 533 error = 0; 534 break; 535 case SIOCGIFMEDIA: 536 case SIOCSIFMEDIA: 537 mii = device_get_softc(sc->sf_miibus); 538 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 539 break; 540 default: 541 error = ether_ioctl(ifp, command, data); 542 break; 543 } 544 545 return(error); 546 } 547 548 static void 549 sf_reset(struct sf_softc *sc) 550 { 551 int i; 552 553 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 554 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 555 DELAY(1000); 556 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 557 558 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 559 560 for (i = 0; i < SF_TIMEOUT; i++) { 561 DELAY(10); 562 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 563 break; 564 } 565 566 if (i == SF_TIMEOUT) 567 kprintf("sf%d: reset never completed!\n", sc->sf_unit); 568 569 /* Wait a little while for the chip to get its brains in order. */ 570 DELAY(1000); 571 return; 572 } 573 574 /* 575 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 576 * IDs against our list and return a device name if we find a match. 577 * We also check the subsystem ID so that we can identify exactly which 578 * NIC has been found, if possible. 579 */ 580 static int 581 sf_probe(device_t dev) 582 { 583 struct sf_type *t; 584 585 t = sf_devs; 586 587 while(t->sf_name != NULL) { 588 if ((pci_get_vendor(dev) == t->sf_vid) && 589 (pci_get_device(dev) == t->sf_did)) { 590 switch((pci_read_config(dev, 591 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 592 case AD_SUBSYSID_62011_REV0: 593 case AD_SUBSYSID_62011_REV1: 594 device_set_desc(dev, 595 "Adaptec ANA-62011 10/100BaseTX"); 596 return(0); 597 break; 598 case AD_SUBSYSID_62022: 599 device_set_desc(dev, 600 "Adaptec ANA-62022 10/100BaseTX"); 601 return(0); 602 break; 603 case AD_SUBSYSID_62044_REV0: 604 case AD_SUBSYSID_62044_REV1: 605 device_set_desc(dev, 606 "Adaptec ANA-62044 10/100BaseTX"); 607 return(0); 608 break; 609 case AD_SUBSYSID_62020: 610 device_set_desc(dev, 611 "Adaptec ANA-62020 10/100BaseFX"); 612 return(0); 613 break; 614 case AD_SUBSYSID_69011: 615 device_set_desc(dev, 616 "Adaptec ANA-69011 10/100BaseTX"); 617 return(0); 618 break; 619 default: 620 device_set_desc(dev, t->sf_name); 621 return(0); 622 break; 623 } 624 } 625 t++; 626 } 627 628 return(ENXIO); 629 } 630 631 /* 632 * Attach the interface. Allocate softc structures, do ifmedia 633 * setup and ethernet/BPF attach. 634 */ 635 static int 636 sf_attach(device_t dev) 637 { 638 int i; 639 u_int32_t command; 640 struct sf_softc *sc; 641 struct ifnet *ifp; 642 int unit, rid, error = 0; 643 644 sc = device_get_softc(dev); 645 unit = device_get_unit(dev); 646 647 /* 648 * Handle power management nonsense. 649 */ 650 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 651 if (command == 0x01) { 652 653 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 654 if (command & SF_PSTATE_MASK) { 655 u_int32_t iobase, membase, irq; 656 657 /* Save important PCI config data. */ 658 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 659 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 660 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 661 662 /* Reset the power state. */ 663 kprintf("sf%d: chip is in D%d power mode " 664 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 665 command &= 0xFFFFFFFC; 666 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 667 668 /* Restore PCI config data. */ 669 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 670 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 671 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 672 } 673 } 674 675 /* 676 * Map control/status registers. 677 */ 678 command = pci_read_config(dev, PCIR_COMMAND, 4); 679 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 680 pci_write_config(dev, PCIR_COMMAND, command, 4); 681 command = pci_read_config(dev, PCIR_COMMAND, 4); 682 683 #ifdef SF_USEIOSPACE 684 if (!(command & PCIM_CMD_PORTEN)) { 685 kprintf("sf%d: failed to enable I/O ports!\n", unit); 686 error = ENXIO; 687 return(error); 688 } 689 #else 690 if (!(command & PCIM_CMD_MEMEN)) { 691 kprintf("sf%d: failed to enable memory mapping!\n", unit); 692 error = ENXIO; 693 return(error); 694 } 695 #endif 696 697 rid = SF_RID; 698 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE); 699 700 if (sc->sf_res == NULL) { 701 kprintf ("sf%d: couldn't map ports\n", unit); 702 error = ENXIO; 703 return(error); 704 } 705 706 sc->sf_btag = rman_get_bustag(sc->sf_res); 707 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 708 709 /* Allocate interrupt */ 710 rid = 0; 711 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 712 RF_SHAREABLE | RF_ACTIVE); 713 714 if (sc->sf_irq == NULL) { 715 kprintf("sf%d: couldn't map interrupt\n", unit); 716 error = ENXIO; 717 goto fail; 718 } 719 720 callout_init(&sc->sf_stat_timer); 721 722 /* Reset the adapter. */ 723 sf_reset(sc); 724 725 /* 726 * Get station address from the EEPROM. 727 */ 728 for (i = 0; i < ETHER_ADDR_LEN; i++) 729 sc->arpcom.ac_enaddr[i] = 730 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 731 732 sc->sf_unit = unit; 733 734 /* Allocate the descriptor queues. */ 735 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 736 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 737 738 if (sc->sf_ldata == NULL) { 739 kprintf("sf%d: no memory for list buffers!\n", unit); 740 error = ENXIO; 741 goto fail; 742 } 743 744 /* Do MII setup. */ 745 if (mii_phy_probe(dev, &sc->sf_miibus, 746 sf_ifmedia_upd, sf_ifmedia_sts)) { 747 kprintf("sf%d: MII without any phy!\n", sc->sf_unit); 748 error = ENXIO; 749 goto fail; 750 } 751 752 ifp = &sc->arpcom.ac_if; 753 ifp->if_softc = sc; 754 if_initname(ifp, "sf", unit); 755 ifp->if_mtu = ETHERMTU; 756 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 757 ifp->if_ioctl = sf_ioctl; 758 ifp->if_start = sf_start; 759 ifp->if_watchdog = sf_watchdog; 760 ifp->if_init = sf_init; 761 ifp->if_baudrate = 10000000; 762 ifq_set_maxlen(&ifp->if_snd, SF_TX_DLIST_CNT - 1); 763 ifq_set_ready(&ifp->if_snd); 764 765 /* 766 * Call MI attach routine. 767 */ 768 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 769 770 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sf_irq)); 771 772 error = bus_setup_intr(dev, sc->sf_irq, INTR_MPSAFE, 773 sf_intr, sc, &sc->sf_intrhand, 774 ifp->if_serializer); 775 776 if (error) { 777 ether_ifdetach(ifp); 778 device_printf(dev, "couldn't set up irq\n"); 779 goto fail; 780 } 781 782 return(0); 783 784 fail: 785 sf_detach(dev); 786 return(error); 787 } 788 789 static int 790 sf_detach(device_t dev) 791 { 792 struct sf_softc *sc = device_get_softc(dev); 793 struct ifnet *ifp = &sc->arpcom.ac_if; 794 795 if (device_is_attached(dev)) { 796 lwkt_serialize_enter(ifp->if_serializer); 797 sf_stop(sc); 798 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 799 lwkt_serialize_exit(ifp->if_serializer); 800 801 ether_ifdetach(ifp); 802 } 803 804 if (sc->sf_miibus) 805 device_delete_child(dev, sc->sf_miibus); 806 bus_generic_detach(dev); 807 808 if (sc->sf_irq) 809 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 810 if(sc->sf_res) 811 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 812 813 if (sc->sf_ldata) { 814 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), 815 M_DEVBUF); 816 } 817 818 return(0); 819 } 820 821 static int 822 sf_init_rx_ring(struct sf_softc *sc) 823 { 824 struct sf_list_data *ld; 825 int i; 826 827 ld = sc->sf_ldata; 828 829 bzero((char *)ld->sf_rx_dlist_big, 830 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 831 bzero((char *)ld->sf_rx_clist, 832 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 833 834 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 835 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 836 return(ENOBUFS); 837 } 838 839 return(0); 840 } 841 842 static void 843 sf_init_tx_ring(struct sf_softc *sc) 844 { 845 struct sf_list_data *ld; 846 int i; 847 848 ld = sc->sf_ldata; 849 850 bzero((char *)ld->sf_tx_dlist, 851 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 852 bzero((char *)ld->sf_tx_clist, 853 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 854 855 for (i = 0; i < SF_TX_DLIST_CNT; i++) 856 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 857 for (i = 0; i < SF_TX_CLIST_CNT; i++) 858 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 859 860 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 861 sc->sf_tx_cnt = 0; 862 863 return; 864 } 865 866 static int 867 sf_newbuf(struct sf_softc *sc, struct sf_rx_bufdesc_type0 *c, 868 struct mbuf *m) 869 { 870 struct mbuf *m_new = NULL; 871 872 if (m == NULL) { 873 MGETHDR(m_new, M_NOWAIT, MT_DATA); 874 if (m_new == NULL) 875 return(ENOBUFS); 876 877 MCLGET(m_new, M_NOWAIT); 878 if (!(m_new->m_flags & M_EXT)) { 879 m_freem(m_new); 880 return(ENOBUFS); 881 } 882 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 883 } else { 884 m_new = m; 885 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 886 m_new->m_data = m_new->m_ext.ext_buf; 887 } 888 889 m_adj(m_new, sizeof(u_int64_t)); 890 891 c->sf_mbuf = m_new; 892 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 893 c->sf_valid = 1; 894 895 return(0); 896 } 897 898 /* 899 * The starfire is programmed to use 'normal' mode for packet reception, 900 * which means we use the consumer/producer model for both the buffer 901 * descriptor queue and the completion descriptor queue. The only problem 902 * with this is that it involves a lot of register accesses: we have to 903 * read the RX completion consumer and producer indexes and the RX buffer 904 * producer index, plus the RX completion consumer and RX buffer producer 905 * indexes have to be updated. It would have been easier if Adaptec had 906 * put each index in a separate register, especially given that the damn 907 * NIC has a 512K register space. 908 * 909 * In spite of all the lovely features that Adaptec crammed into the 6915, 910 * it is marred by one truly stupid design flaw, which is that receive 911 * buffer addresses must be aligned on a longword boundary. This forces 912 * the packet payload to be unaligned, which is suboptimal on the x86 and 913 * completely unuseable on the Alpha. Our only recourse is to copy received 914 * packets into properly aligned buffers before handing them off. 915 */ 916 917 static void 918 sf_rxeof(struct sf_softc *sc) 919 { 920 struct mbuf *m; 921 struct ifnet *ifp; 922 struct sf_rx_bufdesc_type0 *desc; 923 struct sf_rx_cmpdesc_type3 *cur_rx; 924 u_int32_t rxcons, rxprod; 925 int cmpprodidx, cmpconsidx, bufprodidx; 926 927 ifp = &sc->arpcom.ac_if; 928 929 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 930 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 931 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 932 cmpconsidx = SF_IDX_LO(rxcons); 933 bufprodidx = SF_IDX_LO(rxprod); 934 935 while (cmpconsidx != cmpprodidx) { 936 struct mbuf *m0; 937 938 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 939 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 940 m = desc->sf_mbuf; 941 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 942 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 943 944 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 945 IFNET_STAT_INC(ifp, ierrors, 1); 946 sf_newbuf(sc, desc, m); 947 continue; 948 } 949 950 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 951 cur_rx->sf_len + ETHER_ALIGN, 0, ifp); 952 sf_newbuf(sc, desc, m); 953 if (m0 == NULL) { 954 IFNET_STAT_INC(ifp, ierrors, 1); 955 continue; 956 } 957 m_adj(m0, ETHER_ALIGN); 958 m = m0; 959 960 IFNET_STAT_INC(ifp, ipackets, 1); 961 962 ifp->if_input(ifp, m, NULL, -1); 963 } 964 965 csr_write_4(sc, SF_CQ_CONSIDX, 966 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 967 csr_write_4(sc, SF_RXDQ_PTR_Q1, 968 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 969 970 return; 971 } 972 973 /* 974 * Read the transmit status from the completion queue and release 975 * mbufs. Note that the buffer descriptor index in the completion 976 * descriptor is an offset from the start of the transmit buffer 977 * descriptor list in bytes. This is important because the manual 978 * gives the impression that it should match the producer/consumer 979 * index, which is the offset in 8 byte blocks. 980 */ 981 static void 982 sf_txeof(struct sf_softc *sc) 983 { 984 int txcons, cmpprodidx, cmpconsidx; 985 struct sf_tx_cmpdesc_type1 *cur_cmp; 986 struct sf_tx_bufdesc_type0 *cur_tx; 987 struct ifnet *ifp; 988 989 ifp = &sc->arpcom.ac_if; 990 991 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 992 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 993 cmpconsidx = SF_IDX_HI(txcons); 994 995 while (cmpconsidx != cmpprodidx) { 996 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 997 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 998 999 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1000 IFNET_STAT_INC(ifp, opackets, 1); 1001 else { 1002 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1003 sf_txthresh_adjust(sc); 1004 IFNET_STAT_INC(ifp, oerrors, 1); 1005 } 1006 1007 sc->sf_tx_cnt--; 1008 if (cur_tx->sf_mbuf != NULL) { 1009 m_freem(cur_tx->sf_mbuf); 1010 cur_tx->sf_mbuf = NULL; 1011 } else 1012 break; 1013 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1014 } 1015 1016 ifp->if_timer = 0; 1017 ifq_clr_oactive(&ifp->if_snd); 1018 1019 csr_write_4(sc, SF_CQ_CONSIDX, 1020 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1021 ((cmpconsidx << 16) & 0xFFFF0000)); 1022 1023 return; 1024 } 1025 1026 static void 1027 sf_txthresh_adjust(struct sf_softc *sc) 1028 { 1029 u_int32_t txfctl; 1030 u_int8_t txthresh; 1031 1032 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1033 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1034 if (txthresh < 0xFF) { 1035 txthresh++; 1036 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1037 txfctl |= txthresh; 1038 #ifdef DIAGNOSTIC 1039 kprintf("sf%d: tx underrun, increasing " 1040 "tx threshold to %d bytes\n", 1041 sc->sf_unit, txthresh * 4); 1042 #endif 1043 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1044 } 1045 1046 return; 1047 } 1048 1049 static void 1050 sf_intr(void *arg) 1051 { 1052 struct sf_softc *sc; 1053 struct ifnet *ifp; 1054 u_int32_t status; 1055 1056 sc = arg; 1057 ifp = &sc->arpcom.ac_if; 1058 1059 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) 1060 return; 1061 1062 /* Disable interrupts. */ 1063 csr_write_4(sc, SF_IMR, 0x00000000); 1064 1065 for (;;) { 1066 status = csr_read_4(sc, SF_ISR); 1067 if (status) 1068 csr_write_4(sc, SF_ISR, status); 1069 1070 if (!(status & SF_INTRS)) 1071 break; 1072 1073 if (status & SF_ISR_RXDQ1_DMADONE) 1074 sf_rxeof(sc); 1075 1076 if (status & SF_ISR_TX_TXDONE || 1077 status & SF_ISR_TX_DMADONE || 1078 status & SF_ISR_TX_QUEUEDONE) 1079 sf_txeof(sc); 1080 1081 if (status & SF_ISR_TX_LOFIFO) 1082 sf_txthresh_adjust(sc); 1083 1084 if (status & SF_ISR_ABNORMALINTR) { 1085 if (status & SF_ISR_STATSOFLOW) { 1086 callout_stop(&sc->sf_stat_timer); 1087 sf_stats_update(sc); 1088 } else 1089 sf_init(sc); 1090 } 1091 } 1092 1093 /* Re-enable interrupts. */ 1094 csr_write_4(sc, SF_IMR, SF_INTRS); 1095 1096 if (!ifq_is_empty(&ifp->if_snd)) 1097 if_devstart(ifp); 1098 } 1099 1100 static void 1101 sf_init(void *xsc) 1102 { 1103 struct sf_softc *sc = xsc; 1104 struct ifnet *ifp = &sc->arpcom.ac_if; 1105 int i; 1106 1107 sf_stop(sc); 1108 sf_reset(sc); 1109 1110 /* Init all the receive filter registers */ 1111 for (i = SF_RXFILT_PERFECT_BASE; 1112 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1113 csr_write_4(sc, i, 0); 1114 1115 /* Empty stats counter registers. */ 1116 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1117 csr_write_4(sc, SF_STATS_BASE + 1118 (i + sizeof(u_int32_t)), 0); 1119 1120 /* Init our MAC address */ 1121 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1122 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1123 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1124 1125 if (sf_init_rx_ring(sc) == ENOBUFS) { 1126 kprintf("sf%d: initialization failed: no " 1127 "memory for rx buffers\n", sc->sf_unit); 1128 return; 1129 } 1130 1131 sf_init_tx_ring(sc); 1132 1133 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1134 1135 /* If we want promiscuous mode, set the allframes bit. */ 1136 if (ifp->if_flags & IFF_PROMISC) { 1137 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1138 } else { 1139 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1140 } 1141 1142 if (ifp->if_flags & IFF_BROADCAST) { 1143 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1144 } else { 1145 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1146 } 1147 1148 /* 1149 * Load the multicast filter. 1150 */ 1151 sf_setmulti(sc); 1152 1153 /* Init the completion queue indexes */ 1154 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1155 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1156 1157 /* Init the RX completion queue */ 1158 csr_write_4(sc, SF_RXCQ_CTL_1, 1159 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1160 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1161 1162 /* Init RX DMA control. */ 1163 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1164 1165 /* Init the RX buffer descriptor queue. */ 1166 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1167 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1168 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1169 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1170 1171 /* Init the TX completion queue */ 1172 csr_write_4(sc, SF_TXCQ_CTL, 1173 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1174 1175 /* Init the TX buffer descriptor queue. */ 1176 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1177 vtophys(sc->sf_ldata->sf_tx_dlist)); 1178 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1179 csr_write_4(sc, SF_TXDQ_CTL, 1180 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1181 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1182 1183 /* Enable autopadding of short TX frames. */ 1184 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1185 1186 /* Enable interrupts. */ 1187 csr_write_4(sc, SF_IMR, SF_INTRS); 1188 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1189 1190 /* Enable the RX and TX engines. */ 1191 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1192 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1193 1194 /*mii_mediachg(mii);*/ 1195 sf_ifmedia_upd(ifp); 1196 1197 ifp->if_flags |= IFF_RUNNING; 1198 ifq_clr_oactive(&ifp->if_snd); 1199 1200 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc); 1201 } 1202 1203 static int 1204 sf_encap(struct sf_softc *sc, struct sf_tx_bufdesc_type0 *c, 1205 struct mbuf *m_head) 1206 { 1207 int frag = 0; 1208 struct sf_frag *f = NULL; 1209 struct mbuf *m; 1210 1211 for (m = m_head; m != NULL; m = m->m_next) { 1212 if (m->m_len != 0) { 1213 if (frag == SF_MAXFRAGS) 1214 break; 1215 f = &c->sf_frags[frag]; 1216 if (frag == 0) 1217 f->sf_pktlen = m_head->m_pkthdr.len; 1218 f->sf_fraglen = m->m_len; 1219 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1220 frag++; 1221 } 1222 } 1223 /* Caller should make sure that 'm_head' is not excessive fragmented */ 1224 KASSERT(m == NULL, ("too many fragments")); 1225 1226 c->sf_mbuf = m_head; 1227 c->sf_id = SF_TX_BUFDESC_ID; 1228 c->sf_fragcnt = frag; 1229 c->sf_intr = 1; 1230 c->sf_caltcp = 0; 1231 c->sf_crcen = 1; 1232 1233 return(0); 1234 } 1235 1236 static void 1237 sf_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1238 { 1239 struct sf_softc *sc; 1240 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1241 struct mbuf *m_head = NULL, *m_defragged; 1242 int i, txprod, need_trans = 0; 1243 1244 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1245 1246 sc = ifp->if_softc; 1247 1248 if (!sc->sf_link) { 1249 ifq_purge(&ifp->if_snd); 1250 return; 1251 } 1252 1253 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 1254 return; 1255 1256 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1257 i = SF_IDX_HI(txprod) >> 4; 1258 1259 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1260 kprintf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1261 sf_init(sc); 1262 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1263 i = SF_IDX_HI(txprod) >> 4; 1264 } 1265 1266 while (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1267 struct mbuf *m; 1268 int frag; 1269 1270 /* 1271 * Don't get the TX DMA queue get too full. 1272 */ 1273 if (sc->sf_tx_cnt > 64) { 1274 ifq_set_oactive(&ifp->if_snd); 1275 break; 1276 } 1277 #ifdef foo 1278 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1279 ifq_set_oactive(&ifp->if_snd); 1280 break; 1281 } 1282 #endif 1283 1284 m_defragged = NULL; 1285 m_head = ifq_dequeue(&ifp->if_snd); 1286 if (m_head == NULL) 1287 break; 1288 1289 again: 1290 frag = 0; 1291 for (m = m_head; m != NULL; m = m->m_next) 1292 ++frag; 1293 if (frag > SF_MAXFRAGS) { 1294 if (m_defragged != NULL) { 1295 /* 1296 * Even after defragmentation, there 1297 * are still too many fragments, so 1298 * drop this packet. 1299 */ 1300 m_freem(m_head); 1301 continue; 1302 } 1303 1304 m_defragged = m_defrag(m_head, M_NOWAIT); 1305 if (m_defragged == NULL) { 1306 m_freem(m_head); 1307 continue; 1308 } 1309 m_head = m_defragged; 1310 1311 /* Recount # of fragments */ 1312 goto again; 1313 } 1314 1315 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1316 sf_encap(sc, cur_tx, m_head); 1317 BPF_MTAP(ifp, cur_tx->sf_mbuf); 1318 1319 SF_INC(i, SF_TX_DLIST_CNT); 1320 sc->sf_tx_cnt++; 1321 need_trans = 1; 1322 } 1323 1324 if (!need_trans) 1325 return; 1326 1327 /* Transmit */ 1328 csr_write_4(sc, SF_TXDQ_PRODIDX, 1329 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1330 ((i << 20) & 0xFFFF0000)); 1331 1332 ifp->if_timer = 5; 1333 } 1334 1335 static void 1336 sf_stop(struct sf_softc *sc) 1337 { 1338 int i; 1339 struct ifnet *ifp; 1340 1341 ifp = &sc->arpcom.ac_if; 1342 1343 callout_stop(&sc->sf_stat_timer); 1344 1345 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1346 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1347 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1348 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1349 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1350 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1351 csr_write_4(sc, SF_TXCQ_CTL, 0); 1352 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1353 csr_write_4(sc, SF_TXDQ_CTL, 0); 1354 sf_reset(sc); 1355 1356 sc->sf_link = 0; 1357 1358 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1359 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1360 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1361 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1362 } 1363 } 1364 1365 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1366 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1367 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1368 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1369 } 1370 } 1371 1372 ifp->if_flags &= ~IFF_RUNNING; 1373 ifq_clr_oactive(&ifp->if_snd); 1374 1375 return; 1376 } 1377 1378 /* 1379 * Note: it is important that this function not be interrupted. We 1380 * use a two-stage register access scheme: if we are interrupted in 1381 * between setting the indirect address register and reading from the 1382 * indirect data register, the contents of the address register could 1383 * be changed out from under us. 1384 */ 1385 static void 1386 sf_stats_update(void *xsc) 1387 { 1388 struct sf_softc *sc = xsc; 1389 struct ifnet *ifp = &sc->arpcom.ac_if; 1390 struct mii_data *mii = device_get_softc(sc->sf_miibus); 1391 struct sf_stats stats; 1392 u_int32_t *ptr; 1393 int i; 1394 1395 lwkt_serialize_enter(ifp->if_serializer); 1396 1397 ptr = (u_int32_t *)&stats; 1398 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1399 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1400 (i + sizeof(u_int32_t))); 1401 1402 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1403 csr_write_4(sc, SF_STATS_BASE + 1404 (i + sizeof(u_int32_t)), 0); 1405 1406 IFNET_STAT_INC(ifp, collisions, stats.sf_tx_single_colls + 1407 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls); 1408 1409 mii_tick(mii); 1410 if (!sc->sf_link) { 1411 mii_pollstat(mii); 1412 if (mii->mii_media_status & IFM_ACTIVE && 1413 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1414 sc->sf_link++; 1415 if (!ifq_is_empty(&ifp->if_snd)) 1416 if_devstart(ifp); 1417 } 1418 } 1419 1420 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc); 1421 1422 lwkt_serialize_exit(ifp->if_serializer); 1423 } 1424 1425 static void 1426 sf_watchdog(struct ifnet *ifp) 1427 { 1428 struct sf_softc *sc; 1429 1430 sc = ifp->if_softc; 1431 1432 IFNET_STAT_INC(ifp, oerrors, 1); 1433 kprintf("sf%d: watchdog timeout\n", sc->sf_unit); 1434 1435 sf_stop(sc); 1436 sf_reset(sc); 1437 sf_init(sc); 1438 1439 if (!ifq_is_empty(&ifp->if_snd)) 1440 if_devstart(ifp); 1441 } 1442 1443 static void 1444 sf_shutdown(device_t dev) 1445 { 1446 struct sf_softc *sc; 1447 struct ifnet *ifp; 1448 1449 sc = device_get_softc(dev); 1450 ifp = &sc->arpcom.ac_if; 1451 lwkt_serialize_enter(ifp->if_serializer); 1452 sf_stop(sc); 1453 lwkt_serialize_exit(ifp->if_serializer); 1454 1455 return; 1456 } 1457