1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $ 33 * $DragonFly: src/sys/dev/netif/sf/if_sf.c,v 1.6 2004/01/06 01:40:49 dillon Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $ 36 */ 37 38 /* 39 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 40 * Programming manual is available from: 41 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Department of Electical Engineering 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 50 * controller designed with flexibility and reducing CPU load in mind. 51 * The Starfire offers high and low priority buffer queues, a 52 * producer/consumer index mechanism and several different buffer 53 * queue and completion queue descriptor types. Any one of a number 54 * of different driver designs can be used, depending on system and 55 * OS requirements. This driver makes use of type0 transmit frame 56 * descriptors (since BSD fragments packets across an mbuf chain) 57 * and two RX buffer queues prioritized on size (one queue for small 58 * frames that will fit into a single mbuf, another with full size 59 * mbuf clusters for everything else). The producer/consumer indexes 60 * and completion queues are also used. 61 * 62 * One downside to the Starfire has to do with alignment: buffer 63 * queues must be aligned on 256-byte boundaries, and receive buffers 64 * must be aligned on longword boundaries. The receive buffer alignment 65 * causes problems on the Alpha platform, where the packet payload 66 * should be longword aligned. There is no simple way around this. 67 * 68 * For receive filtering, the Starfire offers 16 perfect filter slots 69 * and a 512-bit hash table. 70 * 71 * The Starfire has no internal transceiver, relying instead on an 72 * external MII-based transceiver. Accessing registers on external 73 * PHYs is done through a special register map rather than with the 74 * usual bitbang MDIO method. 75 * 76 * Acesssing the registers on the Starfire is a little tricky. The 77 * Starfire has a 512K internal register space. When programmed for 78 * PCI memory mapped mode, the entire register space can be accessed 79 * directly. However in I/O space mode, only 256 bytes are directly 80 * mapped into PCI I/O space. The other registers can be accessed 81 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 82 * registers inside the 256-byte I/O window. 83 */ 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/socket.h> 92 93 #include <net/if.h> 94 #include <net/if_arp.h> 95 #include <net/ethernet.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 99 #include <net/bpf.h> 100 101 #include <vm/vm.h> /* for vtophys */ 102 #include <vm/pmap.h> /* for vtophys */ 103 #include <machine/clock.h> /* for DELAY */ 104 #include <machine/bus_pio.h> 105 #include <machine/bus_memio.h> 106 #include <machine/bus.h> 107 #include <machine/resource.h> 108 #include <sys/bus.h> 109 #include <sys/rman.h> 110 111 #include "../mii_layer/mii.h" 112 #include "../mii_layer/miivar.h" 113 114 /* "controller miibus0" required. See GENERIC if you get errors here. */ 115 #include "miibus_if.h" 116 117 #include <bus/pci/pcireg.h> 118 #include <bus/pci/pcivar.h> 119 120 #define SF_USEIOSPACE 121 122 #include "if_sfreg.h" 123 124 static struct sf_type sf_devs[] = { 125 { AD_VENDORID, AD_DEVICEID_STARFIRE, 126 "Adaptec AIC-6915 10/100BaseTX" }, 127 { 0, 0, NULL } 128 }; 129 130 static int sf_probe (device_t); 131 static int sf_attach (device_t); 132 static int sf_detach (device_t); 133 static void sf_intr (void *); 134 static void sf_stats_update (void *); 135 static void sf_rxeof (struct sf_softc *); 136 static void sf_txeof (struct sf_softc *); 137 static int sf_encap (struct sf_softc *, 138 struct sf_tx_bufdesc_type0 *, 139 struct mbuf *); 140 static void sf_start (struct ifnet *); 141 static int sf_ioctl (struct ifnet *, u_long, caddr_t); 142 static void sf_init (void *); 143 static void sf_stop (struct sf_softc *); 144 static void sf_watchdog (struct ifnet *); 145 static void sf_shutdown (device_t); 146 static int sf_ifmedia_upd (struct ifnet *); 147 static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 148 static void sf_reset (struct sf_softc *); 149 static int sf_init_rx_ring (struct sf_softc *); 150 static void sf_init_tx_ring (struct sf_softc *); 151 static int sf_newbuf (struct sf_softc *, 152 struct sf_rx_bufdesc_type0 *, 153 struct mbuf *); 154 static void sf_setmulti (struct sf_softc *); 155 static int sf_setperf (struct sf_softc *, int, caddr_t); 156 static int sf_sethash (struct sf_softc *, caddr_t, int); 157 #ifdef notdef 158 static int sf_setvlan (struct sf_softc *, int, u_int32_t); 159 #endif 160 161 static u_int8_t sf_read_eeprom (struct sf_softc *, int); 162 static u_int32_t sf_calchash (caddr_t); 163 164 static int sf_miibus_readreg (device_t, int, int); 165 static int sf_miibus_writereg (device_t, int, int, int); 166 static void sf_miibus_statchg (device_t); 167 168 static u_int32_t csr_read_4 (struct sf_softc *, int); 169 static void csr_write_4 (struct sf_softc *, int, u_int32_t); 170 static void sf_txthresh_adjust (struct sf_softc *); 171 172 #ifdef SF_USEIOSPACE 173 #define SF_RES SYS_RES_IOPORT 174 #define SF_RID SF_PCI_LOIO 175 #else 176 #define SF_RES SYS_RES_MEMORY 177 #define SF_RID SF_PCI_LOMEM 178 #endif 179 180 static device_method_t sf_methods[] = { 181 /* Device interface */ 182 DEVMETHOD(device_probe, sf_probe), 183 DEVMETHOD(device_attach, sf_attach), 184 DEVMETHOD(device_detach, sf_detach), 185 DEVMETHOD(device_shutdown, sf_shutdown), 186 187 /* bus interface */ 188 DEVMETHOD(bus_print_child, bus_generic_print_child), 189 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 190 191 /* MII interface */ 192 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 193 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 194 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 195 196 { 0, 0 } 197 }; 198 199 static driver_t sf_driver = { 200 "sf", 201 sf_methods, 202 sizeof(struct sf_softc), 203 }; 204 205 static devclass_t sf_devclass; 206 207 DECLARE_DUMMY_MODULE(if_sf); 208 DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 209 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 210 211 #define SF_SETBIT(sc, reg, x) \ 212 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 213 214 #define SF_CLRBIT(sc, reg, x) \ 215 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 216 217 static u_int32_t csr_read_4(sc, reg) 218 struct sf_softc *sc; 219 int reg; 220 { 221 u_int32_t val; 222 223 #ifdef SF_USEIOSPACE 224 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 225 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 226 #else 227 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 228 #endif 229 230 return(val); 231 } 232 233 static u_int8_t sf_read_eeprom(sc, reg) 234 struct sf_softc *sc; 235 int reg; 236 { 237 u_int8_t val; 238 239 val = (csr_read_4(sc, SF_EEADDR_BASE + 240 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 241 242 return(val); 243 } 244 245 static void csr_write_4(sc, reg, val) 246 struct sf_softc *sc; 247 int reg; 248 u_int32_t val; 249 { 250 #ifdef SF_USEIOSPACE 251 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 252 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 253 #else 254 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 255 #endif 256 return; 257 } 258 259 static u_int32_t sf_calchash(addr) 260 caddr_t addr; 261 { 262 u_int32_t crc, carry; 263 int i, j; 264 u_int8_t c; 265 266 /* Compute CRC for the address value. */ 267 crc = 0xFFFFFFFF; /* initial value */ 268 269 for (i = 0; i < 6; i++) { 270 c = *(addr + i); 271 for (j = 0; j < 8; j++) { 272 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 273 crc <<= 1; 274 c >>= 1; 275 if (carry) 276 crc = (crc ^ 0x04c11db6) | carry; 277 } 278 } 279 280 /* return the filter bit position */ 281 return(crc >> 23 & 0x1FF); 282 } 283 284 /* 285 * Copy the address 'mac' into the perfect RX filter entry at 286 * offset 'idx.' The perfect filter only has 16 entries so do 287 * some sanity tests. 288 */ 289 static int sf_setperf(sc, idx, mac) 290 struct sf_softc *sc; 291 int idx; 292 caddr_t mac; 293 { 294 u_int16_t *p; 295 296 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 297 return(EINVAL); 298 299 if (mac == NULL) 300 return(EINVAL); 301 302 p = (u_int16_t *)mac; 303 304 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 305 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 306 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 307 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 308 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 309 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 310 311 return(0); 312 } 313 314 /* 315 * Set the bit in the 512-bit hash table that corresponds to the 316 * specified mac address 'mac.' If 'prio' is nonzero, update the 317 * priority hash table instead of the filter hash table. 318 */ 319 static int sf_sethash(sc, mac, prio) 320 struct sf_softc *sc; 321 caddr_t mac; 322 int prio; 323 { 324 u_int32_t h = 0; 325 326 if (mac == NULL) 327 return(EINVAL); 328 329 h = sf_calchash(mac); 330 331 if (prio) { 332 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 333 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 334 } else { 335 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 336 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 337 } 338 339 return(0); 340 } 341 342 #ifdef notdef 343 /* 344 * Set a VLAN tag in the receive filter. 345 */ 346 static int sf_setvlan(sc, idx, vlan) 347 struct sf_softc *sc; 348 int idx; 349 u_int32_t vlan; 350 { 351 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 352 return(EINVAL); 353 354 csr_write_4(sc, SF_RXFILT_HASH_BASE + 355 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 356 357 return(0); 358 } 359 #endif 360 361 static int sf_miibus_readreg(dev, phy, reg) 362 device_t dev; 363 int phy, reg; 364 { 365 struct sf_softc *sc; 366 int i; 367 u_int32_t val = 0; 368 369 sc = device_get_softc(dev); 370 371 for (i = 0; i < SF_TIMEOUT; i++) { 372 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 373 if (val & SF_MII_DATAVALID) 374 break; 375 } 376 377 if (i == SF_TIMEOUT) 378 return(0); 379 380 if ((val & 0x0000FFFF) == 0xFFFF) 381 return(0); 382 383 return(val & 0x0000FFFF); 384 } 385 386 static int sf_miibus_writereg(dev, phy, reg, val) 387 device_t dev; 388 int phy, reg, val; 389 { 390 struct sf_softc *sc; 391 int i; 392 int busy; 393 394 sc = device_get_softc(dev); 395 396 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 397 398 for (i = 0; i < SF_TIMEOUT; i++) { 399 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 400 if (!(busy & SF_MII_BUSY)) 401 break; 402 } 403 404 return(0); 405 } 406 407 static void sf_miibus_statchg(dev) 408 device_t dev; 409 { 410 struct sf_softc *sc; 411 struct mii_data *mii; 412 413 sc = device_get_softc(dev); 414 mii = device_get_softc(sc->sf_miibus); 415 416 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 417 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 418 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 419 } else { 420 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 421 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 422 } 423 424 return; 425 } 426 427 static void sf_setmulti(sc) 428 struct sf_softc *sc; 429 { 430 struct ifnet *ifp; 431 int i; 432 struct ifmultiaddr *ifma; 433 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 434 435 ifp = &sc->arpcom.ac_if; 436 437 /* First zot all the existing filters. */ 438 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 439 sf_setperf(sc, i, (char *)&dummy); 440 for (i = SF_RXFILT_HASH_BASE; 441 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 442 csr_write_4(sc, i, 0); 443 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 444 445 /* Now program new ones. */ 446 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 447 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 448 } else { 449 i = 1; 450 /* First find the tail of the list. */ 451 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 452 ifma = ifma->ifma_link.le_next) { 453 if (ifma->ifma_link.le_next == NULL) 454 break; 455 } 456 /* Now traverse the list backwards. */ 457 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 458 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 459 if (ifma->ifma_addr->sa_family != AF_LINK) 460 continue; 461 /* 462 * Program the first 15 multicast groups 463 * into the perfect filter. For all others, 464 * use the hash table. 465 */ 466 if (i < SF_RXFILT_PERFECT_CNT) { 467 sf_setperf(sc, i, 468 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 469 i++; 470 continue; 471 } 472 473 sf_sethash(sc, 474 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 475 } 476 } 477 478 return; 479 } 480 481 /* 482 * Set media options. 483 */ 484 static int sf_ifmedia_upd(ifp) 485 struct ifnet *ifp; 486 { 487 struct sf_softc *sc; 488 struct mii_data *mii; 489 490 sc = ifp->if_softc; 491 mii = device_get_softc(sc->sf_miibus); 492 sc->sf_link = 0; 493 if (mii->mii_instance) { 494 struct mii_softc *miisc; 495 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 496 miisc = LIST_NEXT(miisc, mii_list)) 497 mii_phy_reset(miisc); 498 } 499 mii_mediachg(mii); 500 501 return(0); 502 } 503 504 /* 505 * Report current media status. 506 */ 507 static void sf_ifmedia_sts(ifp, ifmr) 508 struct ifnet *ifp; 509 struct ifmediareq *ifmr; 510 { 511 struct sf_softc *sc; 512 struct mii_data *mii; 513 514 sc = ifp->if_softc; 515 mii = device_get_softc(sc->sf_miibus); 516 517 mii_pollstat(mii); 518 ifmr->ifm_active = mii->mii_media_active; 519 ifmr->ifm_status = mii->mii_media_status; 520 521 return; 522 } 523 524 static int sf_ioctl(ifp, command, data) 525 struct ifnet *ifp; 526 u_long command; 527 caddr_t data; 528 { 529 struct sf_softc *sc = ifp->if_softc; 530 struct ifreq *ifr = (struct ifreq *) data; 531 struct mii_data *mii; 532 int s, error = 0; 533 534 s = splimp(); 535 536 switch(command) { 537 case SIOCSIFADDR: 538 case SIOCGIFADDR: 539 case SIOCSIFMTU: 540 error = ether_ioctl(ifp, command, data); 541 break; 542 case SIOCSIFFLAGS: 543 if (ifp->if_flags & IFF_UP) { 544 if (ifp->if_flags & IFF_RUNNING && 545 ifp->if_flags & IFF_PROMISC && 546 !(sc->sf_if_flags & IFF_PROMISC)) { 547 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 548 } else if (ifp->if_flags & IFF_RUNNING && 549 !(ifp->if_flags & IFF_PROMISC) && 550 sc->sf_if_flags & IFF_PROMISC) { 551 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 552 } else if (!(ifp->if_flags & IFF_RUNNING)) 553 sf_init(sc); 554 } else { 555 if (ifp->if_flags & IFF_RUNNING) 556 sf_stop(sc); 557 } 558 sc->sf_if_flags = ifp->if_flags; 559 error = 0; 560 break; 561 case SIOCADDMULTI: 562 case SIOCDELMULTI: 563 sf_setmulti(sc); 564 error = 0; 565 break; 566 case SIOCGIFMEDIA: 567 case SIOCSIFMEDIA: 568 mii = device_get_softc(sc->sf_miibus); 569 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 570 break; 571 default: 572 error = EINVAL; 573 break; 574 } 575 576 (void)splx(s); 577 578 return(error); 579 } 580 581 static void sf_reset(sc) 582 struct sf_softc *sc; 583 { 584 register int i; 585 586 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 587 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 588 DELAY(1000); 589 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 590 591 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 592 593 for (i = 0; i < SF_TIMEOUT; i++) { 594 DELAY(10); 595 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 596 break; 597 } 598 599 if (i == SF_TIMEOUT) 600 printf("sf%d: reset never completed!\n", sc->sf_unit); 601 602 /* Wait a little while for the chip to get its brains in order. */ 603 DELAY(1000); 604 return; 605 } 606 607 /* 608 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 609 * IDs against our list and return a device name if we find a match. 610 * We also check the subsystem ID so that we can identify exactly which 611 * NIC has been found, if possible. 612 */ 613 static int sf_probe(dev) 614 device_t dev; 615 { 616 struct sf_type *t; 617 618 t = sf_devs; 619 620 while(t->sf_name != NULL) { 621 if ((pci_get_vendor(dev) == t->sf_vid) && 622 (pci_get_device(dev) == t->sf_did)) { 623 switch((pci_read_config(dev, 624 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 625 case AD_SUBSYSID_62011_REV0: 626 case AD_SUBSYSID_62011_REV1: 627 device_set_desc(dev, 628 "Adaptec ANA-62011 10/100BaseTX"); 629 return(0); 630 break; 631 case AD_SUBSYSID_62022: 632 device_set_desc(dev, 633 "Adaptec ANA-62022 10/100BaseTX"); 634 return(0); 635 break; 636 case AD_SUBSYSID_62044_REV0: 637 case AD_SUBSYSID_62044_REV1: 638 device_set_desc(dev, 639 "Adaptec ANA-62044 10/100BaseTX"); 640 return(0); 641 break; 642 case AD_SUBSYSID_62020: 643 device_set_desc(dev, 644 "Adaptec ANA-62020 10/100BaseFX"); 645 return(0); 646 break; 647 case AD_SUBSYSID_69011: 648 device_set_desc(dev, 649 "Adaptec ANA-69011 10/100BaseTX"); 650 return(0); 651 break; 652 default: 653 device_set_desc(dev, t->sf_name); 654 return(0); 655 break; 656 } 657 } 658 t++; 659 } 660 661 return(ENXIO); 662 } 663 664 /* 665 * Attach the interface. Allocate softc structures, do ifmedia 666 * setup and ethernet/BPF attach. 667 */ 668 static int sf_attach(dev) 669 device_t dev; 670 { 671 int s, i; 672 u_int32_t command; 673 struct sf_softc *sc; 674 struct ifnet *ifp; 675 int unit, rid, error = 0; 676 677 s = splimp(); 678 679 sc = device_get_softc(dev); 680 unit = device_get_unit(dev); 681 bzero(sc, sizeof(struct sf_softc)); 682 683 /* 684 * Handle power management nonsense. 685 */ 686 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 687 if (command == 0x01) { 688 689 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 690 if (command & SF_PSTATE_MASK) { 691 u_int32_t iobase, membase, irq; 692 693 /* Save important PCI config data. */ 694 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 695 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 696 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 697 698 /* Reset the power state. */ 699 printf("sf%d: chip is in D%d power mode " 700 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 701 command &= 0xFFFFFFFC; 702 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 703 704 /* Restore PCI config data. */ 705 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 706 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 707 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 708 } 709 } 710 711 /* 712 * Map control/status registers. 713 */ 714 command = pci_read_config(dev, PCIR_COMMAND, 4); 715 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 716 pci_write_config(dev, PCIR_COMMAND, command, 4); 717 command = pci_read_config(dev, PCIR_COMMAND, 4); 718 719 #ifdef SF_USEIOSPACE 720 if (!(command & PCIM_CMD_PORTEN)) { 721 printf("sf%d: failed to enable I/O ports!\n", unit); 722 error = ENXIO; 723 goto fail; 724 } 725 #else 726 if (!(command & PCIM_CMD_MEMEN)) { 727 printf("sf%d: failed to enable memory mapping!\n", unit); 728 error = ENXIO; 729 goto fail; 730 } 731 #endif 732 733 rid = SF_RID; 734 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 735 0, ~0, 1, RF_ACTIVE); 736 737 if (sc->sf_res == NULL) { 738 printf ("sf%d: couldn't map ports\n", unit); 739 error = ENXIO; 740 goto fail; 741 } 742 743 sc->sf_btag = rman_get_bustag(sc->sf_res); 744 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 745 746 /* Allocate interrupt */ 747 rid = 0; 748 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 749 RF_SHAREABLE | RF_ACTIVE); 750 751 if (sc->sf_irq == NULL) { 752 printf("sf%d: couldn't map interrupt\n", unit); 753 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 754 error = ENXIO; 755 goto fail; 756 } 757 758 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 759 sf_intr, sc, &sc->sf_intrhand); 760 761 if (error) { 762 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 763 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 764 printf("sf%d: couldn't set up irq\n", unit); 765 goto fail; 766 } 767 768 callout_handle_init(&sc->sf_stat_ch); 769 770 /* Reset the adapter. */ 771 sf_reset(sc); 772 773 /* 774 * Get station address from the EEPROM. 775 */ 776 for (i = 0; i < ETHER_ADDR_LEN; i++) 777 sc->arpcom.ac_enaddr[i] = 778 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 779 780 /* 781 * An Adaptec chip was detected. Inform the world. 782 */ 783 printf("sf%d: Ethernet address: %6D\n", unit, 784 sc->arpcom.ac_enaddr, ":"); 785 786 sc->sf_unit = unit; 787 788 /* Allocate the descriptor queues. */ 789 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 790 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 791 792 if (sc->sf_ldata == NULL) { 793 printf("sf%d: no memory for list buffers!\n", unit); 794 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 795 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 796 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 797 error = ENXIO; 798 goto fail; 799 } 800 801 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 802 803 /* Do MII setup. */ 804 if (mii_phy_probe(dev, &sc->sf_miibus, 805 sf_ifmedia_upd, sf_ifmedia_sts)) { 806 printf("sf%d: MII without any phy!\n", sc->sf_unit); 807 contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF); 808 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 809 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 810 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 811 error = ENXIO; 812 goto fail; 813 } 814 815 ifp = &sc->arpcom.ac_if; 816 ifp->if_softc = sc; 817 if_initname(ifp, "sf", unit); 818 ifp->if_mtu = ETHERMTU; 819 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 820 ifp->if_ioctl = sf_ioctl; 821 ifp->if_output = ether_output; 822 ifp->if_start = sf_start; 823 ifp->if_watchdog = sf_watchdog; 824 ifp->if_init = sf_init; 825 ifp->if_baudrate = 10000000; 826 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 827 828 /* 829 * Call MI attach routine. 830 */ 831 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 832 833 fail: 834 splx(s); 835 return(error); 836 } 837 838 static int sf_detach(dev) 839 device_t dev; 840 { 841 struct sf_softc *sc; 842 struct ifnet *ifp; 843 int s; 844 845 s = splimp(); 846 847 sc = device_get_softc(dev); 848 ifp = &sc->arpcom.ac_if; 849 850 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 851 sf_stop(sc); 852 853 bus_generic_detach(dev); 854 device_delete_child(dev, sc->sf_miibus); 855 856 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 857 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 858 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 859 860 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 861 862 splx(s); 863 864 return(0); 865 } 866 867 static int sf_init_rx_ring(sc) 868 struct sf_softc *sc; 869 { 870 struct sf_list_data *ld; 871 int i; 872 873 ld = sc->sf_ldata; 874 875 bzero((char *)ld->sf_rx_dlist_big, 876 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 877 bzero((char *)ld->sf_rx_clist, 878 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 879 880 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 881 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 882 return(ENOBUFS); 883 } 884 885 return(0); 886 } 887 888 static void sf_init_tx_ring(sc) 889 struct sf_softc *sc; 890 { 891 struct sf_list_data *ld; 892 int i; 893 894 ld = sc->sf_ldata; 895 896 bzero((char *)ld->sf_tx_dlist, 897 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 898 bzero((char *)ld->sf_tx_clist, 899 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 900 901 for (i = 0; i < SF_TX_DLIST_CNT; i++) 902 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 903 for (i = 0; i < SF_TX_CLIST_CNT; i++) 904 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 905 906 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 907 sc->sf_tx_cnt = 0; 908 909 return; 910 } 911 912 static int sf_newbuf(sc, c, m) 913 struct sf_softc *sc; 914 struct sf_rx_bufdesc_type0 *c; 915 struct mbuf *m; 916 { 917 struct mbuf *m_new = NULL; 918 919 if (m == NULL) { 920 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 921 if (m_new == NULL) 922 return(ENOBUFS); 923 924 MCLGET(m_new, M_DONTWAIT); 925 if (!(m_new->m_flags & M_EXT)) { 926 m_freem(m_new); 927 return(ENOBUFS); 928 } 929 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 930 } else { 931 m_new = m; 932 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 933 m_new->m_data = m_new->m_ext.ext_buf; 934 } 935 936 m_adj(m_new, sizeof(u_int64_t)); 937 938 c->sf_mbuf = m_new; 939 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 940 c->sf_valid = 1; 941 942 return(0); 943 } 944 945 /* 946 * The starfire is programmed to use 'normal' mode for packet reception, 947 * which means we use the consumer/producer model for both the buffer 948 * descriptor queue and the completion descriptor queue. The only problem 949 * with this is that it involves a lot of register accesses: we have to 950 * read the RX completion consumer and producer indexes and the RX buffer 951 * producer index, plus the RX completion consumer and RX buffer producer 952 * indexes have to be updated. It would have been easier if Adaptec had 953 * put each index in a separate register, especially given that the damn 954 * NIC has a 512K register space. 955 * 956 * In spite of all the lovely features that Adaptec crammed into the 6915, 957 * it is marred by one truly stupid design flaw, which is that receive 958 * buffer addresses must be aligned on a longword boundary. This forces 959 * the packet payload to be unaligned, which is suboptimal on the x86 and 960 * completely unuseable on the Alpha. Our only recourse is to copy received 961 * packets into properly aligned buffers before handing them off. 962 */ 963 964 static void sf_rxeof(sc) 965 struct sf_softc *sc; 966 { 967 struct ether_header *eh; 968 struct mbuf *m; 969 struct ifnet *ifp; 970 struct sf_rx_bufdesc_type0 *desc; 971 struct sf_rx_cmpdesc_type3 *cur_rx; 972 u_int32_t rxcons, rxprod; 973 int cmpprodidx, cmpconsidx, bufprodidx; 974 975 ifp = &sc->arpcom.ac_if; 976 977 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 978 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 979 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 980 cmpconsidx = SF_IDX_LO(rxcons); 981 bufprodidx = SF_IDX_LO(rxprod); 982 983 while (cmpconsidx != cmpprodidx) { 984 struct mbuf *m0; 985 986 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 987 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 988 m = desc->sf_mbuf; 989 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 990 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 991 992 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 993 ifp->if_ierrors++; 994 sf_newbuf(sc, desc, m); 995 continue; 996 } 997 998 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 999 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 1000 sf_newbuf(sc, desc, m); 1001 if (m0 == NULL) { 1002 ifp->if_ierrors++; 1003 continue; 1004 } 1005 m_adj(m0, ETHER_ALIGN); 1006 m = m0; 1007 1008 eh = mtod(m, struct ether_header *); 1009 ifp->if_ipackets++; 1010 1011 /* Remove header from mbuf and pass it on. */ 1012 m_adj(m, sizeof(struct ether_header)); 1013 ether_input(ifp, eh, m); 1014 } 1015 1016 csr_write_4(sc, SF_CQ_CONSIDX, 1017 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1018 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1019 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1020 1021 return; 1022 } 1023 1024 /* 1025 * Read the transmit status from the completion queue and release 1026 * mbufs. Note that the buffer descriptor index in the completion 1027 * descriptor is an offset from the start of the transmit buffer 1028 * descriptor list in bytes. This is important because the manual 1029 * gives the impression that it should match the producer/consumer 1030 * index, which is the offset in 8 byte blocks. 1031 */ 1032 static void sf_txeof(sc) 1033 struct sf_softc *sc; 1034 { 1035 int txcons, cmpprodidx, cmpconsidx; 1036 struct sf_tx_cmpdesc_type1 *cur_cmp; 1037 struct sf_tx_bufdesc_type0 *cur_tx; 1038 struct ifnet *ifp; 1039 1040 ifp = &sc->arpcom.ac_if; 1041 1042 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1043 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1044 cmpconsidx = SF_IDX_HI(txcons); 1045 1046 while (cmpconsidx != cmpprodidx) { 1047 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1048 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1049 1050 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1051 ifp->if_opackets++; 1052 else { 1053 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1054 sf_txthresh_adjust(sc); 1055 ifp->if_oerrors++; 1056 } 1057 1058 sc->sf_tx_cnt--; 1059 if (cur_tx->sf_mbuf != NULL) { 1060 m_freem(cur_tx->sf_mbuf); 1061 cur_tx->sf_mbuf = NULL; 1062 } else 1063 break; 1064 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1065 } 1066 1067 ifp->if_timer = 0; 1068 ifp->if_flags &= ~IFF_OACTIVE; 1069 1070 csr_write_4(sc, SF_CQ_CONSIDX, 1071 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1072 ((cmpconsidx << 16) & 0xFFFF0000)); 1073 1074 return; 1075 } 1076 1077 static void sf_txthresh_adjust(sc) 1078 struct sf_softc *sc; 1079 { 1080 u_int32_t txfctl; 1081 u_int8_t txthresh; 1082 1083 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1084 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1085 if (txthresh < 0xFF) { 1086 txthresh++; 1087 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1088 txfctl |= txthresh; 1089 #ifdef DIAGNOSTIC 1090 printf("sf%d: tx underrun, increasing " 1091 "tx threshold to %d bytes\n", 1092 sc->sf_unit, txthresh * 4); 1093 #endif 1094 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1095 } 1096 1097 return; 1098 } 1099 1100 static void sf_intr(arg) 1101 void *arg; 1102 { 1103 struct sf_softc *sc; 1104 struct ifnet *ifp; 1105 u_int32_t status; 1106 1107 sc = arg; 1108 ifp = &sc->arpcom.ac_if; 1109 1110 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) 1111 return; 1112 1113 /* Disable interrupts. */ 1114 csr_write_4(sc, SF_IMR, 0x00000000); 1115 1116 for (;;) { 1117 status = csr_read_4(sc, SF_ISR); 1118 if (status) 1119 csr_write_4(sc, SF_ISR, status); 1120 1121 if (!(status & SF_INTRS)) 1122 break; 1123 1124 if (status & SF_ISR_RXDQ1_DMADONE) 1125 sf_rxeof(sc); 1126 1127 if (status & SF_ISR_TX_TXDONE || 1128 status & SF_ISR_TX_DMADONE || 1129 status & SF_ISR_TX_QUEUEDONE) 1130 sf_txeof(sc); 1131 1132 if (status & SF_ISR_TX_LOFIFO) 1133 sf_txthresh_adjust(sc); 1134 1135 if (status & SF_ISR_ABNORMALINTR) { 1136 if (status & SF_ISR_STATSOFLOW) { 1137 untimeout(sf_stats_update, sc, 1138 sc->sf_stat_ch); 1139 sf_stats_update(sc); 1140 } else 1141 sf_init(sc); 1142 } 1143 } 1144 1145 /* Re-enable interrupts. */ 1146 csr_write_4(sc, SF_IMR, SF_INTRS); 1147 1148 if (ifp->if_snd.ifq_head != NULL) 1149 sf_start(ifp); 1150 1151 return; 1152 } 1153 1154 static void sf_init(xsc) 1155 void *xsc; 1156 { 1157 struct sf_softc *sc; 1158 struct ifnet *ifp; 1159 struct mii_data *mii; 1160 int i, s; 1161 1162 s = splimp(); 1163 1164 sc = xsc; 1165 ifp = &sc->arpcom.ac_if; 1166 mii = device_get_softc(sc->sf_miibus); 1167 1168 sf_stop(sc); 1169 sf_reset(sc); 1170 1171 /* Init all the receive filter registers */ 1172 for (i = SF_RXFILT_PERFECT_BASE; 1173 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1174 csr_write_4(sc, i, 0); 1175 1176 /* Empty stats counter registers. */ 1177 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1178 csr_write_4(sc, SF_STATS_BASE + 1179 (i + sizeof(u_int32_t)), 0); 1180 1181 /* Init our MAC address */ 1182 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1183 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1184 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1185 1186 if (sf_init_rx_ring(sc) == ENOBUFS) { 1187 printf("sf%d: initialization failed: no " 1188 "memory for rx buffers\n", sc->sf_unit); 1189 (void)splx(s); 1190 return; 1191 } 1192 1193 sf_init_tx_ring(sc); 1194 1195 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1196 1197 /* If we want promiscuous mode, set the allframes bit. */ 1198 if (ifp->if_flags & IFF_PROMISC) { 1199 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1200 } else { 1201 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1202 } 1203 1204 if (ifp->if_flags & IFF_BROADCAST) { 1205 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1206 } else { 1207 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1208 } 1209 1210 /* 1211 * Load the multicast filter. 1212 */ 1213 sf_setmulti(sc); 1214 1215 /* Init the completion queue indexes */ 1216 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1217 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1218 1219 /* Init the RX completion queue */ 1220 csr_write_4(sc, SF_RXCQ_CTL_1, 1221 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1222 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1223 1224 /* Init RX DMA control. */ 1225 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1226 1227 /* Init the RX buffer descriptor queue. */ 1228 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1229 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1230 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1231 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1232 1233 /* Init the TX completion queue */ 1234 csr_write_4(sc, SF_TXCQ_CTL, 1235 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1236 1237 /* Init the TX buffer descriptor queue. */ 1238 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1239 vtophys(sc->sf_ldata->sf_tx_dlist)); 1240 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1241 csr_write_4(sc, SF_TXDQ_CTL, 1242 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1243 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1244 1245 /* Enable autopadding of short TX frames. */ 1246 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1247 1248 /* Enable interrupts. */ 1249 csr_write_4(sc, SF_IMR, SF_INTRS); 1250 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1251 1252 /* Enable the RX and TX engines. */ 1253 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1254 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1255 1256 /*mii_mediachg(mii);*/ 1257 sf_ifmedia_upd(ifp); 1258 1259 ifp->if_flags |= IFF_RUNNING; 1260 ifp->if_flags &= ~IFF_OACTIVE; 1261 1262 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1263 1264 splx(s); 1265 1266 return; 1267 } 1268 1269 static int sf_encap(sc, c, m_head) 1270 struct sf_softc *sc; 1271 struct sf_tx_bufdesc_type0 *c; 1272 struct mbuf *m_head; 1273 { 1274 int frag = 0; 1275 struct sf_frag *f = NULL; 1276 struct mbuf *m; 1277 1278 m = m_head; 1279 1280 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1281 if (m->m_len != 0) { 1282 if (frag == SF_MAXFRAGS) 1283 break; 1284 f = &c->sf_frags[frag]; 1285 if (frag == 0) 1286 f->sf_pktlen = m_head->m_pkthdr.len; 1287 f->sf_fraglen = m->m_len; 1288 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1289 frag++; 1290 } 1291 } 1292 1293 if (m != NULL) { 1294 struct mbuf *m_new = NULL; 1295 1296 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1297 if (m_new == NULL) { 1298 printf("sf%d: no memory for tx list", sc->sf_unit); 1299 return(1); 1300 } 1301 1302 if (m_head->m_pkthdr.len > MHLEN) { 1303 MCLGET(m_new, M_DONTWAIT); 1304 if (!(m_new->m_flags & M_EXT)) { 1305 m_freem(m_new); 1306 printf("sf%d: no memory for tx list", 1307 sc->sf_unit); 1308 return(1); 1309 } 1310 } 1311 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1312 mtod(m_new, caddr_t)); 1313 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1314 m_freem(m_head); 1315 m_head = m_new; 1316 f = &c->sf_frags[0]; 1317 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1318 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1319 frag = 1; 1320 } 1321 1322 c->sf_mbuf = m_head; 1323 c->sf_id = SF_TX_BUFDESC_ID; 1324 c->sf_fragcnt = frag; 1325 c->sf_intr = 1; 1326 c->sf_caltcp = 0; 1327 c->sf_crcen = 1; 1328 1329 return(0); 1330 } 1331 1332 static void sf_start(ifp) 1333 struct ifnet *ifp; 1334 { 1335 struct sf_softc *sc; 1336 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1337 struct mbuf *m_head = NULL; 1338 int i, txprod; 1339 1340 sc = ifp->if_softc; 1341 1342 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) 1343 return; 1344 1345 if (ifp->if_flags & IFF_OACTIVE) 1346 return; 1347 1348 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1349 i = SF_IDX_HI(txprod) >> 4; 1350 1351 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1352 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1353 sf_init(sc); 1354 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1355 i = SF_IDX_HI(txprod) >> 4; 1356 } 1357 1358 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1359 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1360 ifp->if_flags |= IFF_OACTIVE; 1361 cur_tx = NULL; 1362 break; 1363 } 1364 IF_DEQUEUE(&ifp->if_snd, m_head); 1365 if (m_head == NULL) 1366 break; 1367 1368 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1369 if (sf_encap(sc, cur_tx, m_head)) { 1370 IF_PREPEND(&ifp->if_snd, m_head); 1371 ifp->if_flags |= IFF_OACTIVE; 1372 cur_tx = NULL; 1373 break; 1374 } 1375 1376 1377 /* 1378 * If there's a BPF listener, bounce a copy of this frame 1379 * to him. 1380 */ 1381 if (ifp->if_bpf) 1382 bpf_mtap(ifp, m_head); 1383 1384 SF_INC(i, SF_TX_DLIST_CNT); 1385 sc->sf_tx_cnt++; 1386 /* 1387 * Don't get the TX DMA queue get too full. 1388 */ 1389 if (sc->sf_tx_cnt > 64) 1390 break; 1391 } 1392 1393 if (cur_tx == NULL) 1394 return; 1395 1396 /* Transmit */ 1397 csr_write_4(sc, SF_TXDQ_PRODIDX, 1398 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1399 ((i << 20) & 0xFFFF0000)); 1400 1401 ifp->if_timer = 5; 1402 1403 return; 1404 } 1405 1406 static void sf_stop(sc) 1407 struct sf_softc *sc; 1408 { 1409 int i; 1410 struct ifnet *ifp; 1411 1412 ifp = &sc->arpcom.ac_if; 1413 1414 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1415 1416 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1417 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1418 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1419 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1420 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1421 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1422 csr_write_4(sc, SF_TXCQ_CTL, 0); 1423 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1424 csr_write_4(sc, SF_TXDQ_CTL, 0); 1425 sf_reset(sc); 1426 1427 sc->sf_link = 0; 1428 1429 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1430 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1431 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1432 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1433 } 1434 } 1435 1436 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1437 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1438 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1439 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1440 } 1441 } 1442 1443 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1444 1445 return; 1446 } 1447 1448 /* 1449 * Note: it is important that this function not be interrupted. We 1450 * use a two-stage register access scheme: if we are interrupted in 1451 * between setting the indirect address register and reading from the 1452 * indirect data register, the contents of the address register could 1453 * be changed out from under us. 1454 */ 1455 static void sf_stats_update(xsc) 1456 void *xsc; 1457 { 1458 struct sf_softc *sc; 1459 struct ifnet *ifp; 1460 struct mii_data *mii; 1461 struct sf_stats stats; 1462 u_int32_t *ptr; 1463 int i, s; 1464 1465 s = splimp(); 1466 1467 sc = xsc; 1468 ifp = &sc->arpcom.ac_if; 1469 mii = device_get_softc(sc->sf_miibus); 1470 1471 ptr = (u_int32_t *)&stats; 1472 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1473 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1474 (i + sizeof(u_int32_t))); 1475 1476 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1477 csr_write_4(sc, SF_STATS_BASE + 1478 (i + sizeof(u_int32_t)), 0); 1479 1480 ifp->if_collisions += stats.sf_tx_single_colls + 1481 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1482 1483 mii_tick(mii); 1484 if (!sc->sf_link) { 1485 mii_pollstat(mii); 1486 if (mii->mii_media_status & IFM_ACTIVE && 1487 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1488 sc->sf_link++; 1489 if (ifp->if_snd.ifq_head != NULL) 1490 sf_start(ifp); 1491 } 1492 1493 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1494 1495 splx(s); 1496 1497 return; 1498 } 1499 1500 static void sf_watchdog(ifp) 1501 struct ifnet *ifp; 1502 { 1503 struct sf_softc *sc; 1504 1505 sc = ifp->if_softc; 1506 1507 ifp->if_oerrors++; 1508 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1509 1510 sf_stop(sc); 1511 sf_reset(sc); 1512 sf_init(sc); 1513 1514 if (ifp->if_snd.ifq_head != NULL) 1515 sf_start(ifp); 1516 1517 return; 1518 } 1519 1520 static void sf_shutdown(dev) 1521 device_t dev; 1522 { 1523 struct sf_softc *sc; 1524 1525 sc = device_get_softc(dev); 1526 1527 sf_stop(sc); 1528 1529 return; 1530 } 1531