1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $ 33 * $DragonFly: src/sys/dev/netif/sf/if_sf.c,v 1.33 2008/08/17 04:32:34 sephe Exp $ 34 */ 35 36 /* 37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 38 * Programming manual is available from: 39 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Department of Electical Engineering 43 * Columbia University, New York City 44 */ 45 46 /* 47 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 48 * controller designed with flexibility and reducing CPU load in mind. 49 * The Starfire offers high and low priority buffer queues, a 50 * producer/consumer index mechanism and several different buffer 51 * queue and completion queue descriptor types. Any one of a number 52 * of different driver designs can be used, depending on system and 53 * OS requirements. This driver makes use of type0 transmit frame 54 * descriptors (since BSD fragments packets across an mbuf chain) 55 * and two RX buffer queues prioritized on size (one queue for small 56 * frames that will fit into a single mbuf, another with full size 57 * mbuf clusters for everything else). The producer/consumer indexes 58 * and completion queues are also used. 59 * 60 * One downside to the Starfire has to do with alignment: buffer 61 * queues must be aligned on 256-byte boundaries, and receive buffers 62 * must be aligned on longword boundaries. The receive buffer alignment 63 * causes problems on the Alpha platform, where the packet payload 64 * should be longword aligned. There is no simple way around this. 65 * 66 * For receive filtering, the Starfire offers 16 perfect filter slots 67 * and a 512-bit hash table. 68 * 69 * The Starfire has no internal transceiver, relying instead on an 70 * external MII-based transceiver. Accessing registers on external 71 * PHYs is done through a special register map rather than with the 72 * usual bitbang MDIO method. 73 * 74 * Acesssing the registers on the Starfire is a little tricky. The 75 * Starfire has a 512K internal register space. When programmed for 76 * PCI memory mapped mode, the entire register space can be accessed 77 * directly. However in I/O space mode, only 256 bytes are directly 78 * mapped into PCI I/O space. The other registers can be accessed 79 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 80 * registers inside the 256-byte I/O window. 81 */ 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/sockio.h> 86 #include <sys/mbuf.h> 87 #include <sys/malloc.h> 88 #include <sys/kernel.h> 89 #include <sys/interrupt.h> 90 #include <sys/socket.h> 91 #include <sys/serialize.h> 92 #include <sys/bus.h> 93 #include <sys/rman.h> 94 #include <sys/thread2.h> 95 96 #include <net/if.h> 97 #include <net/ifq_var.h> 98 #include <net/if_arp.h> 99 #include <net/ethernet.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 103 #include <net/bpf.h> 104 105 #include <vm/vm.h> /* for vtophys */ 106 #include <vm/pmap.h> /* for vtophys */ 107 108 #include <machine/clock.h> /* for DELAY */ 109 110 #include "../mii_layer/mii.h" 111 #include "../mii_layer/miivar.h" 112 113 /* "controller miibus0" required. See GENERIC if you get errors here. */ 114 #include "miibus_if.h" 115 116 #include <bus/pci/pcidevs.h> 117 #include <bus/pci/pcireg.h> 118 #include <bus/pci/pcivar.h> 119 120 #define SF_USEIOSPACE 121 122 #include "if_sfreg.h" 123 124 static struct sf_type sf_devs[] = { 125 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC6915, 126 "Adaptec AIC-6915 10/100BaseTX" }, 127 { 0, 0, NULL } 128 }; 129 130 static int sf_probe (device_t); 131 static int sf_attach (device_t); 132 static int sf_detach (device_t); 133 static void sf_intr (void *); 134 static void sf_stats_update (void *); 135 static void sf_rxeof (struct sf_softc *); 136 static void sf_txeof (struct sf_softc *); 137 static int sf_encap (struct sf_softc *, 138 struct sf_tx_bufdesc_type0 *, 139 struct mbuf *); 140 static void sf_start (struct ifnet *); 141 static int sf_ioctl (struct ifnet *, u_long, caddr_t, 142 struct ucred *); 143 static void sf_init (void *); 144 static void sf_stop (struct sf_softc *); 145 static void sf_watchdog (struct ifnet *); 146 static void sf_shutdown (device_t); 147 static int sf_ifmedia_upd (struct ifnet *); 148 static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 149 static void sf_reset (struct sf_softc *); 150 static int sf_init_rx_ring (struct sf_softc *); 151 static void sf_init_tx_ring (struct sf_softc *); 152 static int sf_newbuf (struct sf_softc *, 153 struct sf_rx_bufdesc_type0 *, 154 struct mbuf *); 155 static void sf_setmulti (struct sf_softc *); 156 static int sf_setperf (struct sf_softc *, int, caddr_t); 157 static int sf_sethash (struct sf_softc *, caddr_t, int); 158 #ifdef notdef 159 static int sf_setvlan (struct sf_softc *, int, u_int32_t); 160 #endif 161 162 static u_int8_t sf_read_eeprom (struct sf_softc *, int); 163 static u_int32_t sf_calchash (caddr_t); 164 165 static int sf_miibus_readreg (device_t, int, int); 166 static int sf_miibus_writereg (device_t, int, int, int); 167 static void sf_miibus_statchg (device_t); 168 169 static u_int32_t csr_read_4 (struct sf_softc *, int); 170 static void csr_write_4 (struct sf_softc *, int, u_int32_t); 171 static void sf_txthresh_adjust (struct sf_softc *); 172 173 #ifdef SF_USEIOSPACE 174 #define SF_RES SYS_RES_IOPORT 175 #define SF_RID SF_PCI_LOIO 176 #else 177 #define SF_RES SYS_RES_MEMORY 178 #define SF_RID SF_PCI_LOMEM 179 #endif 180 181 static device_method_t sf_methods[] = { 182 /* Device interface */ 183 DEVMETHOD(device_probe, sf_probe), 184 DEVMETHOD(device_attach, sf_attach), 185 DEVMETHOD(device_detach, sf_detach), 186 DEVMETHOD(device_shutdown, sf_shutdown), 187 188 /* bus interface */ 189 DEVMETHOD(bus_print_child, bus_generic_print_child), 190 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 191 192 /* MII interface */ 193 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 194 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 195 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 196 197 { 0, 0 } 198 }; 199 200 static driver_t sf_driver = { 201 "sf", 202 sf_methods, 203 sizeof(struct sf_softc), 204 }; 205 206 static devclass_t sf_devclass; 207 208 DECLARE_DUMMY_MODULE(if_sf); 209 DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 210 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 211 212 #define SF_SETBIT(sc, reg, x) \ 213 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 214 215 #define SF_CLRBIT(sc, reg, x) \ 216 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 217 218 static u_int32_t 219 csr_read_4(struct sf_softc *sc, int reg) 220 { 221 u_int32_t val; 222 223 #ifdef SF_USEIOSPACE 224 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 225 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 226 #else 227 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 228 #endif 229 230 return(val); 231 } 232 233 static u_int8_t 234 sf_read_eeprom(struct sf_softc *sc, int reg) 235 { 236 u_int8_t val; 237 238 val = (csr_read_4(sc, SF_EEADDR_BASE + 239 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 240 241 return(val); 242 } 243 244 static void 245 csr_write_4(struct sf_softc *sc, int reg, u_int32_t val) 246 { 247 #ifdef SF_USEIOSPACE 248 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 249 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 250 #else 251 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 252 #endif 253 return; 254 } 255 256 static u_int32_t 257 sf_calchash(caddr_t addr) 258 { 259 u_int32_t crc, carry; 260 int i, j; 261 u_int8_t c; 262 263 /* Compute CRC for the address value. */ 264 crc = 0xFFFFFFFF; /* initial value */ 265 266 for (i = 0; i < 6; i++) { 267 c = *(addr + i); 268 for (j = 0; j < 8; j++) { 269 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 270 crc <<= 1; 271 c >>= 1; 272 if (carry) 273 crc = (crc ^ 0x04c11db6) | carry; 274 } 275 } 276 277 /* return the filter bit position */ 278 return(crc >> 23 & 0x1FF); 279 } 280 281 /* 282 * Copy the address 'mac' into the perfect RX filter entry at 283 * offset 'idx.' The perfect filter only has 16 entries so do 284 * some sanity tests. 285 */ 286 static int 287 sf_setperf(struct sf_softc *sc, int idx, caddr_t mac) 288 { 289 u_int16_t *p; 290 291 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 292 return(EINVAL); 293 294 if (mac == NULL) 295 return(EINVAL); 296 297 p = (u_int16_t *)mac; 298 299 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 300 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 301 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 302 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 303 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 304 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 305 306 return(0); 307 } 308 309 /* 310 * Set the bit in the 512-bit hash table that corresponds to the 311 * specified mac address 'mac.' If 'prio' is nonzero, update the 312 * priority hash table instead of the filter hash table. 313 */ 314 static int 315 sf_sethash(struct sf_softc *sc, caddr_t mac, int prio) 316 { 317 u_int32_t h = 0; 318 319 if (mac == NULL) 320 return(EINVAL); 321 322 h = sf_calchash(mac); 323 324 if (prio) { 325 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 326 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 327 } else { 328 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 329 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 330 } 331 332 return(0); 333 } 334 335 #ifdef notdef 336 /* 337 * Set a VLAN tag in the receive filter. 338 */ 339 static int 340 sf_setvlan(struct sf_softc *sc, int idx, u_int32_t vlan) 341 { 342 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 343 return(EINVAL); 344 345 csr_write_4(sc, SF_RXFILT_HASH_BASE + 346 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 347 348 return(0); 349 } 350 #endif 351 352 static int 353 sf_miibus_readreg(device_t dev, int phy, int reg) 354 { 355 struct sf_softc *sc; 356 int i; 357 u_int32_t val = 0; 358 359 sc = device_get_softc(dev); 360 361 for (i = 0; i < SF_TIMEOUT; i++) { 362 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 363 if (val & SF_MII_DATAVALID) 364 break; 365 } 366 367 if (i == SF_TIMEOUT) 368 return(0); 369 370 if ((val & 0x0000FFFF) == 0xFFFF) 371 return(0); 372 373 return(val & 0x0000FFFF); 374 } 375 376 static int 377 sf_miibus_writereg(device_t dev, int phy, int reg, int val) 378 { 379 struct sf_softc *sc; 380 int i; 381 int busy; 382 383 sc = device_get_softc(dev); 384 385 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 386 387 for (i = 0; i < SF_TIMEOUT; i++) { 388 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 389 if (!(busy & SF_MII_BUSY)) 390 break; 391 } 392 393 return(0); 394 } 395 396 static void 397 sf_miibus_statchg(device_t dev) 398 { 399 struct sf_softc *sc; 400 struct mii_data *mii; 401 402 sc = device_get_softc(dev); 403 mii = device_get_softc(sc->sf_miibus); 404 405 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 406 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 407 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 408 } else { 409 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 410 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 411 } 412 413 return; 414 } 415 416 static void 417 sf_setmulti(struct sf_softc *sc) 418 { 419 struct ifnet *ifp; 420 int i; 421 struct ifmultiaddr *ifma; 422 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 423 424 ifp = &sc->arpcom.ac_if; 425 426 /* First zot all the existing filters. */ 427 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 428 sf_setperf(sc, i, (char *)&dummy); 429 for (i = SF_RXFILT_HASH_BASE; 430 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 431 csr_write_4(sc, i, 0); 432 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 433 434 /* Now program new ones. */ 435 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 436 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 437 } else { 438 i = 1; 439 /* First find the tail of the list. */ 440 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 441 ifma = ifma->ifma_link.le_next) { 442 if (ifma->ifma_link.le_next == NULL) 443 break; 444 } 445 /* Now traverse the list backwards. */ 446 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 447 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 448 if (ifma->ifma_addr->sa_family != AF_LINK) 449 continue; 450 /* 451 * Program the first 15 multicast groups 452 * into the perfect filter. For all others, 453 * use the hash table. 454 */ 455 if (i < SF_RXFILT_PERFECT_CNT) { 456 sf_setperf(sc, i, 457 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 458 i++; 459 continue; 460 } 461 462 sf_sethash(sc, 463 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 464 } 465 } 466 467 return; 468 } 469 470 /* 471 * Set media options. 472 */ 473 static int 474 sf_ifmedia_upd(struct ifnet *ifp) 475 { 476 struct sf_softc *sc; 477 struct mii_data *mii; 478 479 sc = ifp->if_softc; 480 mii = device_get_softc(sc->sf_miibus); 481 sc->sf_link = 0; 482 if (mii->mii_instance) { 483 struct mii_softc *miisc; 484 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 485 miisc = LIST_NEXT(miisc, mii_list)) 486 mii_phy_reset(miisc); 487 } 488 mii_mediachg(mii); 489 490 return(0); 491 } 492 493 /* 494 * Report current media status. 495 */ 496 static void 497 sf_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 498 { 499 struct sf_softc *sc; 500 struct mii_data *mii; 501 502 sc = ifp->if_softc; 503 mii = device_get_softc(sc->sf_miibus); 504 505 mii_pollstat(mii); 506 ifmr->ifm_active = mii->mii_media_active; 507 ifmr->ifm_status = mii->mii_media_status; 508 509 return; 510 } 511 512 static int 513 sf_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 514 { 515 struct sf_softc *sc = ifp->if_softc; 516 struct ifreq *ifr = (struct ifreq *) data; 517 struct mii_data *mii; 518 int error = 0; 519 520 switch(command) { 521 case SIOCSIFFLAGS: 522 if (ifp->if_flags & IFF_UP) { 523 if (ifp->if_flags & IFF_RUNNING && 524 ifp->if_flags & IFF_PROMISC && 525 !(sc->sf_if_flags & IFF_PROMISC)) { 526 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 527 } else if (ifp->if_flags & IFF_RUNNING && 528 !(ifp->if_flags & IFF_PROMISC) && 529 sc->sf_if_flags & IFF_PROMISC) { 530 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 531 } else if (!(ifp->if_flags & IFF_RUNNING)) 532 sf_init(sc); 533 } else { 534 if (ifp->if_flags & IFF_RUNNING) 535 sf_stop(sc); 536 } 537 sc->sf_if_flags = ifp->if_flags; 538 error = 0; 539 break; 540 case SIOCADDMULTI: 541 case SIOCDELMULTI: 542 sf_setmulti(sc); 543 error = 0; 544 break; 545 case SIOCGIFMEDIA: 546 case SIOCSIFMEDIA: 547 mii = device_get_softc(sc->sf_miibus); 548 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 549 break; 550 default: 551 error = ether_ioctl(ifp, command, data); 552 break; 553 } 554 555 return(error); 556 } 557 558 static void 559 sf_reset(struct sf_softc *sc) 560 { 561 int i; 562 563 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 564 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 565 DELAY(1000); 566 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 567 568 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 569 570 for (i = 0; i < SF_TIMEOUT; i++) { 571 DELAY(10); 572 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 573 break; 574 } 575 576 if (i == SF_TIMEOUT) 577 kprintf("sf%d: reset never completed!\n", sc->sf_unit); 578 579 /* Wait a little while for the chip to get its brains in order. */ 580 DELAY(1000); 581 return; 582 } 583 584 /* 585 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 586 * IDs against our list and return a device name if we find a match. 587 * We also check the subsystem ID so that we can identify exactly which 588 * NIC has been found, if possible. 589 */ 590 static int 591 sf_probe(device_t dev) 592 { 593 struct sf_type *t; 594 595 t = sf_devs; 596 597 while(t->sf_name != NULL) { 598 if ((pci_get_vendor(dev) == t->sf_vid) && 599 (pci_get_device(dev) == t->sf_did)) { 600 switch((pci_read_config(dev, 601 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 602 case AD_SUBSYSID_62011_REV0: 603 case AD_SUBSYSID_62011_REV1: 604 device_set_desc(dev, 605 "Adaptec ANA-62011 10/100BaseTX"); 606 return(0); 607 break; 608 case AD_SUBSYSID_62022: 609 device_set_desc(dev, 610 "Adaptec ANA-62022 10/100BaseTX"); 611 return(0); 612 break; 613 case AD_SUBSYSID_62044_REV0: 614 case AD_SUBSYSID_62044_REV1: 615 device_set_desc(dev, 616 "Adaptec ANA-62044 10/100BaseTX"); 617 return(0); 618 break; 619 case AD_SUBSYSID_62020: 620 device_set_desc(dev, 621 "Adaptec ANA-62020 10/100BaseFX"); 622 return(0); 623 break; 624 case AD_SUBSYSID_69011: 625 device_set_desc(dev, 626 "Adaptec ANA-69011 10/100BaseTX"); 627 return(0); 628 break; 629 default: 630 device_set_desc(dev, t->sf_name); 631 return(0); 632 break; 633 } 634 } 635 t++; 636 } 637 638 return(ENXIO); 639 } 640 641 /* 642 * Attach the interface. Allocate softc structures, do ifmedia 643 * setup and ethernet/BPF attach. 644 */ 645 static int 646 sf_attach(device_t dev) 647 { 648 int i; 649 u_int32_t command; 650 struct sf_softc *sc; 651 struct ifnet *ifp; 652 int unit, rid, error = 0; 653 654 sc = device_get_softc(dev); 655 unit = device_get_unit(dev); 656 657 /* 658 * Handle power management nonsense. 659 */ 660 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 661 if (command == 0x01) { 662 663 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 664 if (command & SF_PSTATE_MASK) { 665 u_int32_t iobase, membase, irq; 666 667 /* Save important PCI config data. */ 668 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 669 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 670 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 671 672 /* Reset the power state. */ 673 kprintf("sf%d: chip is in D%d power mode " 674 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 675 command &= 0xFFFFFFFC; 676 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 677 678 /* Restore PCI config data. */ 679 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 680 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 681 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 682 } 683 } 684 685 /* 686 * Map control/status registers. 687 */ 688 command = pci_read_config(dev, PCIR_COMMAND, 4); 689 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 690 pci_write_config(dev, PCIR_COMMAND, command, 4); 691 command = pci_read_config(dev, PCIR_COMMAND, 4); 692 693 #ifdef SF_USEIOSPACE 694 if (!(command & PCIM_CMD_PORTEN)) { 695 kprintf("sf%d: failed to enable I/O ports!\n", unit); 696 error = ENXIO; 697 return(error); 698 } 699 #else 700 if (!(command & PCIM_CMD_MEMEN)) { 701 kprintf("sf%d: failed to enable memory mapping!\n", unit); 702 error = ENXIO; 703 return(error); 704 } 705 #endif 706 707 rid = SF_RID; 708 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE); 709 710 if (sc->sf_res == NULL) { 711 kprintf ("sf%d: couldn't map ports\n", unit); 712 error = ENXIO; 713 return(error); 714 } 715 716 sc->sf_btag = rman_get_bustag(sc->sf_res); 717 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 718 719 /* Allocate interrupt */ 720 rid = 0; 721 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 722 RF_SHAREABLE | RF_ACTIVE); 723 724 if (sc->sf_irq == NULL) { 725 kprintf("sf%d: couldn't map interrupt\n", unit); 726 error = ENXIO; 727 goto fail; 728 } 729 730 callout_init(&sc->sf_stat_timer); 731 732 /* Reset the adapter. */ 733 sf_reset(sc); 734 735 /* 736 * Get station address from the EEPROM. 737 */ 738 for (i = 0; i < ETHER_ADDR_LEN; i++) 739 sc->arpcom.ac_enaddr[i] = 740 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 741 742 sc->sf_unit = unit; 743 744 /* Allocate the descriptor queues. */ 745 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 746 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 747 748 if (sc->sf_ldata == NULL) { 749 kprintf("sf%d: no memory for list buffers!\n", unit); 750 error = ENXIO; 751 goto fail; 752 } 753 754 /* Do MII setup. */ 755 if (mii_phy_probe(dev, &sc->sf_miibus, 756 sf_ifmedia_upd, sf_ifmedia_sts)) { 757 kprintf("sf%d: MII without any phy!\n", sc->sf_unit); 758 error = ENXIO; 759 goto fail; 760 } 761 762 ifp = &sc->arpcom.ac_if; 763 ifp->if_softc = sc; 764 if_initname(ifp, "sf", unit); 765 ifp->if_mtu = ETHERMTU; 766 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 767 ifp->if_ioctl = sf_ioctl; 768 ifp->if_start = sf_start; 769 ifp->if_watchdog = sf_watchdog; 770 ifp->if_init = sf_init; 771 ifp->if_baudrate = 10000000; 772 ifq_set_maxlen(&ifp->if_snd, SF_TX_DLIST_CNT - 1); 773 ifq_set_ready(&ifp->if_snd); 774 775 /* 776 * Call MI attach routine. 777 */ 778 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 779 780 error = bus_setup_intr(dev, sc->sf_irq, INTR_MPSAFE, 781 sf_intr, sc, &sc->sf_intrhand, 782 ifp->if_serializer); 783 784 if (error) { 785 ether_ifdetach(ifp); 786 device_printf(dev, "couldn't set up irq\n"); 787 goto fail; 788 } 789 790 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sf_irq)); 791 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 792 793 return(0); 794 795 fail: 796 sf_detach(dev); 797 return(error); 798 } 799 800 static int 801 sf_detach(device_t dev) 802 { 803 struct sf_softc *sc = device_get_softc(dev); 804 struct ifnet *ifp = &sc->arpcom.ac_if; 805 806 if (device_is_attached(dev)) { 807 lwkt_serialize_enter(ifp->if_serializer); 808 sf_stop(sc); 809 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 810 lwkt_serialize_exit(ifp->if_serializer); 811 812 ether_ifdetach(ifp); 813 } 814 815 if (sc->sf_miibus) 816 device_delete_child(dev, sc->sf_miibus); 817 bus_generic_detach(dev); 818 819 if (sc->sf_irq) 820 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 821 if(sc->sf_res) 822 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 823 824 if (sc->sf_ldata) { 825 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), 826 M_DEVBUF); 827 } 828 829 return(0); 830 } 831 832 static int 833 sf_init_rx_ring(struct sf_softc *sc) 834 { 835 struct sf_list_data *ld; 836 int i; 837 838 ld = sc->sf_ldata; 839 840 bzero((char *)ld->sf_rx_dlist_big, 841 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 842 bzero((char *)ld->sf_rx_clist, 843 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 844 845 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 846 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 847 return(ENOBUFS); 848 } 849 850 return(0); 851 } 852 853 static void 854 sf_init_tx_ring(struct sf_softc *sc) 855 { 856 struct sf_list_data *ld; 857 int i; 858 859 ld = sc->sf_ldata; 860 861 bzero((char *)ld->sf_tx_dlist, 862 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 863 bzero((char *)ld->sf_tx_clist, 864 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 865 866 for (i = 0; i < SF_TX_DLIST_CNT; i++) 867 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 868 for (i = 0; i < SF_TX_CLIST_CNT; i++) 869 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 870 871 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 872 sc->sf_tx_cnt = 0; 873 874 return; 875 } 876 877 static int 878 sf_newbuf(struct sf_softc *sc, struct sf_rx_bufdesc_type0 *c, 879 struct mbuf *m) 880 { 881 struct mbuf *m_new = NULL; 882 883 if (m == NULL) { 884 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 885 if (m_new == NULL) 886 return(ENOBUFS); 887 888 MCLGET(m_new, MB_DONTWAIT); 889 if (!(m_new->m_flags & M_EXT)) { 890 m_freem(m_new); 891 return(ENOBUFS); 892 } 893 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 894 } else { 895 m_new = m; 896 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 897 m_new->m_data = m_new->m_ext.ext_buf; 898 } 899 900 m_adj(m_new, sizeof(u_int64_t)); 901 902 c->sf_mbuf = m_new; 903 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 904 c->sf_valid = 1; 905 906 return(0); 907 } 908 909 /* 910 * The starfire is programmed to use 'normal' mode for packet reception, 911 * which means we use the consumer/producer model for both the buffer 912 * descriptor queue and the completion descriptor queue. The only problem 913 * with this is that it involves a lot of register accesses: we have to 914 * read the RX completion consumer and producer indexes and the RX buffer 915 * producer index, plus the RX completion consumer and RX buffer producer 916 * indexes have to be updated. It would have been easier if Adaptec had 917 * put each index in a separate register, especially given that the damn 918 * NIC has a 512K register space. 919 * 920 * In spite of all the lovely features that Adaptec crammed into the 6915, 921 * it is marred by one truly stupid design flaw, which is that receive 922 * buffer addresses must be aligned on a longword boundary. This forces 923 * the packet payload to be unaligned, which is suboptimal on the x86 and 924 * completely unuseable on the Alpha. Our only recourse is to copy received 925 * packets into properly aligned buffers before handing them off. 926 */ 927 928 static void 929 sf_rxeof(struct sf_softc *sc) 930 { 931 struct mbuf *m; 932 struct ifnet *ifp; 933 struct sf_rx_bufdesc_type0 *desc; 934 struct sf_rx_cmpdesc_type3 *cur_rx; 935 u_int32_t rxcons, rxprod; 936 int cmpprodidx, cmpconsidx, bufprodidx; 937 938 ifp = &sc->arpcom.ac_if; 939 940 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 941 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 942 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 943 cmpconsidx = SF_IDX_LO(rxcons); 944 bufprodidx = SF_IDX_LO(rxprod); 945 946 while (cmpconsidx != cmpprodidx) { 947 struct mbuf *m0; 948 949 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 950 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 951 m = desc->sf_mbuf; 952 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 953 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 954 955 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 956 ifp->if_ierrors++; 957 sf_newbuf(sc, desc, m); 958 continue; 959 } 960 961 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 962 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 963 sf_newbuf(sc, desc, m); 964 if (m0 == NULL) { 965 ifp->if_ierrors++; 966 continue; 967 } 968 m_adj(m0, ETHER_ALIGN); 969 m = m0; 970 971 ifp->if_ipackets++; 972 973 ifp->if_input(ifp, m); 974 } 975 976 csr_write_4(sc, SF_CQ_CONSIDX, 977 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 978 csr_write_4(sc, SF_RXDQ_PTR_Q1, 979 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 980 981 return; 982 } 983 984 /* 985 * Read the transmit status from the completion queue and release 986 * mbufs. Note that the buffer descriptor index in the completion 987 * descriptor is an offset from the start of the transmit buffer 988 * descriptor list in bytes. This is important because the manual 989 * gives the impression that it should match the producer/consumer 990 * index, which is the offset in 8 byte blocks. 991 */ 992 static void 993 sf_txeof(struct sf_softc *sc) 994 { 995 int txcons, cmpprodidx, cmpconsidx; 996 struct sf_tx_cmpdesc_type1 *cur_cmp; 997 struct sf_tx_bufdesc_type0 *cur_tx; 998 struct ifnet *ifp; 999 1000 ifp = &sc->arpcom.ac_if; 1001 1002 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1003 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1004 cmpconsidx = SF_IDX_HI(txcons); 1005 1006 while (cmpconsidx != cmpprodidx) { 1007 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1008 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1009 1010 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1011 ifp->if_opackets++; 1012 else { 1013 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1014 sf_txthresh_adjust(sc); 1015 ifp->if_oerrors++; 1016 } 1017 1018 sc->sf_tx_cnt--; 1019 if (cur_tx->sf_mbuf != NULL) { 1020 m_freem(cur_tx->sf_mbuf); 1021 cur_tx->sf_mbuf = NULL; 1022 } else 1023 break; 1024 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1025 } 1026 1027 ifp->if_timer = 0; 1028 ifp->if_flags &= ~IFF_OACTIVE; 1029 1030 csr_write_4(sc, SF_CQ_CONSIDX, 1031 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1032 ((cmpconsidx << 16) & 0xFFFF0000)); 1033 1034 return; 1035 } 1036 1037 static void 1038 sf_txthresh_adjust(struct sf_softc *sc) 1039 { 1040 u_int32_t txfctl; 1041 u_int8_t txthresh; 1042 1043 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1044 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1045 if (txthresh < 0xFF) { 1046 txthresh++; 1047 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1048 txfctl |= txthresh; 1049 #ifdef DIAGNOSTIC 1050 kprintf("sf%d: tx underrun, increasing " 1051 "tx threshold to %d bytes\n", 1052 sc->sf_unit, txthresh * 4); 1053 #endif 1054 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1055 } 1056 1057 return; 1058 } 1059 1060 static void 1061 sf_intr(void *arg) 1062 { 1063 struct sf_softc *sc; 1064 struct ifnet *ifp; 1065 u_int32_t status; 1066 1067 sc = arg; 1068 ifp = &sc->arpcom.ac_if; 1069 1070 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) 1071 return; 1072 1073 /* Disable interrupts. */ 1074 csr_write_4(sc, SF_IMR, 0x00000000); 1075 1076 for (;;) { 1077 status = csr_read_4(sc, SF_ISR); 1078 if (status) 1079 csr_write_4(sc, SF_ISR, status); 1080 1081 if (!(status & SF_INTRS)) 1082 break; 1083 1084 if (status & SF_ISR_RXDQ1_DMADONE) 1085 sf_rxeof(sc); 1086 1087 if (status & SF_ISR_TX_TXDONE || 1088 status & SF_ISR_TX_DMADONE || 1089 status & SF_ISR_TX_QUEUEDONE) 1090 sf_txeof(sc); 1091 1092 if (status & SF_ISR_TX_LOFIFO) 1093 sf_txthresh_adjust(sc); 1094 1095 if (status & SF_ISR_ABNORMALINTR) { 1096 if (status & SF_ISR_STATSOFLOW) { 1097 callout_stop(&sc->sf_stat_timer); 1098 sf_stats_update(sc); 1099 } else 1100 sf_init(sc); 1101 } 1102 } 1103 1104 /* Re-enable interrupts. */ 1105 csr_write_4(sc, SF_IMR, SF_INTRS); 1106 1107 if (!ifq_is_empty(&ifp->if_snd)) 1108 if_devstart(ifp); 1109 } 1110 1111 static void 1112 sf_init(void *xsc) 1113 { 1114 struct sf_softc *sc = xsc; 1115 struct ifnet *ifp = &sc->arpcom.ac_if; 1116 int i; 1117 1118 sf_stop(sc); 1119 sf_reset(sc); 1120 1121 /* Init all the receive filter registers */ 1122 for (i = SF_RXFILT_PERFECT_BASE; 1123 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1124 csr_write_4(sc, i, 0); 1125 1126 /* Empty stats counter registers. */ 1127 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1128 csr_write_4(sc, SF_STATS_BASE + 1129 (i + sizeof(u_int32_t)), 0); 1130 1131 /* Init our MAC address */ 1132 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1133 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1134 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1135 1136 if (sf_init_rx_ring(sc) == ENOBUFS) { 1137 kprintf("sf%d: initialization failed: no " 1138 "memory for rx buffers\n", sc->sf_unit); 1139 return; 1140 } 1141 1142 sf_init_tx_ring(sc); 1143 1144 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1145 1146 /* If we want promiscuous mode, set the allframes bit. */ 1147 if (ifp->if_flags & IFF_PROMISC) { 1148 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1149 } else { 1150 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1151 } 1152 1153 if (ifp->if_flags & IFF_BROADCAST) { 1154 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1155 } else { 1156 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1157 } 1158 1159 /* 1160 * Load the multicast filter. 1161 */ 1162 sf_setmulti(sc); 1163 1164 /* Init the completion queue indexes */ 1165 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1166 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1167 1168 /* Init the RX completion queue */ 1169 csr_write_4(sc, SF_RXCQ_CTL_1, 1170 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1171 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1172 1173 /* Init RX DMA control. */ 1174 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1175 1176 /* Init the RX buffer descriptor queue. */ 1177 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1178 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1179 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1180 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1181 1182 /* Init the TX completion queue */ 1183 csr_write_4(sc, SF_TXCQ_CTL, 1184 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1185 1186 /* Init the TX buffer descriptor queue. */ 1187 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1188 vtophys(sc->sf_ldata->sf_tx_dlist)); 1189 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1190 csr_write_4(sc, SF_TXDQ_CTL, 1191 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1192 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1193 1194 /* Enable autopadding of short TX frames. */ 1195 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1196 1197 /* Enable interrupts. */ 1198 csr_write_4(sc, SF_IMR, SF_INTRS); 1199 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1200 1201 /* Enable the RX and TX engines. */ 1202 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1203 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1204 1205 /*mii_mediachg(mii);*/ 1206 sf_ifmedia_upd(ifp); 1207 1208 ifp->if_flags |= IFF_RUNNING; 1209 ifp->if_flags &= ~IFF_OACTIVE; 1210 1211 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc); 1212 } 1213 1214 static int 1215 sf_encap(struct sf_softc *sc, struct sf_tx_bufdesc_type0 *c, 1216 struct mbuf *m_head) 1217 { 1218 int frag = 0; 1219 struct sf_frag *f = NULL; 1220 struct mbuf *m; 1221 1222 for (m = m_head; m != NULL; m = m->m_next) { 1223 if (m->m_len != 0) { 1224 if (frag == SF_MAXFRAGS) 1225 break; 1226 f = &c->sf_frags[frag]; 1227 if (frag == 0) 1228 f->sf_pktlen = m_head->m_pkthdr.len; 1229 f->sf_fraglen = m->m_len; 1230 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1231 frag++; 1232 } 1233 } 1234 /* Caller should make sure that 'm_head' is not excessive fragmented */ 1235 KASSERT(m == NULL, ("too many fragments\n")); 1236 1237 c->sf_mbuf = m_head; 1238 c->sf_id = SF_TX_BUFDESC_ID; 1239 c->sf_fragcnt = frag; 1240 c->sf_intr = 1; 1241 c->sf_caltcp = 0; 1242 c->sf_crcen = 1; 1243 1244 return(0); 1245 } 1246 1247 static void 1248 sf_start(struct ifnet *ifp) 1249 { 1250 struct sf_softc *sc; 1251 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1252 struct mbuf *m_head = NULL, *m_defragged; 1253 int i, txprod, need_trans = 0; 1254 1255 sc = ifp->if_softc; 1256 1257 if (!sc->sf_link) { 1258 ifq_purge(&ifp->if_snd); 1259 return; 1260 } 1261 1262 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 1263 return; 1264 1265 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1266 i = SF_IDX_HI(txprod) >> 4; 1267 1268 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1269 kprintf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1270 sf_init(sc); 1271 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1272 i = SF_IDX_HI(txprod) >> 4; 1273 } 1274 1275 while (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1276 struct mbuf *m; 1277 int frag; 1278 1279 /* 1280 * Don't get the TX DMA queue get too full. 1281 */ 1282 if (sc->sf_tx_cnt > 64) { 1283 ifp->if_flags |= IFF_OACTIVE; 1284 break; 1285 } 1286 #ifdef foo 1287 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1288 ifp->if_flags |= IFF_OACTIVE; 1289 break; 1290 } 1291 #endif 1292 1293 m_defragged = NULL; 1294 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1295 if (m_head == NULL) 1296 break; 1297 1298 again: 1299 frag = 0; 1300 for (m = m_head; m != NULL; m = m->m_next) 1301 ++frag; 1302 if (frag > SF_MAXFRAGS) { 1303 if (m_defragged != NULL) { 1304 /* 1305 * Even after defragmentation, there 1306 * are still too many fragments, so 1307 * drop this packet. 1308 */ 1309 m_freem(m_head); 1310 continue; 1311 } 1312 1313 m_defragged = m_defrag(m_head, MB_DONTWAIT); 1314 if (m_defragged == NULL) { 1315 m_freem(m_head); 1316 continue; 1317 } 1318 m_head = m_defragged; 1319 1320 /* Recount # of fragments */ 1321 goto again; 1322 } 1323 1324 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1325 sf_encap(sc, cur_tx, m_head); 1326 BPF_MTAP(ifp, cur_tx->sf_mbuf); 1327 1328 SF_INC(i, SF_TX_DLIST_CNT); 1329 sc->sf_tx_cnt++; 1330 need_trans = 1; 1331 } 1332 1333 if (!need_trans) 1334 return; 1335 1336 /* Transmit */ 1337 csr_write_4(sc, SF_TXDQ_PRODIDX, 1338 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1339 ((i << 20) & 0xFFFF0000)); 1340 1341 ifp->if_timer = 5; 1342 } 1343 1344 static void 1345 sf_stop(struct sf_softc *sc) 1346 { 1347 int i; 1348 struct ifnet *ifp; 1349 1350 ifp = &sc->arpcom.ac_if; 1351 1352 callout_stop(&sc->sf_stat_timer); 1353 1354 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1355 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1356 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1357 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1358 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1359 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1360 csr_write_4(sc, SF_TXCQ_CTL, 0); 1361 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1362 csr_write_4(sc, SF_TXDQ_CTL, 0); 1363 sf_reset(sc); 1364 1365 sc->sf_link = 0; 1366 1367 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1368 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1369 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1370 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1371 } 1372 } 1373 1374 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1375 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1376 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1377 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1378 } 1379 } 1380 1381 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1382 1383 return; 1384 } 1385 1386 /* 1387 * Note: it is important that this function not be interrupted. We 1388 * use a two-stage register access scheme: if we are interrupted in 1389 * between setting the indirect address register and reading from the 1390 * indirect data register, the contents of the address register could 1391 * be changed out from under us. 1392 */ 1393 static void 1394 sf_stats_update(void *xsc) 1395 { 1396 struct sf_softc *sc = xsc; 1397 struct ifnet *ifp = &sc->arpcom.ac_if; 1398 struct mii_data *mii = device_get_softc(sc->sf_miibus); 1399 struct sf_stats stats; 1400 u_int32_t *ptr; 1401 int i; 1402 1403 lwkt_serialize_enter(ifp->if_serializer); 1404 1405 ptr = (u_int32_t *)&stats; 1406 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1407 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1408 (i + sizeof(u_int32_t))); 1409 1410 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1411 csr_write_4(sc, SF_STATS_BASE + 1412 (i + sizeof(u_int32_t)), 0); 1413 1414 ifp->if_collisions += stats.sf_tx_single_colls + 1415 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1416 1417 mii_tick(mii); 1418 if (!sc->sf_link) { 1419 mii_pollstat(mii); 1420 if (mii->mii_media_status & IFM_ACTIVE && 1421 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1422 sc->sf_link++; 1423 if (!ifq_is_empty(&ifp->if_snd)) 1424 if_devstart(ifp); 1425 } 1426 } 1427 1428 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc); 1429 1430 lwkt_serialize_exit(ifp->if_serializer); 1431 } 1432 1433 static void 1434 sf_watchdog(struct ifnet *ifp) 1435 { 1436 struct sf_softc *sc; 1437 1438 sc = ifp->if_softc; 1439 1440 ifp->if_oerrors++; 1441 kprintf("sf%d: watchdog timeout\n", sc->sf_unit); 1442 1443 sf_stop(sc); 1444 sf_reset(sc); 1445 sf_init(sc); 1446 1447 if (!ifq_is_empty(&ifp->if_snd)) 1448 if_devstart(ifp); 1449 } 1450 1451 static void 1452 sf_shutdown(device_t dev) 1453 { 1454 struct sf_softc *sc; 1455 struct ifnet *ifp; 1456 1457 sc = device_get_softc(dev); 1458 ifp = &sc->arpcom.ac_if; 1459 lwkt_serialize_enter(ifp->if_serializer); 1460 sf_stop(sc); 1461 lwkt_serialize_exit(ifp->if_serializer); 1462 1463 return; 1464 } 1465