1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $ 33 */ 34 35 /* 36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 37 * Programming manual is available from: 38 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Department of Electical Engineering 42 * Columbia University, New York City 43 */ 44 45 /* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82 #include <sys/param.h> 83 #include <sys/systm.h> 84 #include <sys/sockio.h> 85 #include <sys/mbuf.h> 86 #include <sys/malloc.h> 87 #include <sys/kernel.h> 88 #include <sys/interrupt.h> 89 #include <sys/socket.h> 90 #include <sys/serialize.h> 91 #include <sys/bus.h> 92 #include <sys/rman.h> 93 #include <sys/thread2.h> 94 95 #include <net/if.h> 96 #include <net/ifq_var.h> 97 #include <net/if_arp.h> 98 #include <net/ethernet.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 102 #include <net/bpf.h> 103 104 #include <vm/vm.h> /* for vtophys */ 105 #include <vm/pmap.h> /* for vtophys */ 106 107 #include <machine/clock.h> /* for DELAY */ 108 109 #include "../mii_layer/mii.h" 110 #include "../mii_layer/miivar.h" 111 112 /* "controller miibus0" required. See GENERIC if you get errors here. */ 113 #include "miibus_if.h" 114 115 #include "pcidevs.h" 116 #include <bus/pci/pcireg.h> 117 #include <bus/pci/pcivar.h> 118 119 #define SF_USEIOSPACE 120 121 #include "if_sfreg.h" 122 123 static struct sf_type sf_devs[] = { 124 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC6915, 125 "Adaptec AIC-6915 10/100BaseTX" }, 126 { 0, 0, NULL } 127 }; 128 129 static int sf_probe (device_t); 130 static int sf_attach (device_t); 131 static int sf_detach (device_t); 132 static void sf_intr (void *); 133 static void sf_stats_update (void *); 134 static void sf_rxeof (struct sf_softc *); 135 static void sf_txeof (struct sf_softc *); 136 static int sf_encap (struct sf_softc *, 137 struct sf_tx_bufdesc_type0 *, 138 struct mbuf *); 139 static void sf_start (struct ifnet *, struct ifaltq_subque *); 140 static int sf_ioctl (struct ifnet *, u_long, caddr_t, 141 struct ucred *); 142 static void sf_init (void *); 143 static void sf_stop (struct sf_softc *); 144 static void sf_watchdog (struct ifnet *); 145 static void sf_shutdown (device_t); 146 static int sf_ifmedia_upd (struct ifnet *); 147 static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 148 static void sf_reset (struct sf_softc *); 149 static int sf_init_rx_ring (struct sf_softc *); 150 static void sf_init_tx_ring (struct sf_softc *); 151 static int sf_newbuf (struct sf_softc *, 152 struct sf_rx_bufdesc_type0 *, 153 struct mbuf *); 154 static void sf_setmulti (struct sf_softc *); 155 static int sf_setperf (struct sf_softc *, int, caddr_t); 156 static int sf_sethash (struct sf_softc *, caddr_t, int); 157 #ifdef notdef 158 static int sf_setvlan (struct sf_softc *, int, u_int32_t); 159 #endif 160 161 static u_int8_t sf_read_eeprom (struct sf_softc *, int); 162 static u_int32_t sf_calchash (caddr_t); 163 164 static int sf_miibus_readreg (device_t, int, int); 165 static int sf_miibus_writereg (device_t, int, int, int); 166 static void sf_miibus_statchg (device_t); 167 168 static u_int32_t csr_read_4 (struct sf_softc *, int); 169 static void csr_write_4 (struct sf_softc *, int, u_int32_t); 170 static void sf_txthresh_adjust (struct sf_softc *); 171 172 #ifdef SF_USEIOSPACE 173 #define SF_RES SYS_RES_IOPORT 174 #define SF_RID SF_PCI_LOIO 175 #else 176 #define SF_RES SYS_RES_MEMORY 177 #define SF_RID SF_PCI_LOMEM 178 #endif 179 180 static device_method_t sf_methods[] = { 181 /* Device interface */ 182 DEVMETHOD(device_probe, sf_probe), 183 DEVMETHOD(device_attach, sf_attach), 184 DEVMETHOD(device_detach, sf_detach), 185 DEVMETHOD(device_shutdown, sf_shutdown), 186 187 /* bus interface */ 188 DEVMETHOD(bus_print_child, bus_generic_print_child), 189 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 190 191 /* MII interface */ 192 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 193 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 194 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 195 196 DEVMETHOD_END 197 }; 198 199 static driver_t sf_driver = { 200 "sf", 201 sf_methods, 202 sizeof(struct sf_softc), 203 }; 204 205 static devclass_t sf_devclass; 206 207 DECLARE_DUMMY_MODULE(if_sf); 208 DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, NULL, NULL); 209 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, NULL, NULL); 210 211 #define SF_SETBIT(sc, reg, x) \ 212 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 213 214 #define SF_CLRBIT(sc, reg, x) \ 215 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 216 217 static u_int32_t 218 csr_read_4(struct sf_softc *sc, int reg) 219 { 220 u_int32_t val; 221 222 #ifdef SF_USEIOSPACE 223 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 224 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 225 #else 226 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 227 #endif 228 229 return(val); 230 } 231 232 static u_int8_t 233 sf_read_eeprom(struct sf_softc *sc, int reg) 234 { 235 u_int8_t val; 236 237 val = (csr_read_4(sc, SF_EEADDR_BASE + 238 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 239 240 return(val); 241 } 242 243 static void 244 csr_write_4(struct sf_softc *sc, int reg, u_int32_t val) 245 { 246 #ifdef SF_USEIOSPACE 247 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 248 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 249 #else 250 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 251 #endif 252 return; 253 } 254 255 static u_int32_t 256 sf_calchash(caddr_t addr) 257 { 258 u_int32_t crc, carry; 259 int i, j; 260 u_int8_t c; 261 262 /* Compute CRC for the address value. */ 263 crc = 0xFFFFFFFF; /* initial value */ 264 265 for (i = 0; i < 6; i++) { 266 c = *(addr + i); 267 for (j = 0; j < 8; j++) { 268 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 269 crc <<= 1; 270 c >>= 1; 271 if (carry) 272 crc = (crc ^ 0x04c11db6) | carry; 273 } 274 } 275 276 /* return the filter bit position */ 277 return(crc >> 23 & 0x1FF); 278 } 279 280 /* 281 * Copy the address 'mac' into the perfect RX filter entry at 282 * offset 'idx.' The perfect filter only has 16 entries so do 283 * some sanity tests. 284 */ 285 static int 286 sf_setperf(struct sf_softc *sc, int idx, caddr_t mac) 287 { 288 u_int16_t *p; 289 290 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 291 return(EINVAL); 292 293 if (mac == NULL) 294 return(EINVAL); 295 296 p = (u_int16_t *)mac; 297 298 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 299 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 300 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 301 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 302 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 303 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 304 305 return(0); 306 } 307 308 /* 309 * Set the bit in the 512-bit hash table that corresponds to the 310 * specified mac address 'mac.' If 'prio' is nonzero, update the 311 * priority hash table instead of the filter hash table. 312 */ 313 static int 314 sf_sethash(struct sf_softc *sc, caddr_t mac, int prio) 315 { 316 u_int32_t h = 0; 317 318 if (mac == NULL) 319 return(EINVAL); 320 321 h = sf_calchash(mac); 322 323 if (prio) { 324 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 325 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 326 } else { 327 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 328 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 329 } 330 331 return(0); 332 } 333 334 #ifdef notdef 335 /* 336 * Set a VLAN tag in the receive filter. 337 */ 338 static int 339 sf_setvlan(struct sf_softc *sc, int idx, u_int32_t vlan) 340 { 341 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 342 return(EINVAL); 343 344 csr_write_4(sc, SF_RXFILT_HASH_BASE + 345 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 346 347 return(0); 348 } 349 #endif 350 351 static int 352 sf_miibus_readreg(device_t dev, int phy, int reg) 353 { 354 struct sf_softc *sc; 355 int i; 356 u_int32_t val = 0; 357 358 sc = device_get_softc(dev); 359 360 for (i = 0; i < SF_TIMEOUT; i++) { 361 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 362 if (val & SF_MII_DATAVALID) 363 break; 364 } 365 366 if (i == SF_TIMEOUT) 367 return(0); 368 369 if ((val & 0x0000FFFF) == 0xFFFF) 370 return(0); 371 372 return(val & 0x0000FFFF); 373 } 374 375 static int 376 sf_miibus_writereg(device_t dev, int phy, int reg, int val) 377 { 378 struct sf_softc *sc; 379 int i; 380 int busy; 381 382 sc = device_get_softc(dev); 383 384 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 385 386 for (i = 0; i < SF_TIMEOUT; i++) { 387 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 388 if (!(busy & SF_MII_BUSY)) 389 break; 390 } 391 392 return(0); 393 } 394 395 static void 396 sf_miibus_statchg(device_t dev) 397 { 398 struct sf_softc *sc; 399 struct mii_data *mii; 400 401 sc = device_get_softc(dev); 402 mii = device_get_softc(sc->sf_miibus); 403 404 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 405 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 406 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 407 } else { 408 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 409 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 410 } 411 412 return; 413 } 414 415 static void 416 sf_setmulti(struct sf_softc *sc) 417 { 418 struct ifnet *ifp; 419 int i; 420 struct ifmultiaddr *ifma; 421 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 422 423 ifp = &sc->arpcom.ac_if; 424 425 /* First zot all the existing filters. */ 426 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 427 sf_setperf(sc, i, (char *)&dummy); 428 for (i = SF_RXFILT_HASH_BASE; 429 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 430 csr_write_4(sc, i, 0); 431 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 432 433 /* Now program new ones. */ 434 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 435 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 436 } else { 437 i = 1; 438 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 439 if (ifma->ifma_addr->sa_family != AF_LINK) 440 continue; 441 /* 442 * Program the first 15 multicast groups 443 * into the perfect filter. For all others, 444 * use the hash table. 445 */ 446 if (i < SF_RXFILT_PERFECT_CNT) { 447 sf_setperf(sc, i, 448 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 449 i++; 450 continue; 451 } 452 453 sf_sethash(sc, 454 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 455 } 456 } 457 458 return; 459 } 460 461 /* 462 * Set media options. 463 */ 464 static int 465 sf_ifmedia_upd(struct ifnet *ifp) 466 { 467 struct sf_softc *sc; 468 struct mii_data *mii; 469 470 sc = ifp->if_softc; 471 mii = device_get_softc(sc->sf_miibus); 472 sc->sf_link = 0; 473 if (mii->mii_instance) { 474 struct mii_softc *miisc; 475 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 476 miisc = LIST_NEXT(miisc, mii_list)) 477 mii_phy_reset(miisc); 478 } 479 mii_mediachg(mii); 480 481 return(0); 482 } 483 484 /* 485 * Report current media status. 486 */ 487 static void 488 sf_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 489 { 490 struct sf_softc *sc; 491 struct mii_data *mii; 492 493 sc = ifp->if_softc; 494 mii = device_get_softc(sc->sf_miibus); 495 496 mii_pollstat(mii); 497 ifmr->ifm_active = mii->mii_media_active; 498 ifmr->ifm_status = mii->mii_media_status; 499 500 return; 501 } 502 503 static int 504 sf_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 505 { 506 struct sf_softc *sc = ifp->if_softc; 507 struct ifreq *ifr = (struct ifreq *) data; 508 struct mii_data *mii; 509 int error = 0; 510 511 switch(command) { 512 case SIOCSIFFLAGS: 513 if (ifp->if_flags & IFF_UP) { 514 if (ifp->if_flags & IFF_RUNNING && 515 ifp->if_flags & IFF_PROMISC && 516 !(sc->sf_if_flags & IFF_PROMISC)) { 517 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 518 } else if (ifp->if_flags & IFF_RUNNING && 519 !(ifp->if_flags & IFF_PROMISC) && 520 sc->sf_if_flags & IFF_PROMISC) { 521 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 522 } else if (!(ifp->if_flags & IFF_RUNNING)) 523 sf_init(sc); 524 } else { 525 if (ifp->if_flags & IFF_RUNNING) 526 sf_stop(sc); 527 } 528 sc->sf_if_flags = ifp->if_flags; 529 error = 0; 530 break; 531 case SIOCADDMULTI: 532 case SIOCDELMULTI: 533 sf_setmulti(sc); 534 error = 0; 535 break; 536 case SIOCGIFMEDIA: 537 case SIOCSIFMEDIA: 538 mii = device_get_softc(sc->sf_miibus); 539 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 540 break; 541 default: 542 error = ether_ioctl(ifp, command, data); 543 break; 544 } 545 546 return(error); 547 } 548 549 static void 550 sf_reset(struct sf_softc *sc) 551 { 552 int i; 553 554 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 555 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 556 DELAY(1000); 557 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 558 559 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 560 561 for (i = 0; i < SF_TIMEOUT; i++) { 562 DELAY(10); 563 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 564 break; 565 } 566 567 if (i == SF_TIMEOUT) 568 kprintf("sf%d: reset never completed!\n", sc->sf_unit); 569 570 /* Wait a little while for the chip to get its brains in order. */ 571 DELAY(1000); 572 return; 573 } 574 575 /* 576 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 577 * IDs against our list and return a device name if we find a match. 578 * We also check the subsystem ID so that we can identify exactly which 579 * NIC has been found, if possible. 580 */ 581 static int 582 sf_probe(device_t dev) 583 { 584 struct sf_type *t; 585 586 t = sf_devs; 587 588 while(t->sf_name != NULL) { 589 if ((pci_get_vendor(dev) == t->sf_vid) && 590 (pci_get_device(dev) == t->sf_did)) { 591 switch((pci_read_config(dev, 592 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 593 case AD_SUBSYSID_62011_REV0: 594 case AD_SUBSYSID_62011_REV1: 595 device_set_desc(dev, 596 "Adaptec ANA-62011 10/100BaseTX"); 597 return(0); 598 break; 599 case AD_SUBSYSID_62022: 600 device_set_desc(dev, 601 "Adaptec ANA-62022 10/100BaseTX"); 602 return(0); 603 break; 604 case AD_SUBSYSID_62044_REV0: 605 case AD_SUBSYSID_62044_REV1: 606 device_set_desc(dev, 607 "Adaptec ANA-62044 10/100BaseTX"); 608 return(0); 609 break; 610 case AD_SUBSYSID_62020: 611 device_set_desc(dev, 612 "Adaptec ANA-62020 10/100BaseFX"); 613 return(0); 614 break; 615 case AD_SUBSYSID_69011: 616 device_set_desc(dev, 617 "Adaptec ANA-69011 10/100BaseTX"); 618 return(0); 619 break; 620 default: 621 device_set_desc(dev, t->sf_name); 622 return(0); 623 break; 624 } 625 } 626 t++; 627 } 628 629 return(ENXIO); 630 } 631 632 /* 633 * Attach the interface. Allocate softc structures, do ifmedia 634 * setup and ethernet/BPF attach. 635 */ 636 static int 637 sf_attach(device_t dev) 638 { 639 int i; 640 u_int32_t command; 641 struct sf_softc *sc; 642 struct ifnet *ifp; 643 int unit, rid, error = 0; 644 645 sc = device_get_softc(dev); 646 unit = device_get_unit(dev); 647 648 /* 649 * Handle power management nonsense. 650 */ 651 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 652 if (command == 0x01) { 653 654 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 655 if (command & SF_PSTATE_MASK) { 656 u_int32_t iobase, membase, irq; 657 658 /* Save important PCI config data. */ 659 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 660 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 661 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 662 663 /* Reset the power state. */ 664 kprintf("sf%d: chip is in D%d power mode " 665 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 666 command &= 0xFFFFFFFC; 667 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 668 669 /* Restore PCI config data. */ 670 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 671 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 672 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 673 } 674 } 675 676 /* 677 * Map control/status registers. 678 */ 679 command = pci_read_config(dev, PCIR_COMMAND, 4); 680 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 681 pci_write_config(dev, PCIR_COMMAND, command, 4); 682 command = pci_read_config(dev, PCIR_COMMAND, 4); 683 684 #ifdef SF_USEIOSPACE 685 if (!(command & PCIM_CMD_PORTEN)) { 686 kprintf("sf%d: failed to enable I/O ports!\n", unit); 687 error = ENXIO; 688 return(error); 689 } 690 #else 691 if (!(command & PCIM_CMD_MEMEN)) { 692 kprintf("sf%d: failed to enable memory mapping!\n", unit); 693 error = ENXIO; 694 return(error); 695 } 696 #endif 697 698 rid = SF_RID; 699 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE); 700 701 if (sc->sf_res == NULL) { 702 kprintf ("sf%d: couldn't map ports\n", unit); 703 error = ENXIO; 704 return(error); 705 } 706 707 sc->sf_btag = rman_get_bustag(sc->sf_res); 708 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 709 710 /* Allocate interrupt */ 711 rid = 0; 712 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 713 RF_SHAREABLE | RF_ACTIVE); 714 715 if (sc->sf_irq == NULL) { 716 kprintf("sf%d: couldn't map interrupt\n", unit); 717 error = ENXIO; 718 goto fail; 719 } 720 721 callout_init(&sc->sf_stat_timer); 722 723 /* Reset the adapter. */ 724 sf_reset(sc); 725 726 /* 727 * Get station address from the EEPROM. 728 */ 729 for (i = 0; i < ETHER_ADDR_LEN; i++) 730 sc->arpcom.ac_enaddr[i] = 731 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 732 733 sc->sf_unit = unit; 734 735 /* Allocate the descriptor queues. */ 736 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 737 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 738 739 if (sc->sf_ldata == NULL) { 740 kprintf("sf%d: no memory for list buffers!\n", unit); 741 error = ENXIO; 742 goto fail; 743 } 744 745 /* Do MII setup. */ 746 if (mii_phy_probe(dev, &sc->sf_miibus, 747 sf_ifmedia_upd, sf_ifmedia_sts)) { 748 kprintf("sf%d: MII without any phy!\n", sc->sf_unit); 749 error = ENXIO; 750 goto fail; 751 } 752 753 ifp = &sc->arpcom.ac_if; 754 ifp->if_softc = sc; 755 if_initname(ifp, "sf", unit); 756 ifp->if_mtu = ETHERMTU; 757 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 758 ifp->if_ioctl = sf_ioctl; 759 ifp->if_start = sf_start; 760 ifp->if_watchdog = sf_watchdog; 761 ifp->if_init = sf_init; 762 ifp->if_baudrate = 10000000; 763 ifq_set_maxlen(&ifp->if_snd, SF_TX_DLIST_CNT - 1); 764 ifq_set_ready(&ifp->if_snd); 765 766 /* 767 * Call MI attach routine. 768 */ 769 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 770 771 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sf_irq)); 772 773 error = bus_setup_intr(dev, sc->sf_irq, INTR_MPSAFE, 774 sf_intr, sc, &sc->sf_intrhand, 775 ifp->if_serializer); 776 777 if (error) { 778 ether_ifdetach(ifp); 779 device_printf(dev, "couldn't set up irq\n"); 780 goto fail; 781 } 782 783 return(0); 784 785 fail: 786 sf_detach(dev); 787 return(error); 788 } 789 790 static int 791 sf_detach(device_t dev) 792 { 793 struct sf_softc *sc = device_get_softc(dev); 794 struct ifnet *ifp = &sc->arpcom.ac_if; 795 796 if (device_is_attached(dev)) { 797 lwkt_serialize_enter(ifp->if_serializer); 798 sf_stop(sc); 799 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 800 lwkt_serialize_exit(ifp->if_serializer); 801 802 ether_ifdetach(ifp); 803 } 804 805 if (sc->sf_miibus) 806 device_delete_child(dev, sc->sf_miibus); 807 bus_generic_detach(dev); 808 809 if (sc->sf_irq) 810 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 811 if(sc->sf_res) 812 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 813 814 if (sc->sf_ldata) { 815 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), 816 M_DEVBUF); 817 } 818 819 return(0); 820 } 821 822 static int 823 sf_init_rx_ring(struct sf_softc *sc) 824 { 825 struct sf_list_data *ld; 826 int i; 827 828 ld = sc->sf_ldata; 829 830 bzero((char *)ld->sf_rx_dlist_big, 831 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 832 bzero((char *)ld->sf_rx_clist, 833 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 834 835 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 836 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 837 return(ENOBUFS); 838 } 839 840 return(0); 841 } 842 843 static void 844 sf_init_tx_ring(struct sf_softc *sc) 845 { 846 struct sf_list_data *ld; 847 int i; 848 849 ld = sc->sf_ldata; 850 851 bzero((char *)ld->sf_tx_dlist, 852 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 853 bzero((char *)ld->sf_tx_clist, 854 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 855 856 for (i = 0; i < SF_TX_DLIST_CNT; i++) 857 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 858 for (i = 0; i < SF_TX_CLIST_CNT; i++) 859 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 860 861 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 862 sc->sf_tx_cnt = 0; 863 864 return; 865 } 866 867 static int 868 sf_newbuf(struct sf_softc *sc, struct sf_rx_bufdesc_type0 *c, 869 struct mbuf *m) 870 { 871 struct mbuf *m_new = NULL; 872 873 if (m == NULL) { 874 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 875 if (m_new == NULL) 876 return(ENOBUFS); 877 878 MCLGET(m_new, MB_DONTWAIT); 879 if (!(m_new->m_flags & M_EXT)) { 880 m_freem(m_new); 881 return(ENOBUFS); 882 } 883 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 884 } else { 885 m_new = m; 886 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 887 m_new->m_data = m_new->m_ext.ext_buf; 888 } 889 890 m_adj(m_new, sizeof(u_int64_t)); 891 892 c->sf_mbuf = m_new; 893 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 894 c->sf_valid = 1; 895 896 return(0); 897 } 898 899 /* 900 * The starfire is programmed to use 'normal' mode for packet reception, 901 * which means we use the consumer/producer model for both the buffer 902 * descriptor queue and the completion descriptor queue. The only problem 903 * with this is that it involves a lot of register accesses: we have to 904 * read the RX completion consumer and producer indexes and the RX buffer 905 * producer index, plus the RX completion consumer and RX buffer producer 906 * indexes have to be updated. It would have been easier if Adaptec had 907 * put each index in a separate register, especially given that the damn 908 * NIC has a 512K register space. 909 * 910 * In spite of all the lovely features that Adaptec crammed into the 6915, 911 * it is marred by one truly stupid design flaw, which is that receive 912 * buffer addresses must be aligned on a longword boundary. This forces 913 * the packet payload to be unaligned, which is suboptimal on the x86 and 914 * completely unuseable on the Alpha. Our only recourse is to copy received 915 * packets into properly aligned buffers before handing them off. 916 */ 917 918 static void 919 sf_rxeof(struct sf_softc *sc) 920 { 921 struct mbuf *m; 922 struct ifnet *ifp; 923 struct sf_rx_bufdesc_type0 *desc; 924 struct sf_rx_cmpdesc_type3 *cur_rx; 925 u_int32_t rxcons, rxprod; 926 int cmpprodidx, cmpconsidx, bufprodidx; 927 928 ifp = &sc->arpcom.ac_if; 929 930 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 931 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 932 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 933 cmpconsidx = SF_IDX_LO(rxcons); 934 bufprodidx = SF_IDX_LO(rxprod); 935 936 while (cmpconsidx != cmpprodidx) { 937 struct mbuf *m0; 938 939 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 940 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 941 m = desc->sf_mbuf; 942 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 943 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 944 945 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 946 IFNET_STAT_INC(ifp, ierrors, 1); 947 sf_newbuf(sc, desc, m); 948 continue; 949 } 950 951 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 952 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 953 sf_newbuf(sc, desc, m); 954 if (m0 == NULL) { 955 IFNET_STAT_INC(ifp, ierrors, 1); 956 continue; 957 } 958 m_adj(m0, ETHER_ALIGN); 959 m = m0; 960 961 IFNET_STAT_INC(ifp, ipackets, 1); 962 963 ifp->if_input(ifp, m, NULL, -1); 964 } 965 966 csr_write_4(sc, SF_CQ_CONSIDX, 967 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 968 csr_write_4(sc, SF_RXDQ_PTR_Q1, 969 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 970 971 return; 972 } 973 974 /* 975 * Read the transmit status from the completion queue and release 976 * mbufs. Note that the buffer descriptor index in the completion 977 * descriptor is an offset from the start of the transmit buffer 978 * descriptor list in bytes. This is important because the manual 979 * gives the impression that it should match the producer/consumer 980 * index, which is the offset in 8 byte blocks. 981 */ 982 static void 983 sf_txeof(struct sf_softc *sc) 984 { 985 int txcons, cmpprodidx, cmpconsidx; 986 struct sf_tx_cmpdesc_type1 *cur_cmp; 987 struct sf_tx_bufdesc_type0 *cur_tx; 988 struct ifnet *ifp; 989 990 ifp = &sc->arpcom.ac_if; 991 992 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 993 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 994 cmpconsidx = SF_IDX_HI(txcons); 995 996 while (cmpconsidx != cmpprodidx) { 997 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 998 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 999 1000 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1001 IFNET_STAT_INC(ifp, opackets, 1); 1002 else { 1003 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1004 sf_txthresh_adjust(sc); 1005 IFNET_STAT_INC(ifp, oerrors, 1); 1006 } 1007 1008 sc->sf_tx_cnt--; 1009 if (cur_tx->sf_mbuf != NULL) { 1010 m_freem(cur_tx->sf_mbuf); 1011 cur_tx->sf_mbuf = NULL; 1012 } else 1013 break; 1014 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1015 } 1016 1017 ifp->if_timer = 0; 1018 ifq_clr_oactive(&ifp->if_snd); 1019 1020 csr_write_4(sc, SF_CQ_CONSIDX, 1021 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1022 ((cmpconsidx << 16) & 0xFFFF0000)); 1023 1024 return; 1025 } 1026 1027 static void 1028 sf_txthresh_adjust(struct sf_softc *sc) 1029 { 1030 u_int32_t txfctl; 1031 u_int8_t txthresh; 1032 1033 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1034 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1035 if (txthresh < 0xFF) { 1036 txthresh++; 1037 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1038 txfctl |= txthresh; 1039 #ifdef DIAGNOSTIC 1040 kprintf("sf%d: tx underrun, increasing " 1041 "tx threshold to %d bytes\n", 1042 sc->sf_unit, txthresh * 4); 1043 #endif 1044 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1045 } 1046 1047 return; 1048 } 1049 1050 static void 1051 sf_intr(void *arg) 1052 { 1053 struct sf_softc *sc; 1054 struct ifnet *ifp; 1055 u_int32_t status; 1056 1057 sc = arg; 1058 ifp = &sc->arpcom.ac_if; 1059 1060 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) 1061 return; 1062 1063 /* Disable interrupts. */ 1064 csr_write_4(sc, SF_IMR, 0x00000000); 1065 1066 for (;;) { 1067 status = csr_read_4(sc, SF_ISR); 1068 if (status) 1069 csr_write_4(sc, SF_ISR, status); 1070 1071 if (!(status & SF_INTRS)) 1072 break; 1073 1074 if (status & SF_ISR_RXDQ1_DMADONE) 1075 sf_rxeof(sc); 1076 1077 if (status & SF_ISR_TX_TXDONE || 1078 status & SF_ISR_TX_DMADONE || 1079 status & SF_ISR_TX_QUEUEDONE) 1080 sf_txeof(sc); 1081 1082 if (status & SF_ISR_TX_LOFIFO) 1083 sf_txthresh_adjust(sc); 1084 1085 if (status & SF_ISR_ABNORMALINTR) { 1086 if (status & SF_ISR_STATSOFLOW) { 1087 callout_stop(&sc->sf_stat_timer); 1088 sf_stats_update(sc); 1089 } else 1090 sf_init(sc); 1091 } 1092 } 1093 1094 /* Re-enable interrupts. */ 1095 csr_write_4(sc, SF_IMR, SF_INTRS); 1096 1097 if (!ifq_is_empty(&ifp->if_snd)) 1098 if_devstart(ifp); 1099 } 1100 1101 static void 1102 sf_init(void *xsc) 1103 { 1104 struct sf_softc *sc = xsc; 1105 struct ifnet *ifp = &sc->arpcom.ac_if; 1106 int i; 1107 1108 sf_stop(sc); 1109 sf_reset(sc); 1110 1111 /* Init all the receive filter registers */ 1112 for (i = SF_RXFILT_PERFECT_BASE; 1113 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1114 csr_write_4(sc, i, 0); 1115 1116 /* Empty stats counter registers. */ 1117 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1118 csr_write_4(sc, SF_STATS_BASE + 1119 (i + sizeof(u_int32_t)), 0); 1120 1121 /* Init our MAC address */ 1122 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1123 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1124 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1125 1126 if (sf_init_rx_ring(sc) == ENOBUFS) { 1127 kprintf("sf%d: initialization failed: no " 1128 "memory for rx buffers\n", sc->sf_unit); 1129 return; 1130 } 1131 1132 sf_init_tx_ring(sc); 1133 1134 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1135 1136 /* If we want promiscuous mode, set the allframes bit. */ 1137 if (ifp->if_flags & IFF_PROMISC) { 1138 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1139 } else { 1140 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1141 } 1142 1143 if (ifp->if_flags & IFF_BROADCAST) { 1144 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1145 } else { 1146 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1147 } 1148 1149 /* 1150 * Load the multicast filter. 1151 */ 1152 sf_setmulti(sc); 1153 1154 /* Init the completion queue indexes */ 1155 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1156 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1157 1158 /* Init the RX completion queue */ 1159 csr_write_4(sc, SF_RXCQ_CTL_1, 1160 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1161 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1162 1163 /* Init RX DMA control. */ 1164 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1165 1166 /* Init the RX buffer descriptor queue. */ 1167 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1168 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1169 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1170 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1171 1172 /* Init the TX completion queue */ 1173 csr_write_4(sc, SF_TXCQ_CTL, 1174 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1175 1176 /* Init the TX buffer descriptor queue. */ 1177 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1178 vtophys(sc->sf_ldata->sf_tx_dlist)); 1179 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1180 csr_write_4(sc, SF_TXDQ_CTL, 1181 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1182 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1183 1184 /* Enable autopadding of short TX frames. */ 1185 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1186 1187 /* Enable interrupts. */ 1188 csr_write_4(sc, SF_IMR, SF_INTRS); 1189 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1190 1191 /* Enable the RX and TX engines. */ 1192 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1193 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1194 1195 /*mii_mediachg(mii);*/ 1196 sf_ifmedia_upd(ifp); 1197 1198 ifp->if_flags |= IFF_RUNNING; 1199 ifq_clr_oactive(&ifp->if_snd); 1200 1201 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc); 1202 } 1203 1204 static int 1205 sf_encap(struct sf_softc *sc, struct sf_tx_bufdesc_type0 *c, 1206 struct mbuf *m_head) 1207 { 1208 int frag = 0; 1209 struct sf_frag *f = NULL; 1210 struct mbuf *m; 1211 1212 for (m = m_head; m != NULL; m = m->m_next) { 1213 if (m->m_len != 0) { 1214 if (frag == SF_MAXFRAGS) 1215 break; 1216 f = &c->sf_frags[frag]; 1217 if (frag == 0) 1218 f->sf_pktlen = m_head->m_pkthdr.len; 1219 f->sf_fraglen = m->m_len; 1220 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1221 frag++; 1222 } 1223 } 1224 /* Caller should make sure that 'm_head' is not excessive fragmented */ 1225 KASSERT(m == NULL, ("too many fragments")); 1226 1227 c->sf_mbuf = m_head; 1228 c->sf_id = SF_TX_BUFDESC_ID; 1229 c->sf_fragcnt = frag; 1230 c->sf_intr = 1; 1231 c->sf_caltcp = 0; 1232 c->sf_crcen = 1; 1233 1234 return(0); 1235 } 1236 1237 static void 1238 sf_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1239 { 1240 struct sf_softc *sc; 1241 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1242 struct mbuf *m_head = NULL, *m_defragged; 1243 int i, txprod, need_trans = 0; 1244 1245 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1246 1247 sc = ifp->if_softc; 1248 1249 if (!sc->sf_link) { 1250 ifq_purge(&ifp->if_snd); 1251 return; 1252 } 1253 1254 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 1255 return; 1256 1257 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1258 i = SF_IDX_HI(txprod) >> 4; 1259 1260 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1261 kprintf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1262 sf_init(sc); 1263 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1264 i = SF_IDX_HI(txprod) >> 4; 1265 } 1266 1267 while (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1268 struct mbuf *m; 1269 int frag; 1270 1271 /* 1272 * Don't get the TX DMA queue get too full. 1273 */ 1274 if (sc->sf_tx_cnt > 64) { 1275 ifq_set_oactive(&ifp->if_snd); 1276 break; 1277 } 1278 #ifdef foo 1279 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1280 ifq_set_oactive(&ifp->if_snd); 1281 break; 1282 } 1283 #endif 1284 1285 m_defragged = NULL; 1286 m_head = ifq_dequeue(&ifp->if_snd); 1287 if (m_head == NULL) 1288 break; 1289 1290 again: 1291 frag = 0; 1292 for (m = m_head; m != NULL; m = m->m_next) 1293 ++frag; 1294 if (frag > SF_MAXFRAGS) { 1295 if (m_defragged != NULL) { 1296 /* 1297 * Even after defragmentation, there 1298 * are still too many fragments, so 1299 * drop this packet. 1300 */ 1301 m_freem(m_head); 1302 continue; 1303 } 1304 1305 m_defragged = m_defrag(m_head, MB_DONTWAIT); 1306 if (m_defragged == NULL) { 1307 m_freem(m_head); 1308 continue; 1309 } 1310 m_head = m_defragged; 1311 1312 /* Recount # of fragments */ 1313 goto again; 1314 } 1315 1316 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1317 sf_encap(sc, cur_tx, m_head); 1318 BPF_MTAP(ifp, cur_tx->sf_mbuf); 1319 1320 SF_INC(i, SF_TX_DLIST_CNT); 1321 sc->sf_tx_cnt++; 1322 need_trans = 1; 1323 } 1324 1325 if (!need_trans) 1326 return; 1327 1328 /* Transmit */ 1329 csr_write_4(sc, SF_TXDQ_PRODIDX, 1330 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1331 ((i << 20) & 0xFFFF0000)); 1332 1333 ifp->if_timer = 5; 1334 } 1335 1336 static void 1337 sf_stop(struct sf_softc *sc) 1338 { 1339 int i; 1340 struct ifnet *ifp; 1341 1342 ifp = &sc->arpcom.ac_if; 1343 1344 callout_stop(&sc->sf_stat_timer); 1345 1346 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1347 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1348 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1349 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1350 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1351 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1352 csr_write_4(sc, SF_TXCQ_CTL, 0); 1353 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1354 csr_write_4(sc, SF_TXDQ_CTL, 0); 1355 sf_reset(sc); 1356 1357 sc->sf_link = 0; 1358 1359 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1360 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1361 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1362 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1363 } 1364 } 1365 1366 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1367 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1368 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1369 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1370 } 1371 } 1372 1373 ifp->if_flags &= ~IFF_RUNNING; 1374 ifq_clr_oactive(&ifp->if_snd); 1375 1376 return; 1377 } 1378 1379 /* 1380 * Note: it is important that this function not be interrupted. We 1381 * use a two-stage register access scheme: if we are interrupted in 1382 * between setting the indirect address register and reading from the 1383 * indirect data register, the contents of the address register could 1384 * be changed out from under us. 1385 */ 1386 static void 1387 sf_stats_update(void *xsc) 1388 { 1389 struct sf_softc *sc = xsc; 1390 struct ifnet *ifp = &sc->arpcom.ac_if; 1391 struct mii_data *mii = device_get_softc(sc->sf_miibus); 1392 struct sf_stats stats; 1393 u_int32_t *ptr; 1394 int i; 1395 1396 lwkt_serialize_enter(ifp->if_serializer); 1397 1398 ptr = (u_int32_t *)&stats; 1399 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1400 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1401 (i + sizeof(u_int32_t))); 1402 1403 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1404 csr_write_4(sc, SF_STATS_BASE + 1405 (i + sizeof(u_int32_t)), 0); 1406 1407 IFNET_STAT_INC(ifp, collisions, stats.sf_tx_single_colls + 1408 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls); 1409 1410 mii_tick(mii); 1411 if (!sc->sf_link) { 1412 mii_pollstat(mii); 1413 if (mii->mii_media_status & IFM_ACTIVE && 1414 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1415 sc->sf_link++; 1416 if (!ifq_is_empty(&ifp->if_snd)) 1417 if_devstart(ifp); 1418 } 1419 } 1420 1421 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc); 1422 1423 lwkt_serialize_exit(ifp->if_serializer); 1424 } 1425 1426 static void 1427 sf_watchdog(struct ifnet *ifp) 1428 { 1429 struct sf_softc *sc; 1430 1431 sc = ifp->if_softc; 1432 1433 IFNET_STAT_INC(ifp, oerrors, 1); 1434 kprintf("sf%d: watchdog timeout\n", sc->sf_unit); 1435 1436 sf_stop(sc); 1437 sf_reset(sc); 1438 sf_init(sc); 1439 1440 if (!ifq_is_empty(&ifp->if_snd)) 1441 if_devstart(ifp); 1442 } 1443 1444 static void 1445 sf_shutdown(device_t dev) 1446 { 1447 struct sf_softc *sc; 1448 struct ifnet *ifp; 1449 1450 sc = device_get_softc(dev); 1451 ifp = &sc->arpcom.ac_if; 1452 lwkt_serialize_enter(ifp->if_serializer); 1453 sf_stop(sc); 1454 lwkt_serialize_exit(ifp->if_serializer); 1455 1456 return; 1457 } 1458