1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $ 33 * $DragonFly: src/sys/dev/netif/sf/if_sf.c,v 1.27 2005/12/31 14:08:00 sephe Exp $ 34 */ 35 36 /* 37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 38 * Programming manual is available from: 39 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Department of Electical Engineering 43 * Columbia University, New York City 44 */ 45 46 /* 47 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 48 * controller designed with flexibility and reducing CPU load in mind. 49 * The Starfire offers high and low priority buffer queues, a 50 * producer/consumer index mechanism and several different buffer 51 * queue and completion queue descriptor types. Any one of a number 52 * of different driver designs can be used, depending on system and 53 * OS requirements. This driver makes use of type0 transmit frame 54 * descriptors (since BSD fragments packets across an mbuf chain) 55 * and two RX buffer queues prioritized on size (one queue for small 56 * frames that will fit into a single mbuf, another with full size 57 * mbuf clusters for everything else). The producer/consumer indexes 58 * and completion queues are also used. 59 * 60 * One downside to the Starfire has to do with alignment: buffer 61 * queues must be aligned on 256-byte boundaries, and receive buffers 62 * must be aligned on longword boundaries. The receive buffer alignment 63 * causes problems on the Alpha platform, where the packet payload 64 * should be longword aligned. There is no simple way around this. 65 * 66 * For receive filtering, the Starfire offers 16 perfect filter slots 67 * and a 512-bit hash table. 68 * 69 * The Starfire has no internal transceiver, relying instead on an 70 * external MII-based transceiver. Accessing registers on external 71 * PHYs is done through a special register map rather than with the 72 * usual bitbang MDIO method. 73 * 74 * Acesssing the registers on the Starfire is a little tricky. The 75 * Starfire has a 512K internal register space. When programmed for 76 * PCI memory mapped mode, the entire register space can be accessed 77 * directly. However in I/O space mode, only 256 bytes are directly 78 * mapped into PCI I/O space. The other registers can be accessed 79 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 80 * registers inside the 256-byte I/O window. 81 */ 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/sockio.h> 86 #include <sys/mbuf.h> 87 #include <sys/malloc.h> 88 #include <sys/kernel.h> 89 #include <sys/socket.h> 90 #include <sys/serialize.h> 91 92 #include <sys/thread2.h> 93 94 #include <net/if.h> 95 #include <net/ifq_var.h> 96 #include <net/if_arp.h> 97 #include <net/ethernet.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 101 #include <net/bpf.h> 102 103 #include <vm/vm.h> /* for vtophys */ 104 #include <vm/pmap.h> /* for vtophys */ 105 #include <machine/clock.h> /* for DELAY */ 106 #include <machine/bus_pio.h> 107 #include <machine/bus_memio.h> 108 #include <machine/bus.h> 109 #include <machine/resource.h> 110 #include <sys/bus.h> 111 #include <sys/rman.h> 112 113 #include "../mii_layer/mii.h" 114 #include "../mii_layer/miivar.h" 115 116 /* "controller miibus0" required. See GENERIC if you get errors here. */ 117 #include "miibus_if.h" 118 119 #include <bus/pci/pcireg.h> 120 #include <bus/pci/pcivar.h> 121 122 #define SF_USEIOSPACE 123 124 #include "if_sfreg.h" 125 126 static struct sf_type sf_devs[] = { 127 { AD_VENDORID, AD_DEVICEID_STARFIRE, 128 "Adaptec AIC-6915 10/100BaseTX" }, 129 { 0, 0, NULL } 130 }; 131 132 static int sf_probe (device_t); 133 static int sf_attach (device_t); 134 static int sf_detach (device_t); 135 static void sf_intr (void *); 136 static void sf_stats_update (void *); 137 static void sf_rxeof (struct sf_softc *); 138 static void sf_txeof (struct sf_softc *); 139 static int sf_encap (struct sf_softc *, 140 struct sf_tx_bufdesc_type0 *, 141 struct mbuf *); 142 static void sf_start (struct ifnet *); 143 static int sf_ioctl (struct ifnet *, u_long, caddr_t, 144 struct ucred *); 145 static void sf_init (void *); 146 static void sf_stop (struct sf_softc *); 147 static void sf_watchdog (struct ifnet *); 148 static void sf_shutdown (device_t); 149 static int sf_ifmedia_upd (struct ifnet *); 150 static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 151 static void sf_reset (struct sf_softc *); 152 static int sf_init_rx_ring (struct sf_softc *); 153 static void sf_init_tx_ring (struct sf_softc *); 154 static int sf_newbuf (struct sf_softc *, 155 struct sf_rx_bufdesc_type0 *, 156 struct mbuf *); 157 static void sf_setmulti (struct sf_softc *); 158 static int sf_setperf (struct sf_softc *, int, caddr_t); 159 static int sf_sethash (struct sf_softc *, caddr_t, int); 160 #ifdef notdef 161 static int sf_setvlan (struct sf_softc *, int, u_int32_t); 162 #endif 163 164 static u_int8_t sf_read_eeprom (struct sf_softc *, int); 165 static u_int32_t sf_calchash (caddr_t); 166 167 static int sf_miibus_readreg (device_t, int, int); 168 static int sf_miibus_writereg (device_t, int, int, int); 169 static void sf_miibus_statchg (device_t); 170 171 static u_int32_t csr_read_4 (struct sf_softc *, int); 172 static void csr_write_4 (struct sf_softc *, int, u_int32_t); 173 static void sf_txthresh_adjust (struct sf_softc *); 174 175 #ifdef SF_USEIOSPACE 176 #define SF_RES SYS_RES_IOPORT 177 #define SF_RID SF_PCI_LOIO 178 #else 179 #define SF_RES SYS_RES_MEMORY 180 #define SF_RID SF_PCI_LOMEM 181 #endif 182 183 static device_method_t sf_methods[] = { 184 /* Device interface */ 185 DEVMETHOD(device_probe, sf_probe), 186 DEVMETHOD(device_attach, sf_attach), 187 DEVMETHOD(device_detach, sf_detach), 188 DEVMETHOD(device_shutdown, sf_shutdown), 189 190 /* bus interface */ 191 DEVMETHOD(bus_print_child, bus_generic_print_child), 192 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 193 194 /* MII interface */ 195 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 196 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 197 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 198 199 { 0, 0 } 200 }; 201 202 static driver_t sf_driver = { 203 "sf", 204 sf_methods, 205 sizeof(struct sf_softc), 206 }; 207 208 static devclass_t sf_devclass; 209 210 DECLARE_DUMMY_MODULE(if_sf); 211 DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 212 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 213 214 #define SF_SETBIT(sc, reg, x) \ 215 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 216 217 #define SF_CLRBIT(sc, reg, x) \ 218 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 219 220 static u_int32_t 221 csr_read_4(struct sf_softc *sc, int reg) 222 { 223 u_int32_t val; 224 225 #ifdef SF_USEIOSPACE 226 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 227 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 228 #else 229 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 230 #endif 231 232 return(val); 233 } 234 235 static u_int8_t 236 sf_read_eeprom(struct sf_softc *sc, int reg) 237 { 238 u_int8_t val; 239 240 val = (csr_read_4(sc, SF_EEADDR_BASE + 241 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 242 243 return(val); 244 } 245 246 static void 247 csr_write_4(struct sf_softc *sc, int reg, u_int32_t val) 248 { 249 #ifdef SF_USEIOSPACE 250 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 251 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 252 #else 253 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 254 #endif 255 return; 256 } 257 258 static u_int32_t 259 sf_calchash(caddr_t addr) 260 { 261 u_int32_t crc, carry; 262 int i, j; 263 u_int8_t c; 264 265 /* Compute CRC for the address value. */ 266 crc = 0xFFFFFFFF; /* initial value */ 267 268 for (i = 0; i < 6; i++) { 269 c = *(addr + i); 270 for (j = 0; j < 8; j++) { 271 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 272 crc <<= 1; 273 c >>= 1; 274 if (carry) 275 crc = (crc ^ 0x04c11db6) | carry; 276 } 277 } 278 279 /* return the filter bit position */ 280 return(crc >> 23 & 0x1FF); 281 } 282 283 /* 284 * Copy the address 'mac' into the perfect RX filter entry at 285 * offset 'idx.' The perfect filter only has 16 entries so do 286 * some sanity tests. 287 */ 288 static int 289 sf_setperf(struct sf_softc *sc, int idx, caddr_t mac) 290 { 291 u_int16_t *p; 292 293 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 294 return(EINVAL); 295 296 if (mac == NULL) 297 return(EINVAL); 298 299 p = (u_int16_t *)mac; 300 301 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 302 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 303 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 304 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 305 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 306 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 307 308 return(0); 309 } 310 311 /* 312 * Set the bit in the 512-bit hash table that corresponds to the 313 * specified mac address 'mac.' If 'prio' is nonzero, update the 314 * priority hash table instead of the filter hash table. 315 */ 316 static int 317 sf_sethash(struct sf_softc *sc, caddr_t mac, int prio) 318 { 319 u_int32_t h = 0; 320 321 if (mac == NULL) 322 return(EINVAL); 323 324 h = sf_calchash(mac); 325 326 if (prio) { 327 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 328 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 329 } else { 330 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 331 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 332 } 333 334 return(0); 335 } 336 337 #ifdef notdef 338 /* 339 * Set a VLAN tag in the receive filter. 340 */ 341 static int 342 sf_setvlan(struct sf_softc *sc, int idx, u_int32_t vlan) 343 { 344 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 345 return(EINVAL); 346 347 csr_write_4(sc, SF_RXFILT_HASH_BASE + 348 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 349 350 return(0); 351 } 352 #endif 353 354 static int 355 sf_miibus_readreg(device_t dev, int phy, int reg) 356 { 357 struct sf_softc *sc; 358 int i; 359 u_int32_t val = 0; 360 361 sc = device_get_softc(dev); 362 363 for (i = 0; i < SF_TIMEOUT; i++) { 364 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 365 if (val & SF_MII_DATAVALID) 366 break; 367 } 368 369 if (i == SF_TIMEOUT) 370 return(0); 371 372 if ((val & 0x0000FFFF) == 0xFFFF) 373 return(0); 374 375 return(val & 0x0000FFFF); 376 } 377 378 static int 379 sf_miibus_writereg(device_t dev, int phy, int reg, int val) 380 { 381 struct sf_softc *sc; 382 int i; 383 int busy; 384 385 sc = device_get_softc(dev); 386 387 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 388 389 for (i = 0; i < SF_TIMEOUT; i++) { 390 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 391 if (!(busy & SF_MII_BUSY)) 392 break; 393 } 394 395 return(0); 396 } 397 398 static void 399 sf_miibus_statchg(device_t dev) 400 { 401 struct sf_softc *sc; 402 struct mii_data *mii; 403 404 sc = device_get_softc(dev); 405 mii = device_get_softc(sc->sf_miibus); 406 407 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 408 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 409 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 410 } else { 411 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 412 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 413 } 414 415 return; 416 } 417 418 static void 419 sf_setmulti(struct sf_softc *sc) 420 { 421 struct ifnet *ifp; 422 int i; 423 struct ifmultiaddr *ifma; 424 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 425 426 ifp = &sc->arpcom.ac_if; 427 428 /* First zot all the existing filters. */ 429 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 430 sf_setperf(sc, i, (char *)&dummy); 431 for (i = SF_RXFILT_HASH_BASE; 432 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 433 csr_write_4(sc, i, 0); 434 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 435 436 /* Now program new ones. */ 437 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 438 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 439 } else { 440 i = 1; 441 /* First find the tail of the list. */ 442 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 443 ifma = ifma->ifma_link.le_next) { 444 if (ifma->ifma_link.le_next == NULL) 445 break; 446 } 447 /* Now traverse the list backwards. */ 448 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 449 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 450 if (ifma->ifma_addr->sa_family != AF_LINK) 451 continue; 452 /* 453 * Program the first 15 multicast groups 454 * into the perfect filter. For all others, 455 * use the hash table. 456 */ 457 if (i < SF_RXFILT_PERFECT_CNT) { 458 sf_setperf(sc, i, 459 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 460 i++; 461 continue; 462 } 463 464 sf_sethash(sc, 465 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 466 } 467 } 468 469 return; 470 } 471 472 /* 473 * Set media options. 474 */ 475 static int 476 sf_ifmedia_upd(struct ifnet *ifp) 477 { 478 struct sf_softc *sc; 479 struct mii_data *mii; 480 481 sc = ifp->if_softc; 482 mii = device_get_softc(sc->sf_miibus); 483 sc->sf_link = 0; 484 if (mii->mii_instance) { 485 struct mii_softc *miisc; 486 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 487 miisc = LIST_NEXT(miisc, mii_list)) 488 mii_phy_reset(miisc); 489 } 490 mii_mediachg(mii); 491 492 return(0); 493 } 494 495 /* 496 * Report current media status. 497 */ 498 static void 499 sf_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 500 { 501 struct sf_softc *sc; 502 struct mii_data *mii; 503 504 sc = ifp->if_softc; 505 mii = device_get_softc(sc->sf_miibus); 506 507 mii_pollstat(mii); 508 ifmr->ifm_active = mii->mii_media_active; 509 ifmr->ifm_status = mii->mii_media_status; 510 511 return; 512 } 513 514 static int 515 sf_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 516 { 517 struct sf_softc *sc = ifp->if_softc; 518 struct ifreq *ifr = (struct ifreq *) data; 519 struct mii_data *mii; 520 int error = 0; 521 522 switch(command) { 523 case SIOCSIFFLAGS: 524 if (ifp->if_flags & IFF_UP) { 525 if (ifp->if_flags & IFF_RUNNING && 526 ifp->if_flags & IFF_PROMISC && 527 !(sc->sf_if_flags & IFF_PROMISC)) { 528 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 529 } else if (ifp->if_flags & IFF_RUNNING && 530 !(ifp->if_flags & IFF_PROMISC) && 531 sc->sf_if_flags & IFF_PROMISC) { 532 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 533 } else if (!(ifp->if_flags & IFF_RUNNING)) 534 sf_init(sc); 535 } else { 536 if (ifp->if_flags & IFF_RUNNING) 537 sf_stop(sc); 538 } 539 sc->sf_if_flags = ifp->if_flags; 540 error = 0; 541 break; 542 case SIOCADDMULTI: 543 case SIOCDELMULTI: 544 sf_setmulti(sc); 545 error = 0; 546 break; 547 case SIOCGIFMEDIA: 548 case SIOCSIFMEDIA: 549 mii = device_get_softc(sc->sf_miibus); 550 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 551 break; 552 default: 553 error = ether_ioctl(ifp, command, data); 554 break; 555 } 556 557 return(error); 558 } 559 560 static void 561 sf_reset(struct sf_softc *sc) 562 { 563 int i; 564 565 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 566 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 567 DELAY(1000); 568 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 569 570 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 571 572 for (i = 0; i < SF_TIMEOUT; i++) { 573 DELAY(10); 574 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 575 break; 576 } 577 578 if (i == SF_TIMEOUT) 579 printf("sf%d: reset never completed!\n", sc->sf_unit); 580 581 /* Wait a little while for the chip to get its brains in order. */ 582 DELAY(1000); 583 return; 584 } 585 586 /* 587 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 588 * IDs against our list and return a device name if we find a match. 589 * We also check the subsystem ID so that we can identify exactly which 590 * NIC has been found, if possible. 591 */ 592 static int 593 sf_probe(device_t dev) 594 { 595 struct sf_type *t; 596 597 t = sf_devs; 598 599 while(t->sf_name != NULL) { 600 if ((pci_get_vendor(dev) == t->sf_vid) && 601 (pci_get_device(dev) == t->sf_did)) { 602 switch((pci_read_config(dev, 603 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 604 case AD_SUBSYSID_62011_REV0: 605 case AD_SUBSYSID_62011_REV1: 606 device_set_desc(dev, 607 "Adaptec ANA-62011 10/100BaseTX"); 608 return(0); 609 break; 610 case AD_SUBSYSID_62022: 611 device_set_desc(dev, 612 "Adaptec ANA-62022 10/100BaseTX"); 613 return(0); 614 break; 615 case AD_SUBSYSID_62044_REV0: 616 case AD_SUBSYSID_62044_REV1: 617 device_set_desc(dev, 618 "Adaptec ANA-62044 10/100BaseTX"); 619 return(0); 620 break; 621 case AD_SUBSYSID_62020: 622 device_set_desc(dev, 623 "Adaptec ANA-62020 10/100BaseFX"); 624 return(0); 625 break; 626 case AD_SUBSYSID_69011: 627 device_set_desc(dev, 628 "Adaptec ANA-69011 10/100BaseTX"); 629 return(0); 630 break; 631 default: 632 device_set_desc(dev, t->sf_name); 633 return(0); 634 break; 635 } 636 } 637 t++; 638 } 639 640 return(ENXIO); 641 } 642 643 /* 644 * Attach the interface. Allocate softc structures, do ifmedia 645 * setup and ethernet/BPF attach. 646 */ 647 static int 648 sf_attach(device_t dev) 649 { 650 int i; 651 u_int32_t command; 652 struct sf_softc *sc; 653 struct ifnet *ifp; 654 int unit, rid, error = 0; 655 656 sc = device_get_softc(dev); 657 unit = device_get_unit(dev); 658 659 /* 660 * Handle power management nonsense. 661 */ 662 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 663 if (command == 0x01) { 664 665 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 666 if (command & SF_PSTATE_MASK) { 667 u_int32_t iobase, membase, irq; 668 669 /* Save important PCI config data. */ 670 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 671 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 672 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 673 674 /* Reset the power state. */ 675 printf("sf%d: chip is in D%d power mode " 676 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 677 command &= 0xFFFFFFFC; 678 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 679 680 /* Restore PCI config data. */ 681 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 682 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 683 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 684 } 685 } 686 687 /* 688 * Map control/status registers. 689 */ 690 command = pci_read_config(dev, PCIR_COMMAND, 4); 691 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 692 pci_write_config(dev, PCIR_COMMAND, command, 4); 693 command = pci_read_config(dev, PCIR_COMMAND, 4); 694 695 #ifdef SF_USEIOSPACE 696 if (!(command & PCIM_CMD_PORTEN)) { 697 printf("sf%d: failed to enable I/O ports!\n", unit); 698 error = ENXIO; 699 return(error); 700 } 701 #else 702 if (!(command & PCIM_CMD_MEMEN)) { 703 printf("sf%d: failed to enable memory mapping!\n", unit); 704 error = ENXIO; 705 return(error); 706 } 707 #endif 708 709 rid = SF_RID; 710 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE); 711 712 if (sc->sf_res == NULL) { 713 printf ("sf%d: couldn't map ports\n", unit); 714 error = ENXIO; 715 return(error); 716 } 717 718 sc->sf_btag = rman_get_bustag(sc->sf_res); 719 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 720 721 /* Allocate interrupt */ 722 rid = 0; 723 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 724 RF_SHAREABLE | RF_ACTIVE); 725 726 if (sc->sf_irq == NULL) { 727 printf("sf%d: couldn't map interrupt\n", unit); 728 error = ENXIO; 729 goto fail; 730 } 731 732 callout_init(&sc->sf_stat_timer); 733 734 /* Reset the adapter. */ 735 sf_reset(sc); 736 737 /* 738 * Get station address from the EEPROM. 739 */ 740 for (i = 0; i < ETHER_ADDR_LEN; i++) 741 sc->arpcom.ac_enaddr[i] = 742 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 743 744 sc->sf_unit = unit; 745 746 /* Allocate the descriptor queues. */ 747 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 748 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 749 750 if (sc->sf_ldata == NULL) { 751 printf("sf%d: no memory for list buffers!\n", unit); 752 error = ENXIO; 753 goto fail; 754 } 755 756 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 757 758 /* Do MII setup. */ 759 if (mii_phy_probe(dev, &sc->sf_miibus, 760 sf_ifmedia_upd, sf_ifmedia_sts)) { 761 printf("sf%d: MII without any phy!\n", sc->sf_unit); 762 error = ENXIO; 763 goto fail; 764 } 765 766 ifp = &sc->arpcom.ac_if; 767 ifp->if_softc = sc; 768 if_initname(ifp, "sf", unit); 769 ifp->if_mtu = ETHERMTU; 770 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 771 ifp->if_ioctl = sf_ioctl; 772 ifp->if_start = sf_start; 773 ifp->if_watchdog = sf_watchdog; 774 ifp->if_init = sf_init; 775 ifp->if_baudrate = 10000000; 776 ifq_set_maxlen(&ifp->if_snd, SF_TX_DLIST_CNT - 1); 777 ifq_set_ready(&ifp->if_snd); 778 779 /* 780 * Call MI attach routine. 781 */ 782 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 783 784 error = bus_setup_intr(dev, sc->sf_irq, INTR_NETSAFE, 785 sf_intr, sc, &sc->sf_intrhand, 786 ifp->if_serializer); 787 788 if (error) { 789 ether_ifdetach(ifp); 790 device_printf(dev, "couldn't set up irq\n"); 791 goto fail; 792 } 793 794 return(0); 795 796 fail: 797 sf_detach(dev); 798 return(error); 799 } 800 801 static int 802 sf_detach(device_t dev) 803 { 804 struct sf_softc *sc = device_get_softc(dev); 805 struct ifnet *ifp = &sc->arpcom.ac_if; 806 807 if (device_is_attached(dev)) { 808 lwkt_serialize_enter(ifp->if_serializer); 809 sf_stop(sc); 810 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 811 lwkt_serialize_exit(ifp->if_serializer); 812 813 ether_ifdetach(ifp); 814 } 815 816 if (sc->sf_miibus) 817 device_delete_child(dev, sc->sf_miibus); 818 bus_generic_detach(dev); 819 820 if (sc->sf_irq) 821 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 822 if(sc->sf_res) 823 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 824 825 if (sc->sf_ldata) { 826 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), 827 M_DEVBUF); 828 } 829 830 return(0); 831 } 832 833 static int 834 sf_init_rx_ring(struct sf_softc *sc) 835 { 836 struct sf_list_data *ld; 837 int i; 838 839 ld = sc->sf_ldata; 840 841 bzero((char *)ld->sf_rx_dlist_big, 842 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 843 bzero((char *)ld->sf_rx_clist, 844 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 845 846 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 847 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 848 return(ENOBUFS); 849 } 850 851 return(0); 852 } 853 854 static void 855 sf_init_tx_ring(struct sf_softc *sc) 856 { 857 struct sf_list_data *ld; 858 int i; 859 860 ld = sc->sf_ldata; 861 862 bzero((char *)ld->sf_tx_dlist, 863 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 864 bzero((char *)ld->sf_tx_clist, 865 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 866 867 for (i = 0; i < SF_TX_DLIST_CNT; i++) 868 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 869 for (i = 0; i < SF_TX_CLIST_CNT; i++) 870 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 871 872 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 873 sc->sf_tx_cnt = 0; 874 875 return; 876 } 877 878 static int 879 sf_newbuf(struct sf_softc *sc, struct sf_rx_bufdesc_type0 *c, 880 struct mbuf *m) 881 { 882 struct mbuf *m_new = NULL; 883 884 if (m == NULL) { 885 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 886 if (m_new == NULL) 887 return(ENOBUFS); 888 889 MCLGET(m_new, MB_DONTWAIT); 890 if (!(m_new->m_flags & M_EXT)) { 891 m_freem(m_new); 892 return(ENOBUFS); 893 } 894 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 895 } else { 896 m_new = m; 897 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 898 m_new->m_data = m_new->m_ext.ext_buf; 899 } 900 901 m_adj(m_new, sizeof(u_int64_t)); 902 903 c->sf_mbuf = m_new; 904 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 905 c->sf_valid = 1; 906 907 return(0); 908 } 909 910 /* 911 * The starfire is programmed to use 'normal' mode for packet reception, 912 * which means we use the consumer/producer model for both the buffer 913 * descriptor queue and the completion descriptor queue. The only problem 914 * with this is that it involves a lot of register accesses: we have to 915 * read the RX completion consumer and producer indexes and the RX buffer 916 * producer index, plus the RX completion consumer and RX buffer producer 917 * indexes have to be updated. It would have been easier if Adaptec had 918 * put each index in a separate register, especially given that the damn 919 * NIC has a 512K register space. 920 * 921 * In spite of all the lovely features that Adaptec crammed into the 6915, 922 * it is marred by one truly stupid design flaw, which is that receive 923 * buffer addresses must be aligned on a longword boundary. This forces 924 * the packet payload to be unaligned, which is suboptimal on the x86 and 925 * completely unuseable on the Alpha. Our only recourse is to copy received 926 * packets into properly aligned buffers before handing them off. 927 */ 928 929 static void 930 sf_rxeof(struct sf_softc *sc) 931 { 932 struct mbuf *m; 933 struct ifnet *ifp; 934 struct sf_rx_bufdesc_type0 *desc; 935 struct sf_rx_cmpdesc_type3 *cur_rx; 936 u_int32_t rxcons, rxprod; 937 int cmpprodidx, cmpconsidx, bufprodidx; 938 939 ifp = &sc->arpcom.ac_if; 940 941 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 942 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 943 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 944 cmpconsidx = SF_IDX_LO(rxcons); 945 bufprodidx = SF_IDX_LO(rxprod); 946 947 while (cmpconsidx != cmpprodidx) { 948 struct mbuf *m0; 949 950 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 951 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 952 m = desc->sf_mbuf; 953 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 954 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 955 956 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 957 ifp->if_ierrors++; 958 sf_newbuf(sc, desc, m); 959 continue; 960 } 961 962 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 963 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 964 sf_newbuf(sc, desc, m); 965 if (m0 == NULL) { 966 ifp->if_ierrors++; 967 continue; 968 } 969 m_adj(m0, ETHER_ALIGN); 970 m = m0; 971 972 ifp->if_ipackets++; 973 974 ifp->if_input(ifp, m); 975 } 976 977 csr_write_4(sc, SF_CQ_CONSIDX, 978 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 979 csr_write_4(sc, SF_RXDQ_PTR_Q1, 980 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 981 982 return; 983 } 984 985 /* 986 * Read the transmit status from the completion queue and release 987 * mbufs. Note that the buffer descriptor index in the completion 988 * descriptor is an offset from the start of the transmit buffer 989 * descriptor list in bytes. This is important because the manual 990 * gives the impression that it should match the producer/consumer 991 * index, which is the offset in 8 byte blocks. 992 */ 993 static void 994 sf_txeof(struct sf_softc *sc) 995 { 996 int txcons, cmpprodidx, cmpconsidx; 997 struct sf_tx_cmpdesc_type1 *cur_cmp; 998 struct sf_tx_bufdesc_type0 *cur_tx; 999 struct ifnet *ifp; 1000 1001 ifp = &sc->arpcom.ac_if; 1002 1003 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1004 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1005 cmpconsidx = SF_IDX_HI(txcons); 1006 1007 while (cmpconsidx != cmpprodidx) { 1008 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1009 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1010 1011 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1012 ifp->if_opackets++; 1013 else { 1014 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1015 sf_txthresh_adjust(sc); 1016 ifp->if_oerrors++; 1017 } 1018 1019 sc->sf_tx_cnt--; 1020 if (cur_tx->sf_mbuf != NULL) { 1021 m_freem(cur_tx->sf_mbuf); 1022 cur_tx->sf_mbuf = NULL; 1023 } else 1024 break; 1025 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1026 } 1027 1028 ifp->if_timer = 0; 1029 ifp->if_flags &= ~IFF_OACTIVE; 1030 1031 csr_write_4(sc, SF_CQ_CONSIDX, 1032 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1033 ((cmpconsidx << 16) & 0xFFFF0000)); 1034 1035 return; 1036 } 1037 1038 static void 1039 sf_txthresh_adjust(struct sf_softc *sc) 1040 { 1041 u_int32_t txfctl; 1042 u_int8_t txthresh; 1043 1044 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1045 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1046 if (txthresh < 0xFF) { 1047 txthresh++; 1048 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1049 txfctl |= txthresh; 1050 #ifdef DIAGNOSTIC 1051 printf("sf%d: tx underrun, increasing " 1052 "tx threshold to %d bytes\n", 1053 sc->sf_unit, txthresh * 4); 1054 #endif 1055 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1056 } 1057 1058 return; 1059 } 1060 1061 static void 1062 sf_intr(void *arg) 1063 { 1064 struct sf_softc *sc; 1065 struct ifnet *ifp; 1066 u_int32_t status; 1067 1068 sc = arg; 1069 ifp = &sc->arpcom.ac_if; 1070 1071 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) 1072 return; 1073 1074 /* Disable interrupts. */ 1075 csr_write_4(sc, SF_IMR, 0x00000000); 1076 1077 for (;;) { 1078 status = csr_read_4(sc, SF_ISR); 1079 if (status) 1080 csr_write_4(sc, SF_ISR, status); 1081 1082 if (!(status & SF_INTRS)) 1083 break; 1084 1085 if (status & SF_ISR_RXDQ1_DMADONE) 1086 sf_rxeof(sc); 1087 1088 if (status & SF_ISR_TX_TXDONE || 1089 status & SF_ISR_TX_DMADONE || 1090 status & SF_ISR_TX_QUEUEDONE) 1091 sf_txeof(sc); 1092 1093 if (status & SF_ISR_TX_LOFIFO) 1094 sf_txthresh_adjust(sc); 1095 1096 if (status & SF_ISR_ABNORMALINTR) { 1097 if (status & SF_ISR_STATSOFLOW) { 1098 callout_stop(&sc->sf_stat_timer); 1099 sf_stats_update(sc); 1100 } else 1101 sf_init(sc); 1102 } 1103 } 1104 1105 /* Re-enable interrupts. */ 1106 csr_write_4(sc, SF_IMR, SF_INTRS); 1107 1108 if (!ifq_is_empty(&ifp->if_snd)) 1109 sf_start(ifp); 1110 1111 return; 1112 } 1113 1114 static void 1115 sf_init(void *xsc) 1116 { 1117 struct sf_softc *sc = xsc; 1118 struct ifnet *ifp = &sc->arpcom.ac_if; 1119 int i; 1120 1121 sf_stop(sc); 1122 sf_reset(sc); 1123 1124 /* Init all the receive filter registers */ 1125 for (i = SF_RXFILT_PERFECT_BASE; 1126 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1127 csr_write_4(sc, i, 0); 1128 1129 /* Empty stats counter registers. */ 1130 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1131 csr_write_4(sc, SF_STATS_BASE + 1132 (i + sizeof(u_int32_t)), 0); 1133 1134 /* Init our MAC address */ 1135 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1136 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1137 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1138 1139 if (sf_init_rx_ring(sc) == ENOBUFS) { 1140 printf("sf%d: initialization failed: no " 1141 "memory for rx buffers\n", sc->sf_unit); 1142 return; 1143 } 1144 1145 sf_init_tx_ring(sc); 1146 1147 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1148 1149 /* If we want promiscuous mode, set the allframes bit. */ 1150 if (ifp->if_flags & IFF_PROMISC) { 1151 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1152 } else { 1153 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1154 } 1155 1156 if (ifp->if_flags & IFF_BROADCAST) { 1157 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1158 } else { 1159 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1160 } 1161 1162 /* 1163 * Load the multicast filter. 1164 */ 1165 sf_setmulti(sc); 1166 1167 /* Init the completion queue indexes */ 1168 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1169 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1170 1171 /* Init the RX completion queue */ 1172 csr_write_4(sc, SF_RXCQ_CTL_1, 1173 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1174 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1175 1176 /* Init RX DMA control. */ 1177 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1178 1179 /* Init the RX buffer descriptor queue. */ 1180 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1181 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1182 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1183 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1184 1185 /* Init the TX completion queue */ 1186 csr_write_4(sc, SF_TXCQ_CTL, 1187 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1188 1189 /* Init the TX buffer descriptor queue. */ 1190 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1191 vtophys(sc->sf_ldata->sf_tx_dlist)); 1192 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1193 csr_write_4(sc, SF_TXDQ_CTL, 1194 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1195 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1196 1197 /* Enable autopadding of short TX frames. */ 1198 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1199 1200 /* Enable interrupts. */ 1201 csr_write_4(sc, SF_IMR, SF_INTRS); 1202 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1203 1204 /* Enable the RX and TX engines. */ 1205 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1206 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1207 1208 /*mii_mediachg(mii);*/ 1209 sf_ifmedia_upd(ifp); 1210 1211 ifp->if_flags |= IFF_RUNNING; 1212 ifp->if_flags &= ~IFF_OACTIVE; 1213 1214 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc); 1215 } 1216 1217 static int 1218 sf_encap(struct sf_softc *sc, struct sf_tx_bufdesc_type0 *c, 1219 struct mbuf *m_head) 1220 { 1221 int frag = 0; 1222 struct sf_frag *f = NULL; 1223 struct mbuf *m; 1224 1225 m = m_head; 1226 1227 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1228 if (m->m_len != 0) { 1229 if (frag == SF_MAXFRAGS) 1230 break; 1231 f = &c->sf_frags[frag]; 1232 if (frag == 0) 1233 f->sf_pktlen = m_head->m_pkthdr.len; 1234 f->sf_fraglen = m->m_len; 1235 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1236 frag++; 1237 } 1238 } 1239 1240 if (m != NULL) { 1241 struct mbuf *m_new = NULL; 1242 1243 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1244 if (m_new == NULL) { 1245 printf("sf%d: no memory for tx list", sc->sf_unit); 1246 return(1); 1247 } 1248 1249 if (m_head->m_pkthdr.len > MHLEN) { 1250 MCLGET(m_new, MB_DONTWAIT); 1251 if (!(m_new->m_flags & M_EXT)) { 1252 m_freem(m_new); 1253 printf("sf%d: no memory for tx list", 1254 sc->sf_unit); 1255 return(1); 1256 } 1257 } 1258 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1259 mtod(m_new, caddr_t)); 1260 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1261 m_freem(m_head); 1262 m_head = m_new; 1263 f = &c->sf_frags[0]; 1264 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1265 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1266 frag = 1; 1267 } 1268 1269 c->sf_mbuf = m_head; 1270 c->sf_id = SF_TX_BUFDESC_ID; 1271 c->sf_fragcnt = frag; 1272 c->sf_intr = 1; 1273 c->sf_caltcp = 0; 1274 c->sf_crcen = 1; 1275 1276 return(0); 1277 } 1278 1279 static void 1280 sf_start(struct ifnet *ifp) 1281 { 1282 struct sf_softc *sc; 1283 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1284 struct mbuf *m_head = NULL; 1285 int i, txprod; 1286 1287 sc = ifp->if_softc; 1288 1289 if (!sc->sf_link) 1290 return; 1291 1292 if (ifp->if_flags & IFF_OACTIVE) 1293 return; 1294 1295 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1296 i = SF_IDX_HI(txprod) >> 4; 1297 1298 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1299 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1300 sf_init(sc); 1301 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1302 i = SF_IDX_HI(txprod) >> 4; 1303 } 1304 1305 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1306 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1307 ifp->if_flags |= IFF_OACTIVE; 1308 cur_tx = NULL; 1309 break; 1310 } 1311 m_head = ifq_poll(&ifp->if_snd); 1312 if (m_head == NULL) 1313 break; 1314 1315 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1316 if (sf_encap(sc, cur_tx, m_head)) { 1317 ifp->if_flags |= IFF_OACTIVE; 1318 cur_tx = NULL; 1319 break; 1320 } 1321 ifq_dequeue(&ifp->if_snd, m_head); 1322 BPF_MTAP(ifp, cur_tx->sf_mbuf); 1323 1324 SF_INC(i, SF_TX_DLIST_CNT); 1325 sc->sf_tx_cnt++; 1326 /* 1327 * Don't get the TX DMA queue get too full. 1328 */ 1329 if (sc->sf_tx_cnt > 64) 1330 break; 1331 } 1332 1333 if (cur_tx == NULL) 1334 return; 1335 1336 /* Transmit */ 1337 csr_write_4(sc, SF_TXDQ_PRODIDX, 1338 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1339 ((i << 20) & 0xFFFF0000)); 1340 1341 ifp->if_timer = 5; 1342 1343 return; 1344 } 1345 1346 static void 1347 sf_stop(struct sf_softc *sc) 1348 { 1349 int i; 1350 struct ifnet *ifp; 1351 1352 ifp = &sc->arpcom.ac_if; 1353 1354 callout_stop(&sc->sf_stat_timer); 1355 1356 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1357 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1358 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1359 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1360 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1361 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1362 csr_write_4(sc, SF_TXCQ_CTL, 0); 1363 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1364 csr_write_4(sc, SF_TXDQ_CTL, 0); 1365 sf_reset(sc); 1366 1367 sc->sf_link = 0; 1368 1369 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1370 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1371 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1372 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1373 } 1374 } 1375 1376 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1377 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1378 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1379 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1380 } 1381 } 1382 1383 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1384 1385 return; 1386 } 1387 1388 /* 1389 * Note: it is important that this function not be interrupted. We 1390 * use a two-stage register access scheme: if we are interrupted in 1391 * between setting the indirect address register and reading from the 1392 * indirect data register, the contents of the address register could 1393 * be changed out from under us. 1394 */ 1395 static void 1396 sf_stats_update(void *xsc) 1397 { 1398 struct sf_softc *sc = xsc; 1399 struct ifnet *ifp = &sc->arpcom.ac_if; 1400 struct mii_data *mii = device_get_softc(sc->sf_miibus); 1401 struct sf_stats stats; 1402 u_int32_t *ptr; 1403 int i; 1404 1405 lwkt_serialize_enter(ifp->if_serializer); 1406 1407 ptr = (u_int32_t *)&stats; 1408 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1409 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1410 (i + sizeof(u_int32_t))); 1411 1412 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1413 csr_write_4(sc, SF_STATS_BASE + 1414 (i + sizeof(u_int32_t)), 0); 1415 1416 ifp->if_collisions += stats.sf_tx_single_colls + 1417 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1418 1419 mii_tick(mii); 1420 if (!sc->sf_link) { 1421 mii_pollstat(mii); 1422 if (mii->mii_media_status & IFM_ACTIVE && 1423 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1424 sc->sf_link++; 1425 if (!ifq_is_empty(&ifp->if_snd)) 1426 sf_start(ifp); 1427 } 1428 1429 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc); 1430 1431 lwkt_serialize_exit(ifp->if_serializer); 1432 } 1433 1434 static void 1435 sf_watchdog(struct ifnet *ifp) 1436 { 1437 struct sf_softc *sc; 1438 1439 sc = ifp->if_softc; 1440 1441 ifp->if_oerrors++; 1442 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1443 1444 sf_stop(sc); 1445 sf_reset(sc); 1446 sf_init(sc); 1447 1448 if (!ifq_is_empty(&ifp->if_snd)) 1449 sf_start(ifp); 1450 1451 return; 1452 } 1453 1454 static void 1455 sf_shutdown(device_t dev) 1456 { 1457 struct sf_softc *sc; 1458 struct ifnet *ifp; 1459 1460 sc = device_get_softc(dev); 1461 ifp = &sc->arpcom.ac_if; 1462 lwkt_serialize_enter(ifp->if_serializer); 1463 sf_stop(sc); 1464 lwkt_serialize_exit(ifp->if_serializer); 1465 1466 return; 1467 } 1468