1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sfreg.h,v 1.6.2.1 2001/08/16 20:35:04 wpaul Exp $ 33 * $DragonFly: src/sys/dev/netif/sf/if_sfreg.h,v 1.5 2006/08/01 18:08:24 swildner Exp $ 34 */ 35 36 /* 37 * Registers for the Adaptec AIC-6915 Starfire. The Starfire has a 512K 38 * register space. These registers can be accessed in the following way: 39 * - PCI config registers are always accessible through PCI config space 40 * - Full 512K space mapped into memory using PCI memory mapped access 41 * - 256-byte I/O space mapped through PCI I/O access 42 * - Full 512K space mapped through indirect I/O using PCI I/O access 43 * It's possible to use either memory mapped mode or I/O mode to access 44 * the registers, but memory mapped is usually the easiest. All registers 45 * are 32 bits wide and must be accessed using 32-bit operations. 46 */ 47 48 /* 49 * AIC-6915 subsystem IDs. Adaptec uses the subsystem ID to identify 50 * the exact kind of NIC on which the ASIC is mounted. Currently there 51 * are six different variations. Note: the Adaptec manual lists code 0x28 52 * for two different NICs: the 62044 and the 69011/TX. This is a typo: 53 * the code for the 62044 is really 0x18. 54 * 55 * Note that there also appears to be an 0x19 code for a newer rev 56 * 62044 card. 57 */ 58 #define AD_SUBSYSID_62011_REV0 0x0008 /* single port 10/100baseTX 64-bit */ 59 #define AD_SUBSYSID_62011_REV1 0x0009 /* single port 10/100baseTX 64-bit */ 60 #define AD_SUBSYSID_62022 0x0010 /* dual port 10/100baseTX 64-bit */ 61 #define AD_SUBSYSID_62044_REV0 0x0018 /* quad port 10/100baseTX 64-bit */ 62 #define AD_SUBSYSID_62044_REV1 0x0019 /* quad port 10/100baseTX 64-bit */ 63 #define AD_SUBSYSID_62020 0x0020 /* single port 10/100baseFX 64-bit */ 64 #define AD_SUBSYSID_69011 0x0028 /* single port 10/100baseTX 32-bit */ 65 66 /* 67 * Starfire internal register space map. The entire register space 68 * is available using PCI memory mapped mode. The SF_RMAP_INTREG 69 * space is available using PCI I/O mode. The entire space can be 70 * accessed using indirect I/O using the indirect I/O addr and 71 * indirect I/O data registers located within the SF_RMAP_INTREG space. 72 */ 73 #define SF_RMAP_ROMADDR_BASE 0x00000 /* Expansion ROM space */ 74 #define SF_RMAP_ROMADDR_MAX 0x3FFFF 75 76 #define SF_RMAP_EXGPIO_BASE 0x40000 /* External general purpose regs */ 77 #define SF_RMAP_EXGPIO_MAX 0x3FFFF 78 79 #define SF_RMAP_INTREG_BASE 0x50000 /* Internal functional registers */ 80 #define SF_RMAP_INTREG_MAX 0x500FF 81 #define SF_RMAP_GENREG_BASE 0x50100 /* General purpose registers */ 82 #define SF_RMAP_GENREG_MAX 0x5FFFF 83 84 #define SF_RMAP_FIFO_BASE 0x60000 85 #define SF_RMAP_FIFO_MAX 0x6FFFF 86 87 #define SF_RMAP_STS_BASE 0x70000 88 #define SF_RMAP_STS_MAX 0x70083 89 90 #define SF_RMAP_RSVD_BASE 0x70084 91 #define SF_RMAP_RSVD_MAX 0x7FFFF 92 93 /* 94 * PCI config header registers, 0x0000 to 0x003F 95 */ 96 #define SF_PCI_VENDOR_ID 0x0000 97 #define SF_PCI_DEVICE_ID 0x0002 98 #define SF_PCI_COMMAND 0x0004 99 #define SF_PCI_STATUS 0x0006 100 #define SF_PCI_REVID 0x0008 101 #define SF_PCI_CLASSCODE 0x0009 102 #define SF_PCI_CACHELEN 0x000C 103 #define SF_PCI_LATENCY_TIMER 0x000D 104 #define SF_PCI_HEADER_TYPE 0x000E 105 #define SF_PCI_LOMEM 0x0010 106 #define SF_PCI_LOIO 0x0014 107 #define SF_PCI_SUBVEN_ID 0x002C 108 #define SF_PCI_SYBSYS_ID 0x002E 109 #define SF_PCI_BIOSROM 0x0030 110 #define SF_PCI_INTLINE 0x003C 111 #define SF_PCI_INTPIN 0x003D 112 #define SF_PCI_MINGNT 0x003E 113 #define SF_PCI_MINLAT 0x003F 114 115 /* 116 * PCI registers, 0x0040 to 0x006F 117 */ 118 #define SF_PCI_DEVCFG 0x0040 119 #define SF_BACCTL 0x0044 120 #define SF_PCI_MON1 0x0048 121 #define SF_PCI_MON2 0x004C 122 #define SF_PCI_CAPID 0x0050 /* 8 bits */ 123 #define SF_PCI_NEXTPTR 0x0051 /* 8 bits */ 124 #define SF_PCI_PWRMGMTCAP 0x0052 /* 16 bits */ 125 #define SF_PCI_PWRMGMTCTRL 0x0054 /* 16 bits */ 126 #define SF_PCI_PME_EVENT 0x0058 127 #define SF_PCI_EECTL 0x0060 128 #define SF_PCI_COMPLIANCE 0x0064 129 #define SF_INDIRECTIO_ADDR 0x0068 130 #define SF_INDIRECTIO_DATA 0x006C 131 132 #define SF_PCIDEVCFG_RESET 0x00000001 133 #define SF_PCIDEVCFG_FORCE64 0x00000002 134 #define SF_PCIDEVCFG_SYSTEM64 0x00000004 135 #define SF_PCIDEVCFG_RSVD0 0x00000008 136 #define SF_PCIDEVCFG_INCR_INB 0x00000010 137 #define SF_PCIDEVCFG_ABTONPERR 0x00000020 138 #define SF_PCIDEVCFG_STPONPERR 0x00000040 139 #define SF_PCIDEVCFG_MR_ENB 0x00000080 140 #define SF_PCIDEVCFG_FIFOTHR 0x00000F00 141 #define SF_PCIDEVCFG_STPONCA 0x00001000 142 #define SF_PCIDEVCFG_PCIMEN 0x00002000 /* enable PCI bus master */ 143 #define SF_PCIDEVCFG_LATSTP 0x00004000 144 #define SF_PCIDEVCFG_BYTE_ENB 0x00008000 145 #define SF_PCIDEVCFG_EECSWIDTH 0x00070000 146 #define SF_PCIDEVCFG_STPMWCA 0x00080000 147 #define SF_PCIDEVCFG_REGCSWIDTH 0x00700000 148 #define SF_PCIDEVCFG_INTR_ENB 0x00800000 149 #define SF_PCIDEVCFG_DPR_ENB 0x01000000 150 #define SF_PCIDEVCFG_RSVD1 0x02000000 151 #define SF_PCIDEVCFG_RSVD2 0x04000000 152 #define SF_PCIDEVCFG_STA_ENB 0x08000000 153 #define SF_PCIDEVCFG_RTA_ENB 0x10000000 154 #define SF_PCIDEVCFG_RMA_ENB 0x20000000 155 #define SF_PCIDEVCFG_SSE_ENB 0x40000000 156 #define SF_PCIDEVCFG_DPE_ENB 0x80000000 157 158 #define SF_BACCTL_BACDMA_ENB 0x00000001 159 #define SF_BACCTL_PREFER_RXDMA 0x00000002 160 #define SF_BACCTL_PREFER_TXDMA 0x00000004 161 #define SF_BACCTL_SINGLE_DMA 0x00000008 162 #define SF_BACCTL_SWAPMODE_DATA 0x00000030 163 #define SF_BACCTL_SWAPMODE_DESC 0x000000C0 164 165 #define SF_SWAPMODE_LE 0x00000000 166 #define SF_SWAPMODE_BE 0x00000010 167 168 #define SF_PSTATE_MASK 0x0003 169 #define SF_PSTATE_D0 0x0000 170 #define SF_PSTATE_D1 0x0001 171 #define SF_PSTATE_D2 0x0002 172 #define SF_PSTATE_D3 0x0003 173 #define SF_PME_EN 0x0010 174 #define SF_PME_STATUS 0x8000 175 176 177 /* 178 * Ethernet registers 0x0070 to 0x00FF 179 */ 180 #define SF_GEN_ETH_CTL 0x0070 181 #define SF_TIMER_CTL 0x0074 182 #define SF_CURTIME 0x0078 183 #define SF_ISR 0x0080 184 #define SF_ISR_SHADOW 0x0084 185 #define SF_IMR 0x0088 186 #define SF_GPIO 0x008C 187 #define SF_TXDQ_CTL 0x0090 188 #define SF_TXDQ_ADDR_HIPRIO 0x0094 189 #define SF_TXDQ_ADDR_LOPRIO 0x0098 190 #define SF_TXDQ_ADDR_HIADDR 0x009C 191 #define SF_TXDQ_PRODIDX 0x00A0 192 #define SF_TXDQ_CONSIDX 0x00A4 193 #define SF_TXDMA_STS1 0x00A8 194 #define SF_TXDMA_STS2 0x00AC 195 #define SF_TX_FRAMCTL 0x00B0 196 #define SF_TXCQ_ADDR_HI 0x00B4 197 #define SF_TXCQ_CTL 0x00B8 198 #define SF_RXCQ_CTL_1 0x00BC 199 #define SF_RXCQ_CTL_2 0x00C0 200 #define SF_CQ_CONSIDX 0x00C4 201 #define SF_CQ_PRODIDX 0x00C8 202 #define SF_CQ_RXQ2 0x00CC 203 #define SF_RXDMA_CTL 0x00D0 204 #define SF_RXDQ_CTL_1 0x00D4 205 #define SF_RXDQ_CTL_2 0x00D8 206 #define SF_RXDQ_ADDR_HIADDR 0x00DC 207 #define SF_RXDQ_ADDR_Q1 0x00E0 208 #define SF_RXDQ_ADDR_Q2 0x00E4 209 #define SF_RXDQ_PTR_Q1 0x00E8 210 #define SF_RXDQ_PTR_Q2 0x00EC 211 #define SF_RXDMA_STS 0x00F0 212 #define SF_RXFILT 0x00F4 213 #define SF_RX_FRAMETEST_OUT 0x00F8 214 215 /* Ethernet control register */ 216 #define SF_ETHCTL_RX_ENB 0x00000001 217 #define SF_ETHCTL_TX_ENB 0x00000002 218 #define SF_ETHCTL_RXDMA_ENB 0x00000004 219 #define SF_ETHCTL_TXDMA_ENB 0x00000008 220 #define SF_ETHCTL_RXGFP_ENB 0x00000010 221 #define SF_ETHCTL_TXGFP_ENB 0x00000020 222 #define SF_ETHCTL_SOFTINTR 0x00000800 223 224 /* Timer control register */ 225 #define SF_TIMER_IMASK_INTERVAL 0x0000001F 226 #define SF_TIMER_IMASK_MODE 0x00000060 227 #define SF_TIMER_SMALLFRAME_BYP 0x00000100 228 #define SF_TIMER_SMALLRX_FRAME 0x00000600 229 #define SF_TIMER_TIMES_TEN 0x00000800 230 #define SF_TIMER_RXHIPRIO_BYP 0x00001000 231 #define SF_TIMER_TX_DMADONE_DLY 0x00002000 232 #define SF_TIMER_TX_QDONE_DLY 0x00004000 233 #define SF_TIMER_TX_FRDONE_DLY 0x00008000 234 #define SF_TIMER_GENTIMER 0x00FF0000 235 #define SF_TIMER_ONESHOT 0x01000000 236 #define SF_TIMER_GENTIMER_RES 0x02000000 237 #define SF_TIMER_TIMEST_RES 0x04000000 238 #define SF_TIMER_RXQ2DONE_DLY 0x10000000 239 #define SF_TIMER_EARLYRX2_DLY 0x20000000 240 #define SF_TIMER_RXQ1DONE_DLY 0x40000000 241 #define SF_TIMER_EARLYRX1_DLY 0x80000000 242 243 /* Interrupt status register */ 244 #define SF_ISR_PCIINT_ASSERTED 0x00000001 245 #define SF_ISR_GFP_TX 0x00000002 246 #define SF_ISR_GFP_RX 0x00000004 247 #define SF_ISR_TX_BADID_HIPRIO 0x00000008 248 #define SF_ISR_TX_BADID_LOPRIO 0x00000010 249 #define SF_ISR_NO_TX_CSUM 0x00000020 250 #define SF_ISR_RXDQ2_NOBUFS 0x00000040 251 #define SF_ISR_RXGFP_NORESP 0x00000080 252 #define SF_ISR_RXDQ1_DMADONE 0x00000100 253 #define SF_ISR_RXDQ2_DMADONE 0x00000200 254 #define SF_ISR_RXDQ1_EARLY 0x00000400 255 #define SF_ISR_RXDQ2_EARLY 0x00000800 256 #define SF_ISR_TX_QUEUEDONE 0x00001000 257 #define SF_ISR_TX_DMADONE 0x00002000 258 #define SF_ISR_TX_TXDONE 0x00004000 259 #define SF_ISR_NORMALINTR 0x00008000 260 #define SF_ISR_RXDQ1_NOBUFS 0x00010000 261 #define SF_ISR_RXCQ2_NOBUFS 0x00020000 262 #define SF_ISR_TX_LOFIFO 0x00040000 263 #define SF_ISR_DMAERR 0x00080000 264 #define SF_ISR_PCIINT 0x00100000 265 #define SF_ISR_TXCQ_NOBUFS 0x00200000 266 #define SF_ISR_RXCQ1_NOBUFS 0x00400000 267 #define SF_ISR_SOFTINTR 0x00800000 268 #define SF_ISR_GENTIMER 0x01000000 269 #define SF_ISR_ABNORMALINTR 0x02000000 270 #define SF_ISR_RSVD0 0x04000000 271 #define SF_ISR_STATSOFLOW 0x08000000 272 #define SF_ISR_GPIO 0xF0000000 273 274 /* 275 * Shadow interrupt status register. Unlike the normal IRQ register, 276 * reading bits here does not automatically cause them to reset. 277 */ 278 #define SF_SISR_PCIINT_ASSERTED 0x00000001 279 #define SF_SISR_GFP_TX 0x00000002 280 #define SF_SISR_GFP_RX 0x00000004 281 #define SF_SISR_TX_BADID_HIPRIO 0x00000008 282 #define SF_SISR_TX_BADID_LOPRIO 0x00000010 283 #define SF_SISR_NO_TX_CSUM 0x00000020 284 #define SF_SISR_RXDQ2_NOBUFS 0x00000040 285 #define SF_SISR_RXGFP_NORESP 0x00000080 286 #define SF_SISR_RXDQ1_DMADONE 0x00000100 287 #define SF_SISR_RXDQ2_DMADONE 0x00000200 288 #define SF_SISR_RXDQ1_EARLY 0x00000400 289 #define SF_SISR_RXDQ2_EARLY 0x00000800 290 #define SF_SISR_TX_QUEUEDONE 0x00001000 291 #define SF_SISR_TX_DMADONE 0x00002000 292 #define SF_SISR_TX_TXDONE 0x00004000 293 #define SF_SISR_NORMALINTR 0x00008000 294 #define SF_SISR_RXDQ1_NOBUFS 0x00010000 295 #define SF_SISR_RXCQ2_NOBUFS 0x00020000 296 #define SF_SISR_TX_LOFIFO 0x00040000 297 #define SF_SISR_DMAERR 0x00080000 298 #define SF_SISR_PCIINT 0x00100000 299 #define SF_SISR_TXCQ_NOBUFS 0x00200000 300 #define SF_SISR_RXCQ1_NOBUFS 0x00400000 301 #define SF_SISR_SOFTINTR 0x00800000 302 #define SF_SISR_GENTIMER 0x01000000 303 #define SF_SISR_ABNORMALINTR 0x02000000 304 #define SF_SISR_RSVD0 0x04000000 305 #define SF_SISR_STATSOFLOW 0x08000000 306 #define SF_SISR_GPIO 0xF0000000 307 308 /* Interrupt mask register */ 309 #define SF_IMR_PCIINT_ASSERTED 0x00000001 310 #define SF_IMR_GFP_TX 0x00000002 311 #define SF_IMR_GFP_RX 0x00000004 312 #define SF_IMR_TX_BADID_HIPRIO 0x00000008 313 #define SF_IMR_TX_BADID_LOPRIO 0x00000010 314 #define SF_IMR_NO_TX_CSUM 0x00000020 315 #define SF_IMR_RXDQ2_NOBUFS 0x00000040 316 #define SF_IMR_RXGFP_NORESP 0x00000080 317 #define SF_IMR_RXDQ1_DMADONE 0x00000100 318 #define SF_IMR_RXDQ2_DMADONE 0x00000200 319 #define SF_IMR_RXDQ1_EARLY 0x00000400 320 #define SF_IMR_RXDQ2_EARLY 0x00000800 321 #define SF_IMR_TX_QUEUEDONE 0x00001000 322 #define SF_IMR_TX_DMADONE 0x00002000 323 #define SF_IMR_TX_TXDONE 0x00004000 324 #define SF_IMR_NORMALINTR 0x00008000 325 #define SF_IMR_RXDQ1_NOBUFS 0x00010000 326 #define SF_IMR_RXCQ2_NOBUFS 0x00020000 327 #define SF_IMR_TX_LOFIFO 0x00040000 328 #define SF_IMR_DMAERR 0x00080000 329 #define SF_IMR_PCIINT 0x00100000 330 #define SF_IMR_TXCQ_NOBUFS 0x00200000 331 #define SF_IMR_RXCQ1_NOBUFS 0x00400000 332 #define SF_IMR_SOFTINTR 0x00800000 333 #define SF_IMR_GENTIMER 0x01000000 334 #define SF_IMR_ABNORMALINTR 0x02000000 335 #define SF_IMR_RSVD0 0x04000000 336 #define SF_IMR_STATSOFLOW 0x08000000 337 #define SF_IMR_GPIO 0xF0000000 338 339 #define SF_INTRS \ 340 (SF_IMR_RXDQ2_NOBUFS|SF_IMR_RXDQ1_DMADONE|SF_IMR_RXDQ2_DMADONE| \ 341 SF_IMR_TX_TXDONE|SF_IMR_RXDQ1_NOBUFS|SF_IMR_RXDQ2_DMADONE| \ 342 SF_IMR_NORMALINTR|SF_IMR_ABNORMALINTR|SF_IMR_TXCQ_NOBUFS| \ 343 SF_IMR_RXCQ1_NOBUFS|SF_IMR_RXCQ2_NOBUFS|SF_IMR_STATSOFLOW| \ 344 SF_IMR_TX_LOFIFO) 345 346 /* TX descriptor queue control registers */ 347 #define SF_TXDQCTL_DESCTYPE 0x00000007 348 #define SF_TXDQCTL_NODMACMP 0x00000008 349 #define SF_TXDQCTL_MINSPACE 0x00000070 350 #define SF_TXDQCTL_64BITADDR 0x00000080 351 #define SF_TXDQCTL_BURSTLEN 0x00003F00 352 #define SF_TXDQCTL_SKIPLEN 0x001F0000 353 #define SF_TXDQCTL_HIPRIOTHRESH 0xFF000000 354 355 #define SF_TXBUFDESC_TYPE0 0x00000000 356 #define SF_TXBUFDESC_TYPE1 0x00000001 357 #define SF_TXBUFDESC_TYPE2 0x00000002 358 #define SF_TXBUFDESC_TYPE3 0x00000003 359 #define SF_TXBUFDESC_TYPE4 0x00000004 360 361 #define SF_TXMINSPACE_UNLIMIT 0x00000000 362 #define SF_TXMINSPACE_32BYTES 0x00000010 363 #define SF_TXMINSPACE_64BYTES 0x00000020 364 #define SF_TXMINSPACE_128BYTES 0x00000030 365 #define SF_TXMINSPACE_256BYTES 0x00000040 366 367 #define SF_TXSKIPLEN_0BYTES 0x00000000 368 #define SF_TXSKIPLEN_8BYTES 0x00010000 369 #define SF_TXSKIPLEN_16BYTES 0x00020000 370 #define SF_TXSKIPLEN_24BYTES 0x00030000 371 #define SF_TXSKIPLEN_32BYTES 0x00040000 372 373 /* TX frame control register */ 374 #define SF_TXFRMCTL_TXTHRESH 0x000000FF 375 #define SF_TXFRMCTL_CPLAFTERTX 0x00000100 376 #define SF_TXFRMCRL_DEBUG 0x0000FE00 377 #define SF_TXFRMCTL_STATUS 0x01FF0000 378 #define SF_TXFRMCTL_MAC_TXIF 0xFE000000 379 380 /* TX completion queue control register */ 381 #define SF_TXCQ_THRESH 0x0000000F 382 #define SF_TXCQ_COMMON 0x00000010 383 #define SF_TXCQ_SIZE 0x00000020 384 #define SF_TXCQ_WRITEENB 0x00000040 385 #define SF_TXCQ_USE_64BIT 0x00000080 386 #define SF_TXCQ_ADDR 0xFFFFFF00 387 388 /* RX completion queue control register */ 389 #define SF_RXCQ_THRESH 0x0000000F 390 #define SF_RXCQ_TYPE 0x00000030 391 #define SF_RXCQ_WRITEENB 0x00000040 392 #define SF_RXCQ_USE_64BIT 0x00000080 393 #define SF_RXCQ_ADDR 0xFFFFFF00 394 395 #define SF_RXCQTYPE_0 0x00000000 396 #define SF_RXCQTYPE_1 0x00000010 397 #define SF_RXCQTYPE_2 0x00000020 398 #define SF_RXCQTYPE_3 0x00000030 399 400 /* TX descriptor queue producer index register */ 401 #define SF_TXDQ_PRODIDX_LOPRIO 0x000007FF 402 #define SF_TXDQ_PRODIDX_HIPRIO 0x07FF0000 403 404 /* TX descriptor queue consumer index register */ 405 #define SF_TXDQ_CONSIDX_LOPRIO 0x000007FF 406 #define SF_TXDQ_CONSIDX_HIPRIO 0x07FF0000 407 408 /* Completion queue consumer index register */ 409 #define SF_CQ_CONSIDX_RXQ1 0x000003FF 410 #define SF_CQ_CONSIDX_RXTHRMODE 0x00008000 411 #define SF_CQ_CONSIDX_TXQ 0x03FF0000 412 #define SF_CQ_CONSIDX_TXTHRMODE 0x80000000 413 414 /* Completion queue producer index register */ 415 #define SF_CQ_PRODIDX_RXQ1 0x000003FF 416 #define SF_CQ_PRODIDX_TXQ 0x03FF0000 417 418 /* RX completion queue 2 consumer/producer index register */ 419 #define SF_CQ_RXQ2_CONSIDX 0x000003FF 420 #define SF_CQ_RXQ2_RXTHRMODE 0x00008000 421 #define SF_CQ_RXQ2_PRODIDX 0x03FF0000 422 423 #define SF_CQ_RXTHRMODE_INT_ON 0x00008000 424 #define SF_CQ_RXTHRMODE_INT_OFF 0x00000000 425 #define SF_CQ_TXTHRMODE_INT_ON 0x80000000 426 #define SF_CQ_TXTHRMODE_INT_OFF 0x00000000 427 428 #define SF_IDX_LO(x) ((x) & 0x000007FF) 429 #define SF_IDX_HI(x) (((x) >> 16) & 0x000007FF) 430 431 /* RX DMA control register */ 432 #define SF_RXDMA_BURSTSIZE 0x0000007F 433 #define SF_RXDMA_FPTESTMODE 0x00000080 434 #define SF_RXDMA_HIPRIOTHRESH 0x00000F00 435 #define SF_RXDMA_RXEARLYTHRESH 0x0001F000 436 #define SF_RXDMA_DMACRC 0x00040000 437 #define SF_RXDMA_USEBKUPQUEUE 0x00080000 438 #define SF_RXDMA_QUEUEMODE 0x00700000 439 #define SF_RXDMA_RXCQ2_ON 0x00800000 440 #define SF_RXDMA_CSUMMODE 0x03000000 441 #define SF_RXDMA_DMAPAUSEPKTS 0x04000000 442 #define SF_RXDMA_DMACTLPKTS 0x08000000 443 #define SF_RXDMA_DMACRXERRPKTS 0x10000000 444 #define SF_RXDMA_DMABADPKTS 0x20000000 445 #define SF_RXDMA_DMARUNTS 0x40000000 446 #define SF_RXDMA_REPORTBADPKTS 0x80000000 447 448 #define SF_RXDQMODE_Q1ONLY 0x00100000 449 #define SF_RXDQMODE_Q2_ON_FP 0x00200000 450 #define SF_RXDQMODE_Q2_ON_SHORT 0x00300000 451 #define SF_RXDQMODE_Q2_ON_PRIO 0x00400000 452 #define SF_RXDQMODE_SPLITHDR 0x00500000 453 454 #define SF_RXCSUMMODE_IGNORE 0x00000000 455 #define SF_RXCSUMMODE_REJECT_BAD_TCP 0x01000000 456 #define SF_RXCSUMMODE_REJECT_BAD_TCPUDP 0x02000000 457 #define SF_RXCSUMMODE_RSVD 0x03000000 458 459 /* RX descriptor queue control registers */ 460 #define SF_RXDQCTL_MINDESCTHR 0x0000007F 461 #define SF_RXDQCTL_Q1_WE 0x00000080 462 #define SF_RXDQCTL_DESCSPACE 0x00000700 463 #define SF_RXDQCTL_64BITDADDR 0x00000800 464 #define SF_RXDQCTL_64BITBADDR 0x00001000 465 #define SF_RXDQCTL_VARIABLE 0x00002000 466 #define SF_RXDQCTL_ENTRIES 0x00004000 467 #define SF_RXDQCTL_PREFETCH 0x00008000 468 #define SF_RXDQCTL_BUFLEN 0xFFFF0000 469 470 #define SF_DESCSPACE_4BYTES 0x00000000 471 #define SF_DESCSPACE_8BYTES 0x00000100 472 #define SF_DESCSPACE_16BYTES 0x00000200 473 #define SF_DESCSPACE_32BYTES 0x00000300 474 #define SF_DESCSPACE_64BYTES 0x00000400 475 #define SF_DESCSPACE_128_BYTES 0x00000500 476 477 /* RX buffer consumer/producer index registers */ 478 #define SF_RXDQ_PRODIDX 0x000007FF 479 #define SF_RXDQ_CONSIDX 0x07FF0000 480 481 /* RX filter control register */ 482 #define SF_RXFILT_PROMISC 0x00000001 483 #define SF_RXFILT_ALLMULTI 0x00000002 484 #define SF_RXFILT_BROAD 0x00000004 485 #define SF_RXFILT_HASHPRIO 0x00000008 486 #define SF_RXFILT_HASHMODE 0x00000030 487 #define SF_RXFILT_PERFMODE 0x000000C0 488 #define SF_RXFILT_VLANMODE 0x00000300 489 #define SF_RXFILT_WAKEMODE 0x00000C00 490 #define SF_RXFILT_MULTI_NOBROAD 0x00001000 491 #define SF_RXFILT_MIN_VLANPRIO 0x0000E000 492 #define SF_RXFILT_PEFECTPRIO 0xFFFF0000 493 494 /* Hash filtering mode */ 495 #define SF_HASHMODE_OFF 0x00000000 496 #define SF_HASHMODE_WITHVLAN 0x00000010 497 #define SF_HASHMODE_ANYVLAN 0x00000020 498 #define SF_HASHMODE_ANY 0x00000030 499 500 /* Perfect filtering mode */ 501 #define SF_PERFMODE_OFF 0x00000000 502 #define SF_PERFMODE_NORMAL 0x00000040 503 #define SF_PERFMODE_INVERSE 0x00000080 504 #define SF_PERFMODE_VLAN 0x000000C0 505 506 /* VLAN mode */ 507 #define SF_VLANMODE_OFF 0x00000000 508 #define SF_VLANMODE_NOSTRIP 0x00000100 509 #define SF_VLANMODE_STRIP 0x00000200 510 #define SF_VLANMODE_RSVD 0x00000300 511 512 /* Wakeup mode */ 513 #define SF_WAKEMODE_OFF 0x00000000 514 #define SF_WAKEMODE_FILTER 0x00000400 515 #define SF_WAKEMODE_FP 0x00000800 516 #define SF_WAKEMODE_HIPRIO 0x00000C00 517 518 /* 519 * Extra PCI registers 0x0100 to 0x0FFF 520 */ 521 #define SF_PCI_TARGSTAT 0x0100 522 #define SF_PCI_MASTSTAT1 0x0104 523 #define SF_PCI_MASTSTAT2 0x0108 524 #define SF_PCI_DMAHOSTADDR_LO 0x010C 525 #define SF_BAC_DMADIAG0 0x0110 526 #define SF_BAC_DMADIAG1 0x0114 527 #define SF_BAC_DMADIAG2 0x0118 528 #define SF_BAC_DMADIAG3 0x011C 529 #define SF_PAR0 0x0120 530 #define SF_PAR1 0x0124 531 #define SF_PCICB_FUNCEVENT 0x0130 532 #define SF_PCICB_FUNCEVENT_MASK 0x0134 533 #define SF_PCICB_FUNCSTATE 0x0138 534 #define SF_PCICB_FUNCFORCE 0x013C 535 536 /* 537 * Serial EEPROM registers 0x1000 to 0x1FFF 538 * Presumeably the EEPROM is mapped into this 8K window. 539 */ 540 #define SF_EEADDR_BASE 0x1000 541 #define SF_EEADDR_MAX 0x1FFF 542 543 #define SF_EE_NODEADDR 14 544 545 /* 546 * MII registers registers 0x2000 to 0x3FFF 547 * There are 32 sets of 32 registers, one set for each possible 548 * PHY address. Each 32 bit register is split into a 16-bit data 549 * port and a couple of status bits. 550 */ 551 552 #define SF_MIIADDR_BASE 0x2000 553 #define SF_MIIADDR_MAX 0x3FFF 554 #define SF_MII_BLOCKS 32 555 556 #define SF_MII_DATAVALID 0x80000000 557 #define SF_MII_BUSY 0x40000000 558 #define SF_MII_DATAPORT 0x0000FFFF 559 560 #define SF_PHY_REG(phy, reg) \ 561 (SF_MIIADDR_BASE + (phy * SF_MII_BLOCKS * sizeof(u_int32_t)) + \ 562 (reg * sizeof(u_int32_t))) 563 564 /* 565 * Ethernet extra registers 0x4000 to 0x4FFF 566 */ 567 #define SF_TESTMODE 0x4000 568 #define SF_RX_FRAMEPROC_CTL 0x4004 569 #define SF_TX_FRAMEPROC_CTL 0x4008 570 571 /* 572 * MAC registers 0x5000 to 0x5FFF 573 */ 574 #define SF_MACCFG_1 0x5000 575 #define SF_MACCFG_2 0x5004 576 #define SF_BKTOBKIPG 0x5008 577 #define SF_NONBKTOBKIPG 0x500C 578 #define SF_COLRETRY 0x5010 579 #define SF_MAXLEN 0x5014 580 #define SF_TXNIBBLECNT 0x5018 581 #define SF_TXBYTECNT 0x501C 582 #define SF_RETXCNT 0x5020 583 #define SF_RANDNUM 0x5024 584 #define SF_RANDNUM_MASK 0x5028 585 #define SF_TOTALTXCNT 0x5034 586 #define SF_RXBYTECNT 0x5040 587 #define SF_TXPAUSETIMER 0x5060 588 #define SF_VLANTYPE 0x5064 589 #define SF_MIISTATUS 0x5070 590 591 #define SF_MACCFG1_HUGEFRAMES 0x00000001 592 #define SF_MACCFG1_FULLDUPLEX 0x00000002 593 #define SF_MACCFG1_AUTOPAD 0x00000004 594 #define SF_MACCFG1_HDJAM 0x00000008 595 #define SF_MACCFG1_DELAYCRC 0x00000010 596 #define SF_MACCFG1_NOBACKOFF 0x00000020 597 #define SF_MACCFG1_LENGTHCHECK 0x00000040 598 #define SF_MACCFG1_PUREPREAMBLE 0x00000080 599 #define SF_MACCFG1_PASSALLRX 0x00000100 600 #define SF_MACCFG1_PREAM_DETCNT 0x00000200 601 #define SF_MACCFG1_RX_FLOWENB 0x00000400 602 #define SF_MACCFG1_TX_FLOWENB 0x00000800 603 #define SF_MACCFG1_TESTMODE 0x00003000 604 #define SF_MACCFG1_MIILOOPBK 0x00004000 605 #define SF_MACCFG1_SOFTRESET 0x00008000 606 607 /* 608 * There are the recommended IPG nibble counter settings 609 * specified in the Adaptec manual for full duplex and 610 * half duplex operation. 611 */ 612 #define SF_IPGT_FDX 0x15 613 #define SF_IPGT_HDX 0x11 614 615 /* 616 * RX filter registers 0x6000 to 0x6FFF 617 */ 618 #define SF_RXFILT_PERFECT_BASE 0x6000 619 #define SF_RXFILT_PERFECT_MAX 0x60FF 620 #define SF_RXFILT_PERFECT_SKIP 0x0010 621 #define SF_RXFILT_PERFECT_CNT 0x0010 622 623 #define SF_RXFILT_HASH_BASE 0x6100 624 #define SF_RXFILT_HASH_MAX 0x62FF 625 #define SF_RXFILT_HASH_SKIP 0x0010 626 #define SF_RXFILT_HASH_CNT 0x001F 627 #define SF_RXFILT_HASH_ADDROFF 0x0000 628 #define SF_RXFILT_HASH_PRIOOFF 0x0004 629 #define SF_RXFILT_HASH_VLANOFF 0x0008 630 631 /* 632 * Statistics registers 0x7000 to 0x7FFF 633 */ 634 #define SF_STATS_BASE 0x7000 635 #define SF_STATS_END 0x7FFF 636 637 /* 638 * TX frame processor instruction space 0x8000 to 0x9FFF 639 */ 640 641 /* 642 * RX frame processor instruction space 0xA000 to 0xBFFF 643 */ 644 645 /* 646 * Ethernet FIFO access space 0xC000 to 0xDFFF 647 */ 648 649 /* 650 * Reserved 0xE000 to 0xFFFF 651 */ 652 653 /* 654 * Descriptor data structures. 655 */ 656 657 658 /* Receive descriptor formats. */ 659 #define SF_RX_MINSPACING 8 660 #define SF_RX_DLIST_CNT 256 661 #define SF_RX_CLIST_CNT 1024 662 #define SF_RX_HOSTADDR(x) (((x) >> 2) & 0x3FFFFFFF) 663 664 /* 665 * RX buffer descriptor type 0, 32-bit addressing. Note that we 666 * program the RX buffer queue control register(s) to allow a 667 * descriptor spacing of 16 bytes, which leaves room after each 668 * descriptor to store a pointer to the mbuf for each buffer. 669 */ 670 struct sf_rx_bufdesc_type0 { 671 u_int32_t sf_valid:1, 672 sf_end:1, 673 sf_addrlo:30; 674 u_int32_t sf_pad0; 675 #ifdef __i386__ 676 u_int32_t sf_pad1; 677 #endif 678 struct mbuf *sf_mbuf; 679 }; 680 681 /* 682 * RX buffer descriptor type 0, 64-bit addressing. 683 */ 684 struct sf_rx_bufdesc_type1 { 685 u_int32_t sf_valid:1, 686 sf_end:1, 687 sf_addrlo:30; 688 u_int32_t sf_addrhi; 689 #ifdef __i386__ 690 u_int32_t sf_pad; 691 #endif 692 struct mbuf *sf_mbuf; 693 }; 694 695 /* 696 * RX completion descriptor, type 0 (short). 697 */ 698 struct sf_rx_cmpdesc_type0 { 699 u_int32_t sf_len:16, 700 sf_endidx:11, 701 sf_status1:3, 702 sf_id:2; 703 }; 704 705 /* 706 * RX completion descriptor, type 1 (basic). Includes vlan ID 707 * if this is a vlan-addressed packet, plus extended status. 708 */ 709 struct sf_rx_cmpdesc_type1 { 710 u_int32_t sf_len:16, 711 sf_endidx:11, 712 sf_status1:3, 713 sf_id:2; 714 u_int16_t sf_status2; 715 u_int16_t sf_vlanid; 716 }; 717 718 /* 719 * RX completion descriptor, type 2 (checksum). Includes partial TCP/IP 720 * checksum instead of vlan tag, plus extended status. 721 */ 722 struct sf_rx_cmpdesc_type2 { 723 u_int32_t sf_len:16, 724 sf_endidx:11, 725 sf_status1:3, 726 sf_id:2; 727 u_int16_t sf_status2; 728 u_int16_t sf_cksum; 729 }; 730 731 /* 732 * RX completion descriptor type 3 (full). Includes timestamp, partial 733 * TCP/IP checksum, vlan tag plus priority, two extended status fields. 734 */ 735 struct sf_rx_cmpdesc_type3 { 736 u_int32_t sf_len:16, 737 sf_endidx:11, 738 sf_status1:3, 739 sf_id:2; 740 u_int32_t sf_startidx:10, 741 sf_status3:6, 742 sf_status2:16; 743 u_int16_t sf_cksum; 744 u_int16_t sf_vlanid_prio; 745 u_int32_t sf_timestamp; 746 }; 747 748 #define SF_RXSTAT1_QUEUE 0x1 749 #define SF_RXSTAT1_FIFOFULL 0x2 750 #define SF_RXSTAT1_OK 0x4 751 752 /* 0=unknown,5=unsupported */ 753 #define SF_RXSTAT2_FRAMETYPE 0x0007 /* 1=IPv4,2=IPv2,3=IPX,4=ICMP */ 754 #define SF_RXSTAT2_UDP 0x0008 755 #define SF_RXSTAT2_TCP 0x0010 756 #define SF_RXSTAT2_FRAG 0x0020 757 #define SF_RXSTAT2_PCSUM_OK 0x0040 /* partial checksum ok */ 758 #define SF_RXSTAT2_CSUM_BAD 0x0080 /* TCP/IP checksum bad */ 759 #define SF_RXSTAT2_CSUM_OK 0x0100 /* TCP/IP checksum ok */ 760 #define SF_RXSTAT2_VLAN 0x0200 761 #define SF_RXSTAT2_BADRXCODE 0x0400 762 #define SF_RXSTAT2_DRIBBLE 0x0800 763 #define SF_RXSTAT2_ISL_CRCERR 0x1000 764 #define SF_RXSTAT2_CRCERR 0x2000 765 #define SF_RXSTAT2_HASH 0x4000 766 #define SF_RXSTAT2_PERFECT 0x8000 767 768 #define SF_RXSTAT3_TRAILER 0x01 769 #define SF_RXSTAT3_HEADER 0x02 770 #define SF_RXSTAT3_CONTROL 0x04 771 #define SF_RXSTAT3_PAUSE 0x08 772 #define SF_RXSTAT3_ISL 0x10 773 774 /* 775 * Transmit descriptor formats. 776 * Each transmit descriptor type allows for a skip field at the 777 * start of each structure. The size of the skip field can vary, 778 * however we always set it for 8 bytes, which is enough to hold 779 * a pointer (32 bits on x86, 64-bits on alpha) that we can use 780 * to hold the address of the head of the mbuf chain for the 781 * frame or fragment associated with the descriptor. This saves 782 * us from having to create a separate pointer array to hold 783 * the mbuf addresses. 784 */ 785 #define SF_TX_BUFDESC_ID 0xB 786 #define SF_MAXFRAGS 14 787 #define SF_TX_MINSPACING 128 788 #define SF_TX_DLIST_CNT 128 789 #define SF_TX_DLIST_SIZE 16384 790 #define SF_TX_SKIPLEN 1 791 #define SF_TX_CLIST_CNT 1024 792 793 struct sf_frag { 794 u_int32_t sf_addr; 795 u_int16_t sf_fraglen; 796 u_int16_t sf_pktlen; 797 }; 798 799 struct sf_frag_msdos { 800 u_int16_t sf_pktlen; 801 u_int16_t sf_fraglen; 802 u_int32_t sf_addr; 803 }; 804 805 /* 806 * TX frame descriptor type 0, 32-bit addressing. One descriptor can 807 * be used to map multiple packet fragments. We use this format since 808 * BSD networking fragments packet data across mbuf chains. Note that 809 * the number of fragments can be variable depending on how the descriptor 810 * spacing is specified in the TX descriptor queue control register. 811 * We always use a spacing of 128 bytes, and a skipfield length of 8 812 * bytes: this means 16 bytes for the descriptor, including the skipfield, 813 * with 121 bytes left for fragment maps. Each fragment requires 8 bytes, 814 * which allows for 14 fragments per descriptor. The total size of the 815 * transmit buffer queue is limited to 16384 bytes, so with a spacing of 816 * 128 bytes per descriptor, we have room for 128 descriptors in the queue. 817 */ 818 struct sf_tx_bufdesc_type0 { 819 #ifdef __i386__ 820 u_int32_t sf_pad; 821 #endif 822 struct mbuf *sf_mbuf; 823 u_int32_t sf_rsvd0:24, 824 sf_crcen:1, 825 sf_caltcp:1, 826 sf_end:1, 827 sf_intr:1, 828 sf_id:4; 829 u_int8_t sf_fragcnt; 830 u_int8_t sf_rsvd2; 831 u_int16_t sf_rsvd1; 832 struct sf_frag sf_frags[14]; 833 }; 834 835 /* 836 * TX buffer descriptor type 1, 32-bit addressing. Each descriptor 837 * maps a single fragment. 838 */ 839 struct sf_tx_bufdesc_type1 { 840 #ifdef __i386__ 841 u_int32_t sf_pad; 842 #endif 843 struct mbuf *sf_mbuf; 844 u_int32_t sf_fraglen:16, 845 sf_fragcnt:8, 846 sf_crcen:1, 847 sf_caltcp:1, 848 sf_end:1, 849 sf_intr:1, 850 sf_id:4; 851 u_int32_t sf_addr; 852 }; 853 854 /* 855 * TX buffer descriptor type 2, 64-bit addressing. Each descriptor 856 * maps a single fragment. 857 */ 858 struct sf_tx_bufdesc_type2 { 859 #ifdef __i386__ 860 u_int32_t sf_pad; 861 #endif 862 struct mbuf *sf_mbuf; 863 u_int32_t sf_fraglen:16, 864 sf_fragcnt:8, 865 sf_crcen:1, 866 sf_caltcp:1, 867 sf_end:1, 868 sf_intr:1, 869 sf_id:4; 870 u_int32_t sf_addrlo; 871 u_int32_t sf_addrhi; 872 }; 873 874 /* TX buffer descriptor type 3 is not defined. */ 875 876 /* 877 * TX frame descriptor type 4, 32-bit addressing. This is a special 878 * case of the type 0 descriptor, identical except that the fragment 879 * address and length fields are ordered differently. This is done 880 * to optimize copies in MS-DOS and OS/2 drivers. 881 */ 882 struct sf_tx_bufdesc_type4 { 883 #ifdef __i386__ 884 u_int32_t sf_pad; 885 #endif 886 struct mbuf *sf_mbuf; 887 u_int32_t sf_rsvd0:24, 888 sf_crcen:1, 889 sf_caltcp:1, 890 sf_end:1, 891 sf_intr:1, 892 sf_id:4; 893 u_int8_t sf_fragcnt; 894 u_int8_t sf_rsvd2; 895 u_int16_t sf_rsvd1; 896 struct sf_frag_msdos sf_frags[14]; 897 }; 898 899 /* 900 * Transmit completion queue descriptor formats. 901 */ 902 903 /* 904 * Transmit DMA completion descriptor, type 0. 905 */ 906 #define SF_TXCMPTYPE_DMA 0x4 907 struct sf_tx_cmpdesc_type0 { 908 u_int32_t sf_index:15, 909 sf_priority:1, 910 sf_timestamp:13, 911 sf_type:3; 912 }; 913 914 /* 915 * Transmit completion descriptor, type 1. 916 */ 917 #define SF_TXCMPTYPE_TX 0x5 918 struct sf_tx_cmpdesc_type1 { 919 u_int32_t sf_index:15, 920 sf_priority:1, 921 sf_txstat:13, 922 sf_type:3; 923 }; 924 925 #define SF_TXSTAT_CRCERR 0x0001 926 #define SF_TXSTAT_LENCHECKERR 0x0002 927 #define SF_TXSTAT_LENRANGEERR 0x0004 928 #define SF_TXSTAT_TX_OK 0x0008 929 #define SF_TXSTAT_TX_DEFERED 0x0010 930 #define SF_TXSTAT_EXCESS_DEFER 0x0020 931 #define SF_TXSTAT_EXCESS_COLL 0x0040 932 #define SF_TXSTAT_LATE_COLL 0x0080 933 #define SF_TXSTAT_TOOBIG 0x0100 934 #define SF_TXSTAT_TX_UNDERRUN 0x0200 935 #define SF_TXSTAT_CTLFRAME_OK 0x0400 936 #define SF_TXSTAT_PAUSEFRAME_OK 0x0800 937 #define SF_TXSTAT_PAUSED 0x1000 938 939 /* Statistics counters. */ 940 struct sf_stats { 941 u_int32_t sf_tx_frames; 942 u_int32_t sf_tx_single_colls; 943 u_int32_t sf_tx_multi_colls; 944 u_int32_t sf_tx_crcerrs; 945 u_int32_t sf_tx_bytes; 946 u_int32_t sf_tx_defered; 947 u_int32_t sf_tx_late_colls; 948 u_int32_t sf_tx_pause_frames; 949 u_int32_t sf_tx_control_frames; 950 u_int32_t sf_tx_excess_colls; 951 u_int32_t sf_tx_excess_defer; 952 u_int32_t sf_tx_mcast_frames; 953 u_int32_t sf_tx_bcast_frames; 954 u_int32_t sf_tx_frames_lost; 955 u_int32_t sf_rx_rx_frames; 956 u_int32_t sf_rx_crcerrs; 957 u_int32_t sf_rx_alignerrs; 958 u_int32_t sf_rx_bytes; 959 u_int32_t sf_rx_control_frames; 960 u_int32_t sf_rx_unsup_control_frames; 961 u_int32_t sf_rx_giants; 962 u_int32_t sf_rx_runts; 963 u_int32_t sf_rx_jabbererrs; 964 u_int32_t sf_rx_pkts_64; 965 u_int32_t sf_rx_pkts_65_127; 966 u_int32_t sf_rx_pkts_128_255; 967 u_int32_t sf_rx_pkts_256_511; 968 u_int32_t sf_rx_pkts_512_1023; 969 u_int32_t sf_rx_pkts_1024_1518; 970 u_int32_t sf_rx_frames_lost; 971 u_int16_t sf_tx_underruns; 972 u_int16_t sf_pad; 973 }; 974 975 /* 976 * register space access macros 977 */ 978 #define CSR_WRITE_4(sc, reg, val) \ 979 bus_space_write_4(sc->sf_btag, sc->sf_bhandle, reg, val) 980 981 #define CSR_READ_4(sc, reg) \ 982 bus_space_read_4(sc->sf_btag, sc->sf_bhandle, reg) 983 984 #define CSR_READ_1(sc, reg) \ 985 bus_space_read_1(sc->sf_btag, sc->sf_bhandle, reg) 986 987 988 struct sf_type { 989 u_int16_t sf_vid; 990 u_int16_t sf_did; 991 char *sf_name; 992 }; 993 994 #define SF_INC(x, y) (x) = (x + 1) % y 995 996 #define ETHER_ALIGN 2 997 998 /* 999 * Note: alignment is important here: each list must be aligned to 1000 * a 256-byte boundary. It turns out that each ring is some multiple 1001 * of 4K in length, so we can stack them all on top of each other 1002 * and just worry about aligning the whole mess. There's one transmit 1003 * buffer ring and two receive buffer rings: one RX ring is for small 1004 * packets and the other is for large packets. Each buffer ring also 1005 * has a companion completion queue. 1006 */ 1007 struct sf_list_data { 1008 struct sf_tx_bufdesc_type0 sf_tx_dlist[SF_TX_DLIST_CNT]; 1009 struct sf_tx_cmpdesc_type1 sf_tx_clist[SF_TX_CLIST_CNT]; 1010 struct sf_rx_bufdesc_type0 sf_rx_dlist_big[SF_RX_DLIST_CNT]; 1011 #ifdef notdef 1012 /* 1013 * Unfortunately, because the Starfire doesn't allow arbitrary 1014 * byte alignment, we have to copy packets in the RX handler in 1015 * order to align the payload correctly. This means that we 1016 * don't gain anything by having separate large and small descriptor 1017 * lists, so for now we don't bother with the small one. 1018 */ 1019 struct sf_rx_bufdesc_type0 sf_rx_dlist_small[SF_RX_DLIST_CNT]; 1020 #endif 1021 struct sf_rx_cmpdesc_type3 sf_rx_clist[SF_RX_CLIST_CNT]; 1022 }; 1023 1024 struct sf_softc { 1025 struct arpcom arpcom; /* interface info */ 1026 bus_space_handle_t sf_bhandle; /* bus space handle */ 1027 bus_space_tag_t sf_btag; /* bus space tag */ 1028 void *sf_intrhand; /* interrupt handler cookie */ 1029 struct resource *sf_irq; /* irq resource descriptor */ 1030 struct resource *sf_res; /* mem/ioport resource */ 1031 struct sf_type *sf_info; /* Starfire adapter info */ 1032 device_t sf_miibus; 1033 u_int8_t sf_unit; /* interface number */ 1034 struct sf_list_data *sf_ldata; 1035 int sf_tx_cnt; 1036 u_int8_t sf_link; 1037 int sf_if_flags; 1038 struct callout sf_stat_timer; 1039 }; 1040 1041 #define SF_TIMEOUT 1000 1042