1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sfreg.h,v 1.6.2.1 2001/08/16 20:35:04 wpaul Exp $ 33 * $DragonFly: src/sys/dev/netif/sf/if_sfreg.h,v 1.2 2003/06/17 04:28:57 dillon Exp $ 34 */ 35 36 /* 37 * Registers for the Adaptec AIC-6915 Starfire. The Starfire has a 512K 38 * register space. These registers can be accessed in the following way: 39 * - PCI config registers are always accessible through PCI config space 40 * - Full 512K space mapped into memory using PCI memory mapped access 41 * - 256-byte I/O space mapped through PCI I/O access 42 * - Full 512K space mapped through indirect I/O using PCI I/O access 43 * It's possible to use either memory mapped mode or I/O mode to access 44 * the registers, but memory mapped is usually the easiest. All registers 45 * are 32 bits wide and must be accessed using 32-bit operations. 46 */ 47 48 /* 49 * Adaptec PCI vendor ID. 50 */ 51 #define AD_VENDORID 0x9004 52 53 /* 54 * AIC-6915 PCI device ID. 55 */ 56 #define AD_DEVICEID_STARFIRE 0x6915 57 58 /* 59 * AIC-6915 subsystem IDs. Adaptec uses the subsystem ID to identify 60 * the exact kind of NIC on which the ASIC is mounted. Currently there 61 * are six different variations. Note: the Adaptec manual lists code 0x28 62 * for two different NICs: the 62044 and the 69011/TX. This is a typo: 63 * the code for the 62044 is really 0x18. 64 * 65 * Note that there also appears to be an 0x19 code for a newer rev 66 * 62044 card. 67 */ 68 #define AD_SUBSYSID_62011_REV0 0x0008 /* single port 10/100baseTX 64-bit */ 69 #define AD_SUBSYSID_62011_REV1 0x0009 /* single port 10/100baseTX 64-bit */ 70 #define AD_SUBSYSID_62022 0x0010 /* dual port 10/100baseTX 64-bit */ 71 #define AD_SUBSYSID_62044_REV0 0x0018 /* quad port 10/100baseTX 64-bit */ 72 #define AD_SUBSYSID_62044_REV1 0x0019 /* quad port 10/100baseTX 64-bit */ 73 #define AD_SUBSYSID_62020 0x0020 /* single port 10/100baseFX 64-bit */ 74 #define AD_SUBSYSID_69011 0x0028 /* single port 10/100baseTX 32-bit */ 75 76 /* 77 * Starfire internal register space map. The entire register space 78 * is available using PCI memory mapped mode. The SF_RMAP_INTREG 79 * space is available using PCI I/O mode. The entire space can be 80 * accessed using indirect I/O using the indirect I/O addr and 81 * indirect I/O data registers located within the SF_RMAP_INTREG space. 82 */ 83 #define SF_RMAP_ROMADDR_BASE 0x00000 /* Expansion ROM space */ 84 #define SF_RMAP_ROMADDR_MAX 0x3FFFF 85 86 #define SF_RMAP_EXGPIO_BASE 0x40000 /* External general purpose regs */ 87 #define SF_RMAP_EXGPIO_MAX 0x3FFFF 88 89 #define SF_RMAP_INTREG_BASE 0x50000 /* Internal functional registers */ 90 #define SF_RMAP_INTREG_MAX 0x500FF 91 #define SF_RMAP_GENREG_BASE 0x50100 /* General purpose registers */ 92 #define SF_RMAP_GENREG_MAX 0x5FFFF 93 94 #define SF_RMAP_FIFO_BASE 0x60000 95 #define SF_RMAP_FIFO_MAX 0x6FFFF 96 97 #define SF_RMAP_STS_BASE 0x70000 98 #define SF_RMAP_STS_MAX 0x70083 99 100 #define SF_RMAP_RSVD_BASE 0x70084 101 #define SF_RMAP_RSVD_MAX 0x7FFFF 102 103 /* 104 * PCI config header registers, 0x0000 to 0x003F 105 */ 106 #define SF_PCI_VENDOR_ID 0x0000 107 #define SF_PCI_DEVICE_ID 0x0002 108 #define SF_PCI_COMMAND 0x0004 109 #define SF_PCI_STATUS 0x0006 110 #define SF_PCI_REVID 0x0008 111 #define SF_PCI_CLASSCODE 0x0009 112 #define SF_PCI_CACHELEN 0x000C 113 #define SF_PCI_LATENCY_TIMER 0x000D 114 #define SF_PCI_HEADER_TYPE 0x000E 115 #define SF_PCI_LOMEM 0x0010 116 #define SF_PCI_LOIO 0x0014 117 #define SF_PCI_SUBVEN_ID 0x002C 118 #define SF_PCI_SYBSYS_ID 0x002E 119 #define SF_PCI_BIOSROM 0x0030 120 #define SF_PCI_INTLINE 0x003C 121 #define SF_PCI_INTPIN 0x003D 122 #define SF_PCI_MINGNT 0x003E 123 #define SF_PCI_MINLAT 0x003F 124 125 /* 126 * PCI registers, 0x0040 to 0x006F 127 */ 128 #define SF_PCI_DEVCFG 0x0040 129 #define SF_BACCTL 0x0044 130 #define SF_PCI_MON1 0x0048 131 #define SF_PCI_MON2 0x004C 132 #define SF_PCI_CAPID 0x0050 /* 8 bits */ 133 #define SF_PCI_NEXTPTR 0x0051 /* 8 bits */ 134 #define SF_PCI_PWRMGMTCAP 0x0052 /* 16 bits */ 135 #define SF_PCI_PWRMGMTCTRL 0x0054 /* 16 bits */ 136 #define SF_PCI_PME_EVENT 0x0058 137 #define SF_PCI_EECTL 0x0060 138 #define SF_PCI_COMPLIANCE 0x0064 139 #define SF_INDIRECTIO_ADDR 0x0068 140 #define SF_INDIRECTIO_DATA 0x006C 141 142 #define SF_PCIDEVCFG_RESET 0x00000001 143 #define SF_PCIDEVCFG_FORCE64 0x00000002 144 #define SF_PCIDEVCFG_SYSTEM64 0x00000004 145 #define SF_PCIDEVCFG_RSVD0 0x00000008 146 #define SF_PCIDEVCFG_INCR_INB 0x00000010 147 #define SF_PCIDEVCFG_ABTONPERR 0x00000020 148 #define SF_PCIDEVCFG_STPONPERR 0x00000040 149 #define SF_PCIDEVCFG_MR_ENB 0x00000080 150 #define SF_PCIDEVCFG_FIFOTHR 0x00000F00 151 #define SF_PCIDEVCFG_STPONCA 0x00001000 152 #define SF_PCIDEVCFG_PCIMEN 0x00002000 /* enable PCI bus master */ 153 #define SF_PCIDEVCFG_LATSTP 0x00004000 154 #define SF_PCIDEVCFG_BYTE_ENB 0x00008000 155 #define SF_PCIDEVCFG_EECSWIDTH 0x00070000 156 #define SF_PCIDEVCFG_STPMWCA 0x00080000 157 #define SF_PCIDEVCFG_REGCSWIDTH 0x00700000 158 #define SF_PCIDEVCFG_INTR_ENB 0x00800000 159 #define SF_PCIDEVCFG_DPR_ENB 0x01000000 160 #define SF_PCIDEVCFG_RSVD1 0x02000000 161 #define SF_PCIDEVCFG_RSVD2 0x04000000 162 #define SF_PCIDEVCFG_STA_ENB 0x08000000 163 #define SF_PCIDEVCFG_RTA_ENB 0x10000000 164 #define SF_PCIDEVCFG_RMA_ENB 0x20000000 165 #define SF_PCIDEVCFG_SSE_ENB 0x40000000 166 #define SF_PCIDEVCFG_DPE_ENB 0x80000000 167 168 #define SF_BACCTL_BACDMA_ENB 0x00000001 169 #define SF_BACCTL_PREFER_RXDMA 0x00000002 170 #define SF_BACCTL_PREFER_TXDMA 0x00000004 171 #define SF_BACCTL_SINGLE_DMA 0x00000008 172 #define SF_BACCTL_SWAPMODE_DATA 0x00000030 173 #define SF_BACCTL_SWAPMODE_DESC 0x000000C0 174 175 #define SF_SWAPMODE_LE 0x00000000 176 #define SF_SWAPMODE_BE 0x00000010 177 178 #define SF_PSTATE_MASK 0x0003 179 #define SF_PSTATE_D0 0x0000 180 #define SF_PSTATE_D1 0x0001 181 #define SF_PSTATE_D2 0x0002 182 #define SF_PSTATE_D3 0x0003 183 #define SF_PME_EN 0x0010 184 #define SF_PME_STATUS 0x8000 185 186 187 /* 188 * Ethernet registers 0x0070 to 0x00FF 189 */ 190 #define SF_GEN_ETH_CTL 0x0070 191 #define SF_TIMER_CTL 0x0074 192 #define SF_CURTIME 0x0078 193 #define SF_ISR 0x0080 194 #define SF_ISR_SHADOW 0x0084 195 #define SF_IMR 0x0088 196 #define SF_GPIO 0x008C 197 #define SF_TXDQ_CTL 0x0090 198 #define SF_TXDQ_ADDR_HIPRIO 0x0094 199 #define SF_TXDQ_ADDR_LOPRIO 0x0098 200 #define SF_TXDQ_ADDR_HIADDR 0x009C 201 #define SF_TXDQ_PRODIDX 0x00A0 202 #define SF_TXDQ_CONSIDX 0x00A4 203 #define SF_TXDMA_STS1 0x00A8 204 #define SF_TXDMA_STS2 0x00AC 205 #define SF_TX_FRAMCTL 0x00B0 206 #define SF_TXCQ_ADDR_HI 0x00B4 207 #define SF_TXCQ_CTL 0x00B8 208 #define SF_RXCQ_CTL_1 0x00BC 209 #define SF_RXCQ_CTL_2 0x00C0 210 #define SF_CQ_CONSIDX 0x00C4 211 #define SF_CQ_PRODIDX 0x00C8 212 #define SF_CQ_RXQ2 0x00CC 213 #define SF_RXDMA_CTL 0x00D0 214 #define SF_RXDQ_CTL_1 0x00D4 215 #define SF_RXDQ_CTL_2 0x00D8 216 #define SF_RXDQ_ADDR_HIADDR 0x00DC 217 #define SF_RXDQ_ADDR_Q1 0x00E0 218 #define SF_RXDQ_ADDR_Q2 0x00E4 219 #define SF_RXDQ_PTR_Q1 0x00E8 220 #define SF_RXDQ_PTR_Q2 0x00EC 221 #define SF_RXDMA_STS 0x00F0 222 #define SF_RXFILT 0x00F4 223 #define SF_RX_FRAMETEST_OUT 0x00F8 224 225 /* Ethernet control register */ 226 #define SF_ETHCTL_RX_ENB 0x00000001 227 #define SF_ETHCTL_TX_ENB 0x00000002 228 #define SF_ETHCTL_RXDMA_ENB 0x00000004 229 #define SF_ETHCTL_TXDMA_ENB 0x00000008 230 #define SF_ETHCTL_RXGFP_ENB 0x00000010 231 #define SF_ETHCTL_TXGFP_ENB 0x00000020 232 #define SF_ETHCTL_SOFTINTR 0x00000800 233 234 /* Timer control register */ 235 #define SF_TIMER_IMASK_INTERVAL 0x0000001F 236 #define SF_TIMER_IMASK_MODE 0x00000060 237 #define SF_TIMER_SMALLFRAME_BYP 0x00000100 238 #define SF_TIMER_SMALLRX_FRAME 0x00000600 239 #define SF_TIMER_TIMES_TEN 0x00000800 240 #define SF_TIMER_RXHIPRIO_BYP 0x00001000 241 #define SF_TIMER_TX_DMADONE_DLY 0x00002000 242 #define SF_TIMER_TX_QDONE_DLY 0x00004000 243 #define SF_TIMER_TX_FRDONE_DLY 0x00008000 244 #define SF_TIMER_GENTIMER 0x00FF0000 245 #define SF_TIMER_ONESHOT 0x01000000 246 #define SF_TIMER_GENTIMER_RES 0x02000000 247 #define SF_TIMER_TIMEST_RES 0x04000000 248 #define SF_TIMER_RXQ2DONE_DLY 0x10000000 249 #define SF_TIMER_EARLYRX2_DLY 0x20000000 250 #define SF_TIMER_RXQ1DONE_DLY 0x40000000 251 #define SF_TIMER_EARLYRX1_DLY 0x80000000 252 253 /* Interrupt status register */ 254 #define SF_ISR_PCIINT_ASSERTED 0x00000001 255 #define SF_ISR_GFP_TX 0x00000002 256 #define SF_ISR_GFP_RX 0x00000004 257 #define SF_ISR_TX_BADID_HIPRIO 0x00000008 258 #define SF_ISR_TX_BADID_LOPRIO 0x00000010 259 #define SF_ISR_NO_TX_CSUM 0x00000020 260 #define SF_ISR_RXDQ2_NOBUFS 0x00000040 261 #define SF_ISR_RXGFP_NORESP 0x00000080 262 #define SF_ISR_RXDQ1_DMADONE 0x00000100 263 #define SF_ISR_RXDQ2_DMADONE 0x00000200 264 #define SF_ISR_RXDQ1_EARLY 0x00000400 265 #define SF_ISR_RXDQ2_EARLY 0x00000800 266 #define SF_ISR_TX_QUEUEDONE 0x00001000 267 #define SF_ISR_TX_DMADONE 0x00002000 268 #define SF_ISR_TX_TXDONE 0x00004000 269 #define SF_ISR_NORMALINTR 0x00008000 270 #define SF_ISR_RXDQ1_NOBUFS 0x00010000 271 #define SF_ISR_RXCQ2_NOBUFS 0x00020000 272 #define SF_ISR_TX_LOFIFO 0x00040000 273 #define SF_ISR_DMAERR 0x00080000 274 #define SF_ISR_PCIINT 0x00100000 275 #define SF_ISR_TXCQ_NOBUFS 0x00200000 276 #define SF_ISR_RXCQ1_NOBUFS 0x00400000 277 #define SF_ISR_SOFTINTR 0x00800000 278 #define SF_ISR_GENTIMER 0x01000000 279 #define SF_ISR_ABNORMALINTR 0x02000000 280 #define SF_ISR_RSVD0 0x04000000 281 #define SF_ISR_STATSOFLOW 0x08000000 282 #define SF_ISR_GPIO 0xF0000000 283 284 /* 285 * Shadow interrupt status register. Unlike the normal IRQ register, 286 * reading bits here does not automatically cause them to reset. 287 */ 288 #define SF_SISR_PCIINT_ASSERTED 0x00000001 289 #define SF_SISR_GFP_TX 0x00000002 290 #define SF_SISR_GFP_RX 0x00000004 291 #define SF_SISR_TX_BADID_HIPRIO 0x00000008 292 #define SF_SISR_TX_BADID_LOPRIO 0x00000010 293 #define SF_SISR_NO_TX_CSUM 0x00000020 294 #define SF_SISR_RXDQ2_NOBUFS 0x00000040 295 #define SF_SISR_RXGFP_NORESP 0x00000080 296 #define SF_SISR_RXDQ1_DMADONE 0x00000100 297 #define SF_SISR_RXDQ2_DMADONE 0x00000200 298 #define SF_SISR_RXDQ1_EARLY 0x00000400 299 #define SF_SISR_RXDQ2_EARLY 0x00000800 300 #define SF_SISR_TX_QUEUEDONE 0x00001000 301 #define SF_SISR_TX_DMADONE 0x00002000 302 #define SF_SISR_TX_TXDONE 0x00004000 303 #define SF_SISR_NORMALINTR 0x00008000 304 #define SF_SISR_RXDQ1_NOBUFS 0x00010000 305 #define SF_SISR_RXCQ2_NOBUFS 0x00020000 306 #define SF_SISR_TX_LOFIFO 0x00040000 307 #define SF_SISR_DMAERR 0x00080000 308 #define SF_SISR_PCIINT 0x00100000 309 #define SF_SISR_TXCQ_NOBUFS 0x00200000 310 #define SF_SISR_RXCQ1_NOBUFS 0x00400000 311 #define SF_SISR_SOFTINTR 0x00800000 312 #define SF_SISR_GENTIMER 0x01000000 313 #define SF_SISR_ABNORMALINTR 0x02000000 314 #define SF_SISR_RSVD0 0x04000000 315 #define SF_SISR_STATSOFLOW 0x08000000 316 #define SF_SISR_GPIO 0xF0000000 317 318 /* Interrupt mask register */ 319 #define SF_IMR_PCIINT_ASSERTED 0x00000001 320 #define SF_IMR_GFP_TX 0x00000002 321 #define SF_IMR_GFP_RX 0x00000004 322 #define SF_IMR_TX_BADID_HIPRIO 0x00000008 323 #define SF_IMR_TX_BADID_LOPRIO 0x00000010 324 #define SF_IMR_NO_TX_CSUM 0x00000020 325 #define SF_IMR_RXDQ2_NOBUFS 0x00000040 326 #define SF_IMR_RXGFP_NORESP 0x00000080 327 #define SF_IMR_RXDQ1_DMADONE 0x00000100 328 #define SF_IMR_RXDQ2_DMADONE 0x00000200 329 #define SF_IMR_RXDQ1_EARLY 0x00000400 330 #define SF_IMR_RXDQ2_EARLY 0x00000800 331 #define SF_IMR_TX_QUEUEDONE 0x00001000 332 #define SF_IMR_TX_DMADONE 0x00002000 333 #define SF_IMR_TX_TXDONE 0x00004000 334 #define SF_IMR_NORMALINTR 0x00008000 335 #define SF_IMR_RXDQ1_NOBUFS 0x00010000 336 #define SF_IMR_RXCQ2_NOBUFS 0x00020000 337 #define SF_IMR_TX_LOFIFO 0x00040000 338 #define SF_IMR_DMAERR 0x00080000 339 #define SF_IMR_PCIINT 0x00100000 340 #define SF_IMR_TXCQ_NOBUFS 0x00200000 341 #define SF_IMR_RXCQ1_NOBUFS 0x00400000 342 #define SF_IMR_SOFTINTR 0x00800000 343 #define SF_IMR_GENTIMER 0x01000000 344 #define SF_IMR_ABNORMALINTR 0x02000000 345 #define SF_IMR_RSVD0 0x04000000 346 #define SF_IMR_STATSOFLOW 0x08000000 347 #define SF_IMR_GPIO 0xF0000000 348 349 #define SF_INTRS \ 350 (SF_IMR_RXDQ2_NOBUFS|SF_IMR_RXDQ1_DMADONE|SF_IMR_RXDQ2_DMADONE| \ 351 SF_IMR_TX_TXDONE|SF_IMR_RXDQ1_NOBUFS|SF_IMR_RXDQ2_DMADONE| \ 352 SF_IMR_NORMALINTR|SF_IMR_ABNORMALINTR|SF_IMR_TXCQ_NOBUFS| \ 353 SF_IMR_RXCQ1_NOBUFS|SF_IMR_RXCQ2_NOBUFS|SF_IMR_STATSOFLOW| \ 354 SF_IMR_TX_LOFIFO) 355 356 /* TX descriptor queue control registers */ 357 #define SF_TXDQCTL_DESCTYPE 0x00000007 358 #define SF_TXDQCTL_NODMACMP 0x00000008 359 #define SF_TXDQCTL_MINSPACE 0x00000070 360 #define SF_TXDQCTL_64BITADDR 0x00000080 361 #define SF_TXDQCTL_BURSTLEN 0x00003F00 362 #define SF_TXDQCTL_SKIPLEN 0x001F0000 363 #define SF_TXDQCTL_HIPRIOTHRESH 0xFF000000 364 365 #define SF_TXBUFDESC_TYPE0 0x00000000 366 #define SF_TXBUFDESC_TYPE1 0x00000001 367 #define SF_TXBUFDESC_TYPE2 0x00000002 368 #define SF_TXBUFDESC_TYPE3 0x00000003 369 #define SF_TXBUFDESC_TYPE4 0x00000004 370 371 #define SF_TXMINSPACE_UNLIMIT 0x00000000 372 #define SF_TXMINSPACE_32BYTES 0x00000010 373 #define SF_TXMINSPACE_64BYTES 0x00000020 374 #define SF_TXMINSPACE_128BYTES 0x00000030 375 #define SF_TXMINSPACE_256BYTES 0x00000040 376 377 #define SF_TXSKIPLEN_0BYTES 0x00000000 378 #define SF_TXSKIPLEN_8BYTES 0x00010000 379 #define SF_TXSKIPLEN_16BYTES 0x00020000 380 #define SF_TXSKIPLEN_24BYTES 0x00030000 381 #define SF_TXSKIPLEN_32BYTES 0x00040000 382 383 /* TX frame control register */ 384 #define SF_TXFRMCTL_TXTHRESH 0x000000FF 385 #define SF_TXFRMCTL_CPLAFTERTX 0x00000100 386 #define SF_TXFRMCRL_DEBUG 0x0000FE00 387 #define SF_TXFRMCTL_STATUS 0x01FF0000 388 #define SF_TXFRMCTL_MAC_TXIF 0xFE000000 389 390 /* TX completion queue control register */ 391 #define SF_TXCQ_THRESH 0x0000000F 392 #define SF_TXCQ_COMMON 0x00000010 393 #define SF_TXCQ_SIZE 0x00000020 394 #define SF_TXCQ_WRITEENB 0x00000040 395 #define SF_TXCQ_USE_64BIT 0x00000080 396 #define SF_TXCQ_ADDR 0xFFFFFF00 397 398 /* RX completion queue control register */ 399 #define SF_RXCQ_THRESH 0x0000000F 400 #define SF_RXCQ_TYPE 0x00000030 401 #define SF_RXCQ_WRITEENB 0x00000040 402 #define SF_RXCQ_USE_64BIT 0x00000080 403 #define SF_RXCQ_ADDR 0xFFFFFF00 404 405 #define SF_RXCQTYPE_0 0x00000000 406 #define SF_RXCQTYPE_1 0x00000010 407 #define SF_RXCQTYPE_2 0x00000020 408 #define SF_RXCQTYPE_3 0x00000030 409 410 /* TX descriptor queue producer index register */ 411 #define SF_TXDQ_PRODIDX_LOPRIO 0x000007FF 412 #define SF_TXDQ_PRODIDX_HIPRIO 0x07FF0000 413 414 /* TX descriptor queue consumer index register */ 415 #define SF_TXDQ_CONSIDX_LOPRIO 0x000007FF 416 #define SF_TXDQ_CONSIDX_HIPRIO 0x07FF0000 417 418 /* Completion queue consumer index register */ 419 #define SF_CQ_CONSIDX_RXQ1 0x000003FF 420 #define SF_CQ_CONSIDX_RXTHRMODE 0x00008000 421 #define SF_CQ_CONSIDX_TXQ 0x03FF0000 422 #define SF_CQ_CONSIDX_TXTHRMODE 0x80000000 423 424 /* Completion queue producer index register */ 425 #define SF_CQ_PRODIDX_RXQ1 0x000003FF 426 #define SF_CQ_PRODIDX_TXQ 0x03FF0000 427 428 /* RX completion queue 2 consumer/producer index register */ 429 #define SF_CQ_RXQ2_CONSIDX 0x000003FF 430 #define SF_CQ_RXQ2_RXTHRMODE 0x00008000 431 #define SF_CQ_RXQ2_PRODIDX 0x03FF0000 432 433 #define SF_CQ_RXTHRMODE_INT_ON 0x00008000 434 #define SF_CQ_RXTHRMODE_INT_OFF 0x00000000 435 #define SF_CQ_TXTHRMODE_INT_ON 0x80000000 436 #define SF_CQ_TXTHRMODE_INT_OFF 0x00000000 437 438 #define SF_IDX_LO(x) ((x) & 0x000007FF) 439 #define SF_IDX_HI(x) (((x) >> 16) & 0x000007FF) 440 441 /* RX DMA control register */ 442 #define SF_RXDMA_BURSTSIZE 0x0000007F 443 #define SF_RXDMA_FPTESTMODE 0x00000080 444 #define SF_RXDMA_HIPRIOTHRESH 0x00000F00 445 #define SF_RXDMA_RXEARLYTHRESH 0x0001F000 446 #define SF_RXDMA_DMACRC 0x00040000 447 #define SF_RXDMA_USEBKUPQUEUE 0x00080000 448 #define SF_RXDMA_QUEUEMODE 0x00700000 449 #define SF_RXDMA_RXCQ2_ON 0x00800000 450 #define SF_RXDMA_CSUMMODE 0x03000000 451 #define SF_RXDMA_DMAPAUSEPKTS 0x04000000 452 #define SF_RXDMA_DMACTLPKTS 0x08000000 453 #define SF_RXDMA_DMACRXERRPKTS 0x10000000 454 #define SF_RXDMA_DMABADPKTS 0x20000000 455 #define SF_RXDMA_DMARUNTS 0x40000000 456 #define SF_RXDMA_REPORTBADPKTS 0x80000000 457 458 #define SF_RXDQMODE_Q1ONLY 0x00100000 459 #define SF_RXDQMODE_Q2_ON_FP 0x00200000 460 #define SF_RXDQMODE_Q2_ON_SHORT 0x00300000 461 #define SF_RXDQMODE_Q2_ON_PRIO 0x00400000 462 #define SF_RXDQMODE_SPLITHDR 0x00500000 463 464 #define SF_RXCSUMMODE_IGNORE 0x00000000 465 #define SF_RXCSUMMODE_REJECT_BAD_TCP 0x01000000 466 #define SF_RXCSUMMODE_REJECT_BAD_TCPUDP 0x02000000 467 #define SF_RXCSUMMODE_RSVD 0x03000000 468 469 /* RX descriptor queue control registers */ 470 #define SF_RXDQCTL_MINDESCTHR 0x0000007F 471 #define SF_RXDQCTL_Q1_WE 0x00000080 472 #define SF_RXDQCTL_DESCSPACE 0x00000700 473 #define SF_RXDQCTL_64BITDADDR 0x00000800 474 #define SF_RXDQCTL_64BITBADDR 0x00001000 475 #define SF_RXDQCTL_VARIABLE 0x00002000 476 #define SF_RXDQCTL_ENTRIES 0x00004000 477 #define SF_RXDQCTL_PREFETCH 0x00008000 478 #define SF_RXDQCTL_BUFLEN 0xFFFF0000 479 480 #define SF_DESCSPACE_4BYTES 0x00000000 481 #define SF_DESCSPACE_8BYTES 0x00000100 482 #define SF_DESCSPACE_16BYTES 0x00000200 483 #define SF_DESCSPACE_32BYTES 0x00000300 484 #define SF_DESCSPACE_64BYTES 0x00000400 485 #define SF_DESCSPACE_128_BYTES 0x00000500 486 487 /* RX buffer consumer/producer index registers */ 488 #define SF_RXDQ_PRODIDX 0x000007FF 489 #define SF_RXDQ_CONSIDX 0x07FF0000 490 491 /* RX filter control register */ 492 #define SF_RXFILT_PROMISC 0x00000001 493 #define SF_RXFILT_ALLMULTI 0x00000002 494 #define SF_RXFILT_BROAD 0x00000004 495 #define SF_RXFILT_HASHPRIO 0x00000008 496 #define SF_RXFILT_HASHMODE 0x00000030 497 #define SF_RXFILT_PERFMODE 0x000000C0 498 #define SF_RXFILT_VLANMODE 0x00000300 499 #define SF_RXFILT_WAKEMODE 0x00000C00 500 #define SF_RXFILT_MULTI_NOBROAD 0x00001000 501 #define SF_RXFILT_MIN_VLANPRIO 0x0000E000 502 #define SF_RXFILT_PEFECTPRIO 0xFFFF0000 503 504 /* Hash filtering mode */ 505 #define SF_HASHMODE_OFF 0x00000000 506 #define SF_HASHMODE_WITHVLAN 0x00000010 507 #define SF_HASHMODE_ANYVLAN 0x00000020 508 #define SF_HASHMODE_ANY 0x00000030 509 510 /* Perfect filtering mode */ 511 #define SF_PERFMODE_OFF 0x00000000 512 #define SF_PERFMODE_NORMAL 0x00000040 513 #define SF_PERFMODE_INVERSE 0x00000080 514 #define SF_PERFMODE_VLAN 0x000000C0 515 516 /* VLAN mode */ 517 #define SF_VLANMODE_OFF 0x00000000 518 #define SF_VLANMODE_NOSTRIP 0x00000100 519 #define SF_VLANMODE_STRIP 0x00000200 520 #define SF_VLANMODE_RSVD 0x00000300 521 522 /* Wakeup mode */ 523 #define SF_WAKEMODE_OFF 0x00000000 524 #define SF_WAKEMODE_FILTER 0x00000400 525 #define SF_WAKEMODE_FP 0x00000800 526 #define SF_WAKEMODE_HIPRIO 0x00000C00 527 528 /* 529 * Extra PCI registers 0x0100 to 0x0FFF 530 */ 531 #define SF_PCI_TARGSTAT 0x0100 532 #define SF_PCI_MASTSTAT1 0x0104 533 #define SF_PCI_MASTSTAT2 0x0108 534 #define SF_PCI_DMAHOSTADDR_LO 0x010C 535 #define SF_BAC_DMADIAG0 0x0110 536 #define SF_BAC_DMADIAG1 0x0114 537 #define SF_BAC_DMADIAG2 0x0118 538 #define SF_BAC_DMADIAG3 0x011C 539 #define SF_PAR0 0x0120 540 #define SF_PAR1 0x0124 541 #define SF_PCICB_FUNCEVENT 0x0130 542 #define SF_PCICB_FUNCEVENT_MASK 0x0134 543 #define SF_PCICB_FUNCSTATE 0x0138 544 #define SF_PCICB_FUNCFORCE 0x013C 545 546 /* 547 * Serial EEPROM registers 0x1000 to 0x1FFF 548 * Presumeably the EEPROM is mapped into this 8K window. 549 */ 550 #define SF_EEADDR_BASE 0x1000 551 #define SF_EEADDR_MAX 0x1FFF 552 553 #define SF_EE_NODEADDR 14 554 555 /* 556 * MII registers registers 0x2000 to 0x3FFF 557 * There are 32 sets of 32 registers, one set for each possible 558 * PHY address. Each 32 bit register is split into a 16-bit data 559 * port and a couple of status bits. 560 */ 561 562 #define SF_MIIADDR_BASE 0x2000 563 #define SF_MIIADDR_MAX 0x3FFF 564 #define SF_MII_BLOCKS 32 565 566 #define SF_MII_DATAVALID 0x80000000 567 #define SF_MII_BUSY 0x40000000 568 #define SF_MII_DATAPORT 0x0000FFFF 569 570 #define SF_PHY_REG(phy, reg) \ 571 (SF_MIIADDR_BASE + (phy * SF_MII_BLOCKS * sizeof(u_int32_t)) + \ 572 (reg * sizeof(u_int32_t))) 573 574 /* 575 * Ethernet extra registers 0x4000 to 0x4FFF 576 */ 577 #define SF_TESTMODE 0x4000 578 #define SF_RX_FRAMEPROC_CTL 0x4004 579 #define SF_TX_FRAMEPROC_CTL 0x4008 580 581 /* 582 * MAC registers 0x5000 to 0x5FFF 583 */ 584 #define SF_MACCFG_1 0x5000 585 #define SF_MACCFG_2 0x5004 586 #define SF_BKTOBKIPG 0x5008 587 #define SF_NONBKTOBKIPG 0x500C 588 #define SF_COLRETRY 0x5010 589 #define SF_MAXLEN 0x5014 590 #define SF_TXNIBBLECNT 0x5018 591 #define SF_TXBYTECNT 0x501C 592 #define SF_RETXCNT 0x5020 593 #define SF_RANDNUM 0x5024 594 #define SF_RANDNUM_MASK 0x5028 595 #define SF_TOTALTXCNT 0x5034 596 #define SF_RXBYTECNT 0x5040 597 #define SF_TXPAUSETIMER 0x5060 598 #define SF_VLANTYPE 0x5064 599 #define SF_MIISTATUS 0x5070 600 601 #define SF_MACCFG1_HUGEFRAMES 0x00000001 602 #define SF_MACCFG1_FULLDUPLEX 0x00000002 603 #define SF_MACCFG1_AUTOPAD 0x00000004 604 #define SF_MACCFG1_HDJAM 0x00000008 605 #define SF_MACCFG1_DELAYCRC 0x00000010 606 #define SF_MACCFG1_NOBACKOFF 0x00000020 607 #define SF_MACCFG1_LENGTHCHECK 0x00000040 608 #define SF_MACCFG1_PUREPREAMBLE 0x00000080 609 #define SF_MACCFG1_PASSALLRX 0x00000100 610 #define SF_MACCFG1_PREAM_DETCNT 0x00000200 611 #define SF_MACCFG1_RX_FLOWENB 0x00000400 612 #define SF_MACCFG1_TX_FLOWENB 0x00000800 613 #define SF_MACCFG1_TESTMODE 0x00003000 614 #define SF_MACCFG1_MIILOOPBK 0x00004000 615 #define SF_MACCFG1_SOFTRESET 0x00008000 616 617 /* 618 * There are the recommended IPG nibble counter settings 619 * specified in the Adaptec manual for full duplex and 620 * half duplex operation. 621 */ 622 #define SF_IPGT_FDX 0x15 623 #define SF_IPGT_HDX 0x11 624 625 /* 626 * RX filter registers 0x6000 to 0x6FFF 627 */ 628 #define SF_RXFILT_PERFECT_BASE 0x6000 629 #define SF_RXFILT_PERFECT_MAX 0x60FF 630 #define SF_RXFILT_PERFECT_SKIP 0x0010 631 #define SF_RXFILT_PERFECT_CNT 0x0010 632 633 #define SF_RXFILT_HASH_BASE 0x6100 634 #define SF_RXFILT_HASH_MAX 0x62FF 635 #define SF_RXFILT_HASH_SKIP 0x0010 636 #define SF_RXFILT_HASH_CNT 0x001F 637 #define SF_RXFILT_HASH_ADDROFF 0x0000 638 #define SF_RXFILT_HASH_PRIOOFF 0x0004 639 #define SF_RXFILT_HASH_VLANOFF 0x0008 640 641 /* 642 * Statistics registers 0x7000 to 0x7FFF 643 */ 644 #define SF_STATS_BASE 0x7000 645 #define SF_STATS_END 0x7FFF 646 647 /* 648 * TX frame processor instruction space 0x8000 to 0x9FFF 649 */ 650 651 /* 652 * RX frame processor instruction space 0xA000 to 0xBFFF 653 */ 654 655 /* 656 * Ethernet FIFO access space 0xC000 to 0xDFFF 657 */ 658 659 /* 660 * Reserved 0xE000 to 0xFFFF 661 */ 662 663 /* 664 * Descriptor data structures. 665 */ 666 667 668 /* Receive descriptor formats. */ 669 #define SF_RX_MINSPACING 8 670 #define SF_RX_DLIST_CNT 256 671 #define SF_RX_CLIST_CNT 1024 672 #define SF_RX_HOSTADDR(x) (((x) >> 2) & 0x3FFFFFFF) 673 674 /* 675 * RX buffer descriptor type 0, 32-bit addressing. Note that we 676 * program the RX buffer queue control register(s) to allow a 677 * descriptor spacing of 16 bytes, which leaves room after each 678 * descriptor to store a pointer to the mbuf for each buffer. 679 */ 680 struct sf_rx_bufdesc_type0 { 681 u_int32_t sf_valid:1, 682 sf_end:1, 683 sf_addrlo:30; 684 u_int32_t sf_pad0; 685 #ifdef __i386__ 686 u_int32_t sf_pad1; 687 #endif 688 struct mbuf *sf_mbuf; 689 }; 690 691 /* 692 * RX buffer descriptor type 0, 64-bit addressing. 693 */ 694 struct sf_rx_bufdesc_type1 { 695 u_int32_t sf_valid:1, 696 sf_end:1, 697 sf_addrlo:30; 698 u_int32_t sf_addrhi; 699 #ifdef __i386__ 700 u_int32_t sf_pad; 701 #endif 702 struct mbuf *sf_mbuf; 703 }; 704 705 /* 706 * RX completion descriptor, type 0 (short). 707 */ 708 struct sf_rx_cmpdesc_type0 { 709 u_int32_t sf_len:16, 710 sf_endidx:11, 711 sf_status1:3, 712 sf_id:2; 713 }; 714 715 /* 716 * RX completion descriptor, type 1 (basic). Includes vlan ID 717 * if this is a vlan-addressed packet, plus extended status. 718 */ 719 struct sf_rx_cmpdesc_type1 { 720 u_int32_t sf_len:16, 721 sf_endidx:11, 722 sf_status1:3, 723 sf_id:2; 724 u_int16_t sf_status2; 725 u_int16_t sf_vlanid; 726 }; 727 728 /* 729 * RX completion descriptor, type 2 (checksum). Includes partial TCP/IP 730 * checksum instead of vlan tag, plus extended status. 731 */ 732 struct sf_rx_cmpdesc_type2 { 733 u_int32_t sf_len:16, 734 sf_endidx:11, 735 sf_status1:3, 736 sf_id:2; 737 u_int16_t sf_status2; 738 u_int16_t sf_cksum; 739 }; 740 741 /* 742 * RX completion descriptor type 3 (full). Includes timestamp, partial 743 * TCP/IP checksum, vlan tag plus priority, two extended status fields. 744 */ 745 struct sf_rx_cmpdesc_type3 { 746 u_int32_t sf_len:16, 747 sf_endidx:11, 748 sf_status1:3, 749 sf_id:2; 750 u_int32_t sf_startidx:10, 751 sf_status3:6, 752 sf_status2:16; 753 u_int16_t sf_cksum; 754 u_int16_t sf_vlanid_prio; 755 u_int32_t sf_timestamp; 756 }; 757 758 #define SF_RXSTAT1_QUEUE 0x1 759 #define SF_RXSTAT1_FIFOFULL 0x2 760 #define SF_RXSTAT1_OK 0x4 761 762 /* 0=unknown,5=unsupported */ 763 #define SF_RXSTAT2_FRAMETYPE 0x0007 /* 1=IPv4,2=IPv2,3=IPX,4=ICMP */ 764 #define SF_RXSTAT2_UDP 0x0008 765 #define SF_RXSTAT2_TCP 0x0010 766 #define SF_RXSTAT2_FRAG 0x0020 767 #define SF_RXSTAT2_PCSUM_OK 0x0040 /* partial checksum ok */ 768 #define SF_RXSTAT2_CSUM_BAD 0x0080 /* TCP/IP checksum bad */ 769 #define SF_RXSTAT2_CSUM_OK 0x0100 /* TCP/IP checksum ok */ 770 #define SF_RXSTAT2_VLAN 0x0200 771 #define SF_RXSTAT2_BADRXCODE 0x0400 772 #define SF_RXSTAT2_DRIBBLE 0x0800 773 #define SF_RXSTAT2_ISL_CRCERR 0x1000 774 #define SF_RXSTAT2_CRCERR 0x2000 775 #define SF_RXSTAT2_HASH 0x4000 776 #define SF_RXSTAT2_PERFECT 0x8000 777 778 #define SF_RXSTAT3_TRAILER 0x01 779 #define SF_RXSTAT3_HEADER 0x02 780 #define SF_RXSTAT3_CONTROL 0x04 781 #define SF_RXSTAT3_PAUSE 0x08 782 #define SF_RXSTAT3_ISL 0x10 783 784 /* 785 * Transmit descriptor formats. 786 * Each transmit descriptor type allows for a skip field at the 787 * start of each structure. The size of the skip field can vary, 788 * however we always set it for 8 bytes, which is enough to hold 789 * a pointer (32 bits on x86, 64-bits on alpha) that we can use 790 * to hold the address of the head of the mbuf chain for the 791 * frame or fragment associated with the descriptor. This saves 792 * us from having to create a separate pointer array to hold 793 * the mbuf addresses. 794 */ 795 #define SF_TX_BUFDESC_ID 0xB 796 #define SF_MAXFRAGS 14 797 #define SF_TX_MINSPACING 128 798 #define SF_TX_DLIST_CNT 128 799 #define SF_TX_DLIST_SIZE 16384 800 #define SF_TX_SKIPLEN 1 801 #define SF_TX_CLIST_CNT 1024 802 803 struct sf_frag { 804 u_int32_t sf_addr; 805 u_int16_t sf_fraglen; 806 u_int16_t sf_pktlen; 807 }; 808 809 struct sf_frag_msdos { 810 u_int16_t sf_pktlen; 811 u_int16_t sf_fraglen; 812 u_int32_t sf_addr; 813 }; 814 815 /* 816 * TX frame descriptor type 0, 32-bit addressing. One descriptor can 817 * be used to map multiple packet fragments. We use this format since 818 * BSD networking fragments packet data across mbuf chains. Note that 819 * the number of fragments can be variable depending on how the descriptor 820 * spacing is specified in the TX descriptor queue control register. 821 * We always use a spacing of 128 bytes, and a skipfield length of 8 822 * bytes: this means 16 bytes for the descriptor, including the skipfield, 823 * with 121 bytes left for fragment maps. Each fragment requires 8 bytes, 824 * which allows for 14 fragments per descriptor. The total size of the 825 * transmit buffer queue is limited to 16384 bytes, so with a spacing of 826 * 128 bytes per descriptor, we have room for 128 descriptors in the queue. 827 */ 828 struct sf_tx_bufdesc_type0 { 829 #ifdef __i386__ 830 u_int32_t sf_pad; 831 #endif 832 struct mbuf *sf_mbuf; 833 u_int32_t sf_rsvd0:24, 834 sf_crcen:1, 835 sf_caltcp:1, 836 sf_end:1, 837 sf_intr:1, 838 sf_id:4; 839 u_int8_t sf_fragcnt; 840 u_int8_t sf_rsvd2; 841 u_int16_t sf_rsvd1; 842 struct sf_frag sf_frags[14]; 843 }; 844 845 /* 846 * TX buffer descriptor type 1, 32-bit addressing. Each descriptor 847 * maps a single fragment. 848 */ 849 struct sf_tx_bufdesc_type1 { 850 #ifdef __i386__ 851 u_int32_t sf_pad; 852 #endif 853 struct mbuf *sf_mbuf; 854 u_int32_t sf_fraglen:16, 855 sf_fragcnt:8, 856 sf_crcen:1, 857 sf_caltcp:1, 858 sf_end:1, 859 sf_intr:1, 860 sf_id:4; 861 u_int32_t sf_addr; 862 }; 863 864 /* 865 * TX buffer descriptor type 2, 64-bit addressing. Each descriptor 866 * maps a single fragment. 867 */ 868 struct sf_tx_bufdesc_type2 { 869 #ifdef __i386__ 870 u_int32_t sf_pad; 871 #endif 872 struct mbuf *sf_mbuf; 873 u_int32_t sf_fraglen:16, 874 sf_fragcnt:8, 875 sf_crcen:1, 876 sf_caltcp:1, 877 sf_end:1, 878 sf_intr:1, 879 sf_id:4; 880 u_int32_t sf_addrlo; 881 u_int32_t sf_addrhi; 882 }; 883 884 /* TX buffer descriptor type 3 is not defined. */ 885 886 /* 887 * TX frame descriptor type 4, 32-bit addressing. This is a special 888 * case of the type 0 descriptor, identical except that the fragment 889 * address and length fields are ordered differently. This is done 890 * to optimize copies in MS-DOS and OS/2 drivers. 891 */ 892 struct sf_tx_bufdesc_type4 { 893 #ifdef __i386__ 894 u_int32_t sf_pad; 895 #endif 896 struct mbuf *sf_mbuf; 897 u_int32_t sf_rsvd0:24, 898 sf_crcen:1, 899 sf_caltcp:1, 900 sf_end:1, 901 sf_intr:1, 902 sf_id:4; 903 u_int8_t sf_fragcnt; 904 u_int8_t sf_rsvd2; 905 u_int16_t sf_rsvd1; 906 struct sf_frag_msdos sf_frags[14]; 907 }; 908 909 /* 910 * Transmit completion queue descriptor formats. 911 */ 912 913 /* 914 * Transmit DMA completion descriptor, type 0. 915 */ 916 #define SF_TXCMPTYPE_DMA 0x4 917 struct sf_tx_cmpdesc_type0 { 918 u_int32_t sf_index:15, 919 sf_priority:1, 920 sf_timestamp:13, 921 sf_type:3; 922 }; 923 924 /* 925 * Transmit completion descriptor, type 1. 926 */ 927 #define SF_TXCMPTYPE_TX 0x5 928 struct sf_tx_cmpdesc_type1 { 929 u_int32_t sf_index:15, 930 sf_priority:1, 931 sf_txstat:13, 932 sf_type:3; 933 }; 934 935 #define SF_TXSTAT_CRCERR 0x0001 936 #define SF_TXSTAT_LENCHECKERR 0x0002 937 #define SF_TXSTAT_LENRANGEERR 0x0004 938 #define SF_TXSTAT_TX_OK 0x0008 939 #define SF_TXSTAT_TX_DEFERED 0x0010 940 #define SF_TXSTAT_EXCESS_DEFER 0x0020 941 #define SF_TXSTAT_EXCESS_COLL 0x0040 942 #define SF_TXSTAT_LATE_COLL 0x0080 943 #define SF_TXSTAT_TOOBIG 0x0100 944 #define SF_TXSTAT_TX_UNDERRUN 0x0200 945 #define SF_TXSTAT_CTLFRAME_OK 0x0400 946 #define SF_TXSTAT_PAUSEFRAME_OK 0x0800 947 #define SF_TXSTAT_PAUSED 0x1000 948 949 /* Statistics counters. */ 950 struct sf_stats { 951 u_int32_t sf_tx_frames; 952 u_int32_t sf_tx_single_colls; 953 u_int32_t sf_tx_multi_colls; 954 u_int32_t sf_tx_crcerrs; 955 u_int32_t sf_tx_bytes; 956 u_int32_t sf_tx_defered; 957 u_int32_t sf_tx_late_colls; 958 u_int32_t sf_tx_pause_frames; 959 u_int32_t sf_tx_control_frames; 960 u_int32_t sf_tx_excess_colls; 961 u_int32_t sf_tx_excess_defer; 962 u_int32_t sf_tx_mcast_frames; 963 u_int32_t sf_tx_bcast_frames; 964 u_int32_t sf_tx_frames_lost; 965 u_int32_t sf_rx_rx_frames; 966 u_int32_t sf_rx_crcerrs; 967 u_int32_t sf_rx_alignerrs; 968 u_int32_t sf_rx_bytes; 969 u_int32_t sf_rx_control_frames; 970 u_int32_t sf_rx_unsup_control_frames; 971 u_int32_t sf_rx_giants; 972 u_int32_t sf_rx_runts; 973 u_int32_t sf_rx_jabbererrs; 974 u_int32_t sf_rx_pkts_64; 975 u_int32_t sf_rx_pkts_65_127; 976 u_int32_t sf_rx_pkts_128_255; 977 u_int32_t sf_rx_pkts_256_511; 978 u_int32_t sf_rx_pkts_512_1023; 979 u_int32_t sf_rx_pkts_1024_1518; 980 u_int32_t sf_rx_frames_lost; 981 u_int16_t sf_tx_underruns; 982 u_int16_t sf_pad; 983 }; 984 985 /* 986 * register space access macros 987 */ 988 #define CSR_WRITE_4(sc, reg, val) \ 989 bus_space_write_4(sc->sf_btag, sc->sf_bhandle, reg, val) 990 991 #define CSR_READ_4(sc, reg) \ 992 bus_space_read_4(sc->sf_btag, sc->sf_bhandle, reg) 993 994 #define CSR_READ_1(sc, reg) \ 995 bus_space_read_1(sc->sf_btag, sc->sf_bhandle, reg) 996 997 998 struct sf_type { 999 u_int16_t sf_vid; 1000 u_int16_t sf_did; 1001 char *sf_name; 1002 }; 1003 1004 #define SF_INC(x, y) (x) = (x + 1) % y 1005 1006 #define ETHER_ALIGN 2 1007 1008 /* 1009 * Note: alignment is important here: each list must be aligned to 1010 * a 256-byte boundary. It turns out that each ring is some multiple 1011 * of 4K in length, so we can stack them all on top of each other 1012 * and just worry about aligning the whole mess. There's one transmit 1013 * buffer ring and two receive buffer rings: one RX ring is for small 1014 * packets and the other is for large packets. Each buffer ring also 1015 * has a companion completion queue. 1016 */ 1017 struct sf_list_data { 1018 struct sf_tx_bufdesc_type0 sf_tx_dlist[SF_TX_DLIST_CNT]; 1019 struct sf_tx_cmpdesc_type1 sf_tx_clist[SF_TX_CLIST_CNT]; 1020 struct sf_rx_bufdesc_type0 sf_rx_dlist_big[SF_RX_DLIST_CNT]; 1021 #ifdef notdef 1022 /* 1023 * Unfortunately, because the Starfire doesn't allow arbitrary 1024 * byte alignment, we have to copy packets in the RX handler in 1025 * order to align the payload correctly. This means that we 1026 * don't gain anything by having separate large and small descriptor 1027 * lists, so for now we don't bother with the small one. 1028 */ 1029 struct sf_rx_bufdesc_type0 sf_rx_dlist_small[SF_RX_DLIST_CNT]; 1030 #endif 1031 struct sf_rx_cmpdesc_type3 sf_rx_clist[SF_RX_CLIST_CNT]; 1032 }; 1033 1034 struct sf_softc { 1035 struct arpcom arpcom; /* interface info */ 1036 bus_space_handle_t sf_bhandle; /* bus space handle */ 1037 bus_space_tag_t sf_btag; /* bus space tag */ 1038 void *sf_intrhand; /* interrupt handler cookie */ 1039 struct resource *sf_irq; /* irq resource descriptor */ 1040 struct resource *sf_res; /* mem/ioport resource */ 1041 struct sf_type *sf_info; /* Starfire adapter info */ 1042 device_t sf_miibus; 1043 u_int8_t sf_unit; /* interface number */ 1044 struct sf_list_data *sf_ldata; 1045 int sf_tx_cnt; 1046 u_int8_t sf_link; 1047 int sf_if_flags; 1048 struct callout_handle sf_stat_ch; 1049 }; 1050 1051 #define SF_TIMEOUT 1000 1052 1053 #ifdef __alpha__ 1054 #undef vtophys 1055 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1056 #endif 1057