1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/sis/if_sis.c,v 1.14 2004/05/06 10:15:37 joerg Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $ 36 */ 37 38 /* 39 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 40 * available from http://www.sis.com.tw. 41 * 42 * This driver also supports the NatSemi DP83815. Datasheets are 43 * available from http://www.national.com. 44 * 45 * Written by Bill Paul <wpaul@ee.columbia.edu> 46 * Electrical Engineering Department 47 * Columbia University, New York City 48 */ 49 50 /* 51 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 52 * simple TX and RX descriptors of 3 longwords in size. The receiver 53 * has a single perfect filter entry for the station address and a 54 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 55 * transceiver while the 7016 requires an external transceiver chip. 56 * Both chips offer the standard bit-bang MII interface as well as 57 * an enchanced PHY interface which simplifies accessing MII registers. 58 * 59 * The only downside to this chipset is that RX descriptors must be 60 * longword aligned. 61 */ 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/sockio.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/socket.h> 70 #include <sys/sysctl.h> 71 72 #include <net/if.h> 73 #include <net/if_arp.h> 74 #include <net/ethernet.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_types.h> 78 #include <net/vlan/if_vlan_var.h> 79 80 #include <net/bpf.h> 81 82 #include <machine/bus_pio.h> 83 #include <machine/bus_memio.h> 84 #include <machine/bus.h> 85 #include <machine/resource.h> 86 #include <sys/bus.h> 87 #include <sys/rman.h> 88 89 #include <dev/netif/mii_layer/mii.h> 90 #include <dev/netif/mii_layer/miivar.h> 91 92 #include <bus/pci/pcireg.h> 93 #include <bus/pci/pcivar.h> 94 95 #define SIS_USEIOSPACE 96 97 #include "if_sisreg.h" 98 99 /* "controller miibus0" required. See GENERIC if you get errors here. */ 100 #include "miibus_if.h" 101 102 /* 103 * Various supported device vendors/types and their names. 104 */ 105 static struct sis_type sis_devs[] = { 106 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 107 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 108 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 109 { 0, 0, NULL } 110 }; 111 112 static int sis_probe(device_t); 113 static int sis_attach(device_t); 114 static int sis_detach(device_t); 115 116 static int sis_newbuf(struct sis_softc *, struct sis_desc *, 117 struct mbuf *); 118 static int sis_encap(struct sis_softc *, struct mbuf *, uint32_t *); 119 static void sis_rxeof(struct sis_softc *); 120 static void sis_rxeoc(struct sis_softc *); 121 static void sis_txeof(struct sis_softc *); 122 static void sis_intr(void *); 123 static void sis_tick(void *); 124 static void sis_start(struct ifnet *); 125 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 126 static void sis_init(void *); 127 static void sis_stop(struct sis_softc *); 128 static void sis_watchdog(struct ifnet *); 129 static void sis_shutdown(device_t); 130 static int sis_ifmedia_upd(struct ifnet *); 131 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 132 133 static uint16_t sis_reverse(uint16_t); 134 static void sis_delay(struct sis_softc *); 135 static void sis_eeprom_idle(struct sis_softc *); 136 static void sis_eeprom_putbyte(struct sis_softc *, int); 137 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *); 138 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int); 139 #ifdef __i386__ 140 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int); 141 static void sis_read_mac(struct sis_softc *, device_t, caddr_t); 142 static device_t sis_find_bridge(device_t); 143 #endif 144 145 static void sis_mii_sync(struct sis_softc *); 146 static void sis_mii_send(struct sis_softc *, uint32_t, int); 147 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *); 148 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *); 149 static int sis_miibus_readreg(device_t, int, int); 150 static int sis_miibus_writereg(device_t, int, int, int); 151 static void sis_miibus_statchg(device_t); 152 153 static void sis_setmulti_sis(struct sis_softc *); 154 static void sis_setmulti_ns(struct sis_softc *); 155 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *); 156 static void sis_reset(struct sis_softc *); 157 static int sis_list_rx_init(struct sis_softc *); 158 static int sis_list_tx_init(struct sis_softc *); 159 160 static void sis_dma_map_desc_ptr(void *, bus_dma_segment_t *, int, int); 161 static void sis_dma_map_desc_next(void *, bus_dma_segment_t *, int, int); 162 static void sis_dma_map_ring(void *, bus_dma_segment_t *, int, int); 163 #ifdef SIS_USEIOSPACE 164 #define SIS_RES SYS_RES_IOPORT 165 #define SIS_RID SIS_PCI_LOIO 166 #else 167 #define SIS_RES SYS_RES_MEMORY 168 #define SIS_RID SIS_PCI_LOMEM 169 #endif 170 171 static device_method_t sis_methods[] = { 172 /* Device interface */ 173 DEVMETHOD(device_probe, sis_probe), 174 DEVMETHOD(device_attach, sis_attach), 175 DEVMETHOD(device_detach, sis_detach), 176 DEVMETHOD(device_shutdown, sis_shutdown), 177 178 /* bus interface */ 179 DEVMETHOD(bus_print_child, bus_generic_print_child), 180 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 181 182 /* MII interface */ 183 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 184 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 185 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 186 187 { 0, 0 } 188 }; 189 190 static driver_t sis_driver = { 191 "sis", 192 sis_methods, 193 sizeof(struct sis_softc) 194 }; 195 196 static devclass_t sis_devclass; 197 198 DECLARE_DUMMY_MODULE(if_sis); 199 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 200 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 201 202 #define SIS_SETBIT(sc, reg, x) \ 203 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 204 205 #define SIS_CLRBIT(sc, reg, x) \ 206 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 207 208 #define SIO_SET(x) \ 209 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 210 211 #define SIO_CLR(x) \ 212 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 213 214 static void 215 sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error) 216 { 217 struct sis_desc *r; 218 219 r = arg; 220 r->sis_next = segs->ds_addr; 221 } 222 223 static void 224 sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 225 { 226 struct sis_desc *r; 227 228 r = arg; 229 r->sis_ptr = segs->ds_addr; 230 } 231 232 static void 233 sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error) 234 { 235 uint32_t *p; 236 237 p = arg; 238 *p = segs->ds_addr; 239 } 240 241 /* 242 * Routine to reverse the bits in a word. Stolen almost 243 * verbatim from /usr/games/fortune. 244 */ 245 static uint16_t 246 sis_reverse(uint16_t n) 247 { 248 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 249 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 250 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 251 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 252 253 return(n); 254 } 255 256 static void 257 sis_delay(struct sis_softc *sc) 258 { 259 int idx; 260 261 for (idx = (300 / 33) + 1; idx > 0; idx--) 262 CSR_READ_4(sc, SIS_CSR); 263 } 264 265 static void 266 sis_eeprom_idle(struct sis_softc *sc) 267 { 268 int i; 269 270 SIO_SET(SIS_EECTL_CSEL); 271 sis_delay(sc); 272 SIO_SET(SIS_EECTL_CLK); 273 sis_delay(sc); 274 275 for (i = 0; i < 25; i++) { 276 SIO_CLR(SIS_EECTL_CLK); 277 sis_delay(sc); 278 SIO_SET(SIS_EECTL_CLK); 279 sis_delay(sc); 280 } 281 282 SIO_CLR(SIS_EECTL_CLK); 283 sis_delay(sc); 284 SIO_CLR(SIS_EECTL_CSEL); 285 sis_delay(sc); 286 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 287 } 288 289 /* 290 * Send a read command and address to the EEPROM, check for ACK. 291 */ 292 static void 293 sis_eeprom_putbyte(struct sis_softc *sc, int addr) 294 { 295 int d, i; 296 297 d = addr | SIS_EECMD_READ; 298 299 /* 300 * Feed in each bit and stobe the clock. 301 */ 302 for (i = 0x400; i; i >>= 1) { 303 if (d & i) 304 SIO_SET(SIS_EECTL_DIN); 305 else 306 SIO_CLR(SIS_EECTL_DIN); 307 sis_delay(sc); 308 SIO_SET(SIS_EECTL_CLK); 309 sis_delay(sc); 310 SIO_CLR(SIS_EECTL_CLK); 311 sis_delay(sc); 312 } 313 } 314 315 /* 316 * Read a word of data stored in the EEPROM at address 'addr.' 317 */ 318 static void 319 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 320 { 321 int i; 322 uint16_t word = 0; 323 324 /* Force EEPROM to idle state. */ 325 sis_eeprom_idle(sc); 326 327 /* Enter EEPROM access mode. */ 328 sis_delay(sc); 329 SIO_CLR(SIS_EECTL_CLK); 330 sis_delay(sc); 331 SIO_SET(SIS_EECTL_CSEL); 332 sis_delay(sc); 333 334 /* 335 * Send address of word we want to read. 336 */ 337 sis_eeprom_putbyte(sc, addr); 338 339 /* 340 * Start reading bits from EEPROM. 341 */ 342 for (i = 0x8000; i; i >>= 1) { 343 SIO_SET(SIS_EECTL_CLK); 344 sis_delay(sc); 345 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 346 word |= i; 347 sis_delay(sc); 348 SIO_CLR(SIS_EECTL_CLK); 349 sis_delay(sc); 350 } 351 352 /* Turn off EEPROM access mode. */ 353 sis_eeprom_idle(sc); 354 355 *dest = word; 356 } 357 358 /* 359 * Read a sequence of words from the EEPROM. 360 */ 361 static void 362 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 363 { 364 int i; 365 uint16_t word = 0, *ptr; 366 367 for (i = 0; i < cnt; i++) { 368 sis_eeprom_getword(sc, off + i, &word); 369 ptr = (uint16_t *)(dest + (i * 2)); 370 if (swap) 371 *ptr = ntohs(word); 372 else 373 *ptr = word; 374 } 375 } 376 377 #ifdef __i386__ 378 static device_t 379 sis_find_bridge(device_t dev) 380 { 381 devclass_t pci_devclass; 382 device_t *pci_devices; 383 int pci_count = 0; 384 device_t *pci_children; 385 int pci_childcount = 0; 386 device_t *busp, *childp; 387 device_t child = NULL; 388 int i, j; 389 390 if ((pci_devclass = devclass_find("pci")) == NULL) 391 return(NULL); 392 393 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 394 395 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 396 pci_childcount = 0; 397 device_get_children(*busp, &pci_children, &pci_childcount); 398 for (j = 0, childp = pci_children; j < pci_childcount; 399 j++, childp++) { 400 if (pci_get_vendor(*childp) == SIS_VENDORID && 401 pci_get_device(*childp) == 0x0008) { 402 child = *childp; 403 goto done; 404 } 405 } 406 } 407 408 done: 409 free(pci_devices, M_TEMP); 410 free(pci_children, M_TEMP); 411 return(child); 412 } 413 414 static void 415 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, 416 int cnt) 417 { 418 device_t bridge; 419 uint8_t reg; 420 int i; 421 bus_space_tag_t btag; 422 423 bridge = sis_find_bridge(dev); 424 if (bridge == NULL) 425 return; 426 reg = pci_read_config(bridge, 0x48, 1); 427 pci_write_config(bridge, 0x48, reg|0x40, 1); 428 429 /* XXX */ 430 btag = I386_BUS_SPACE_IO; 431 432 for (i = 0; i < cnt; i++) { 433 bus_space_write_1(btag, 0x0, 0x70, i + off); 434 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 435 } 436 437 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 438 } 439 440 static void 441 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 442 { 443 uint32_t filtsave, csrsave; 444 445 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 446 csrsave = CSR_READ_4(sc, SIS_CSR); 447 448 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 449 CSR_WRITE_4(sc, SIS_CSR, 0); 450 451 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 452 453 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 454 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 455 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 456 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 457 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 458 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 459 460 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 461 CSR_WRITE_4(sc, SIS_CSR, csrsave); 462 } 463 #endif 464 465 /* 466 * Sync the PHYs by setting data bit and strobing the clock 32 times. 467 */ 468 static void 469 sis_mii_sync(struct sis_softc *sc) 470 { 471 int i; 472 473 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 474 475 for (i = 0; i < 32; i++) { 476 SIO_SET(SIS_MII_CLK); 477 DELAY(1); 478 SIO_CLR(SIS_MII_CLK); 479 DELAY(1); 480 } 481 } 482 483 /* 484 * Clock a series of bits through the MII. 485 */ 486 static void 487 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) 488 { 489 int i; 490 491 SIO_CLR(SIS_MII_CLK); 492 493 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 494 if (bits & i) 495 SIO_SET(SIS_MII_DATA); 496 else 497 SIO_CLR(SIS_MII_DATA); 498 DELAY(1); 499 SIO_CLR(SIS_MII_CLK); 500 DELAY(1); 501 SIO_SET(SIS_MII_CLK); 502 } 503 } 504 505 /* 506 * Read an PHY register through the MII. 507 */ 508 static int 509 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) 510 { 511 int i, ack, s; 512 513 s = splimp(); 514 515 /* 516 * Set up frame for RX. 517 */ 518 frame->mii_stdelim = SIS_MII_STARTDELIM; 519 frame->mii_opcode = SIS_MII_READOP; 520 frame->mii_turnaround = 0; 521 frame->mii_data = 0; 522 523 /* 524 * Turn on data xmit. 525 */ 526 SIO_SET(SIS_MII_DIR); 527 528 sis_mii_sync(sc); 529 530 /* 531 * Send command/address info. 532 */ 533 sis_mii_send(sc, frame->mii_stdelim, 2); 534 sis_mii_send(sc, frame->mii_opcode, 2); 535 sis_mii_send(sc, frame->mii_phyaddr, 5); 536 sis_mii_send(sc, frame->mii_regaddr, 5); 537 538 /* Idle bit */ 539 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 540 DELAY(1); 541 SIO_SET(SIS_MII_CLK); 542 DELAY(1); 543 544 /* Turn off xmit. */ 545 SIO_CLR(SIS_MII_DIR); 546 547 /* Check for ack */ 548 SIO_CLR(SIS_MII_CLK); 549 DELAY(1); 550 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 551 SIO_SET(SIS_MII_CLK); 552 DELAY(1); 553 554 /* 555 * Now try reading data bits. If the ack failed, we still 556 * need to clock through 16 cycles to keep the PHY(s) in sync. 557 */ 558 if (ack) { 559 for(i = 0; i < 16; i++) { 560 SIO_CLR(SIS_MII_CLK); 561 DELAY(1); 562 SIO_SET(SIS_MII_CLK); 563 DELAY(1); 564 } 565 goto fail; 566 } 567 568 for (i = 0x8000; i; i >>= 1) { 569 SIO_CLR(SIS_MII_CLK); 570 DELAY(1); 571 if (!ack) { 572 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 573 frame->mii_data |= i; 574 DELAY(1); 575 } 576 SIO_SET(SIS_MII_CLK); 577 DELAY(1); 578 } 579 580 fail: 581 582 SIO_CLR(SIS_MII_CLK); 583 DELAY(1); 584 SIO_SET(SIS_MII_CLK); 585 DELAY(1); 586 587 splx(s); 588 589 if (ack) 590 return(1); 591 return(0); 592 } 593 594 /* 595 * Write to a PHY register through the MII. 596 */ 597 static int 598 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) 599 { 600 int s; 601 602 s = splimp(); 603 /* 604 * Set up frame for TX. 605 */ 606 607 frame->mii_stdelim = SIS_MII_STARTDELIM; 608 frame->mii_opcode = SIS_MII_WRITEOP; 609 frame->mii_turnaround = SIS_MII_TURNAROUND; 610 611 /* 612 * Turn on data output. 613 */ 614 SIO_SET(SIS_MII_DIR); 615 616 sis_mii_sync(sc); 617 618 sis_mii_send(sc, frame->mii_stdelim, 2); 619 sis_mii_send(sc, frame->mii_opcode, 2); 620 sis_mii_send(sc, frame->mii_phyaddr, 5); 621 sis_mii_send(sc, frame->mii_regaddr, 5); 622 sis_mii_send(sc, frame->mii_turnaround, 2); 623 sis_mii_send(sc, frame->mii_data, 16); 624 625 /* Idle bit. */ 626 SIO_SET(SIS_MII_CLK); 627 DELAY(1); 628 SIO_CLR(SIS_MII_CLK); 629 DELAY(1); 630 631 /* 632 * Turn off xmit. 633 */ 634 SIO_CLR(SIS_MII_DIR); 635 636 splx(s); 637 638 return(0); 639 } 640 641 static int 642 sis_miibus_readreg(device_t dev, int phy, int reg) 643 { 644 struct sis_softc *sc; 645 struct sis_mii_frame frame; 646 647 sc = device_get_softc(dev); 648 649 if (sc->sis_type == SIS_TYPE_83815) { 650 if (phy != 0) 651 return(0); 652 /* 653 * The NatSemi chip can take a while after 654 * a reset to come ready, during which the BMSR 655 * returns a value of 0. This is *never* supposed 656 * to happen: some of the BMSR bits are meant to 657 * be hardwired in the on position, and this can 658 * confuse the miibus code a bit during the probe 659 * and attach phase. So we make an effort to check 660 * for this condition and wait for it to clear. 661 */ 662 if (!CSR_READ_4(sc, NS_BMSR)) 663 DELAY(1000); 664 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 665 } 666 /* 667 * Chipsets < SIS_635 seem not to be able to read/write 668 * through mdio. Use the enhanced PHY access register 669 * again for them. 670 */ 671 if (sc->sis_type == SIS_TYPE_900 && 672 sc->sis_rev < SIS_REV_635) { 673 int i, val = 0; 674 675 if (phy != 0) 676 return(0); 677 678 CSR_WRITE_4(sc, SIS_PHYCTL, 679 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 680 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 681 682 for (i = 0; i < SIS_TIMEOUT; i++) { 683 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 684 break; 685 } 686 687 if (i == SIS_TIMEOUT) { 688 device_printf(dev, "PHY failed to come ready\n"); 689 return(0); 690 } 691 692 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 693 694 if (val == 0xFFFF) 695 return(0); 696 697 return(val); 698 } else { 699 bzero((char *)&frame, sizeof(frame)); 700 701 frame.mii_phyaddr = phy; 702 frame.mii_regaddr = reg; 703 sis_mii_readreg(sc, &frame); 704 705 return(frame.mii_data); 706 } 707 } 708 709 static int 710 sis_miibus_writereg(device_t dev, int phy, int reg, int data) 711 { 712 struct sis_softc *sc; 713 struct sis_mii_frame frame; 714 715 sc = device_get_softc(dev); 716 717 if (sc->sis_type == SIS_TYPE_83815) { 718 if (phy != 0) 719 return(0); 720 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 721 return(0); 722 } 723 724 if (sc->sis_type == SIS_TYPE_900 && 725 sc->sis_rev < SIS_REV_635) { 726 int i; 727 728 if (phy != 0) 729 return(0); 730 731 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 732 (reg << 6) | SIS_PHYOP_WRITE); 733 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 734 735 for (i = 0; i < SIS_TIMEOUT; i++) { 736 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 737 break; 738 } 739 740 if (i == SIS_TIMEOUT) 741 device_printf(dev, "PHY failed to come ready\n"); 742 } else { 743 bzero((char *)&frame, sizeof(frame)); 744 745 frame.mii_phyaddr = phy; 746 frame.mii_regaddr = reg; 747 frame.mii_data = data; 748 sis_mii_writereg(sc, &frame); 749 } 750 return(0); 751 } 752 753 static void sis_miibus_statchg(device_t dev) 754 { 755 struct sis_softc *sc; 756 757 sc = device_get_softc(dev); 758 sis_init(sc); 759 } 760 761 static uint32_t 762 sis_mchash(struct sis_softc *sc, const uint8_t *addr) 763 { 764 uint32_t crc, carry; 765 int i, j; 766 uint8_t c; 767 768 /* Compute CRC for the address value. */ 769 crc = 0xFFFFFFFF; /* initial value */ 770 771 for (i = 0; i < 6; i++) { 772 c = *(addr + i); 773 for (j = 0; j < 8; j++) { 774 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 775 crc <<= 1; 776 c >>= 1; 777 if (carry) 778 crc = (crc ^ 0x04c11db6) | carry; 779 } 780 } 781 782 /* 783 * return the filter bit position 784 * 785 * The NatSemi chip has a 512-bit filter, which is 786 * different than the SiS, so we special-case it. 787 */ 788 if (sc->sis_type == SIS_TYPE_83815) 789 return (crc >> 23); 790 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 791 return (crc >> 24); 792 else 793 return (crc >> 25); 794 } 795 796 static void 797 sis_setmulti_ns(struct sis_softc *sc) 798 { 799 struct ifnet *ifp; 800 struct ifmultiaddr *ifma; 801 uint32_t h = 0, i, filtsave; 802 int bit, index; 803 804 ifp = &sc->arpcom.ac_if; 805 806 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 807 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 808 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 809 return; 810 } 811 812 /* 813 * We have to explicitly enable the multicast hash table 814 * on the NatSemi chip if we want to use it, which we do. 815 */ 816 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 817 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 818 819 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 820 821 /* first, zot all the existing hash bits */ 822 for (i = 0; i < 32; i++) { 823 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 824 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 825 } 826 827 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 828 if (ifma->ifma_addr->sa_family != AF_LINK) 829 continue; 830 h = sis_mchash(sc, 831 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 832 index = h >> 3; 833 bit = h & 0x1F; 834 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 835 if (bit > 0xF) 836 bit -= 0x10; 837 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 838 } 839 840 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 841 } 842 843 static void 844 sis_setmulti_sis(struct sis_softc *sc) 845 { 846 struct ifnet *ifp; 847 struct ifmultiaddr *ifma; 848 uint32_t h, i, n, ctl; 849 uint16_t hashes[16]; 850 851 ifp = &sc->arpcom.ac_if; 852 853 /* hash table size */ 854 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 855 n = 16; 856 else 857 n = 8; 858 859 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 860 861 if (ifp->if_flags & IFF_BROADCAST) 862 ctl |= SIS_RXFILTCTL_BROAD; 863 864 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 865 ctl |= SIS_RXFILTCTL_ALLMULTI; 866 if (ifp->if_flags & IFF_PROMISC) 867 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 868 for (i = 0; i < n; i++) 869 hashes[i] = ~0; 870 } else { 871 for (i = 0; i < n; i++) 872 hashes[i] = 0; 873 i = 0; 874 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 875 if (ifma->ifma_addr->sa_family != AF_LINK) 876 continue; 877 h = sis_mchash(sc, 878 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 879 hashes[h >> 4] |= 1 << (h & 0xf); 880 i++; 881 } 882 if (i > n) { 883 ctl |= SIS_RXFILTCTL_ALLMULTI; 884 for (i = 0; i < n; i++) 885 hashes[i] = ~0; 886 } 887 } 888 889 for (i = 0; i < n; i++) { 890 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 891 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 892 } 893 894 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 895 } 896 897 static void 898 sis_reset(struct sis_softc *sc) 899 { 900 struct ifnet *ifp = &sc->arpcom.ac_if; 901 int i; 902 903 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 904 905 for (i = 0; i < SIS_TIMEOUT; i++) { 906 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 907 break; 908 } 909 910 if (i == SIS_TIMEOUT) 911 if_printf(ifp, "reset never completed\n"); 912 913 /* Wait a little while for the chip to get its brains in order. */ 914 DELAY(1000); 915 916 /* 917 * If this is a NetSemi chip, make sure to clear 918 * PME mode. 919 */ 920 if (sc->sis_type == SIS_TYPE_83815) { 921 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 922 CSR_WRITE_4(sc, NS_CLKRUN, 0); 923 } 924 } 925 926 /* 927 * Probe for an SiS chip. Check the PCI vendor and device 928 * IDs against our list and return a device name if we find a match. 929 */ 930 static int 931 sis_probe(device_t dev) 932 { 933 struct sis_type *t; 934 935 t = sis_devs; 936 937 while(t->sis_name != NULL) { 938 if ((pci_get_vendor(dev) == t->sis_vid) && 939 (pci_get_device(dev) == t->sis_did)) { 940 device_set_desc(dev, t->sis_name); 941 return(0); 942 } 943 t++; 944 } 945 946 return(ENXIO); 947 } 948 949 /* 950 * Attach the interface. Allocate softc structures, do ifmedia 951 * setup and ethernet/BPF attach. 952 */ 953 static int 954 sis_attach(device_t dev) 955 { 956 uint8_t eaddr[ETHER_ADDR_LEN]; 957 uint32_t command; 958 struct sis_softc *sc; 959 struct ifnet *ifp; 960 int error, rid, waittime; 961 962 error = waittime = 0; 963 sc = device_get_softc(dev); 964 bzero(sc, sizeof(struct sis_softc)); 965 966 if (pci_get_device(dev) == SIS_DEVICEID_900) 967 sc->sis_type = SIS_TYPE_900; 968 if (pci_get_device(dev) == SIS_DEVICEID_7016) 969 sc->sis_type = SIS_TYPE_7016; 970 if (pci_get_vendor(dev) == NS_VENDORID) 971 sc->sis_type = SIS_TYPE_83815; 972 973 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 974 975 /* 976 * Handle power management nonsense. 977 */ 978 979 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF; 980 if (command == 0x01) { 981 982 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4); 983 if (command & SIS_PSTATE_MASK) { 984 uint32_t iobase, membase, irq; 985 986 /* Save important PCI config data. */ 987 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 988 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 989 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 990 991 /* Reset the power state. */ 992 device_printf(dev, "chip is in D%d power mode " 993 "-- setting to D0\n", command & SIS_PSTATE_MASK); 994 command &= 0xFFFFFFFC; 995 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4); 996 997 /* Restore PCI config data. */ 998 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 999 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 1000 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 1001 } 1002 } 1003 1004 /* 1005 * Map control/status registers. 1006 */ 1007 command = pci_read_config(dev, PCIR_COMMAND, 4); 1008 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1009 pci_write_config(dev, PCIR_COMMAND, command, 4); 1010 command = pci_read_config(dev, PCIR_COMMAND, 4); 1011 1012 #ifdef SIS_USEIOSPACE 1013 if (!(command & PCIM_CMD_PORTEN)) { 1014 device_printf(dev, "failed to enable I/O ports!\n"); 1015 error = ENXIO;; 1016 goto fail; 1017 } 1018 #else 1019 if (!(command & PCIM_CMD_MEMEN)) { 1020 device_printf(dev, "failed to enable memory mapping!\n"); 1021 error = ENXIO;; 1022 goto fail; 1023 } 1024 #endif 1025 1026 rid = SIS_RID; 1027 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 1028 0, ~0, 1, RF_ACTIVE); 1029 1030 if (sc->sis_res == NULL) { 1031 device_printf(dev, "couldn't map ports/memory\n"); 1032 error = ENXIO; 1033 goto fail; 1034 } 1035 1036 sc->sis_btag = rman_get_bustag(sc->sis_res); 1037 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1038 1039 /* Allocate interrupt */ 1040 rid = 0; 1041 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1042 RF_SHAREABLE | RF_ACTIVE); 1043 1044 if (sc->sis_irq == NULL) { 1045 device_printf(dev, "couldn't map interrupt\n"); 1046 error = ENXIO; 1047 goto fail; 1048 } 1049 1050 /* Reset the adapter. */ 1051 sis_reset(sc); 1052 1053 if (sc->sis_type == SIS_TYPE_900 && 1054 (sc->sis_rev == SIS_REV_635 || 1055 sc->sis_rev == SIS_REV_900B)) { 1056 SIO_SET(SIS_CFG_RND_CNT); 1057 SIO_SET(SIS_CFG_PERR_DETECT); 1058 } 1059 1060 /* 1061 * Get station address from the EEPROM. 1062 */ 1063 switch (pci_get_vendor(dev)) { 1064 case NS_VENDORID: 1065 /* 1066 * Reading the MAC address out of the EEPROM on 1067 * the NatSemi chip takes a bit more work than 1068 * you'd expect. The address spans 4 16-bit words, 1069 * with the first word containing only a single bit. 1070 * You have to shift everything over one bit to 1071 * get it aligned properly. Also, the bits are 1072 * stored backwards (the LSB is really the MSB, 1073 * and so on) so you have to reverse them in order 1074 * to get the MAC address into the form we want. 1075 * Why? Who the hell knows. 1076 */ 1077 { 1078 uint16_t tmp[4]; 1079 1080 sis_read_eeprom(sc, (caddr_t)&tmp, 1081 NS_EE_NODEADDR, 4, 0); 1082 1083 /* Shift everything over one bit. */ 1084 tmp[3] = tmp[3] >> 1; 1085 tmp[3] |= tmp[2] << 15; 1086 tmp[2] = tmp[2] >> 1; 1087 tmp[2] |= tmp[1] << 15; 1088 tmp[1] = tmp[1] >> 1; 1089 tmp[1] |= tmp[0] << 15; 1090 1091 /* Now reverse all the bits. */ 1092 tmp[3] = sis_reverse(tmp[3]); 1093 tmp[2] = sis_reverse(tmp[2]); 1094 tmp[1] = sis_reverse(tmp[1]); 1095 1096 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1097 } 1098 break; 1099 case SIS_VENDORID: 1100 default: 1101 #ifdef __i386__ 1102 /* 1103 * If this is a SiS 630E chipset with an embedded 1104 * SiS 900 controller, we have to read the MAC address 1105 * from the APC CMOS RAM. Our method for doing this 1106 * is very ugly since we have to reach out and grab 1107 * ahold of hardware for which we cannot properly 1108 * allocate resources. This code is only compiled on 1109 * the i386 architecture since the SiS 630E chipset 1110 * is for x86 motherboards only. Note that there are 1111 * a lot of magic numbers in this hack. These are 1112 * taken from SiS's Linux driver. I'd like to replace 1113 * them with proper symbolic definitions, but that 1114 * requires some datasheets that I don't have access 1115 * to at the moment. 1116 */ 1117 if (sc->sis_rev == SIS_REV_630S || 1118 sc->sis_rev == SIS_REV_630E || 1119 sc->sis_rev == SIS_REV_630EA1) 1120 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1121 1122 else if (sc->sis_rev == SIS_REV_635 || 1123 sc->sis_rev == SIS_REV_630ET) 1124 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1125 else if (sc->sis_rev == SIS_REV_96x) { 1126 /* 1127 * Allow to read EEPROM from LAN. It is shared 1128 * between a 1394 controller and the NIC and each 1129 * time we access it, we need to set SIS_EECMD_REQ. 1130 */ 1131 SIO_SET(SIS_EECMD_REQ); 1132 for (waittime = 0; waittime < SIS_TIMEOUT; 1133 waittime++) { 1134 /* Force EEPROM to idle state. */ 1135 sis_eeprom_idle(sc); 1136 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1137 sis_read_eeprom(sc, (caddr_t)&eaddr, 1138 SIS_EE_NODEADDR, 3, 0); 1139 break; 1140 } 1141 DELAY(1); 1142 } 1143 /* 1144 * Set SIS_EECTL_CLK to high, so a other master 1145 * can operate on the i2c bus. 1146 */ 1147 SIO_SET(SIS_EECTL_CLK); 1148 /* Refuse EEPROM access by LAN */ 1149 SIO_SET(SIS_EECMD_DONE); 1150 } else 1151 #endif 1152 sis_read_eeprom(sc, (caddr_t)&eaddr, 1153 SIS_EE_NODEADDR, 3, 0); 1154 break; 1155 } 1156 1157 /* 1158 * A SiS chip was detected. Inform the world. 1159 */ 1160 device_printf(dev, "Ethernet address: %6D\n", eaddr, ":"); 1161 1162 callout_init(&sc->sis_timer); 1163 1164 /* 1165 * Allocate the parent bus DMA tag appropriate for PCI. 1166 */ 1167 #define SIS_NSEG_NEW 32 1168 error = bus_dma_tag_create(NULL, /* parent */ 1169 1, 0, /* alignment, boundary */ 1170 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1171 BUS_SPACE_MAXADDR, /* highaddr */ 1172 NULL, NULL, /* filter, filterarg */ 1173 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1174 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1175 BUS_DMA_ALLOCNOW, /* flags */ 1176 &sc->sis_parent_tag); 1177 if (error) 1178 goto fail; 1179 1180 /* 1181 * Now allocate a tag for the DMA descriptor lists and a chunk 1182 * of DMA-able memory based on the tag. Also obtain the physical 1183 * addresses of the RX and TX ring, which we'll need later. 1184 * All of our lists are allocated as a contiguous block of memory. 1185 */ 1186 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1187 1, 0, /* alignment, boundary */ 1188 BUS_SPACE_MAXADDR, /* lowaddr */ 1189 BUS_SPACE_MAXADDR, /* highaddr */ 1190 NULL, NULL, /* filter, filterarg */ 1191 SIS_RX_LIST_SZ, 1, /* maxsize, nsegments */ 1192 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1193 0, /* flags */ 1194 &sc->sis_ldata.sis_rx_tag); 1195 if (error) 1196 goto fail; 1197 1198 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1199 (void **)&sc->sis_ldata.sis_rx_list, 1200 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1201 &sc->sis_ldata.sis_rx_dmamap); 1202 1203 if (error) { 1204 device_printf(dev, "no memory for rx list buffers!\n"); 1205 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1206 sc->sis_ldata.sis_rx_tag = NULL; 1207 goto fail; 1208 } 1209 1210 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1211 sc->sis_ldata.sis_rx_dmamap, 1212 sc->sis_ldata.sis_rx_list, 1213 sizeof(struct sis_desc), sis_dma_map_ring, 1214 &sc->sis_cdata.sis_rx_paddr, 0); 1215 1216 if (error) { 1217 device_printf(dev, "cannot get address of the rx ring!\n"); 1218 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1219 sc->sis_ldata.sis_rx_list, 1220 sc->sis_ldata.sis_rx_dmamap); 1221 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1222 sc->sis_ldata.sis_rx_tag = NULL; 1223 goto fail; 1224 } 1225 1226 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1227 1, 0, /* alignment, boundary */ 1228 BUS_SPACE_MAXADDR, /* lowaddr */ 1229 BUS_SPACE_MAXADDR, /* highaddr */ 1230 NULL, NULL, /* filter, filterarg */ 1231 SIS_TX_LIST_SZ, 1, /* maxsize, nsegments */ 1232 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1233 0, /* flags */ 1234 &sc->sis_ldata.sis_tx_tag); 1235 if (error) 1236 goto fail; 1237 1238 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1239 (void **)&sc->sis_ldata.sis_tx_list, 1240 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1241 &sc->sis_ldata.sis_tx_dmamap); 1242 1243 if (error) { 1244 device_printf(dev, "no memory for tx list buffers!\n"); 1245 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1246 sc->sis_ldata.sis_tx_tag = NULL; 1247 goto fail; 1248 } 1249 1250 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1251 sc->sis_ldata.sis_tx_dmamap, 1252 sc->sis_ldata.sis_tx_list, 1253 sizeof(struct sis_desc), sis_dma_map_ring, 1254 &sc->sis_cdata.sis_tx_paddr, 0); 1255 1256 if (error) { 1257 device_printf(dev, "cannot get address of the tx ring!\n"); 1258 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1259 sc->sis_ldata.sis_tx_list, 1260 sc->sis_ldata.sis_tx_dmamap); 1261 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1262 sc->sis_ldata.sis_tx_tag = NULL; 1263 goto fail; 1264 } 1265 1266 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1267 1, 0, /* alignment, boundary */ 1268 BUS_SPACE_MAXADDR, /* lowaddr */ 1269 BUS_SPACE_MAXADDR, /* highaddr */ 1270 NULL, NULL, /* filter, filterarg */ 1271 MCLBYTES, 1, /* maxsize, nsegments */ 1272 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1273 0, /* flags */ 1274 &sc->sis_tag); 1275 if (error) 1276 goto fail; 1277 1278 ifp = &sc->arpcom.ac_if; 1279 ifp->if_softc = sc; 1280 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1281 ifp->if_mtu = ETHERMTU; 1282 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1283 ifp->if_ioctl = sis_ioctl; 1284 ifp->if_output = ether_output; 1285 ifp->if_start = sis_start; 1286 ifp->if_watchdog = sis_watchdog; 1287 ifp->if_init = sis_init; 1288 ifp->if_baudrate = 10000000; 1289 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 1290 1291 /* 1292 * Do MII setup. 1293 */ 1294 if (mii_phy_probe(dev, &sc->sis_miibus, 1295 sis_ifmedia_upd, sis_ifmedia_sts)) { 1296 device_printf(dev, "MII without any PHY!\n"); 1297 error = ENXIO; 1298 goto fail; 1299 } 1300 1301 /* 1302 * Call MI attach routine. 1303 */ 1304 ether_ifattach(ifp, eaddr); 1305 1306 /* 1307 * Tell the upper layer(s) we support long frames. 1308 */ 1309 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1310 1311 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 1312 sis_intr, sc, &sc->sis_intrhand); 1313 1314 if (error) { 1315 device_printf(dev, "couldn't set up irq\n"); 1316 ether_ifdetach(ifp); 1317 goto fail; 1318 } 1319 1320 fail: 1321 if (error) 1322 sis_detach(dev); 1323 1324 return(error); 1325 } 1326 1327 /* 1328 * Shutdown hardware and free up resources. It is called in both the error case 1329 * and the normal detach case so it needs to be careful about only freeing 1330 * resources that have actually been allocated. 1331 */ 1332 static int 1333 sis_detach(device_t dev) 1334 { 1335 struct sis_softc *sc; 1336 struct ifnet *ifp; 1337 int s; 1338 1339 s = splimp(); 1340 1341 sc = device_get_softc(dev); 1342 ifp = &sc->arpcom.ac_if; 1343 1344 if (device_is_attached(dev)) { 1345 sis_reset(sc); 1346 sis_stop(sc); 1347 ether_ifdetach(ifp); 1348 } 1349 if (sc->sis_miibus) 1350 device_delete_child(dev, sc->sis_miibus); 1351 bus_generic_detach(dev); 1352 1353 if (sc->sis_intrhand) 1354 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1355 if (sc->sis_irq) 1356 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1357 if (sc->sis_res) 1358 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1359 1360 if (sc->sis_ldata.sis_rx_tag) { 1361 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1362 sc->sis_ldata.sis_rx_dmamap); 1363 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1364 sc->sis_ldata.sis_rx_list, 1365 sc->sis_ldata.sis_rx_dmamap); 1366 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1367 } 1368 1369 if (sc->sis_ldata.sis_tx_tag) { 1370 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1371 sc->sis_ldata.sis_tx_dmamap); 1372 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1373 sc->sis_ldata.sis_tx_list, 1374 sc->sis_ldata.sis_tx_dmamap); 1375 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1376 } 1377 if (sc->sis_tag) 1378 bus_dma_tag_destroy(sc->sis_tag); 1379 if (sc->sis_parent_tag) 1380 bus_dma_tag_destroy(sc->sis_parent_tag); 1381 1382 splx(s); 1383 1384 return(0); 1385 } 1386 1387 /* 1388 * Initialize the transmit descriptors. 1389 */ 1390 static int 1391 sis_list_tx_init(struct sis_softc *sc) 1392 { 1393 struct sis_list_data *ld; 1394 struct sis_ring_data *cd; 1395 int i, nexti; 1396 1397 cd = &sc->sis_cdata; 1398 ld = &sc->sis_ldata; 1399 1400 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1401 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1402 ld->sis_tx_list[i].sis_nextdesc = 1403 &ld->sis_tx_list[nexti]; 1404 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1405 sc->sis_ldata.sis_tx_dmamap, 1406 &ld->sis_tx_list[nexti], 1407 sizeof(struct sis_desc), sis_dma_map_desc_next, 1408 &ld->sis_tx_list[i], 0); 1409 ld->sis_tx_list[i].sis_mbuf = NULL; 1410 ld->sis_tx_list[i].sis_ptr = 0; 1411 ld->sis_tx_list[i].sis_ctl = 0; 1412 } 1413 1414 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1415 1416 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_tx_dmamap, 1417 BUS_DMASYNC_PREWRITE); 1418 1419 return(0); 1420 } 1421 1422 /* 1423 * Initialize the RX descriptors and allocate mbufs for them. Note that 1424 * we arrange the descriptors in a closed ring, so that the last descriptor 1425 * points back to the first. 1426 */ 1427 static int 1428 sis_list_rx_init(struct sis_softc *sc) 1429 { 1430 struct sis_list_data *ld; 1431 struct sis_ring_data *cd; 1432 int i, nexti; 1433 1434 ld = &sc->sis_ldata; 1435 cd = &sc->sis_cdata; 1436 1437 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1438 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1439 return(ENOBUFS); 1440 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1441 ld->sis_rx_list[i].sis_nextdesc = 1442 &ld->sis_rx_list[nexti]; 1443 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1444 sc->sis_ldata.sis_rx_dmamap, 1445 &ld->sis_rx_list[nexti], 1446 sizeof(struct sis_desc), sis_dma_map_desc_next, 1447 &ld->sis_rx_list[i], 0); 1448 } 1449 1450 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_dmamap, 1451 BUS_DMASYNC_PREWRITE); 1452 1453 cd->sis_rx_prod = 0; 1454 1455 return(0); 1456 } 1457 1458 /* 1459 * Initialize an RX descriptor and attach an MBUF cluster. 1460 */ 1461 static int 1462 sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m) 1463 { 1464 if (m == NULL) { 1465 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1466 if (m == NULL) 1467 return(ENOBUFS); 1468 } else { 1469 m->m_data = m->m_ext.ext_buf; 1470 } 1471 1472 c->sis_mbuf = m; 1473 c->sis_ctl = SIS_RXLEN; 1474 1475 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1476 bus_dmamap_load(sc->sis_tag, c->sis_map, mtod(m, void *), MCLBYTES, 1477 sis_dma_map_desc_ptr, c, 0); 1478 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1479 1480 return(0); 1481 } 1482 1483 /* 1484 * A frame has been uploaded: pass the resulting mbuf chain up to 1485 * the higher level protocols. 1486 */ 1487 static void 1488 sis_rxeof(struct sis_softc *sc) 1489 { 1490 struct mbuf *m; 1491 struct ifnet *ifp; 1492 struct sis_desc *cur_rx; 1493 int i, total_len = 0; 1494 uint32_t rxstat; 1495 1496 ifp = &sc->arpcom.ac_if; 1497 i = sc->sis_cdata.sis_rx_prod; 1498 1499 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1500 1501 #ifdef DEVICE_POLLING 1502 if (ifp->if_flags & IFF_POLLING) { 1503 if (sc->rxcycles <= 0) 1504 break; 1505 sc->rxcycles--; 1506 } 1507 #endif /* DEVICE_POLLING */ 1508 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1509 rxstat = cur_rx->sis_rxstat; 1510 bus_dmamap_sync(sc->sis_tag, cur_rx->sis_map, 1511 BUS_DMASYNC_POSTWRITE); 1512 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1513 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1514 m = cur_rx->sis_mbuf; 1515 cur_rx->sis_mbuf = NULL; 1516 total_len = SIS_RXBYTES(cur_rx); 1517 SIS_INC(i, SIS_RX_LIST_CNT); 1518 1519 /* 1520 * If an error occurs, update stats, clear the 1521 * status word and leave the mbuf cluster in place: 1522 * it should simply get re-used next time this descriptor 1523 * comes up in the ring. 1524 */ 1525 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1526 ifp->if_ierrors++; 1527 if (rxstat & SIS_RXSTAT_COLL) 1528 ifp->if_collisions++; 1529 sis_newbuf(sc, cur_rx, m); 1530 continue; 1531 } 1532 1533 /* No errors; receive the packet. */ 1534 #ifdef __i386__ 1535 /* 1536 * On the x86 we do not have alignment problems, so try to 1537 * allocate a new buffer for the receive ring, and pass up 1538 * the one where the packet is already, saving the expensive 1539 * copy done in m_devget(). 1540 * If we are on an architecture with alignment problems, or 1541 * if the allocation fails, then use m_devget and leave the 1542 * existing buffer in the receive ring. 1543 */ 1544 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1545 m->m_pkthdr.len = m->m_len = total_len; 1546 else 1547 #endif 1548 { 1549 struct mbuf *m0; 1550 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1551 total_len + ETHER_ALIGN, 0, ifp, NULL); 1552 sis_newbuf(sc, cur_rx, m); 1553 if (m0 == NULL) { 1554 ifp->if_ierrors++; 1555 continue; 1556 } 1557 m_adj(m0, ETHER_ALIGN); 1558 m = m0; 1559 } 1560 1561 ifp->if_ipackets++; 1562 ether_input(ifp, NULL, m); 1563 } 1564 1565 sc->sis_cdata.sis_rx_prod = i; 1566 } 1567 1568 static void 1569 sis_rxeoc(struct sis_softc *sc) 1570 { 1571 sis_rxeof(sc); 1572 sis_init(sc); 1573 } 1574 1575 /* 1576 * A frame was downloaded to the chip. It's safe for us to clean up 1577 * the list buffers. 1578 */ 1579 1580 static void 1581 sis_txeof(struct sis_softc *sc) 1582 { 1583 struct sis_desc *cur_tx; 1584 struct ifnet *ifp; 1585 uint32_t idx; 1586 1587 ifp = &sc->arpcom.ac_if; 1588 1589 /* 1590 * Go through our tx list and free mbufs for those 1591 * frames that have been transmitted. 1592 */ 1593 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1594 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1595 cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1596 1597 if (SIS_OWNDESC(cur_tx)) 1598 break; 1599 1600 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1601 continue; 1602 1603 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1604 ifp->if_oerrors++; 1605 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1606 ifp->if_collisions++; 1607 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1608 ifp->if_collisions++; 1609 } 1610 1611 ifp->if_collisions += 1612 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1613 1614 ifp->if_opackets++; 1615 if (cur_tx->sis_mbuf != NULL) { 1616 m_freem(cur_tx->sis_mbuf); 1617 cur_tx->sis_mbuf = NULL; 1618 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1619 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1620 } 1621 } 1622 1623 if (idx != sc->sis_cdata.sis_tx_cons) { 1624 /* we freed up some buffers */ 1625 sc->sis_cdata.sis_tx_cons = idx; 1626 ifp->if_flags &= ~IFF_OACTIVE; 1627 } 1628 1629 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1630 } 1631 1632 static void 1633 sis_tick(void *xsc) 1634 { 1635 struct sis_softc *sc; 1636 struct mii_data *mii; 1637 struct ifnet *ifp; 1638 int s; 1639 1640 s = splimp(); 1641 1642 sc = xsc; 1643 ifp = &sc->arpcom.ac_if; 1644 1645 mii = device_get_softc(sc->sis_miibus); 1646 mii_tick(mii); 1647 1648 if (!sc->sis_link) { 1649 mii_pollstat(mii); 1650 if (mii->mii_media_status & IFM_ACTIVE && 1651 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1652 sc->sis_link++; 1653 if (ifp->if_snd.ifq_head != NULL) 1654 sis_start(ifp); 1655 } 1656 1657 callout_reset(&sc->sis_timer, hz, sis_tick, sc); 1658 1659 splx(s); 1660 } 1661 1662 #ifdef DEVICE_POLLING 1663 static poll_handler_t sis_poll; 1664 1665 static void 1666 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1667 { 1668 struct sis_softc *sc = ifp->if_softc; 1669 1670 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1671 CSR_WRITE_4(sc, SIS_IER, 1); 1672 return; 1673 } 1674 1675 /* 1676 * On the sis, reading the status register also clears it. 1677 * So before returning to intr mode we must make sure that all 1678 * possible pending sources of interrupts have been served. 1679 * In practice this means run to completion the *eof routines, 1680 * and then call the interrupt routine 1681 */ 1682 sc->rxcycles = count; 1683 sis_rxeof(sc); 1684 sis_txeof(sc); 1685 if (ifp->if_snd.ifq_head != NULL) 1686 sis_start(ifp); 1687 1688 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1689 uint32_t status; 1690 1691 /* Reading the ISR register clears all interrupts. */ 1692 status = CSR_READ_4(sc, SIS_ISR); 1693 1694 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1695 sis_rxeoc(sc); 1696 1697 if (status & (SIS_ISR_RX_IDLE)) 1698 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1699 1700 if (status & SIS_ISR_SYSERR) { 1701 sis_reset(sc); 1702 sis_init(sc); 1703 } 1704 } 1705 } 1706 #endif /* DEVICE_POLLING */ 1707 1708 static void 1709 sis_intr(void *arg) 1710 { 1711 struct sis_softc *sc; 1712 struct ifnet *ifp; 1713 uint32_t status; 1714 1715 sc = arg; 1716 ifp = &sc->arpcom.ac_if; 1717 1718 #ifdef DEVICE_POLLING 1719 if (ifp->if_flags & IFF_POLLING) 1720 return; 1721 if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1722 CSR_WRITE_4(sc, SIS_IER, 0); 1723 sis_poll(ifp, 0, 1); 1724 return; 1725 } 1726 #endif /* DEVICE_POLLING */ 1727 1728 /* Supress unwanted interrupts */ 1729 if (!(ifp->if_flags & IFF_UP)) { 1730 sis_stop(sc); 1731 return; 1732 } 1733 1734 /* Disable interrupts. */ 1735 CSR_WRITE_4(sc, SIS_IER, 0); 1736 1737 for (;;) { 1738 /* Reading the ISR register clears all interrupts. */ 1739 status = CSR_READ_4(sc, SIS_ISR); 1740 1741 if ((status & SIS_INTRS) == 0) 1742 break; 1743 1744 if (status & 1745 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK | 1746 SIS_ISR_TX_IDLE) ) 1747 sis_txeof(sc); 1748 1749 if (status & 1750 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE)) 1751 sis_rxeof(sc); 1752 1753 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1754 sis_rxeoc(sc); 1755 1756 if (status & (SIS_ISR_RX_IDLE)) 1757 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1758 1759 if (status & SIS_ISR_SYSERR) { 1760 sis_reset(sc); 1761 sis_init(sc); 1762 } 1763 } 1764 1765 /* Re-enable interrupts. */ 1766 CSR_WRITE_4(sc, SIS_IER, 1); 1767 1768 if (ifp->if_snd.ifq_head != NULL) 1769 sis_start(ifp); 1770 } 1771 1772 /* 1773 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1774 * pointers to the fragment pointers. 1775 */ 1776 static int 1777 sis_encap(struct sis_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1778 { 1779 struct sis_desc *f = NULL; 1780 struct mbuf *m; 1781 int frag, cur, cnt = 0; 1782 1783 /* 1784 * If there's no way we can send any packets, return now. 1785 */ 1786 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2) 1787 return (ENOBUFS); 1788 1789 /* 1790 * Start packing the mbufs in this chain into 1791 * the fragment pointers. Stop when we run out 1792 * of fragments or hit the end of the mbuf chain. 1793 */ 1794 m = m_head; 1795 cur = frag = *txidx; 1796 1797 for (m = m_head; m != NULL; m = m->m_next) { 1798 if (m->m_len != 0) { 1799 if ((SIS_TX_LIST_CNT - 1800 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1801 return(ENOBUFS); 1802 f = &sc->sis_ldata.sis_tx_list[frag]; 1803 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1804 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1805 bus_dmamap_load(sc->sis_tag, f->sis_map, 1806 mtod(m, void *), m->m_len, 1807 sis_dma_map_desc_ptr, f, 0); 1808 bus_dmamap_sync(sc->sis_tag, f->sis_map, 1809 BUS_DMASYNC_PREREAD); 1810 if (cnt != 0) 1811 f->sis_ctl |= SIS_CMDSTS_OWN; 1812 cur = frag; 1813 SIS_INC(frag, SIS_TX_LIST_CNT); 1814 cnt++; 1815 } 1816 } 1817 1818 if (m != NULL) 1819 return(ENOBUFS); 1820 1821 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head; 1822 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1823 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1824 sc->sis_cdata.sis_tx_cnt += cnt; 1825 *txidx = frag; 1826 1827 return(0); 1828 } 1829 1830 /* 1831 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1832 * to the mbuf data regions directly in the transmit lists. We also save a 1833 * copy of the pointers since the transmit list fragment pointers are 1834 * physical addresses. 1835 */ 1836 1837 static void 1838 sis_start(struct ifnet *ifp) 1839 { 1840 struct sis_softc *sc; 1841 struct mbuf *m_head = NULL; 1842 uint32_t idx; 1843 1844 sc = ifp->if_softc; 1845 1846 if (!sc->sis_link) 1847 return; 1848 1849 idx = sc->sis_cdata.sis_tx_prod; 1850 1851 if (ifp->if_flags & IFF_OACTIVE) 1852 return; 1853 1854 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 1855 IF_DEQUEUE(&ifp->if_snd, m_head); 1856 if (m_head == NULL) 1857 break; 1858 1859 if (sis_encap(sc, m_head, &idx)) { 1860 IF_PREPEND(&ifp->if_snd, m_head); 1861 ifp->if_flags |= IFF_OACTIVE; 1862 break; 1863 } 1864 1865 /* 1866 * If there's a BPF listener, bounce a copy of this frame 1867 * to him. 1868 */ 1869 BPF_MTAP(ifp, m_head); 1870 } 1871 1872 /* Transmit */ 1873 sc->sis_cdata.sis_tx_prod = idx; 1874 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1875 1876 /* 1877 * Set a timeout in case the chip goes out to lunch. 1878 */ 1879 ifp->if_timer = 5; 1880 } 1881 1882 static void 1883 sis_init(void *xsc) 1884 { 1885 struct sis_softc *sc = xsc; 1886 struct ifnet *ifp = &sc->arpcom.ac_if; 1887 struct mii_data *mii; 1888 int s; 1889 1890 s = splimp(); 1891 1892 /* 1893 * Cancel pending I/O and free all RX/TX buffers. 1894 */ 1895 sis_stop(sc); 1896 1897 mii = device_get_softc(sc->sis_miibus); 1898 1899 /* Set MAC address */ 1900 if (sc->sis_type == SIS_TYPE_83815) { 1901 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1902 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1903 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1904 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1905 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1906 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1907 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1908 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1909 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1910 } else { 1911 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1912 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1913 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1914 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1915 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1916 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1917 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1918 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1919 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1920 } 1921 1922 /* Init circular RX list. */ 1923 if (sis_list_rx_init(sc) == ENOBUFS) { 1924 if_printf(ifp, "initialization failed: " 1925 "no memory for rx buffers\n"); 1926 sis_stop(sc); 1927 splx(s); 1928 return; 1929 } 1930 1931 /* 1932 * Init tx descriptors. 1933 */ 1934 sis_list_tx_init(sc); 1935 1936 /* 1937 * For the NatSemi chip, we have to explicitly enable the 1938 * reception of ARP frames, as well as turn on the 'perfect 1939 * match' filter where we store the station address, otherwise 1940 * we won't receive unicasts meant for this host. 1941 */ 1942 if (sc->sis_type == SIS_TYPE_83815) { 1943 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1944 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1945 } 1946 1947 /* If we want promiscuous mode, set the allframes bit. */ 1948 if (ifp->if_flags & IFF_PROMISC) 1949 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1950 else 1951 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1952 1953 /* 1954 * Set the capture broadcast bit to capture broadcast frames. 1955 */ 1956 if (ifp->if_flags & IFF_BROADCAST) 1957 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1958 else 1959 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1960 1961 /* 1962 * Load the multicast filter. 1963 */ 1964 if (sc->sis_type == SIS_TYPE_83815) 1965 sis_setmulti_ns(sc); 1966 else 1967 sis_setmulti_sis(sc); 1968 1969 /* Turn the receive filter on */ 1970 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1971 1972 /* 1973 * Load the address of the RX and TX lists. 1974 */ 1975 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 1976 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 1977 1978 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 1979 * the PCI bus. When this bit is set, the Max DMA Burst Size 1980 * for TX/RX DMA should be no larger than 16 double words. 1981 */ 1982 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) 1983 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 1984 else 1985 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 1986 1987 /* Accept Long Packets for VLAN support */ 1988 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1989 1990 /* Set TX configuration */ 1991 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) 1992 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1993 else 1994 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1995 1996 /* Set full/half duplex mode. */ 1997 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1998 SIS_SETBIT(sc, SIS_TX_CFG, 1999 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2000 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2001 } else { 2002 SIS_CLRBIT(sc, SIS_TX_CFG, 2003 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2004 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2005 } 2006 2007 /* 2008 * Enable interrupts. 2009 */ 2010 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2011 #ifdef DEVICE_POLLING 2012 /* 2013 * ... only enable interrupts if we are not polling, make sure 2014 * they are off otherwise. 2015 */ 2016 if (ifp->if_flags & IFF_POLLING) 2017 CSR_WRITE_4(sc, SIS_IER, 0); 2018 else 2019 #endif /* DEVICE_POLLING */ 2020 CSR_WRITE_4(sc, SIS_IER, 1); 2021 2022 /* Enable receiver and transmitter. */ 2023 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2024 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2025 2026 #ifdef notdef 2027 mii_mediachg(mii); 2028 #endif 2029 2030 /* 2031 * Page 75 of the DP83815 manual recommends the 2032 * following register settings "for optimum 2033 * performance." Note however that at least three 2034 * of the registers are listed as "reserved" in 2035 * the register map, so who knows what they do. 2036 */ 2037 if (sc->sis_type == SIS_TYPE_83815) { 2038 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2039 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2040 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2041 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2042 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2043 } 2044 2045 ifp->if_flags |= IFF_RUNNING; 2046 ifp->if_flags &= ~IFF_OACTIVE; 2047 2048 splx(s); 2049 2050 callout_reset(&sc->sis_timer, hz, sis_tick, sc); 2051 } 2052 2053 /* 2054 * Set media options. 2055 */ 2056 static int 2057 sis_ifmedia_upd(struct ifnet *ifp) 2058 { 2059 struct sis_softc *sc; 2060 struct mii_data *mii; 2061 2062 sc = ifp->if_softc; 2063 2064 mii = device_get_softc(sc->sis_miibus); 2065 sc->sis_link = 0; 2066 if (mii->mii_instance) { 2067 struct mii_softc *miisc; 2068 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2069 mii_phy_reset(miisc); 2070 } 2071 mii_mediachg(mii); 2072 2073 return(0); 2074 } 2075 2076 /* 2077 * Report current media status. 2078 */ 2079 static void 2080 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2081 { 2082 struct sis_softc *sc; 2083 struct mii_data *mii; 2084 2085 sc = ifp->if_softc; 2086 2087 mii = device_get_softc(sc->sis_miibus); 2088 mii_pollstat(mii); 2089 ifmr->ifm_active = mii->mii_media_active; 2090 ifmr->ifm_status = mii->mii_media_status; 2091 } 2092 2093 static int 2094 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2095 { 2096 struct sis_softc *sc = ifp->if_softc; 2097 struct ifreq *ifr = (struct ifreq *) data; 2098 struct mii_data *mii; 2099 int s, error = 0; 2100 2101 switch(command) { 2102 case SIOCSIFFLAGS: 2103 if (ifp->if_flags & IFF_UP) { 2104 sis_init(sc); 2105 } else { 2106 if (ifp->if_flags & IFF_RUNNING) 2107 sis_stop(sc); 2108 } 2109 error = 0; 2110 break; 2111 case SIOCADDMULTI: 2112 case SIOCDELMULTI: 2113 s = splimp(); 2114 if (sc->sis_type == SIS_TYPE_83815) 2115 sis_setmulti_ns(sc); 2116 else 2117 sis_setmulti_sis(sc); 2118 splx(s); 2119 error = 0; 2120 break; 2121 case SIOCGIFMEDIA: 2122 case SIOCSIFMEDIA: 2123 mii = device_get_softc(sc->sis_miibus); 2124 s = splimp(); 2125 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2126 splx(s); 2127 break; 2128 default: 2129 error = ether_ioctl(ifp, command, data); 2130 break; 2131 } 2132 2133 return(error); 2134 } 2135 2136 static void 2137 sis_watchdog(struct ifnet *ifp) 2138 { 2139 struct sis_softc *sc; 2140 2141 sc = ifp->if_softc; 2142 2143 ifp->if_oerrors++; 2144 if_printf(ifp, "watchdog timeout\n"); 2145 2146 sis_stop(sc); 2147 sis_reset(sc); 2148 sis_init(sc); 2149 2150 if (ifp->if_snd.ifq_head != NULL) 2151 sis_start(ifp); 2152 } 2153 2154 /* 2155 * Stop the adapter and free any mbufs allocated to the 2156 * RX and TX lists. 2157 */ 2158 static void 2159 sis_stop(struct sis_softc *sc) 2160 { 2161 int i; 2162 struct ifnet *ifp; 2163 2164 ifp = &sc->arpcom.ac_if; 2165 ifp->if_timer = 0; 2166 2167 callout_stop(&sc->sis_timer); 2168 2169 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2170 #ifdef DEVICE_POLLING 2171 ether_poll_deregister(ifp); 2172 #endif 2173 CSR_WRITE_4(sc, SIS_IER, 0); 2174 CSR_WRITE_4(sc, SIS_IMR, 0); 2175 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2176 DELAY(1000); 2177 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2178 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2179 2180 sc->sis_link = 0; 2181 2182 /* 2183 * Free data in the RX lists. 2184 */ 2185 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2186 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2187 bus_dmamap_unload(sc->sis_tag, 2188 sc->sis_ldata.sis_rx_list[i].sis_map); 2189 bus_dmamap_destroy(sc->sis_tag, 2190 sc->sis_ldata.sis_rx_list[i].sis_map); 2191 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2192 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2193 } 2194 } 2195 bzero(sc->sis_ldata.sis_rx_list, sizeof(sc->sis_ldata.sis_rx_list)); 2196 2197 /* 2198 * Free the TX list buffers. 2199 */ 2200 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2201 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2202 bus_dmamap_unload(sc->sis_tag, 2203 sc->sis_ldata.sis_tx_list[i].sis_map); 2204 bus_dmamap_destroy(sc->sis_tag, 2205 sc->sis_ldata.sis_tx_list[i].sis_map); 2206 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2207 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2208 } 2209 } 2210 2211 bzero(sc->sis_ldata.sis_tx_list, sizeof(sc->sis_ldata.sis_tx_list)); 2212 } 2213 2214 /* 2215 * Stop all chip I/O so that the kernel's probe routines don't 2216 * get confused by errant DMAs when rebooting. 2217 */ 2218 static void 2219 sis_shutdown(device_t dev) 2220 { 2221 struct sis_softc *sc; 2222 2223 sc = device_get_softc(dev); 2224 2225 sis_reset(sc); 2226 sis_stop(sc); 2227 } 2228